| created Mon Jun 13 18:56:28 2022 |
| Chiplet Control Register 0 - VITL CCFG | ||||
|---|---|---|---|---|
| Addr: |
0000000011000000 (SCOM) 0000000011000010 (SCOM1) 0000000011000020 (SCOM2) | |||
| Name: | TP.TCPAU1.CPLT_CTRL0 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | TP.TCPAU1.EPS.CTRL.CPLT_CTRL0_INST.CCFG_Q_INST.FSILAT.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | SCOM1 | SCOM2 | Dial: Description |
| 0 | RW | WO_OR | WO_CLEAR | CTRL_CC_ABSTCLK_MUXSEL_DC: Select ABIST clock source for Arrays on Chiplet Boundary. When set to 1, clocks where used from Chiplet with ABIST |
| 1 | RW | WO_OR | WO_CLEAR | TC_UNIT_SYNCCLK_MUXSEL_DC: Select the sync clock for async latches (init value 1) |
| 2 | RW | WO_OR | WO_CLEAR | CTRL_CC_FLUSHMODE_INH: Prevent plats from going into flush mode (init value 1) |
| 3 | RW | WO_OR | WO_CLEAR | CTRL_CC_FORCE_ALIGN: Force align signal to be sent (init value 1, drop before dropping flushmode_inh) |
| 4 | RW | WO_OR | WO_CLEAR | TC_UNIT_ARY_WRT_THRU_DC: Set Array into write thru mode, used for LBIST |
| 5 | RW | WO_OR | WO_CLEAR | UNUSED_5A: unused |
| 6 | RW | WO_OR | WO_CLEAR | TC_VITL_PROTECTION: VITL LBIST protection - turn on for LBIST only |
| 7 | RW | WO_OR | WO_CLEAR | UNUSED_7A: unused |
| 8 | RW | WO_OR | WO_CLEAR | CTRL_CC_ABIST_RECOV_DISABLE_DC: new signal to disable recovery |
| 9 | RW | WO_OR | WO_CLEAR | UNUSED_9A: unused |
| 10 | RW | WO_OR | WO_CLEAR | UNUSED_10A: unused |
| 11 | RW | WO_OR | WO_CLEAR | RESERVED_11A: reserved |
| 12 | RW | WO_OR | WO_CLEAR | TC_SKIT_MODE_BIST_DC: |
| 13 | RW | WO_OR | WO_CLEAR | TC_UNIT_DETERMINISTIC_TEST_ENA_DC: Forces login into deterministic test mode e.g. for LBIST |
| 14 | RW | WO_OR | WO_CLEAR | TC_UNIT_CONSTRAIN_SAFESCAN_DC: Safe scan of N1L latches. Prevent lck when switching SE |
| 15 | RW | WO_OR | WO_CLEAR | TC_UNIT_RRFA_TEST_ENA_DC: |
| 16 | RW | WO_OR | WO_CLEAR | UNUSED_16A: unused |
| 17 | RW | WO_OR | WO_CLEAR | UNUSED_17A: unused |
| 18 | RW | WO_OR | WO_CLEAR | RESERVED_18A: reserved |
| 19 | RW | WO_OR | WO_CLEAR | RESERVED_19A: reserved |
| 20:27 | RW | WO_OR | WO_CLEAR | TC_PSRO_SEL_DC: PSRO Select |
| 28 | RW | WO_OR | WO_CLEAR | UNUSED_28A: unused |
| 29 | RW | WO_OR | WO_CLEAR | UNUSED_29A: unused |
| 30 | RW | WO_OR | WO_CLEAR | UNUSED_30A: unused |
| 31 | RW | WO_OR | WO_CLEAR | UNUSED_31A: unused |
| 32 | RW | WO_OR | WO_CLEAR | RESERVED_32A: reserved |
| 33 | RW | WO_OR | WO_CLEAR | RESERVED_33A: reserved |
| 34 | RW | WO_OR | WO_CLEAR | RESERVED_34A: reserved |
| 35 | RW | WO_OR | WO_CLEAR | RESERVED_35A: reserved |
| 36 | RW | WO_OR | WO_CLEAR | RESERVED_36A: reserved |
| 37 | RW | WO_OR | WO_CLEAR | RESERVED_37A: reserved |
| 38 | RW | WO_OR | WO_CLEAR | RESERVED_38A: reserved |
| 39 | RW | WO_OR | WO_CLEAR | RESERVED_39A: reserved |
| 40:41 | RW | WO_OR | WO_CLEAR | CTRL_MISC_CLKDIV_SEL_DC: Clock Divider Select 00=1024:1 01=64:1 10=16:1 11=4:1 |
| 42 | RW | WO_OR | WO_CLEAR | RESERVED_42A: reserved |
| 43 | RW | WO_OR | WO_CLEAR | RESERVED_43A: reserved |
| 44 | RW | WO_OR | WO_CLEAR | UNUSED_44A: unused |
| 45 | RW | WO_OR | WO_CLEAR | UNUSED_45A: unused |
| 46 | RW | WO_OR | WO_CLEAR | UNUSED_46A: unused |
| 47 | RW | WO_OR | WO_CLEAR | CTRL_CC_PIN_LBIST_DC: TE=1 only - PIN LBIST mode - LBIST is controlled via Pin, not by OPCG |
| 48 | RW | WO_OR | WO_CLEAR | FREE_USAGE_48A: free usage |
| 49 | RW | WO_OR | WO_CLEAR | FREE_USAGE_49A: free usage |
| 50 | RW | WO_OR | WO_CLEAR | FREE_USAGE_50A: free usage |
| 51 | RW | WO_OR | WO_CLEAR | FREE_USAGE_51A: free usage |
| 52 | RW | WO_OR | WO_CLEAR | FREE_USAGE_52A: free usage |
| 53 | RW | WO_OR | WO_CLEAR | FREE_USAGE_53A: free usage |
| 54 | RW | WO_OR | WO_CLEAR | FREE_USAGE_54A: free usage |
| 55 | RW | WO_OR | WO_CLEAR | RESERVED_55A: reserved |
| 56 | RW | WO_OR | WO_CLEAR | FREE_USAGE_56A: free usage |
| 57 | RW | WO_OR | WO_CLEAR | FREE_USAGE_57A: free usage |
| 58 | RW | WO_OR | WO_CLEAR | FREE_USAGE_58A: free usage |
| 59 | RW | WO_OR | WO_CLEAR | FREE_USAGE_59A: free usage |
| 60 | RW | WO_OR | WO_CLEAR | FREE_USAGE_60A: free usage |
| 61 | RW | WO_OR | WO_CLEAR | FREE_USAGE_61A: free usage |
| 62 | RW | WO_OR | WO_CLEAR | FREE_USAGE_62A: free usage |
| 63 | RW | WO_OR | WO_CLEAR | FREE_USAGE_63A: free usage |
| Chiplet Control Register 1 - VITL CCFG | ||||
|---|---|---|---|---|
| Addr: |
0000000011000001 (SCOM) 0000000011000011 (SCOM1) 0000000011000021 (SCOM2) | |||
| Name: | TP.TCPAU1.CPLT_CTRL1 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:31 | TP.TCPAU1.EPS.CTRL.CPLT_CTRL1_INST.CCFG_Q_INST.FSILAT.LATC.L2(0:31) [00000000000000000000000000000000] | |||
| Bit(s) | SCOM | SCOM1 | SCOM2 | Dial: Description |
| 0 | RW | WO_OR | WO_CLEAR | TC_UNIT_MULTICYCLE_TEST_FENCE_DC: Mutlicycle test fence for LBIST |
| 1 | RW | WO_OR | WO_CLEAR | UNUSED_1B: unused |
| 2 | RW | WO_OR | WO_CLEAR | UNUSED_2B: unused |
| 3 | RW | WO_OR | WO_CLEAR | UNUSED_3B: unused |
| 4 | RW | WO_OR | WO_CLEAR | TC_REGION0_FENCE_DC: Fence for perv region |
| 5 | RW | WO_OR | WO_CLEAR | TC_REGION1_FENCE_DC: Fence for region 1 - pau0 |
| 6 | RW | WO_OR | WO_CLEAR | TC_REGION2_FENCE_DC: Fence for region 2 - pau1 |
| 7 | RW | WO_OR | WO_CLEAR | TC_REGION3_FENCE_DC: Fence for region 3 - reserved |
| 8 | RW | WO_OR | WO_CLEAR | TC_REGION4_FENCE_DC: Fence for region 4 - reserved |
| 9 | RW | WO_OR | WO_CLEAR | TC_REGION5_FENCE_DC: Fence for region 5 - tl |
| 10 | RW | WO_OR | WO_CLEAR | TC_REGION6_FENCE_DC: Fence for region 6 - ioppe |
| 11 | RW | WO_OR | WO_CLEAR | TC_REGION7_FENCE_DC: Fence for region 7 - unused |
| 12 | RW | WO_OR | WO_CLEAR | TC_REGION8_FENCE_DC: Fence for region 8 - unused |
| 13 | RW | WO_OR | WO_CLEAR | TC_REGION9_FENCE_DC: Fence for region 9 - unused |
| 14 | RW | WO_OR | WO_CLEAR | TC_REGION10_FENCE_DC: Fence for region 10 - unused |
| 15 | RW | WO_OR | WO_CLEAR | TC_REGION11_FENCE_DC: Fence for region 11 - unused |
| 16 | RW | WO_OR | WO_CLEAR | TC_REGION12_FENCE_DC: Fence for region 12 - unused |
| 17 | RW | WO_OR | WO_CLEAR | TC_REGION13_FENCE_DC: Fence for region 13 - unused |
| 18 | RW | WO_OR | WO_CLEAR | TC_REGION14_FENCE_DC: Fence for region 14 - unused |
| 19 | RW | WO_OR | WO_CLEAR | UNUSED_19B: unused |
| 20 | RW | WO_OR | WO_CLEAR | UNUSED_20B: unused |
| 21 | RW | WO_OR | WO_CLEAR | UNUSED_21B: unused |
| 22 | RW | WO_OR | WO_CLEAR | TC_STG_ACT_EN_DC: |
| 23 | RW | WO_OR | WO_CLEAR | UNUSED_23B: unused |
| 24 | RW | WO_OR | WO_CLEAR | UNUSED_24B: unused |
| 25 | RW | WO_OR | WO_CLEAR | UNUSED_25B: unused |
| 26 | RW | WO_OR | WO_CLEAR | UNUSED_26B: unused |
| 27 | RW | WO_OR | WO_CLEAR | UNUSED_27B: unused |
| 28 | RW | WO_OR | WO_CLEAR | UNUSED_28B: unused |
| 29 | RW | WO_OR | WO_CLEAR | UNUSED_29B: unused |
| 30 | RW | WO_OR | WO_CLEAR | UNUSED_30B: unused |
| 31 | RW | WO_OR | WO_CLEAR | UNUSED_31B: unused |
| Chiplet Control Register 2 - Region Partial Good | ||||
|---|---|---|---|---|
| Addr: |
0000000011000002 (SCOM) 0000000011000012 (SCOM1) 0000000011000022 (SCOM2) | |||
| Name: | TP.TCPAU1.CPLT_CTRL2 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 4:18 | TP.TCPAU1.EPS.CTRL.CPLT_CTRL2_INST.CCFG_Q_INST.FSILAT.LATC.L2(0:14) [000000000000000] | |||
| Bit(s) | SCOM | SCOM1 | SCOM2 | Dial: Description |
| 0:3 | RO | RO | RO | constant=0b0000 |
| 4 | RW | WO_OR | WO_CLEAR | CTRL_EPS_REGION0_PGOOD: Partial Good for region0 0=bad, 1=good |
| 5 | RW | WO_OR | WO_CLEAR | CTRL_EPS_REGION1_PGOOD: Partial Good for region 1 - pau0 0=bad, 1=good |
| 6 | RW | WO_OR | WO_CLEAR | CTRL_EPS_REGION2_PGOOD: Partial Good for region 2 - pau1 0=bad, 1=good |
| 7 | RW | WO_OR | WO_CLEAR | CTRL_EPS_REGION3_PGOOD: Partial Good for region 3 - reserved 0=bad, 1=good |
| 8 | RW | WO_OR | WO_CLEAR | CTRL_EPS_REGION4_PGOOD: Partial Good for region 4 - reserved 0=bad, 1=good |
| 9 | RW | WO_OR | WO_CLEAR | CTRL_EPS_REGION5_PGOOD: Partial Good for region 5 - tl 0=bad, 1=good |
| 10 | RW | WO_OR | WO_CLEAR | CTRL_EPS_REGION6_PGOOD: Partial Good for region 6 - ioppe 0=bad, 1=good |
| 11 | RW | WO_OR | WO_CLEAR | CTRL_EPS_REGION7_PGOOD: Partial Good for region 7 - unused 0=bad, 1=good |
| 12 | RW | WO_OR | WO_CLEAR | CTRL_EPS_REGION8_PGOOD: Partial Good for region 8 - unused 0=bad, 1=good |
| 13 | RW | WO_OR | WO_CLEAR | CTRL_EPS_REGION9_PGOOD: Partial Good for region 9 - unused 0=bad, 1=good |
| 14 | RW | WO_OR | WO_CLEAR | CTRL_EPS_REGION10_PGOOD: Partial Good for region 10 - unused 0=bad, 1=good |
| 15 | RW | WO_OR | WO_CLEAR | CTRL_EPS_REGION11_PGOOD: Partial Good for region 11 - unused 0=bad, 1=good |
| 16 | RW | WO_OR | WO_CLEAR | CTRL_EPS_REGION12_PGOOD: Partial Good for region 12 - unused 0=bad, 1=good |
| 17 | RW | WO_OR | WO_CLEAR | CTRL_EPS_REGION13_PGOOD: Partial Good for region 13 - unused 0=bad, 1=good |
| 18 | RW | WO_OR | WO_CLEAR | CTRL_EPS_REGION14_PGOOD: Partial Good for region 14 - unused 0=bad, 1=good |
| Chiplet Control Register 3 - Region PSCOM Enable | ||||
|---|---|---|---|---|
| Addr: |
0000000011000003 (SCOM) 0000000011000013 (SCOM1) 0000000011000023 (SCOM2) | |||
| Name: | TP.TCPAU1.CPLT_CTRL3 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 4:18 | TP.TCPAU1.EPS.CTRL.CPLT_CTRL3_INST.CCFG_Q_INST.FSILAT.LATC.L2(0:14) [000000000000000] | |||
| Bit(s) | SCOM | SCOM1 | SCOM2 | Dial: Description |
| 0:3 | RO | RO | RO | constant=0b0000 |
| 4 | RW | WO_OR | WO_CLEAR | CTRL_EPS_REGION0_PSCOM_EN: Region0 PSCOM enable - set to 1, to allow PSCOM access on this region |
| 5 | RW | WO_OR | WO_CLEAR | CTRL_EPS_REGION1_PSCOM_EN: region 1 - pau0 - PSCOM enable - set to 1, to allow PSCOM access on this region |
| 6 | RW | WO_OR | WO_CLEAR | CTRL_EPS_REGION2_PSCOM_EN: region 2 - pau1 - PSCOM enable - set to 1, to allow PSCOM access on this region |
| 7 | RW | WO_OR | WO_CLEAR | CTRL_EPS_REGION3_PSCOM_EN: region 3 - reserved - PSCOM enable - set to 1, to allow PSCOM access on this region |
| 8 | RW | WO_OR | WO_CLEAR | CTRL_EPS_REGION4_PSCOM_EN: region 4 - reserved - PSCOM enable - set to 1, to allow PSCOM access on this region |
| 9 | RW | WO_OR | WO_CLEAR | CTRL_EPS_REGION5_PSCOM_EN: region 5 - tl - PSCOM enable - set to 1, to allow PSCOM access on this region |
| 10 | RW | WO_OR | WO_CLEAR | CTRL_EPS_REGION6_PSCOM_EN: region 6 - ioppe - PSCOM enable - set to 1, to allow PSCOM access on this region |
| 11 | RW | WO_OR | WO_CLEAR | CTRL_EPS_REGION7_PSCOM_EN: region 7 - unused - PSCOM enable - set to 1, to allow PSCOM access on this region |
| 12 | RW | WO_OR | WO_CLEAR | CTRL_EPS_REGION8_PSCOM_EN: region 8 - unused - PSCOM enable - set to 1, to allow PSCOM access on this region |
| 13 | RW | WO_OR | WO_CLEAR | CTRL_EPS_REGION9_PSCOM_EN: region 9 - unused - PSCOM enable - set to 1, to allow PSCOM access on this region |
| 14 | RW | WO_OR | WO_CLEAR | CTRL_EPS_REGION10_PSCOM_EN: region 10 - unused - PSCOM enable - set to 1, to allow PSCOM access on this region |
| 15 | RW | WO_OR | WO_CLEAR | CTRL_EPS_REGION11_PSCOM_EN: region 11 - unused - PSCOM enable - set to 1, to allow PSCOM access on this region |
| 16 | RW | WO_OR | WO_CLEAR | CTRL_EPS_REGION12_PSCOM_EN: region 12 - unused - PSCOM enable - set to 1, to allow PSCOM access on this region |
| 17 | RW | WO_OR | WO_CLEAR | CTRL_EPS_REGION13_PSCOM_EN: region 13 - unused - PSCOM enable - set to 1, to allow PSCOM access on this region |
| 18 | RW | WO_OR | WO_CLEAR | CTRL_EPS_REGION14_PSCOM_EN: region 14 - unused - PSCOM enable - set to 1, to allow PSCOM access on this region |
| Chiplet Control Register 4 - Region Flushmode inhibit | ||||
|---|---|---|---|---|
| Addr: |
0000000011000004 (SCOM) 0000000011000014 (SCOM1) 0000000011000024 (SCOM2) | |||
| Name: | TP.TCPAU1.CPLT_CTRL4 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 4:18 | TP.TCPAU1.EPS.CTRL.CPLT_CTRL4_INST.CCFG_Q_INST.FSILAT.LATC.L2(0:14) [000000000000000] | |||
| Bit(s) | SCOM | SCOM1 | SCOM2 | Dial: Description |
| 0:3 | RO | RO | RO | constant=0b0000 |
| 4 | RW | WO_OR | WO_CLEAR | CTRL_CC_REGION0_FLUSHMODE_INH: Region0 flushmode inhibit - set to 1, to bring only this region out of flush |
| 5 | RW | WO_OR | WO_CLEAR | CTRL_CC_REGION1_FLUSHMODE_INH: region 1 - pau0 - flushmode inhibit - set to 1, to bring only this region out of flush |
| 6 | RW | WO_OR | WO_CLEAR | CTRL_CC_REGION2_FLUSHMODE_INH: region 2 - pau1 - flushmode inhibit - set to 1, to bring only this region out of flush |
| 7 | RW | WO_OR | WO_CLEAR | CTRL_CC_REGION3_FLUSHMODE_INH: region 3 - reserved - flushmode inhibit - set to 1, to bring only this region out of flush |
| 8 | RW | WO_OR | WO_CLEAR | CTRL_CC_REGION4_FLUSHMODE_INH: region 4 - reserved - flushmode inhibit - set to 1, to bring only this region out of flush |
| 9 | RW | WO_OR | WO_CLEAR | CTRL_CC_REGION5_FLUSHMODE_INH: region 5 - tl - flushmode inhibit - set to 1, to bring only this region out of flush |
| 10 | RW | WO_OR | WO_CLEAR | CTRL_CC_REGION6_FLUSHMODE_INH: region 6 - ioppe - flushmode inhibit - set to 1, to bring only this region out of flush |
| 11 | RW | WO_OR | WO_CLEAR | CTRL_CC_REGION7_FLUSHMODE_INH: region 7 - unused - flushmode inhibit - set to 1, to bring only this region out of flush |
| 12 | RW | WO_OR | WO_CLEAR | CTRL_CC_REGION8_FLUSHMODE_INH: region 8 - unused - flushmode inhibit - set to 1, to bring only this region out of flush |
| 13 | RW | WO_OR | WO_CLEAR | CTRL_CC_REGION9_FLUSHMODE_INH: region 9 - unused - flushmode inhibit - set to 1, to bring only this region out of flush |
| 14 | RW | WO_OR | WO_CLEAR | CTRL_CC_REGION10_FLUSHMODE_INH: region 10 - unused - flushmode inhibit - set to 1, to bring only this region out of flush |
| 15 | RW | WO_OR | WO_CLEAR | CTRL_CC_REGION11_FLUSHMODE_INH: region 11 - unused - flushmode inhibit - set to 1, to bring only this region out of flush |
| 16 | RW | WO_OR | WO_CLEAR | CTRL_CC_REGION12_FLUSHMODE_INH: region 12 - unused - flushmode inhibit - set to 1, to bring only this region out of flush |
| 17 | RW | WO_OR | WO_CLEAR | CTRL_CC_REGION13_FLUSHMODE_INH: region 13 - unused - flushmode inhibit - set to 1, to bring only this region out of flush |
| 18 | RW | WO_OR | WO_CLEAR | CTRL_CC_REGION14_FLUSHMODE_INH: region 14 - unused - flushmode inhibit - set to 1, to bring only this region out of flush |
| Chiplet Control Register 5 - Power Gate | ||||
|---|---|---|---|---|
| Addr: |
0000000011000005 (SCOM) 0000000011000015 (SCOM1) 0000000011000025 (SCOM2) | |||
| Name: | TP.TCPAU1.CPLT_CTRL5 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:19 | TP.TCPAU1.EPS.CTRL.CPLT_CTRL5_INST.CCFG_Q_INST.FSILAT.LATC.L2(0:19) [00000000000000000000] | |||
| Bit(s) | SCOM | SCOM1 | SCOM2 | Dial: Description |
| 0 | RW | WO_OR | WO_CLEAR | CPLT_CTRL5_00: Power Gate Control |
| 1 | RW | WO_OR | WO_CLEAR | CPLT_CTRL5_01: Power Gate Control |
| 2 | RW | WO_OR | WO_CLEAR | CPLT_CTRL5_02: Power Gate Control |
| 3 | RW | WO_OR | WO_CLEAR | CPLT_CTRL5_03: Power Gate Control - EQ: DFT Fence vitl |
| 4 | RW | WO_OR | WO_CLEAR | CPLT_CTRL5_04: Power Gate Control - EQ: DFT Fence Perv |
| 5 | RW | WO_OR | WO_CLEAR | CPLT_CTRL5_05: Power Gate Control - EQ: DFT Fence region 1 - pau0 - |
| 6 | RW | WO_OR | WO_CLEAR | CPLT_CTRL5_06: Power Gate Control - EQ: DFT Fence region 2 - pau1 - |
| 7 | RW | WO_OR | WO_CLEAR | CPLT_CTRL5_07: Power Gate Control - EQ: DFT Fence region 3 - reserved - |
| 8 | RW | WO_OR | WO_CLEAR | CPLT_CTRL5_08: Power Gate Control - EQ: DFT Fence region 4 - reserved - |
| 9 | RW | WO_OR | WO_CLEAR | CPLT_CTRL5_09: Power Gate Control - EQ: DFT Fence region 5 - tl - |
| 10 | RW | WO_OR | WO_CLEAR | CPLT_CTRL5_010: Power Gate Control - EQ: DFT Fence region 6 - ioppe - |
| 11 | RW | WO_OR | WO_CLEAR | CPLT_CTRL5_011: Power Gate Control - EQ: DFT Fence region 7 - unused - |
| 12 | RW | WO_OR | WO_CLEAR | CPLT_CTRL5_012: Power Gate Control - EQ: DFT Fence region 8 - unused - |
| 13 | RW | WO_OR | WO_CLEAR | CPLT_CTRL5_013: Power Gate Control - EQ: DFT Fence region 9 - unused - |
| 14 | RW | WO_OR | WO_CLEAR | CPLT_CTRL5_014: Power Gate Control - EQ: DFT Fence region 10 - unused - |
| 15 | RW | WO_OR | WO_CLEAR | CPLT_CTRL5_015: Power Gate Control - EQ: DFT Fence region 11 - unused - |
| 16 | RW | WO_OR | WO_CLEAR | CPLT_CTRL5_016: Power Gate Control - EQ: DFT Fence region 12 - unused - |
| 17 | RW | WO_OR | WO_CLEAR | CPLT_CTRL5_017: Power Gate Control - EQ: DFT Fence region 13 - unused - |
| 18 | RW | WO_OR | WO_CLEAR | CPLT_CTRL5_018: Power Gate Control - EQ: DFT Fence region 14 - unused - |
| 19 | RW | WO_OR | WO_CLEAR | CPLT_CTRL5_019: Power Gate Control |
| Chiplet Config Register 0 - VITL FUNC | ||||
|---|---|---|---|---|
| Addr: |
0000000011000008 (SCOM) 0000000011000018 (SCOM1) 0000000011000028 (SCOM2) | |||
| Name: | TP.TCPAU1.CPLT_CONF0 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | TP.TCPAU1.EPS.CTRL.CPLT_CONF0_OUT_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | SCOM1 | SCOM2 | Dial: Description |
| 0:5 | RW | WO_OR | WO_CLEAR | CTRL_MISC_PROBE0_SEL_DC: Probe 0 select please look at Probe spec for more details |
| 6 | RW | WO_OR | WO_CLEAR | RESERVED_6G: reserved |
| 7 | RW | WO_OR | WO_CLEAR | RESERVED_7G: reserved |
| 8:13 | RW | WO_OR | WO_CLEAR | CTRL_MISC_PROBE1_SEL_DC: Probe 1 select please look at Probe spec for more details |
| 14 | RW | WO_OR | WO_CLEAR | RESERVED_14G: reserved |
| 15 | RW | WO_OR | WO_CLEAR | RESERVED_15G: reserved |
| 16:21 | RW | WO_OR | WO_CLEAR | CTRL_MISC_PROBE2_SEL_DC: Probe 2 select please look at Probe spec for more details |
| 22 | RW | WO_OR | WO_CLEAR | RESERVED_22G: reserved |
| 23 | RW | WO_OR | WO_CLEAR | RESERVED_23G: reserved |
| 24:29 | RW | WO_OR | WO_CLEAR | CTRL_MISC_PROBE3_SEL_DC: Probe 3 select please look at Probe spec for more details |
| 30 | RW | WO_OR | WO_CLEAR | RESERVED_30G: reserved |
| 31 | RW | WO_OR | WO_CLEAR | RESERVED_31G: reserved |
| 32 | RW | WO_OR | WO_CLEAR | CTRL_MISC_OFLOW_FEH_SEL_DC: ABIST Overflow/Fail Ever Happen Select |
| 33 | RW | WO_OR | WO_CLEAR | CTRL_CC_SCAN_PROTECT_DC: Enables Scan Protection - Enables Scan Collision Error Mechanism |
| 34 | RW | WO_OR | WO_CLEAR | CTRL_CC_SDIS_DC_N: For Scan Diagnostic to Discable Scan path |
| 35 | RW | WO_OR | WO_CLEAR | CTRL_CC_SCAN_DIAG_DC: For System Scan diag control |
| 36 | RW | WO_OR | WO_CLEAR | RESERVED_TEST_CONTROL_36G: reserved test control |
| 37 | RW | WO_OR | WO_CLEAR | RESERVED_TEST_CONTROL_37G: reserved test control |
| 38 | RW | WO_OR | WO_CLEAR | RESERVED_TEST_CONTROL_38G: reserved test control |
| 39 | RW | WO_OR | WO_CLEAR | RESERVED_TEST_CONTROL_39G: reserved test control |
| 40 | RW | WO_OR | WO_CLEAR | CTRL_EPS_MASK_VITL_PCB_ERR_DC: Mask VITL PCB Errors from CC or CPLT_CTRL |
| 41 | RW | WO_OR | WO_CLEAR | CTRL_CC_MASK_VITL_SCAN_OPCG_ERR_DC: Mask VITL Errors in CC, which are not PCB related |
| 42 | RW | WO_OR | WO_CLEAR | RESERVED_42G: RESERVED |
| 43 | RW | WO_OR | WO_CLEAR | RESERVED_43G: RESERVED |
| 44 | RW | WO_OR | WO_CLEAR | TC_PCB_DBG_GLB_BRCST_EN: DD2 only: Enable Debug Broadcast |
| 45 | RW | WO_OR | WO_CLEAR | RESERVED_45G: reserved |
| 46 | RW | WO_OR | WO_CLEAR | TC_SKIT_CANARY_MODE_DC: |
| 47 | RW | WO_OR | WO_CLEAR | TC_TOPOLOGY_MODE_DC: |
| 48:51 | RW | WO_OR | WO_CLEAR | TC_TOPOLOGY_ID_DC: Topology ID |
| 52 | RW | WO_OR | WO_CLEAR | FREE_USAGE_52G: free usage |
| 53 | RW | WO_OR | WO_CLEAR | FREE_USAGE_53G: free usage |
| 54 | RW | WO_OR | WO_CLEAR | FREE_USAGE_54G: free usage |
| 55 | RW | WO_OR | WO_CLEAR | FREE_USAGE_55G: free usage |
| 56 | RW | WO_OR | WO_CLEAR | FREE_USAGE_56G: free usage |
| 57 | RW | WO_OR | WO_CLEAR | FREE_USAGE_57G: free usage |
| 58 | RW | WO_OR | WO_CLEAR | FREE_USAGE_58G: free usage |
| 59 | RW | WO_OR | WO_CLEAR | FREE_USAGE_59G: free usage |
| 60 | RW | WO_OR | WO_CLEAR | FREE_USAGE_60G: free usage |
| 61 | RW | WO_OR | WO_CLEAR | FREE_USAGE_61G: free usage |
| 62 | RW | WO_OR | WO_CLEAR | FREE_USAGE_62G: free usage |
| 63 | RW | WO_OR | WO_CLEAR | FREE_USAGE_63G: free usage |
| Chiplet Config Register 1 - VITL FUNC | ||||
|---|---|---|---|---|
| Addr: |
0000000011000009 (SCOM) 0000000011000019 (SCOM1) 0000000011000029 (SCOM2) | |||
| Name: | TP.TCPAU1.CPLT_CONF1 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:31 | TP.TCPAU1.EPS.CTRL.CPLT_CONF1_OUT_INST.LATC.L2(0:31) [00000000000000000000000000000000] | |||
| Bit(s) | SCOM | SCOM1 | SCOM2 | Dial: Description |
| 0 | RW | WO_OR | WO_CLEAR | TC_NV0_IOVALID_DC: AMUX or LaneCTL or IOVAILD or RATIO |
| 1 | RW | WO_OR | WO_CLEAR | TC_NV1_IOVALID_DC: AMUX or LaneCTL or IOVAILD or RATIO |
| 2 | RW | WO_OR | WO_CLEAR | TC_NV2_IOVALID_DC: AMUX or LaneCTL or IOVAILD or RATIO |
| 3 | RW | WO_OR | WO_CLEAR | TC_NV3_IOVALID_DC: AMUX or LaneCTL or IOVAILD or RATIO |
| 4 | RW | WO_OR | WO_CLEAR | UNUSED_4H: unused |
| 5 | RW | WO_OR | WO_CLEAR | UNUSED_5H: unused |
| 6 | RW | WO_OR | WO_CLEAR | UNUSED_6H: unused |
| 7 | RW | WO_OR | WO_CLEAR | UNUSED_7H: unused |
| 8 | RW | WO_OR | WO_CLEAR | UNUSED_8H: unused |
| 9 | RW | WO_OR | WO_CLEAR | UNUSED_9H: unused |
| 10 | RW | WO_OR | WO_CLEAR | UNUSED_10H: unused |
| 11 | RW | WO_OR | WO_CLEAR | UNUSED_11H: unused |
| 12 | RW | WO_OR | WO_CLEAR | UNUSED_12H: unused |
| 13 | RW | WO_OR | WO_CLEAR | UNUSED_13H: unused |
| 14 | RW | WO_OR | WO_CLEAR | UNUSED_14H: unused |
| 15 | RW | WO_OR | WO_CLEAR | UNUSED_15H: unused |
| 16 | RW | WO_OR | WO_CLEAR | UNUSED_16H: unused |
| 17 | RW | WO_OR | WO_CLEAR | UNUSED_17H: unused |
| 18 | RW | WO_OR | WO_CLEAR | UNUSED_18H: unused |
| 19 | RW | WO_OR | WO_CLEAR | UNUSED_19H: unused |
| 20 | RW | WO_OR | WO_CLEAR | UNUSED_20H: unused |
| 21 | RW | WO_OR | WO_CLEAR | UNUSED_21H: unused |
| 22 | RW | WO_OR | WO_CLEAR | UNUSED_22H: unused |
| 23 | RW | WO_OR | WO_CLEAR | UNUSED_23H: unused |
| 24 | RW | WO_OR | WO_CLEAR | UNUSED_24H: unused |
| 25 | RW | WO_OR | WO_CLEAR | UNUSED_25H: unused |
| 26 | RW | WO_OR | WO_CLEAR | UNUSED_26H: unused |
| 27 | RW | WO_OR | WO_CLEAR | UNUSED_27H: unused |
| 28 | RW | WO_OR | WO_CLEAR | UNUSED_28H: unused |
| 29 | RW | WO_OR | WO_CLEAR | UNUSED_29H: unused |
| 30 | RW | WO_OR | WO_CLEAR | UNUSED_30H: unused |
| 31 | RW | WO_OR | WO_CLEAR | UNUSED_31H: unused |
| Chiplet Status Register - Interrupt send out on bit change if not masked via Chiplet Mask Register. Mask only mask the interrupt, not the status register! | ||||
|---|---|---|---|---|
| Addr: |
0000000011000100 (SCOM) | |||
| Name: | TP.TCPAU1.CPLT_STAT0 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:31 | TP.TCPAU1.EPS.CTRL.CPLT_STAT_OUT_INST.LATC.L2(0:31) [00000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | ROX | ABIST_DONE_DC: abist_done_dc | ||
| 1 | ROX | UNUSED_1I: unused | ||
| 2 | ROX | RESERVED_2I: reserved | ||
| 3 | ROX | RESERVED_3I: reserved | ||
| 4 | ROX | TC_DIAG_PORT0_OUT: Diagnostic out port | ||
| 5 | ROX | TC_DIAG_PORT1_OUT: Diagnostic out port | ||
| 6 | ROX | RESERVED_6I: reserved | ||
| 7 | ROX | UNUSED_7I: unused | ||
| 8 | ROX | CC_CTRL_OPCG_DONE_DC: OPCG done. For LBIST, ABIST, or other OPCG runs | ||
| 9 | ROX | CC_CTRL_CHIPLET_IS_ALIGNED_DC: Indicates that Chiplet is aligned | ||
| 10 | ROX | FREE_USAGE_10I: free usage | ||
| 11 | ROX | FREE_USAGE_11I: free usage | ||
| 12 | ROX | FREE_USAGE_12I: free usage | ||
| 13 | ROX | FREE_USAGE_13I: free usage | ||
| 14 | ROX | FREE_USAGE_14I: free usage | ||
| 15 | ROX | FREE_USAGE_15I: free usage | ||
| 16 | ROX | FREE_USAGE_16I: free usage | ||
| 17 | ROX | FREE_USAGE_17I: free usage | ||
| 18 | ROX | FREE_USAGE_18I: free usage | ||
| 19 | ROX | FREE_USAGE_19I: free usage | ||
| 20 | ROX | FREE_USAGE_20I: free usage | ||
| 21 | ROX | FREE_USAGE_21I: free usage | ||
| 22 | ROX | FREE_USAGE_22I: free usage | ||
| 23 | ROX | FREE_USAGE_23I: free usage | ||
| 24 | ROX | GLOBAL_FEH_DC: chiplet specific | ||
| 25 | ROX | FREE_USAGE_25I: free usage | ||
| 26 | ROX | FREE_USAGE_26I: free usage | ||
| 27 | ROX | FREE_USAGE_27I: free usage | ||
| 28 | ROX | FREE_USAGE_28I: free usage | ||
| 29 | ROX | FREE_USAGE_29I: free usage | ||
| 30 | ROX | FREE_USAGE_30I: free usage | ||
| 31 | ROX | FREE_USAGE_31I: free usage | ||
| Chiplet Mask Register - Masking the Interrupt on a bitchange of the Chiplet Status Register. Does not mask the status itself! | ||||
|---|---|---|---|---|
| Addr: |
0000000011000101 (SCOM) | |||
| Name: | TP.TCPAU1.CPLT_MASK0 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:31 | TP.TCPAU1.EPS.CTRL.CPLT_MASK_OUT_INST.LATC.L2(0:31) [00000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:31 | RW | ITR_MASK: Bitwise masking of cplt_stat0 - will prevent interrupt | ||
| CTRL Protect Mode Register | ||||
|---|---|---|---|---|
| Addr: |
00000000110003FE (SCOM) | |||
| Name: | TP.TCPAU1.CTRL_PROTECT_MODE_REG | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0 | TP.TCPAU1.EPS.CTRL.PCB_IF.PROTECT_MODE.RD_PROTECT_ENA_INST.LATC.L2(0) [0] | |||
| 1 | TP.TCPAU1.EPS.CTRL.PCB_IF.PROTECT_MODE.WR_PROTECT_ENA_INST.LATC.L2(0) [0] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | RW | CTRL_READ_PROTECT_ENABLE: Enable read protection | ||
| 1 | RW | CTRL_WRITE_PROTECT_ENABLE: Enable write protection | ||
| Atomic Lock Register | ||||
|---|---|---|---|---|
| Addr: |
00000000110003FF (SCOM) | |||
| Name: | TP.TCPAU1.CTRL_ATOMIC_LOCK_REG | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0 | TP.TCPAU1.EPS.CTRL.PCB_IF.ATOMIC_LOCK.ATOMIC_LOCK_ENA_INST.LATC.L2(0) [0] | |||
| 1:4 | TP.TCPAU1.EPS.CTRL.PCB_IF.ATOMIC_LOCK.ATOMIC_ID_Q_INST.LATC.L2(0:3) [0000] | |||
| 8:15 | TP.TCPAU1.EPS.CTRL.PCB_IF.ATOMIC_LOCK.ATOMIC_LOCK_ACTIVITY_Q_INST.LATC.L2(0:7) [00000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | RW | CTRL_ATOMIC_LOCK_ENABLE: Enable atomic lock | ||
| 1:4 | ROX | CTRL_ATOMIC_ID: Atomic ID | ||
| 5:7 | RO | constant=0b000 | ||
| 8:15 | ROX | CTRL_ATOMIC_ACTIVITY: Atomic lock counter | ||
| PSCOMLE mode register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010000 (SCOM) | |||
| Name: | TP.TCPAU1.EPS.PSC.PSC.PSCOM_MODE_REG | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:11 | TP.TCPAU1.EPS.PSC.PSC.PSCOM_MODE_LT_INST.LATC.L2(0:11) [000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | RW | ABORT_ON_PCB_ADDR_PARITY_ERROR: abort_on_PCB_addr_parity_error | ||
| 1 | RW | ABORT_ON_PCB_WDATA_PARITY_ERROR: abort_on_PCB_wdata_parity_error | ||
| 2 | RW | UNUSED_MODE_REG_BIT_2: unused_mode_reg_bit_2 | ||
| 3 | RW | ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR: abort_on_DL_return_wdata_parity_error | ||
| 4 | RW | WATCHDOG_ENABLE: watchdog_enable | ||
| 5:6 | RW | SCOM_HANG_LIMIT: 0b11: 256, 0b10:512, 0b01:768, 0b00:1023 | ||
| 7 | RW | FORCE_ALL_RINGS: set to logic 1 if all rings should be enable independent of ring address | ||
| 8 | RW | FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE: fsm_selfreset_on_statevec_parityerror_enable | ||
| 9:11 | RW | RESERVED_PSCOM_MODE_LT: reserved | ||
| PSCOMLE error register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010001 (SCOM) | |||
| Name: | TP.TCPAU1.EPS.PSC.PSC.PSCOM_STATUS_ERROR_REG | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:17 | TP.TCPAU1.EPS.PSC.PSC.PSCOM_ERR_LT_0_INST.LATC.L2(0:17) [000000000000000000] | |||
| 18:35 | TP.TCPAU1.EPS.PSC.PSC.PSCOM_ERR_TRAP_LT_0_INST.LATC.L2(0:17) [000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | RWX | ACCUMULATED_PCB_WDATA_PARITY_ERROR: Accumulated_PCB_wdata_parity_error | ||
| 1 | RWX | ACCUMULATED_PCB_ADDRESS_PARITY_ERROR: Accumulated_PCB_address_parity_error | ||
| 2 | RWX | ACCUMULATED_DL_RETURN_WDATA_PARITY_ERROR: Accumulated_DL_return_wdata_parity_error | ||
| 3 | RWX | ACCUMULATED_DL_RETURN_P0_ERROR: Accumulated_DL_return_P0_error | ||
| 4 | RWX | ACCUMULATED_UL_RDATA_PARITY_ERROR: Accumulated_UL_rdata_parity_error | ||
| 5 | RWX | ACCUMULATED_UL_P0_ERROR: Accumulated_UL_P0_error | ||
| 6 | RWX | ACCUMULATED_PARITY_ERROR_ON_INTERFACE_MACHINE: Accumulated_parity_error_on_interface_machine | ||
| 7 | RWX | ACCUMULATED_PARITY_ERROR_ON_P2S_MACHINE: Accumulated_parity_error_on_p2s_machine | ||
| 8 | RWX | ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH: Accumulated_timeout_while_waiting_for_ULCCH | ||
| 9 | RWX | ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN: Accumulated_timeout_while_waiting_for_DLDCH_return | ||
| 10 | RWX | ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH: Accumulated_timeout_while_waiting_for_ULDCH | ||
| 11 | RWX | ACCUMULATED_PSCOM_LOCK_ERR: Accumulated_pscom_lock_err | ||
| 12 | RWX | ACCUMULATED_PSCOM_PARALLEL_READ_WRITE_NVLD: Accumulated_pscom_parallel_read_write_nvld | ||
| 13 | RWX | ACCUMULATED_PSCOM_PARALLEL_ADDR_INVALID: Accumulated_pscom_parallel_addr_invalid | ||
| 14 | RWX | ACCUMULATED_PCB_COMMAND_PARITY_ERROR: Accumulated_PCB_command_parity_error | ||
| 15 | RWX | ACCUMULATED_GENERAL_TIMEOUT: Accumulated_General_timeout | ||
| 16 | RWX | ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION: Accumulated_satellite_acknowledge_access_violation | ||
| 17 | RWX | ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER: Accumulated_satellite_acknowledge_invalid_register | ||
| 18 | RWX | TRAPPED_PCB_WDATA_PARITY_ERROR: Trapped_PCB_wdata_parity_error | ||
| 19 | RWX | TRAPPED_PCB_ADDRESS_PARITY_ERROR: Trapped_PCB_address_parity_error | ||
| 20 | RWX | TRAPPED_DL_RETURN_WDATA_PARITY_ERROR: Trapped_DL_return_wdata_parity_error | ||
| 21 | RWX | TRAPPED_DL_RETURN_P0_ERROR: Trapped_DL_return_P0_error | ||
| 22 | RWX | TRAPPED_UL_RDATA_PARITY_ERROR: Trapped_UL_rdata_parity_error | ||
| 23 | RWX | TRAPPED_UL_P0_ERROR: Trapped_UL_P0_error | ||
| 24 | RWX | TRAPPED_PARITY_ERROR_ON_INTERFACE_MACHINE: Trapped_parity_error_on_interface_machine | ||
| 25 | RWX | TRAPPED_PARITY_ERROR_ON_P2S_MACHINE: Trapped_parity_error_on_p2s_machine | ||
| 26 | RWX | TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH: Trapped_timeout_while_waiting_for_ULCCH | ||
| 27 | RWX | TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN: Trapped_timeout_while_waiting_for_DLDCH_return | ||
| 28 | RWX | TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH: Trapped_timeout_while_waiting_for_ULDCH | ||
| 29 | RWX | TRAPPED_PSCOM_LOCK_ERR: Trapped_pscom_lock_err | ||
| 30 | RWX | TRAPPED_PSCOM_PARALLEL_READ_WRITE_NVLD: Trapped_pscom_parallel_read_write_nvld | ||
| 31 | RWX | TRAPPED_PSCOM_PARALLEL_ADDR_INVALID: Trapped_pscom_parallel_addr_invalid | ||
| 32 | RWX | TRAPPED_PCB_COMMAND_PARITY_ERROR: Trapped_PCB_command_parity_error | ||
| 33 | RWX | TRAPPED_GENERAL_TIMEOUT: Trapped_General_timeout | ||
| 34 | RWX | TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION: Trapped_satellite_acknowledge_access_violation | ||
| 35 | RWX | TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER: Trapped_satellite_acknowledge_invalid_register | ||
| PSCOMLE error mask register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010002 (SCOM) | |||
| Name: | TP.TCPAU1.EPS.PSC.PSC.PSCOM_ERROR_MASK | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:17 | TP.TCPAU1.EPS.PSC.PSC.PSCOM_ERR_MASK_LT_INST.LATC.L2(0:17) [000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | RW | MASK_PCB_WDATA_PARITY_ERROR: mask_PCB_wdata_parity_error | ||
| 1 | RW | MASK_PCB_ADDRESS_PARITY_ERROR: mask_PCB_address_parity_error | ||
| 2 | RW | MASK_DL_RETURN_WDATA_PARITY_ERROR: mask_DL_return_wdata_parity_error | ||
| 3 | RW | MASK_DL_RETURN_P0_ERROR: mask_DL_return_P0_error | ||
| 4 | RW | MASK_UL_RDATA_PARITY_ERROR: mask_UL_rdata_parity_error | ||
| 5 | RW | MASK_UL_P0_ERROR: mask_UL_P0_error | ||
| 6 | RW | MASK_PARITY_ERROR_ON_INTERFACE_MACHINE: mask_parity_error_on_interface_machine | ||
| 7 | RW | MASK_PARITY_ERROR_ON_P2S_MACHINE: mask_parity_error_on_p2s_machine | ||
| 8 | RW | MASK_TIMEOUT_WHILE_WAITING_FOR_ULCCH: mask_timeout_while_waiting_for_ULCCH | ||
| 9 | RW | MASK_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN: mask_timeout_while_waiting_for_DLDCH_return | ||
| 10 | RW | MASK_TIMEOUT_WHILE_WAITING_FOR_ULDCH: mask_timeout_while_waiting_for_ULDCH | ||
| 11 | RW | MASK_PSCOM_LOCK_ERR: mask_pscom_lock_err | ||
| 12 | RW | MASK_PSCOM_PARALLEL_READ_WRITE_NVLD: mask_pscom_parallel_read_write_nvld | ||
| 13 | RW | MASK_PSCOM_PARALLEL_ADDR_INVALID: mask_pscom_parallel_addr_invalid | ||
| 14 | RW | MASK_PCB_COMMAND_PARITY_ERROR: mask_PCB_command_parity_error | ||
| 15 | RW | MASK_GENERAL_TIMEOUT: mask_general_timeout | ||
| 16 | RW | MASK_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION: mask_satellite_acknowledge_access_violation | ||
| 17 | RW | MASK_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER: mask_satellite_acknowledge_invalid_register | ||
| PSCOMLE Address Trap Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010003 (SCOM) | |||
| Name: | TP.TCPAU1.EPS.PSC.PSC.ADDR_TRAP_REG | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:17 | TP.TCPAU1.EPS.PSC.PSC.ADDR_LAST_TRAP_LT_INST.LATC.L2(0:17) [000000000000000000] | |||
| 18:30 | TP.TCPAU1.EPS.PSC.PSC.FSM_STATE_CAPTURE_LT_0_INST.LATC.L2(0:12) [0000000000000] | |||
| 31:34 | TP.TCPAU1.EPS.PSC.PSC.SATELLITE_ACK_TRAP_LT_0_INST.LATC.L2(0:3) [0000] | |||
| 35:38 | TP.TCPAU1.EPS.PSC.PSC.PCB_REQ_MASTER_ADDR_TRAP_LT_INST.LATC.L2(0:3) [0000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:15 | ROX | PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR: PCB_address_of_last_transaction_with_error | ||
| 16 | ROX | PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR: PCB_read_notwrite_of_last_transaction_with_error | ||
| 17 | ROX | RESERVED_ADDR_LAST_TRAP_LT: reserved_0 | ||
| 18:30 | ROX | SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR: Serial2Parallel_state_machine_at_time_of_error | ||
| 31 | ROX | SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY: Satellite acknoledge bit: set to 1 if no parity error detected of Sat.No and Ack-bits | ||
| 32 | ROX | SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR: set if write parity error detected by satellite | ||
| 33 | ROX | SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION: set if invalid read or write access detected by satellite | ||
| 34 | ROX | SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER: set if invalid register address detected by satellite | ||
| 35:38 | ROX | LAST_MASTERID: MasterID of the last non-internal PSCOM transation | ||
| Ring Lock Enable Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010005 (SCOM) | |||
| Name: | TP.TCPAU1.EPS.PSC.PSC.WRITE_PROTECT_ENABLE_REG | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:1 | TP.TCPAU1.EPS.PSC.PSC.WRITE_PROTECT_Q_INST.LATC.L2(0:1) [00] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | RW | ENABLE_RING_LOCKING: General enable of ring locking upon write to specific ring | ||
| 1 | RW | RESERVED_RING_LOCKING: reserved | ||
| WRITE PROTECT RINGS Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010006 (SCOM) | |||
| Name: | TP.TCPAU1.EPS.PSC.PSC.WRITE_PROTECT_RINGS_REG | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:31 | TP.TCPAU1.EPS.PSC.PSC.WRITE_PROTECT_RINGS_Q_INST.LATC.L2(0:31) [00000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:31 | RW | WRITE_PROTECT_RINGS: write protect bit map for each ring | ||
| Atomic Lock Mask Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010007 (SCOM) | |||
| Name: | TP.TCPAU1.EPS.PSC.PSC.ATOMIC_LOCK_MASK_LATCH_REG | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:31 | TP.TCPAU1.EPS.PSC.PSC.ATOMIC_LOCK_ENABLE_MASK_Q_INST.LATC.L2(0:31) [00000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:31 | RW | ATOMIC_LOCK_MASK: bit mask for atomic locking on a ring-by-ring basis | ||
| Ring Fence Enable Mask Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010008 (SCOM) | |||
| Name: | TP.TCPAU1.EPS.PSC.PSC.RING_FENCE_MASK_LATCH_REG | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 1:31 | TP.TCPAU1.EPS.PSC.PSC.RING_FENCE_ENABLE_MASK_Q_INST.LATC.L2(1:31) [0000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | RO | constant=0b0 | ||
| 1:31 | RW | RING_FENCE_ENABLE_MASK: bit mask for ring fenceing on a ring-by-ring basis | ||
| Trace Array High Data Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010400 (SCOM) | |||
| Name: | TP.TCPAU1.TRA0.TR0.TRACE_HI_DATA_REG | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | TP.TCPAU1.TRA0.TR0.SAMP.TRACE_DATA_LT_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:63 | ROX | TRACE_HI_DATA: Trace Array Data 0:63 | ||
| Trace Array Low Data Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010401 (SCOM) | |||
| Name: | TP.TCPAU1.TRA0.TR0.TRACE_LO_DATA_REG | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:31 | TP.TCPAU1.TRA0.TR0.SAMP.TRACE_DATA_LT_INST.LATC.L2(64:95) [00000000000000000000000000000000] | |||
| 32:41 | TP.TCPAU1.TRA0.TR0.SAMP.TR_ADDRESS_LT_INST.LATC.L2(0:9) [0000000000] | |||
| 42:50 | TP.TCPAU1.TRA0.TR0.SAMP.TR_LAST_BANK_LT_INST.LATC.L2(0:8) [000000000] | |||
| 51 | TP.TCPAU1.TRA0.TR0.SAMP.TR_LAST_BANK_VALID_LT_INST.LATC.L2(0) [0] | |||
| 52 | TP.TCPAU1.TRA0.TR0.SAMP.TR_WRITE_ON_RUN_LT_INST.LATC.L2(0) [0] | |||
| 53 | TP.TCPAU1.TRA0.TR0.SAMP.TR_RUN_LT_INST.LATC.L2(0) [0] | |||
| 54:63 | TP.TCPAU1.TRA0.TR0.SAMP.TR_HOLD_ADDRESS_LT_INST.LATC.L2(0:9) [0000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:31 | ROX | TRACE_LO_DATA: Trace Array Data 64:95 | ||
| 32:41 | ROX | TRACE_ADDRESS: Trace Address | ||
| 42:50 | ROX | TRACE_LAST_BANK: Trace Last Bank | ||
| 51 | ROX | TRACE_LAST_BANK_VALID: Trace Last Bank Valid | ||
| 52 | ROX | TRACE_WRITE_ON_RUN: Trace Write-On-Run indicator | ||
| 53 | ROX | TRACE_RUNNING: Trace Run indicator | ||
| 54:63 | ROX | TRACE_HOLD_ADDRESS: Trace Hold Address (pointing to last entry) | ||
| trace control configuration register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010402 (SCOM) | |||
| Name: | TP.TCPAU1.TRA0.TR0.TRACE_TRCTRL_CONFIG | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:27 | TP.TCPAU1.TRA0.TR0.CTRL.SCOMABLE_0.TRCTRL_CONFIG_Q_INST.LATC.L2(0:27) [0000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | RW | STORE_ON_TRIG_MODE: enable store on trigger mode | ||
| 1 | RW | WRITE_ON_RUN_MODE: NOT IMPLEMENTED, use TRACE_TRDATA_CONFIG_9 bit 0 instead: force unconditional write when trace_run | ||
| 2:9 | RW | EXTEND_TRIG_MODE: counter value for extended trigger mode | ||
| 10 | RW | BANK_MODE: enable bank mode | ||
| 11 | RW | ENH_TRACE_MODE: Suppress writing timestamps in store on trigger mode | ||
| 12:13 | RW | LOCAL_CLOCK_GATE_CONTROL: local clock gate control selection: x0 = normal clock gating; x1, = rd_act to trace array turned off | ||
| 14:17 | RW | TRACE_SELECT_CONTROL: selector for 2 sets of external trace bus multiplexers tra_mux0_sel(0:1) and tra_mux1_sel(0:1) | ||
| 18 | RW | TRACE_RUN_HOLD_OFF: hold trace_off when trace_run input is inactive | ||
| 19 | ROX | TRACE_RUN_STATUS: Actual current ORed status of trace_run inputs (trace_run from debug macro and unit logic) | ||
| 20 | RWX | TRACE_RUN_STICKY: trace_run sticky bit, set by trace_run, reset by write to trace_control_reg | ||
| 21 | RW | DISABLE_BANK_EDGE_DETECT: disable trace bank edge detect mode | ||
| 22 | RW | DISABLE_SCOM_TRCTRL_TRARR_RD_ACT: disable constant rd_act | ||
| 23 | RW | MASTER_CLOCK_ENABLE_INT: master clock enable switch | ||
| 24:27 | RW | TRACE_CONTROL_UNUSED: unused | ||
| trdata configuration register 0 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010403 (SCOM) | |||
| Name: | TP.TCPAU1.TRA0.TR0.TRACE_TRDATA_CONFIG_0 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | TP.TCPAU1.TRA0.TR0.DATA.SCOMABLE_CMP_MSK.CMP_MSK_INITONE_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:63 | RW | CMP_MSK_LT_B_0_TO_63: Trace data compression mask for trace bus bits 0 to 63. '1' means record an entry when this bit changes, '0' means ignore this bit. Setting the mask to all zeros will result in no trace entries being recorded just from bit changes. | ||
| trdata configuration register 1 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010404 (SCOM) | |||
| Name: | TP.TCPAU1.TRA0.TR0.TRACE_TRDATA_CONFIG_1 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:23 | TP.TCPAU1.TRA0.TR0.DATA.SCOMABLE_CMP_MSK.CMP_MSK_INITONE_Q_0_INST.LATC.L2(64:87) [000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:23 | RW | CMP_MSK_LT_B_64_TO_87: Trace data compression mask for bits 64 to 87. See TRACE_TRDATA_CONFIG_0 for meaning of bits. | ||
| trdata configuration register 2 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010405 (SCOM) | |||
| Name: | TP.TCPAU1.TRA0.TR0.TRACE_TRDATA_CONFIG_2 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:23 | TP.TCPAU1.TRA0.TR0.DATA.PATTERN_MISR.PATA_Q_INST.LATC.L2(0:23) [000000000000000000000000] | |||
| 24:47 | TP.TCPAU1.TRA0.TR0.DATA.PATTERN_MISR.PATB_Q_INST.LATC.L2(0:23) [000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:23 | RW | PATTERNA: pattern_match_pata_0_to_23: pattern A for trace data compare function | ||
| 24:47 | RW | PATTERNB: pattern_match_patb_0_to_23: pattern B for trace data compare function | ||
| trdata configuration register 3 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010406 (SCOM) | |||
| Name: | TP.TCPAU1.TRA0.TR0.TRACE_TRDATA_CONFIG_3 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:23 | TP.TCPAU1.TRA0.TR0.DATA.PATTERN_MISR.PATC_Q_INST.LATC.L2(0:23) [000000000000000000000000] | |||
| 24:47 | TP.TCPAU1.TRA0.TR0.DATA.PATTERN_MISR.PATD_Q_INST.LATC.L2(0:23) [000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:23 | RW | PATTERNC: pattern_match_patc_0_to_23: pattern C for trace data compare function | ||
| 24:47 | RW | PATTERND: pattern_match_patd_0_to_23: pattern D for trace data compare function | ||
| trdata configuration register 4 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010407 (SCOM) | |||
| Name: | TP.TCPAU1.TRA0.TR0.TRACE_TRDATA_CONFIG_4 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:23 | TP.TCPAU1.TRA0.TR0.DATA.PATTERN_MISR.MSKA_Q_INST.LATC.L2(0:23) [000000000000000000000000] | |||
| 24:47 | TP.TCPAU1.TRA0.TR0.DATA.PATTERN_MISR.MSKB_Q_INST.LATC.L2(0:23) [000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:23 | RW | MASKA: mska: mask bits for pattern A trace data compare function: set to 1 to mask off individual bits | ||
| 24:47 | RW | MASKB: mskb: mask bits for pattern B trace data compare function: set to 1 to mask off individual bits | ||
| trdata configuration register 5 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010408 (SCOM) | |||
| Name: | TP.TCPAU1.TRA0.TR0.TRACE_TRDATA_CONFIG_5 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:23 | TP.TCPAU1.TRA0.TR0.DATA.PATTERN_MISR.MSKC_Q_INST.LATC.L2(0:23) [000000000000000000000000] | |||
| 24:47 | TP.TCPAU1.TRA0.TR0.DATA.PATTERN_MISR.MSKD_Q_INST.LATC.L2(0:23) [000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:23 | RW | MASKC: mskc | ||
| 24:47 | RW | MASKD: mskd | ||
| trdata configuration register 9 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010409 (SCOM) | |||
| Name: | TP.TCPAU1.TRA0.TR0.TRACE_TRDATA_CONFIG_9 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:37 | TP.TCPAU1.TRA0.TR0.DATA.SCOMABLE_CTRL.TRDATA_SCOM_CTRL_Q_0_INST.LATC.L2(0:37) [00000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | RW | DISABLE_COMPRESSION: Disable Trace Data Compression (store data every cycle) | ||
| 1 | RW | ERROR_BIT_COMPRESSION_CARE_MASK: Take into account (care about) changes in the Error bit for trace data compression (default = 0) | ||
| 2:3 | RW | MATCHA_MUXSEL: Match PATTERNA against: 0b00 = Trace bus bits (00:23) 0b01 = Trace bus bits (24:47) 0b10 = Trace bus bits (48:71) 0b11 = Trace bus bits (72:87) | 8 zeroes Dial enums: BITS_00_TO_23=>0b00 BITS_24_TO_47=>0b01 BITS_48_TO_71=>0b10 BITS_72_TO_87_Z8=>0b11 | ||
| 4:5 | RW | MATCHB_MUXSEL: Match PATTERNB against: 0b00 = Trace bus bits (00:23) 0b01 = Trace bus bits (24:47) 0b10 = Trace bus bits (48:71) 0b11 = Trace bus bits (72:87) | 8 zeroes Dial enums: BITS_00_TO_23=>0b00 BITS_24_TO_47=>0b01 BITS_48_TO_71=>0b10 BITS_72_TO_87_Z8=>0b11 | ||
| 6:7 | RW | MATCHC_MUXSEL: Match PATTERNC against: 0b00 = Trace bus bits (00:23) 0b01 = Trace bus bits (24:47) 0b10 = Trace bus bits (48:71) 0b11 = Trace bus bits (72:87) | 8 zeroes Dial enums: BITS_00_TO_23=>0b00 BITS_24_TO_47=>0b01 BITS_48_TO_71=>0b10 BITS_72_TO_87_Z8=>0b11 | ||
| 8:9 | RW | MATCHD_MUXSEL: Match PATTERND against: 0b00 = Trace bus bits (00:23) 0b01 = Trace bus bits (24:47) 0b10 = Trace bus bits (48:71) 0b11 = Trace bus bits (72:87) | 8 zeroes Dial enums: BITS_00_TO_23=>0b00 BITS_24_TO_47=>0b01 BITS_48_TO_71=>0b10 BITS_72_TO_87_Z8=>0b11 | ||
| 10:13 | RW | TRIG0_OR_MASK: NOTE: the OR of all selected MATCHes is ORd with result of TRIG0_AND 0b1XXX selects MATCHA OR 0bX1XX selects MATCHB OR 0bXX1X selects MATCHC OR 0bXXX1 selects MATCHD OR 0b0000 selects to not OR any MATCHes | ||
| 14:17 | RW | TRIG0_AND_MASK: NOTE: the AND of following selected MATCHes is ORd with result of TRIG0_OR 0b1XXX selects MATCHA AND 0bX1XX selects MATCHB AND 0bXX1X selects MATCHC AND 0bXXX1 selects MATCHD AND 0b0000 selects to not AND any MATCHes together to form TRIG0 | ||
| 18:21 | RW | TRIG1_OR_MASK: NOTE: the OR of all selected MATCHes is ORd with result of TRIG1_AND 0b1XXX selects MATCHA OR 0bX1XX selects MATCHB OR 0bXX1X selects MATCHC OR 0bXXX1 selects MATCHD OR 0b0000 selects to not OR any MATCHes to form TRIG1 | ||
| 22:25 | RW | TRIG1_AND_MASK: NOTE: the AND of following selected MATCHes is ORd with result of TRIG1_OR 0b1XXX selects MATCHA AND 0bX1XX selects MATCHB AND 0bXX1X selects MATCHC AND 0bXXX1 selects MATCHD AND 0b0000 selects to not AND any MATCHes together to form TRIG1 | ||
| 26 | RW | TRIG0_NOT_MODE: Invert TRIG0 before using it | ||
| 27 | RW | TRIG1_NOT_MODE: Invert TRIG1 before using it | ||
| 28:31 | RW | MATCH_NOT_MODE: Invert the match polarity before using it to form a TRIGger 0b1000 inverts MATCHA 0b0100 inverts MATCHB 0b0010 inverts MATCHC 0b0001 inverts MATCHD | ||
| 32 | RW | ERROR_CMP_MASK: 0 to compare the trace error bit, 1 to ignore it and always match. No, we don't think this makes sense either. | ||
| 33 | RW | ERROR_CMP_PATTERN: Value to compare trace error against | ||
| 34 | RW | TRIG0_ERR_CMP: Include (via OR) error comparison result into trig0 | ||
| 35 | RW | TRIG1_ERR_CMP: Include (via OR) error comparison result into trig1 | ||
| 36 | RW | DD1_STRETCH_TRIGGER_PULSES: (DD1 workaround) Stretch trigger output pulses to two clocks. Must be enabled for MCFAST and L2FAST traces. | ||
| 37 | RW | spare_lt | ||
| Trace Array High Data Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010440 (SCOM) | |||
| Name: | TP.TCPAU1.TRA0.TR1.TRACE_HI_DATA_REG | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | TP.TCPAU1.TRA0.TR1.SAMP.TRACE_DATA_LT_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:63 | ROX | TRACE_HI_DATA: Trace Array Data 0:63 | ||
| Trace Array Low Data Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010441 (SCOM) | |||
| Name: | TP.TCPAU1.TRA0.TR1.TRACE_LO_DATA_REG | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:31 | TP.TCPAU1.TRA0.TR1.SAMP.TRACE_DATA_LT_INST.LATC.L2(64:95) [00000000000000000000000000000000] | |||
| 32:41 | TP.TCPAU1.TRA0.TR1.SAMP.TR_ADDRESS_LT_INST.LATC.L2(0:9) [0000000000] | |||
| 42:50 | TP.TCPAU1.TRA0.TR1.SAMP.TR_LAST_BANK_LT_INST.LATC.L2(0:8) [000000000] | |||
| 51 | TP.TCPAU1.TRA0.TR1.SAMP.TR_LAST_BANK_VALID_LT_INST.LATC.L2(0) [0] | |||
| 52 | TP.TCPAU1.TRA0.TR1.SAMP.TR_WRITE_ON_RUN_LT_INST.LATC.L2(0) [0] | |||
| 53 | TP.TCPAU1.TRA0.TR1.SAMP.TR_RUN_LT_INST.LATC.L2(0) [0] | |||
| 54:63 | TP.TCPAU1.TRA0.TR1.SAMP.TR_HOLD_ADDRESS_LT_INST.LATC.L2(0:9) [0000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:31 | ROX | TRACE_LO_DATA: Trace Array Data 64:95 | ||
| 32:41 | ROX | TRACE_ADDRESS: Trace Address | ||
| 42:50 | ROX | TRACE_LAST_BANK: Trace Last Bank | ||
| 51 | ROX | TRACE_LAST_BANK_VALID: Trace Last Bank Valid | ||
| 52 | ROX | TRACE_WRITE_ON_RUN: Trace Write-On-Run indicator | ||
| 53 | ROX | TRACE_RUNNING: Trace Run indicator | ||
| 54:63 | ROX | TRACE_HOLD_ADDRESS: Trace Hold Address (pointing to last entry) | ||
| trace control configuration register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010442 (SCOM) | |||
| Name: | TP.TCPAU1.TRA0.TR1.TRACE_TRCTRL_CONFIG | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:27 | TP.TCPAU1.TRA0.TR1.CTRL.SCOMABLE_0.TRCTRL_CONFIG_Q_INST.LATC.L2(0:27) [0000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | RW | STORE_ON_TRIG_MODE: enable store on trigger mode | ||
| 1 | RW | WRITE_ON_RUN_MODE: NOT IMPLEMENTED, use TRACE_TRDATA_CONFIG_9 bit 0 instead: force unconditional write when trace_run | ||
| 2:9 | RW | EXTEND_TRIG_MODE: counter value for extended trigger mode | ||
| 10 | RW | BANK_MODE: enable bank mode | ||
| 11 | RW | ENH_TRACE_MODE: Suppress writing timestamps in store on trigger mode | ||
| 12:13 | RW | LOCAL_CLOCK_GATE_CONTROL: local clock gate control selection: x0 = normal clock gating; x1, = rd_act to trace array turned off | ||
| 14:17 | RW | TRACE_SELECT_CONTROL: selector for 2 sets of external trace bus multiplexers tra_mux0_sel(0:1) and tra_mux1_sel(0:1) | ||
| 18 | RW | TRACE_RUN_HOLD_OFF: hold trace_off when trace_run input is inactive | ||
| 19 | ROX | TRACE_RUN_STATUS: Actual current ORed status of trace_run inputs (trace_run from debug macro and unit logic) | ||
| 20 | RWX | TRACE_RUN_STICKY: trace_run sticky bit, set by trace_run, reset by write to trace_control_reg | ||
| 21 | RW | DISABLE_BANK_EDGE_DETECT: disable trace bank edge detect mode | ||
| 22 | RW | DISABLE_SCOM_TRCTRL_TRARR_RD_ACT: disable constant rd_act | ||
| 23 | RW | MASTER_CLOCK_ENABLE_INT: master clock enable switch | ||
| 24:27 | RW | TRACE_CONTROL_UNUSED: unused | ||
| trdata configuration register 0 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010443 (SCOM) | |||
| Name: | TP.TCPAU1.TRA0.TR1.TRACE_TRDATA_CONFIG_0 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | TP.TCPAU1.TRA0.TR1.DATA.SCOMABLE_CMP_MSK.CMP_MSK_INITONE_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:63 | RW | CMP_MSK_LT_B_0_TO_63: Trace data compression mask for trace bus bits 0 to 63. '1' means record an entry when this bit changes, '0' means ignore this bit. Setting the mask to all zeros will result in no trace entries being recorded just from bit changes. | ||
| trdata configuration register 1 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010444 (SCOM) | |||
| Name: | TP.TCPAU1.TRA0.TR1.TRACE_TRDATA_CONFIG_1 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:23 | TP.TCPAU1.TRA0.TR1.DATA.SCOMABLE_CMP_MSK.CMP_MSK_INITONE_Q_0_INST.LATC.L2(64:87) [000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:23 | RW | CMP_MSK_LT_B_64_TO_87: Trace data compression mask for bits 64 to 87. See TRACE_TRDATA_CONFIG_0 for meaning of bits. | ||
| trdata configuration register 2 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010445 (SCOM) | |||
| Name: | TP.TCPAU1.TRA0.TR1.TRACE_TRDATA_CONFIG_2 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:23 | TP.TCPAU1.TRA0.TR1.DATA.PATTERN_MISR.PATA_Q_INST.LATC.L2(0:23) [000000000000000000000000] | |||
| 24:47 | TP.TCPAU1.TRA0.TR1.DATA.PATTERN_MISR.PATB_Q_INST.LATC.L2(0:23) [000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:23 | RW | PATTERNA: pattern_match_pata_0_to_23: pattern A for trace data compare function | ||
| 24:47 | RW | PATTERNB: pattern_match_patb_0_to_23: pattern B for trace data compare function | ||
| trdata configuration register 3 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010446 (SCOM) | |||
| Name: | TP.TCPAU1.TRA0.TR1.TRACE_TRDATA_CONFIG_3 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:23 | TP.TCPAU1.TRA0.TR1.DATA.PATTERN_MISR.PATC_Q_INST.LATC.L2(0:23) [000000000000000000000000] | |||
| 24:47 | TP.TCPAU1.TRA0.TR1.DATA.PATTERN_MISR.PATD_Q_INST.LATC.L2(0:23) [000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:23 | RW | PATTERNC: pattern_match_patc_0_to_23: pattern C for trace data compare function | ||
| 24:47 | RW | PATTERND: pattern_match_patd_0_to_23: pattern D for trace data compare function | ||
| trdata configuration register 4 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010447 (SCOM) | |||
| Name: | TP.TCPAU1.TRA0.TR1.TRACE_TRDATA_CONFIG_4 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:23 | TP.TCPAU1.TRA0.TR1.DATA.PATTERN_MISR.MSKA_Q_INST.LATC.L2(0:23) [000000000000000000000000] | |||
| 24:47 | TP.TCPAU1.TRA0.TR1.DATA.PATTERN_MISR.MSKB_Q_INST.LATC.L2(0:23) [000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:23 | RW | MASKA: mska: mask bits for pattern A trace data compare function: set to 1 to mask off individual bits | ||
| 24:47 | RW | MASKB: mskb: mask bits for pattern B trace data compare function: set to 1 to mask off individual bits | ||
| trdata configuration register 5 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010448 (SCOM) | |||
| Name: | TP.TCPAU1.TRA0.TR1.TRACE_TRDATA_CONFIG_5 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:23 | TP.TCPAU1.TRA0.TR1.DATA.PATTERN_MISR.MSKC_Q_INST.LATC.L2(0:23) [000000000000000000000000] | |||
| 24:47 | TP.TCPAU1.TRA0.TR1.DATA.PATTERN_MISR.MSKD_Q_INST.LATC.L2(0:23) [000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:23 | RW | MASKC: mskc | ||
| 24:47 | RW | MASKD: mskd | ||
| trdata configuration register 9 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010449 (SCOM) | |||
| Name: | TP.TCPAU1.TRA0.TR1.TRACE_TRDATA_CONFIG_9 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:37 | TP.TCPAU1.TRA0.TR1.DATA.SCOMABLE_CTRL.TRDATA_SCOM_CTRL_Q_0_INST.LATC.L2(0:37) [00000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | RW | DISABLE_COMPRESSION: Disable Trace Data Compression (store data every cycle) | ||
| 1 | RW | ERROR_BIT_COMPRESSION_CARE_MASK: Take into account (care about) changes in the Error bit for trace data compression (default = 0) | ||
| 2:3 | RW | MATCHA_MUXSEL: Match PATTERNA against: 0b00 = Trace bus bits (00:23) 0b01 = Trace bus bits (24:47) 0b10 = Trace bus bits (48:71) 0b11 = Trace bus bits (72:87) | 8 zeroes Dial enums: BITS_00_TO_23=>0b00 BITS_24_TO_47=>0b01 BITS_48_TO_71=>0b10 BITS_72_TO_87_Z8=>0b11 | ||
| 4:5 | RW | MATCHB_MUXSEL: Match PATTERNB against: 0b00 = Trace bus bits (00:23) 0b01 = Trace bus bits (24:47) 0b10 = Trace bus bits (48:71) 0b11 = Trace bus bits (72:87) | 8 zeroes Dial enums: BITS_00_TO_23=>0b00 BITS_24_TO_47=>0b01 BITS_48_TO_71=>0b10 BITS_72_TO_87_Z8=>0b11 | ||
| 6:7 | RW | MATCHC_MUXSEL: Match PATTERNC against: 0b00 = Trace bus bits (00:23) 0b01 = Trace bus bits (24:47) 0b10 = Trace bus bits (48:71) 0b11 = Trace bus bits (72:87) | 8 zeroes Dial enums: BITS_00_TO_23=>0b00 BITS_24_TO_47=>0b01 BITS_48_TO_71=>0b10 BITS_72_TO_87_Z8=>0b11 | ||
| 8:9 | RW | MATCHD_MUXSEL: Match PATTERND against: 0b00 = Trace bus bits (00:23) 0b01 = Trace bus bits (24:47) 0b10 = Trace bus bits (48:71) 0b11 = Trace bus bits (72:87) | 8 zeroes Dial enums: BITS_00_TO_23=>0b00 BITS_24_TO_47=>0b01 BITS_48_TO_71=>0b10 BITS_72_TO_87_Z8=>0b11 | ||
| 10:13 | RW | TRIG0_OR_MASK: NOTE: the OR of all selected MATCHes is ORd with result of TRIG0_AND 0b1XXX selects MATCHA OR 0bX1XX selects MATCHB OR 0bXX1X selects MATCHC OR 0bXXX1 selects MATCHD OR 0b0000 selects to not OR any MATCHes | ||
| 14:17 | RW | TRIG0_AND_MASK: NOTE: the AND of following selected MATCHes is ORd with result of TRIG0_OR 0b1XXX selects MATCHA AND 0bX1XX selects MATCHB AND 0bXX1X selects MATCHC AND 0bXXX1 selects MATCHD AND 0b0000 selects to not AND any MATCHes together to form TRIG0 | ||
| 18:21 | RW | TRIG1_OR_MASK: NOTE: the OR of all selected MATCHes is ORd with result of TRIG1_AND 0b1XXX selects MATCHA OR 0bX1XX selects MATCHB OR 0bXX1X selects MATCHC OR 0bXXX1 selects MATCHD OR 0b0000 selects to not OR any MATCHes to form TRIG1 | ||
| 22:25 | RW | TRIG1_AND_MASK: NOTE: the AND of following selected MATCHes is ORd with result of TRIG1_OR 0b1XXX selects MATCHA AND 0bX1XX selects MATCHB AND 0bXX1X selects MATCHC AND 0bXXX1 selects MATCHD AND 0b0000 selects to not AND any MATCHes together to form TRIG1 | ||
| 26 | RW | TRIG0_NOT_MODE: Invert TRIG0 before using it | ||
| 27 | RW | TRIG1_NOT_MODE: Invert TRIG1 before using it | ||
| 28:31 | RW | MATCH_NOT_MODE: Invert the match polarity before using it to form a TRIGger 0b1000 inverts MATCHA 0b0100 inverts MATCHB 0b0010 inverts MATCHC 0b0001 inverts MATCHD | ||
| 32 | RW | ERROR_CMP_MASK: 0 to compare the trace error bit, 1 to ignore it and always match. No, we don't think this makes sense either. | ||
| 33 | RW | ERROR_CMP_PATTERN: Value to compare trace error against | ||
| 34 | RW | TRIG0_ERR_CMP: Include (via OR) error comparison result into trig0 | ||
| 35 | RW | TRIG1_ERR_CMP: Include (via OR) error comparison result into trig1 | ||
| 36 | RW | DD1_STRETCH_TRIGGER_PULSES: (DD1 workaround) Stretch trigger output pulses to two clocks. Must be enabled for MCFAST and L2FAST traces. | ||
| 37 | RW | spare_lt | ||
| Debug macro configuration register 0 for config component | ||||
|---|---|---|---|---|
| Addr: |
00000000110107C0 (SCOM) | |||
| Name: | TP.TCPAU1.EPS.DBG.DBG_MODE_REG | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0 | TP.TCPAU1.EPS.DBG.CONFIG.DBG_LAT_REQ#0.LAT.DBG_REG_MODE.LATC.L2(0) [0] | |||
| 1 | TP.TCPAU1.EPS.DBG.CONFIG.DBG_LAT_REQ#1.LAT.DBG_REG_MODE.LATC.L2(0) [0] | |||
| 2 | TP.TCPAU1.EPS.DBG.CONFIG.DBG_LAT_REQ#2.LAT.DBG_REG_MODE.LATC.L2(0) [0] | |||
| 3 | TP.TCPAU1.EPS.DBG.CONFIG.DBG_LAT_REQ#3.LAT.DBG_REG_MODE.LATC.L2(0) [0] | |||
| 4 | TP.TCPAU1.EPS.DBG.CONFIG.DBG_LAT_REQ#4.LAT.DBG_REG_MODE.LATC.L2(0) [0] | |||
| 5 | TP.TCPAU1.EPS.DBG.CONFIG.DBG_LAT_REQ#5.LAT.DBG_REG_MODE.LATC.L2(0) [0] | |||
| 6 | TP.TCPAU1.EPS.DBG.CONFIG.DBG_LAT_REQ#6.LAT.DBG_REG_MODE.LATC.L2(0) [0] | |||
| 7 | TP.TCPAU1.EPS.DBG.CONFIG.DBG_LAT_REQ#7.LAT.DBG_REG_MODE.LATC.L2(0) [0] | |||
| 8 | TP.TCPAU1.EPS.DBG.CONFIG.DBG_LAT_REQ#8.LAT.DBG_REG_MODE.LATC.L2(0) [0] | |||
| 9 | TP.TCPAU1.EPS.DBG.CONFIG.DBG_LAT_REQ#9.LAT.DBG_REG_MODE.LATC.L2(0) [0] | |||
| 10 | TP.TCPAU1.EPS.DBG.CONFIG.DBG_LAT_REQ#10.LAT.DBG_REG_MODE.LATC.L2(0) [0] | |||
| 11 | TP.TCPAU1.EPS.DBG.CONFIG.DBG_LAT_REQ#11.LAT.DBG_REG_MODE.LATC.L2(0) [0] | |||
| 12 | TP.TCPAU1.EPS.DBG.CONFIG.DBG_LAT_REQ#12.LAT.DBG_REG_MODE.LATC.L2(0) [0] | |||
| 13 | TP.TCPAU1.EPS.DBG.CONFIG.DBG_LAT_REQ#13.LAT.DBG_REG_MODE.LATC.L2(0) [0] | |||
| 16 | TP.TCPAU1.EPS.DBG.DBG_PSC_SM_STATUS_INT(0) [0] | |||
| 17:18 | TP.TCPAU1.EPS.DBG.BKEND.TRACE_STATE_LAT_INST.LATC.L2(0:1) [00] | |||
| 19 | TP.TCPAU1.EPS.DBG.BKEND.TRACE_FREEZE_LT_INST.LATC.L2(0) [0] | |||
| 20:31 | TP.TCPAU1.EPS.DBG.BKEND.CONDITION_HISTORY_Q_INST.LATC.L2(0:11) [000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:2 | RW | GLB_BRCST_MODE: global_broadcast_mode (0 to 2): 100: dbg_trace_run & dbg_trace_freeze 101: pc_tcdbg_trace_run_fncd & dbg_trace_freeze 110: dbg_triggers_out(0 to 1) 111: pc_tcdbg_triggers(0 to 1) (from core) glb_brcst_mode | ||
| 3:5 | RW | TRACE_SEL_MODE: Select source for trace_run and bank 001: core trace run & bank 010: tp broadcast run & 0 011: tc_dbg_inter_brcst latched else: dbg_trace_run & dbg_trace_bank trace_sel_mode | ||
| 6:7 | RW | TRIG_SEL_MODE: Select source for tcdbg_trigger(0) 10: global broadcast 11: pc_tcdbg_trigger (from core) else: dbg_triggers_out(0:1) trig_sel_mode | ||
| 8 | RW | STOP_ON_XSTOP_SELECTION: enable trace stop on checkstop stop_on_xstop_selection | ||
| 9 | RW | STOP_ON_RECOV_ERR_SELECTION: enabel trace stop on recoverable error stop_on_recov_err_selection | ||
| 10 | RW | STOP_ON_SPATTN_SELECTION: enable trace stop on special attention stop_on_spattn_selection | ||
| 11 | RW | STOP_ON_HOSTATTN_SELECTION: enable trace stop on host attention stop_on_hostattn_selection | ||
| 12 | RW | FREEZE_SEL_MODE: select freeze source: 0: local debug freeze 1: via broadcast: tp_tcdbg_glb_brcst(1) master_clock_enable | ||
| 13 | RW | MASTER_CLOCK_ENABLE: master_clock_enable for debug macro | ||
| 14:15 | RO | constant=0b00 | ||
| 16 | ROX | trace_run_on trace_run_status | ||
| 17:18 | ROX | TRACE_RUN_STATUS: 00 is stopped, 01 is run, 10 is run-n, 11 is wait-n stopped_00_running_01_runn_10_waitn_11_status | ||
| 19 | ROX | IS_FROZEN_STATUS: 1 is frozen (needs reset) is_frozen_status | ||
| 20:22 | ROX | INST1_CONDITION_HISTORY_STATUS: Shows which condition was triggered, 1xx is condition1, x1x is condition2 or 3, xx1 is condition2 timeout Shows last condition triggered before last trace_run activated (accumulate_history = 0) or accumulated conditions (accumulate_history = 1) inst1_condition_history_status | ||
| 23:25 | ROX | INST2_CONDITION_HISTORY_STATUS: Shows which condition was triggered, 1xx is condition1, x1x is condition2 or 3, xx1 is condition2 timeout Shows last condition triggered before last trace_run activated (accumulate_history = 0) or accumulated conditions (accumulate_history = 1) inst2_condition_history_status | ||
| 26:31 | ROX | unused unused | ||
| 32:63 | RO | constant=0b00000000000000000000000000000000 | ||
| Debug macro configuration register 1 for front end 1 componet | ||||
|---|---|---|---|---|
| Addr: |
00000000110107C1 (SCOM) | |||
| Name: | TP.TCPAU1.EPS.DBG.DBG_INST1_COND_REG_1 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#0.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 1 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#1.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 2 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#2.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 3 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#3.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 4 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#4.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 5 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#5.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 6 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#6.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 7 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#7.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 8 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#8.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 9 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#9.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 10 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#10.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 11 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#11.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 12 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#12.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 13 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#13.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 14 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#14.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 15 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#15.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 16 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#16.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 17 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#17.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 18 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#18.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 19 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#19.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 20 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#20.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 21 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#21.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 22 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#22.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 23 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#23.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 24 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#24.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 25 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#25.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 26 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#26.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 27 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#27.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 28 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#28.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 29 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#29.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 30 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#30.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 31 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#31.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 32 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#32.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 33 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#33.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 34 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#34.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 35 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#35.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 36 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#36.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 37 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#37.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 38 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#38.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 39 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#39.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 40 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#40.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 41 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#41.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 42 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#42.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 43 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#43.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 44 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#44.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 45 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#45.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 46 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#46.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 47 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#47.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 48 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#48.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 49 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#49.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 50 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#50.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 51 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#51.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 52 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#52.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 53 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#53.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 54 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#54.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 55 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#55.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 56 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#56.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 57 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#57.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 58 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#58.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 59 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#59.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 60 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#60.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 61 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#61.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 62 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#62.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:7 | RW | INST1_COND1_SEL_A: Multiplexer for cond1_trig_in(0) 000 select constant 0 001 select constant 1 -- CONDITION FEEDBACK -- 002 select inst1_dbg_cond1 003 select inst1_dbg_cond2 004 select inst1_dbg_cond3 005 select inst1_dbg_cond2timeout 006 select inst2_dbg_cond1 007 select inst2_dbg_cond2 008 select inst2_dbg_cond3 009 select inst2_dbg_cond2timeout 010 select inst3_dbg_cond1 � unused, tied down 011 select inst3_dbg_cond2 � unused, tied down 012 select inst3_dbg_cond3 � unused, tied down 013 select inst3_dbg_cond2timeout � unused, tied down 014 select inst4_dbg_cond1 � unused, tied down 015 select inst4_dbg_cond2 � unused, tied down 016 select inst4_dbg_cond3 � unused, tied down 017 select inst4_dbg_cond2timeout � unused, tied down 018 select inst1_dbg_trig_sp 019 select inst2_dbg_trig_sp 020 select inst3_dbg_trig_sp � unused, tied down 021 select inst4_dbg_trig_sp � unused, tied down 022 select tctrc_tcdbg_trigger_a(0) 023 select tctrc_tcdbg_trigger_b(0) 024 select tctrc_tcdbg_trigger_a(0) and tctrc_tcdbg_trigger_b(0) 025 select tctrc_tcdbg_trigger_a(1) 026 select tctrc_tcdbg_trigger_b(1) 027 select tctrc_tcdbg_trigger_a(1) and tctrc_tcdbg_trigger_b(1) 028 select tctrc_tcdbg_trigger_a(2) 029 select tctrc_tcdbg_trigger_b(2) 030 select tctrc_tcdbg_trigger_a(2) and tctrc_tcdbg_trigger_b(2) 031 select tctrc_tcdbg_trigger_a(3) 032 select tctrc_tcdbg_trigger_b(3) 033 select tctrc_tcdbg_trigger_a(3) and tctrc_tcdbg_trigger_b(3) 034 select tctrc_tcdbg_trigger_a(4) 035 select tctrc_tcdbg_trigger_b(4) 036 select tctrc_tcdbg_trigger_a(4) and tctrc_tcdbg_trigger_b(4) 037 select tctrc_tcdbg_trigger_a(5) 038 select tctrc_tcdbg_trigger_b(5) 039 select tctrc_tcdbg_trigger_a(5) and tctrc_tcdbg_trigger_b(5) 040 select tctrc_tcdbg_trigger_a(6) 041 select tctrc_tcdbg_trigger_b(6) 042 select tctrc_tcdbg_trigger_a(6) and tctrc_tcdbg_trigger_b(6) 043 select tctrc_tcdbg_trigger_a(7) 044 select tctrc_tcdbg_trigger_b(7) 045 select tctrc_tcdbg_trigger_a(7) and tctrc_tcdbg_trigger_b(7) 046 select tctrc_tcdbg_trigger_a(8) 047 select tctrc_tcdbg_trigger_b(8) 048 select tctrc_tcdbg_trigger_a(8) and tctrc_tcdbg_trigger_b(8) 049 select tctrc_tcdbg_trigger_a(9) 050 select tctrc_tcdbg_trigger_b(9) 051 select tctrc_tcdbg_trigger_a(9) and tctrc_tcdbg_trigger_b(9) 052 select tctrc_tcdbg_trigger_a(10) 053 select tctrc_tcdbg_trigger_b(10) 054 select tctrc_tcdbg_trigger_a(10) and tctrc_tcdbg_trigger_b(10) 055 select tctrc_tcdbg_trigger_a(11) 056 select tctrc_tcdbg_trigger_b(11) 057 select tctrc_tcdbg_trigger_a(11) and tctrc_tcdbg_trigger_b(11) 058 select tctrc_tcdbg_trigger_a(12) 059 select tctrc_tcdbg_trigger_b(12) 060 select tctrc_tcdbg_trigger_a(12) and tctrc_tcdbg_trigger_b(12) 061 select tctrc_tcdbg_trigger_a(13) 062 select tctrc_tcdbg_trigger_b(13) 063 select tctrc_tcdbg_trigger_a(13) and tctrc_tcdbg_trigger_b(13) 064 select tctrc_tcdbg_trigger_a(14) 065 select tctrc_tcdbg_trigger_b(14) 066 select tctrc_tcdbg_trigger_a(14) and tctrc_tcdbg_trigger_b(14) -- LOGIC (UNIT) TRIGGERS -- EP: 0:3 L3C0, 4:7 L3C1, 8:9 GX, 10 TP (hang), 11 spare, 12:13 MCA, 14:15 spare ES: 0:4 L4C, 5:6 L4F, 7:8 TPTOD, 9 TP (hang), 10:15 spare 067 select logic_trigger_in(0) 068 select logic_trigger_in(1) 069 select logic_trigger_in(2) 070 select logic_trigger_in(3) 071 select logic_trigger_in(4) 072 select logic_trigger_in(5) 073 select logic_trigger_in(6) 074 select logic_trigger_in(7) 075 select logic_trigger_in(8) 076 select logic_trigger_in(9) 077 select logic_trigger_in(10) 078 select logic_trigger_in(11) 079 select logic_trigger_in(12) 080 select logic_trigger_in(13) 081 select logic_trigger_in(14) 082 select logic_trigger_in(15) 083 select pc_tcdbg_trigger(0) 084 select pc_tcdbg_trigger(1) 085 select tctrc_tcdbg_glb_brcst(0) 086 select tctrc_tcdbg_glb_brcst(1) 087 select xstop_err 088 select recov_err 089 select spattn 090 select hostattn 091 select fir_dbg_local_xstop_err 092 select tc_dbg_inter_brcst(0) 093 select tc_dbg_inter_brcst(1) -- CORE TRIGGERS (EP chip only) -- Note: set core_slave_mode to honor ec[0:5]_tc_trace_run 094 select core trigger 0: any rising edge of ec[0:5]_tc_trace_run(0) 095 select core trigger 1: any rising edge of ec[0:5]_tc_trace_run(1) 096 select core trigger 2: any falling edge of ec[0:5]_tc_trace_run(0) 097 select core trigger 3: any falling edge of ec[0:5]_tc_trace_run(1) 098 select glb_trig_or_trace_in(0) 099 select glb_trig_or_trace_in(1) 100 select core_local_brcst_trc(0) 101 select core_local_brcst_trc(1) 102 select glb_freeze_brcst_rec(0) 103 select trig_2_extern_in(0) 104 select trig_2_extern_in(1) 105 select dbg_triggers_out(2) 106 select dbg_triggers_out(3) 107 select dbg_triggers_out(4) 108 select dbg_triggers_out(5) 109 select dbg_triggers_out(6) 100 select tcdbg_trigger_in(0) 111 select tcdbg_trigger_in(1) | ||
| 8:15 | RW | INST1_COND1_SEL_B: Multiplexer for cond1_trig_in(1) Selection as cond1_trig_in(0) | ||
| 16:23 | RW | INST1_COND2_SEL_A: Multiplexer for cond2_trig_in(0) Selection as cond1_trig_in(0) | ||
| 24:31 | RW | INST1_COND2_SEL_B: Multiplexer for cond2_trig_in(1) Selection as cond1_trig_in(0) | ||
| 32 | RW | INST1_C1_INAROW_MODE: front end instance 1 c1_inarow_mode | ||
| 33 | RW | INST1_AND_TRIGGER_MODE1: front end instance 1 and trigger mode condition1 | ||
| 34 | RW | INST1_NOT_TRIGGER_MODE1: front end instance 1 inverted trigger mode condition1 | ||
| 35 | RW | INST1_EDGE_TRIGGER_MODE1: front end instance 1 edge trigger mode condition1 | ||
| 36:38 | RWX | INST1_UNUSED_1: UNUSED | ||
| 39 | RW | INST1_C2_INAROW_MODE: front end instance 1 Counter 2 in-a-rwo mode | ||
| 40 | RW | INST1_AND_TRIGGER_MODE2: front end instance 1 and trigger mode2 | ||
| 41 | RW | INST1_NOT_TRIGGER_MODE2: front end instance 1 inverted (not) trigger | ||
| 42 | RW | INST1_EDGE_TRIGGER_MODE2: front end instance 1edge trigger | ||
| 43:45 | RWX | INST1_UNUSED_2: UNUSED | ||
| 46 | RW | INST1_COND3_ENABLE_RESET: front end instance 1 condition3 enable | ||
| 47 | RW | INST1_EXACT_TO_MODE: front end instance 1 exact timeout mode | ||
| 48 | RW | INST1_RESET_C2TIMER_ON_C1: front end instance 1 reset condition2 timer on condition1 | ||
| 49 | RW | INST1_RESET_C3_ON_C0: front end instance 1 reset condition3 on condition0 | ||
| 50 | RW | INST1_SLOW_TO_MODE: front end instance 1 slow timeout mode | ||
| 51 | RW | INST1_EXACT_RESET_C3_ON_TO: front end instance 1 exact reset condition3 on timeout | ||
| 52:55 | RW | INST1_C1_COUNT_LT: inst1 condition1 counter compare value | ||
| 56:59 | RW | INST1_C2_COUNT_LT: inst1 condition2 counter compare value | ||
| 60:62 | RW | INST1_RESET_C3_SELECT: front end instance 1: reset condition3 for reset_c3_on_c0 0b100: dbg_cross_couple_triggers(4) 0b101: dbg_cross_couple_triggers(12) 0b110: dbg_cross_couple_triggers(20) 0b111: dbg_cross_couple_triggers(28) | ||
| Debug macro configuration register 2 for fronte end 1 component | ||||
|---|---|---|---|---|
| Addr: |
00000000110107C2 (SCOM) | |||
| Name: | TP.TCPAU1.EPS.DBG.DBG_INST1_COND_REG_2 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#64.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 1 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#65.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 2 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#66.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 3 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#67.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 4 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#68.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 5 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#69.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 6 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#70.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 7 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#71.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 8 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#72.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 9 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#73.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 10 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#74.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 11 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#75.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 12 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#76.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 13 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#77.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 14 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#78.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 15 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#79.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 16 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#80.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 17 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#81.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 18 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#82.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 19 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#83.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 20 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#84.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 21 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#85.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 22 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#86.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 23 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#87.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 24 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#88.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 25 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#89.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 26 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#90.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 27 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#91.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 28 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#92.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 29 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#93.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 30 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#94.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 31 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#95.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 32 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#96.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 33 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#97.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 34 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#98.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 35 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#99.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 36 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#100.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 37 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#101.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 38 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#102.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 39 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#103.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 40 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#104.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 41 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#105.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 42 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#106.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 43 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#107.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:4 | RW | INST1_CROSS_COUPLE_SELECT_1_A: Cross coupling is the same of all selectors: 00000 - selects inst1_cond1_trig_a 00001 - selects inst1_cond1_trig_b 00010 - selects inst1_cond2_trig_a 00011 - selects inst1_cond2_trig_b 00100 - selects inst1_condition1 00101 - selects inst1_condition2 00110 - selects inst1_condition3 00111 - selects inst1_cond2_timeout 01000 - selects inst2_cond1_trig_a 01001 - selects inst2_cond1_trig_b 01010 - selects inst2_cond2_trig_a 01011 - selects inst2_cond2_trig_b 01100 - selects inst2_condition1 01101 - selects inst2_condition2 01110 - selects inst2_condition3 01111 - selects inst2_cond2_timeout 10000 - selects inst3_cond1_trig_a 10001 - selects inst3_cond1_trig_b 10010 - selects inst3_cond2_trig_a 10011 - selects inst3_cond2_trig_b 10100 - selects inst3_condition1 10101 - selects inst3_condition2 10110 - selects inst3_condition3 10111 - selects inst3_cond2_timeout 11000 - selects inst4_cond1_trig_a 11001 - selects inst4_cond1_trig_b 11010 - selects inst4_cond2_trig_a 11011 - selects inst4_cond2_trig_b 11100 - selects inst4_condition1 11101 - selects inst4_condition2 11110 - selects inst4_condition3 11111 - selects inst4_cond2_timeout | ||
| 5:9 | RW | INST1_CROSS_COUPLE_SELECT_1_B: inst1_cross_couple_select_1_b | ||
| 10:14 | RW | INST1_CROSS_COUPLE_SELECT_2_A: inst1_cross_couple_select_2_a | ||
| 15:19 | RW | INST1_CROSS_COUPLE_SELECT_2_B: inst1_cross_couple_select_2_b | ||
| 20:43 | RW | INST1_TO_CMP_LT: compare value for special counter sp_cnt_lt in debug component 1 | ||
| Addr: |
00000000110107C3 (SCOM) | |||
|---|---|---|---|---|
| Name: | TP.TCPAU1.EPS.DBG.DBG_INST1_COND_REG_3 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| Bit(s) | SCOM | Dial: Description | ||
| 0:63 | RO | constant=0b0000000000000000000000000000000000000000000000000000000000000000 | ||
| Debug macro configuration register 1 for front end 1 componet | ||||
|---|---|---|---|---|
| Addr: |
00000000110107C4 (SCOM) | |||
| Name: | TP.TCPAU1.EPS.DBG.DBG_INST2_COND_REG_1 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#0.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 1 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#1.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 2 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#2.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 3 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#3.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 4 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#4.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 5 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#5.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 6 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#6.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 7 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#7.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 8 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#8.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 9 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#9.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 10 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#10.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 11 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#11.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 12 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#12.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 13 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#13.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 14 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#14.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 15 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#15.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 16 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#16.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 17 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#17.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 18 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#18.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 19 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#19.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 20 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#20.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 21 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#21.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 22 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#22.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 23 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#23.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 24 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#24.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 25 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#25.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 26 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#26.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 27 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#27.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 28 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#28.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 29 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#29.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 30 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#30.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 31 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#31.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 32 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#32.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 33 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#33.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 34 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#34.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 35 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#35.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 36 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#36.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 37 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#37.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 38 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#38.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 39 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#39.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 40 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#40.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 41 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#41.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 42 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#42.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 43 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#43.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 44 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#44.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 45 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#45.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 46 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#46.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 47 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#47.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 48 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#48.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 49 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#49.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 50 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#50.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 51 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#51.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 52 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#52.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 53 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#53.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 54 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#54.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 55 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#55.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 56 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#56.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 57 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#57.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 58 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#58.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 59 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#59.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 60 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#60.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 61 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#61.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 62 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#62.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:7 | RW | INST2_COND1_SEL_A: Multiplexer for cond1_trig_in(0) 000 select constant 0 001 select constant 1 -- CONDITION FEEDBACK -- 002 select inst1_dbg_cond1 003 select inst1_dbg_cond2 004 select inst1_dbg_cond3 005 select inst1_dbg_cond2timeout 006 select inst2_dbg_cond1 007 select inst2_dbg_cond2 008 select inst2_dbg_cond3 009 select inst2_dbg_cond2timeout 010 select inst3_dbg_cond1 � unused, tied down 011 select inst3_dbg_cond2 � unused, tied down 012 select inst3_dbg_cond3 � unused, tied down 013 select inst3_dbg_cond2timeout � unused, tied down 014 select inst4_dbg_cond1 � unused, tied down 015 select inst4_dbg_cond2 � unused, tied down 016 select inst4_dbg_cond3 � unused, tied down 017 select inst4_dbg_cond2timeout � unused, tied down 018 select inst1_dbg_trig_sp 019 select inst2_dbg_trig_sp 020 select inst3_dbg_trig_sp � unused, tied down 021 select inst4_dbg_trig_sp � unused, tied down 022 select tctrc_tcdbg_trigger_a(0) 023 select tctrc_tcdbg_trigger_b(0) 024 select tctrc_tcdbg_trigger_a(0) and tctrc_tcdbg_trigger_b(0) 025 select tctrc_tcdbg_trigger_a(1) 026 select tctrc_tcdbg_trigger_b(1) 027 select tctrc_tcdbg_trigger_a(1) and tctrc_tcdbg_trigger_b(1) 028 select tctrc_tcdbg_trigger_a(2) 029 select tctrc_tcdbg_trigger_b(2) 030 select tctrc_tcdbg_trigger_a(2) and tctrc_tcdbg_trigger_b(2) 031 select tctrc_tcdbg_trigger_a(3) 032 select tctrc_tcdbg_trigger_b(3) 033 select tctrc_tcdbg_trigger_a(3) and tctrc_tcdbg_trigger_b(3) 034 select tctrc_tcdbg_trigger_a(4) 035 select tctrc_tcdbg_trigger_b(4) 036 select tctrc_tcdbg_trigger_a(4) and tctrc_tcdbg_trigger_b(4) 037 select tctrc_tcdbg_trigger_a(5) 038 select tctrc_tcdbg_trigger_b(5) 039 select tctrc_tcdbg_trigger_a(5) and tctrc_tcdbg_trigger_b(5) 040 select tctrc_tcdbg_trigger_a(6) 041 select tctrc_tcdbg_trigger_b(6) 042 select tctrc_tcdbg_trigger_a(6) and tctrc_tcdbg_trigger_b(6) 043 select tctrc_tcdbg_trigger_a(7) 044 select tctrc_tcdbg_trigger_b(7) 045 select tctrc_tcdbg_trigger_a(7) and tctrc_tcdbg_trigger_b(7) 046 select tctrc_tcdbg_trigger_a(8) 047 select tctrc_tcdbg_trigger_b(8) 048 select tctrc_tcdbg_trigger_a(8) and tctrc_tcdbg_trigger_b(8) 049 select tctrc_tcdbg_trigger_a(9) 050 select tctrc_tcdbg_trigger_b(9) 051 select tctrc_tcdbg_trigger_a(9) and tctrc_tcdbg_trigger_b(9) 052 select tctrc_tcdbg_trigger_a(10) 053 select tctrc_tcdbg_trigger_b(10) 054 select tctrc_tcdbg_trigger_a(10) and tctrc_tcdbg_trigger_b(10) 055 select tctrc_tcdbg_trigger_a(11) 056 select tctrc_tcdbg_trigger_b(11) 057 select tctrc_tcdbg_trigger_a(11) and tctrc_tcdbg_trigger_b(11) 058 select tctrc_tcdbg_trigger_a(12) 059 select tctrc_tcdbg_trigger_b(12) 060 select tctrc_tcdbg_trigger_a(12) and tctrc_tcdbg_trigger_b(12) 061 select tctrc_tcdbg_trigger_a(13) 062 select tctrc_tcdbg_trigger_b(13) 063 select tctrc_tcdbg_trigger_a(13) and tctrc_tcdbg_trigger_b(13) 064 select tctrc_tcdbg_trigger_a(14) 065 select tctrc_tcdbg_trigger_b(14) 066 select tctrc_tcdbg_trigger_a(14) and tctrc_tcdbg_trigger_b(14) -- LOGIC (UNIT) TRIGGERS -- EP: 0:3 L3C0, 4:7 L3C1, 8:9 GX, 10 TP (hang), 11 spare, 12:13 MCA, 14:15 spare ES: 0:4 L4C, 5:6 L4F, 7:8 TPTOD, 9 TP (hang), 10:15 spare 067 select logic_trigger_in(0) 068 select logic_trigger_in(1) 069 select logic_trigger_in(2) 070 select logic_trigger_in(3) 071 select logic_trigger_in(4) 072 select logic_trigger_in(5) 073 select logic_trigger_in(6) 074 select logic_trigger_in(7) 075 select logic_trigger_in(8) 076 select logic_trigger_in(9) 077 select logic_trigger_in(10) 078 select logic_trigger_in(11) 079 select logic_trigger_in(12) 080 select logic_trigger_in(13) 081 select logic_trigger_in(14) 082 select logic_trigger_in(15) 083 select pc_tcdbg_trigger(0) 084 select pc_tcdbg_trigger(1) 085 select tctrc_tcdbg_glb_brcst(0) 086 select tctrc_tcdbg_glb_brcst(1) 087 select xstop_err 088 select recov_err 089 select spattn 090 select hostattn 091 select fir_dbg_local_xstop_err 092 select tc_dbg_inter_brcst(0) 093 select tc_dbg_inter_brcst(1) -- CORE TRIGGERS (EP chip only) -- Note: set core_slave_mode to honor ec[0:5]_tc_trace_run 094 select core trigger 0: any rising edge of ec[0:5]_tc_trace_run(0) 095 select core trigger 1: any rising edge of ec[0:5]_tc_trace_run(1) 096 select core trigger 2: any falling edge of ec[0:5]_tc_trace_run(0) 097 select core trigger 3: any falling edge of ec[0:5]_tc_trace_run(1) 098 select glb_trig_or_trace_in(0) 099 select glb_trig_or_trace_in(1) 100 select core_local_brcst_trc(0) 101 select core_local_brcst_trc(1) 102 select glb_freeze_brcst_rec(0) 103 select trig_2_extern_in(0) 104 select trig_2_extern_in(1) 105 select dbg_triggers_out(2) 106 select dbg_triggers_out(3) 107 select dbg_triggers_out(4) 108 select dbg_triggers_out(5) 109 select dbg_triggers_out(6) 100 select tcdbg_trigger_in(0) 111 select tcdbg_trigger_in(1) | ||
| 8:15 | RW | INST2_COND1_SEL_B: Multiplexer for cond1_trig_in(1) Selection as cond1_trig_in(0) | ||
| 16:23 | RW | INST2_COND2_SEL_A: Multiplexer for cond2_trig_in(0) Selection as cond1_trig_in(0) | ||
| 24:31 | RW | INST2_COND2_SEL_B: Multiplexer for cond2_trig_in(1) Selection as cond1_trig_in(0) | ||
| 32 | RW | INST2_C1_INAROW_MODE: front end instance 1 c1_inarow_mode | ||
| 33 | RW | INST2_AND_TRIGGER_MODE1: front end instance 1 and trigger mode condition1 | ||
| 34 | RW | INST2_NOT_TRIGGER_MODE1: front end instance 1 inverted trigger mode condition1 | ||
| 35 | RW | INST2_EDGE_TRIGGER_MODE1: front end instance 1 edge trigger mode condition1 | ||
| 36:38 | RWX | INST2_UNUSED_1: UNUSED | ||
| 39 | RW | INST2_C2_INAROW_MODE: front end instance 1 Counter 2 in-a-rwo mode | ||
| 40 | RW | INST2_AND_TRIGGER_MODE2: front end instance 1 and trigger mode2 | ||
| 41 | RW | INST2_NOT_TRIGGER_MODE2: front end instance 1 inverted (not) trigger | ||
| 42 | RW | INST2_EDGE_TRIGGER_MODE2: front end instance 1edge trigger | ||
| 43:45 | RWX | INST2_UNUSED_2: UNUSED | ||
| 46 | RW | INST2_COND3_ENABLE_RESET: front end instance 1 condition3 enable | ||
| 47 | RW | INST2_EXACT_TO_MODE: front end instance 1 exact timeout mode | ||
| 48 | RW | INST2_RESET_C2TIMER_ON_C1: front end instance 1 reset condition2 timer on condition1 | ||
| 49 | RW | INST2_RESET_C3_ON_C0: front end instance 1 reset condition3 on condition0 | ||
| 50 | RW | INST2_SLOW_TO_MODE: front end instance 1 slow timeout mode | ||
| 51 | RW | INST2_EXACT_RESET_C3_ON_TO: front end instance 1 exact reset condition3 on timeout | ||
| 52:55 | RW | INST2_C1_COUNT_LT: inst2 condition1 counter compare value | ||
| 56:59 | RW | INST2_C2_COUNT_LT: inst2 condition2 counter compare value | ||
| 60:62 | RW | INST2_RESET_C3_SELECT: front end instance 1: reset condition3 for reset_c3_on_c0 0b100: dbg_cross_couple_triggers(4) 0b101: dbg_cross_couple_triggers(12) 0b110: dbg_cross_couple_triggers(20) 0b111: dbg_cross_couple_triggers(28) | ||
| Debug macro configuration register 2 for fronte end 1 component | ||||
|---|---|---|---|---|
| Addr: |
00000000110107C5 (SCOM) | |||
| Name: | TP.TCPAU1.EPS.DBG.DBG_INST2_COND_REG_2 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#64.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 1 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#65.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 2 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#66.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 3 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#67.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 4 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#68.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 5 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#69.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 6 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#70.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 7 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#71.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 8 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#72.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 9 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#73.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 10 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#74.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 11 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#75.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 12 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#76.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 13 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#77.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 14 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#78.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 15 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#79.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 16 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#80.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 17 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#81.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 18 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#82.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 19 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#83.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 20 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#84.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 21 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#85.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 22 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#86.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 23 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#87.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 24 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#88.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 25 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#89.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 26 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#90.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 27 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#91.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 28 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#92.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 29 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#93.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 30 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#94.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 31 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#95.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 32 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#96.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 33 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#97.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 34 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#98.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 35 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#99.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 36 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#100.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 37 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#101.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 38 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#102.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 39 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#103.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 40 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#104.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 41 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#105.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 42 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#106.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| 43 | TP.TCPAU1.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#107.LAT.COND_REG_MODE.LATC.L2(0) [0] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:4 | RW | INST2_CROSS_COUPLE_SELECT_1_A: Cross coupling is the same of all selectors: 00000 - selects inst1_cond1_trig_a 00001 - selects inst1_cond1_trig_b 00010 - selects inst1_cond2_trig_a 00011 - selects inst1_cond2_trig_b 00100 - selects inst1_condition1 00101 - selects inst1_condition2 00110 - selects inst1_condition3 00111 - selects inst1_cond2_timeout 01000 - selects inst2_cond1_trig_a 01001 - selects inst2_cond1_trig_b 01010 - selects inst2_cond2_trig_a 01011 - selects inst2_cond2_trig_b 01100 - selects inst2_condition1 01101 - selects inst2_condition2 01110 - selects inst2_condition3 01111 - selects inst2_cond2_timeout 10000 - selects inst3_cond1_trig_a 10001 - selects inst3_cond1_trig_b 10010 - selects inst3_cond2_trig_a 10011 - selects inst3_cond2_trig_b 10100 - selects inst3_condition1 10101 - selects inst3_condition2 10110 - selects inst3_condition3 10111 - selects inst3_cond2_timeout 11000 - selects inst4_cond1_trig_a 11001 - selects inst4_cond1_trig_b 11010 - selects inst4_cond2_trig_a 11011 - selects inst4_cond2_trig_b 11100 - selects inst4_condition1 11101 - selects inst4_condition2 11110 - selects inst4_condition3 11111 - selects inst4_cond2_timeout | ||
| 5:9 | RW | INST2_CROSS_COUPLE_SELECT_1_B: inst2_cross_couple_select_1_b | ||
| 10:14 | RW | INST2_CROSS_COUPLE_SELECT_2_A: inst2_cross_couple_select_2_a | ||
| 15:19 | RW | INST2_CROSS_COUPLE_SELECT_2_B: inst2_cross_couple_select_2_b | ||
| 20:43 | RW | INST2_TO_CMP_LT: compare value for special counter sp_cnt_lt in debug component 2 | ||
| Addr: |
00000000110107C6 (SCOM) | |||
|---|---|---|---|---|
| Name: | TP.TCPAU1.EPS.DBG.DBG_INST2_COND_REG_3 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| Bit(s) | SCOM | Dial: Description | ||
| 0:63 | RO | constant=0b0000000000000000000000000000000000000000000000000000000000000000 | ||
| Debug Macro configuration register 10 for debug backend component | ||||
|---|---|---|---|---|
| Addr: |
00000000110107CD (SCOM) | |||
| Name: | TP.TCPAU1.EPS.DBG.DBG_TRACE_REG_0 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#0.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 1 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#1.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 2 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#2.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 3 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#3.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 4 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#4.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 5 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#5.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 6 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#6.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 7 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#7.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 8 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#8.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 9 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#9.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 10 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#10.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 11 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#11.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 12 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#12.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 13 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#13.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 14 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#14.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 15 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#15.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 16 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#16.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 17 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#17.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 18 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#18.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 19 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#19.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 32 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#32.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 33 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#33.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 34 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#34.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 35 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#35.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 36 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#36.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 37 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#37.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 38 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#38.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 39 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#39.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 40 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#40.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 41 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#41.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 42 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#42.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 43 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#43.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 44 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#44.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 45 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#45.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 46 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#46.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 47 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#47.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 48 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#48.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 49 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#49.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 50 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#50.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 51 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#51.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 52 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#52.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 53 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#53.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 54 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#54.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 55 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#55.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 56 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#56.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 57 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#57.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | RW | INST1_COND3_ENABLE: Enable of instance 1 condition 3 | ||
| 1 | RW | INST2_COND3_ENABLE: Enable of instance 2 condition 3 | ||
| 2 | RW | INST3_COND3_ENABLE: UNUSED | ||
| 3 | RW | INST4_COND3_ENABLE: UNUSED | ||
| 4 | RW | INST1_SLOW_LFSR_MODE: Enable slow lfsr mode of front end instance 1 | ||
| 5 | RW | INST2_SLOW_LFSR_MODE: Enable slow lfsr mode of front end instance 2 | ||
| 6 | RW | INST3_SLOW_LFSR_MODE: UNUSED | ||
| 7 | RW | INST4_SLOW_LFSR_MODE: UNUSED | ||
| 8:9 | RW | INST1_CONDITION1_TRIG_SEL: Select inst1 condition1 for output (external) triggers 00 = do nothing 01 = trigger_out(0) 10 = trigger_out(1) 11 = trigger_out(2) | ||
| 10:11 | RW | INST1_CONDITION2_TRIG_SEL: Select inst1 condition2 for output (external) triggers 00 = do nothing 01 = trigger_out(0) 10 = trigger_out(1) 11 = trigger_out(2) | ||
| 12:13 | RW | INST1_C2_TIMEOUT_TRIG_SEL: Select inst1 c2 time-out counter for output (external) triggers 00 = do nothing 01 = trigger_out(0) 10 = trigger_out(1) 11 = trigger_out(2) | ||
| 14:15 | RW | INST2_CONDITION1_TRIG_SEL: Select inst2 condition1 for output (external) triggers 00 = do nothing 01 = trigger_out(0) 10 = trigger_out(1) 11 = trigger_out(2) | ||
| 16:17 | RW | INST2_CONDITION2_TRIG_SEL: Select inst2 condition2 trigger for output (external) triggers 00 = do nothing 01 = trigger_out(0) 10 = trigger_out(1) 11 = trigger_out(2) | ||
| 18:19 | RW | INST2_C2_TIMEOUT_TRIG_SEL: Select inst2 c2 time-out counter for output (external) triggers 00 = do nothing 01 = trigger_out(0) 10 = trigger_out(1) 11 = trigger_out(2) | ||
| 20:31 | RO | constant=0b000000000000 | ||
| 32 | RW | EXT_TRIG_ON_STOP: enable trigger on stop | ||
| 33 | RW | EXT_TRIG_ON_FREEZE: enable trigger on freeze | ||
| 34:38 | RW | CORE_RAS0_TRIG_SEL: Select which of the debug events of the debug front end component will be used for dbg_triggers_out(3) of the debug backend component 00001 = inst1_condition1_lt 00010 = inst1_cond2_3_event 00100 = inst1_cond2_timeout 01001 = inst2_condition1_lt 01010 = inst2_cond2_3_event 01100 = inst2_cond2_timeout 10001 = inst3_condition1_lt unused 10010 = inst3_cond2_3_event unused 10100 = inst3_cond2_timeout unused 11001 = inst4_condition1_lt unused 11010 = inst4_cond2_3_event unused 11100 = inst4_cond2_timeout unused | ||
| 39:43 | RW | CORE_RAS1_TRIG_SEL: Select which of the debug event of the debug front end component s will be multiplexed to dbg_triggers_out(4) of the debug backend component 00001 = inst1_condition1_lt 00010 = inst1_cond2_3_event 00100 = inst1_cond2_timeout 01001 = inst2_condition1_lt 01010 = inst2_cond2_3_event 01100 = inst2_cond2_timeout 10001 = inst3_condition1_lt unused 10010 = inst3_cond2_3_event unused 10100 = inst3_cond2_timeout unused 11001 = inst4_condition1_lt unused 11010 = inst4_cond2_3_event unused 11100 = inst4_cond2_timeout unused | ||
| 44:45 | RW | PC_TP_TRIG_SEL: select which of the debug events will be multiplexed to dbg_triggers_out(5 to 6) of the debug backend logic component 00 = triggers_out_lt(0) & triggers_out_lt(1) 01 = triggers_out_lt(0) & triggers_out_lt(2) 10 = triggers_out_lt(1) & triggers_out_lt(2) 11 = unused | ||
| 46:49 | RW | DBG_ARM_SEL: select which of the debug events will be multiplexed to dbg_wat_arm (unused) XXXX = unused | ||
| 50:53 | RW | TRIG0_LEVEL_SEL: Select additional conditions for output (external) trigger signal trigger_out(0) Note: some are N/A for zG+ (inst3/4 conditions are tied to zero) 0001 = inst1_cond3_state_int(1) 0010 = inst1_cond3_state_int(0) 0011 = inst2_cond3_state_int(1) 0100 = inst2_cond3_state_int(0) 0101 = inst3_cond3_state_int(1) 0110 = inst3_cond3_state_int(0) 0111 = inst4_cond3_state_int(1) 1000 = inst4_cond3_state_int(0) 1001 = inst1_cond3_state_int(1) or inst2_cond3_state_int(1) 1010 = inst1_cond3_state_int(1) and inst2_cond3_state_int(1) 1011 = inst3_cond3_state_int(1) or inst4_cond3_state_int(1) 1100 = inst3_cond3_state_int(1) and inst4_cond3_state_int(1) 1101 = inst1_cond3_state_int(1) or inst2_cond3_state_int(1) or inst3_cond3_state_int(1) 1110 = inst1_cond3_state_int(1) and inst2_cond3_state_int(1) and inst3_cond3_state_int(1) 1111 = inst1_cond3_state_int(1) or inst2_cond3_state_int(1) or inst3_cond3_state_int(1) or inst4_cond3_state_int(1) | ||
| 54:57 | RW | TRIG1_LEVEL_SEL: Select additional conditions for output (external) trigger signal trigger_out(1) Note: some are N/A for zG+ (inst3/4 conditions are tied to zero) 0001 = inst1_cond3_state_int(1) 0010 = inst1_cond3_state_int(0) 0011 = inst2_cond3_state_int(1) 0100 = inst2_cond3_state_int(0) 0101 = inst3_cond3_state_int(1) 0110 = inst3_cond3_state_int(0) 0111 = inst4_cond3_state_int(1) 1000 = inst4_cond3_state_int(0) 1001 = inst1_cond3_state_int(1) or inst2_cond3_state_int(1) 1010 = inst1_cond3_state_int(1) and inst2_cond3_state_int(1) 1011 = inst3_cond3_state_int(1) or inst4_cond3_state_int(1) 1100 = inst3_cond3_state_int(1) and inst4_cond3_state_int(1) 1101 = inst1_cond3_state_int(1) or inst2_cond3_state_int(1) or inst3_cond3_state_int(1) 1110 = inst1_cond3_state_int(1) and inst2_cond3_state_int(1) and inst3_cond3_state_int(1) 1111 = inst1_cond3_state_int(1) or inst2_cond3_state_int(1) or inst3_cond3_state_int(1) or inst4_cond3_state_int(1) | ||
| 58:63 | RO | constant=0b000000 | ||
| Debug macro configuration register 11 for backend component | ||||
|---|---|---|---|---|
| Addr: |
00000000110107CE (SCOM) | |||
| Name: | TP.TCPAU1.EPS.DBG.DBG_TRACE_REG_1 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#64.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 1 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#65.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 2 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#66.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 3 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#67.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 4 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#68.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 5 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#69.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 6 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#70.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 7 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#71.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 8 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#72.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 9 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#73.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 10 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#74.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 11 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#75.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 24 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#88.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 25 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#89.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 26 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#90.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 27 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#91.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 28 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#92.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 29 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#93.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 36 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#100.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 37 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#101.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 38 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#102.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 39 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#103.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 40 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#104.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 41 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#105.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 48 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#112.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 49 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#113.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 50 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#114.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 51 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#115.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 52 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#116.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 53 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#117.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 54 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#118.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 55 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#119.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:1 | RW | INST1_CONDITION1_ACTION_DO: Inst1 action selection , condition1: 00 = nothing, 01 = start, 10 = stop, 11 = run-N: start now, stop after n cycles | ||
| 2:3 | RW | INST1_CONDITION2_ACTION_DO: Inst1 action selection , condition2: 00 = nothing, 01 = start, 10 = stop, 11 = run-N: start now, stop after n cycles | ||
| 4:5 | RW | INST1_C2_TIMEOUT_ACTION_DO: Inst1 action selection , c2_timeout: 00 = nothing, 01 = start, 10 = stop, 11 = run-N: start now, stop after n cycles | ||
| 6:7 | RW | INST2_CONDITION1_ACTION_DO: inst2 action selection , condition1: 00 = nothing, 01 = start, 10 = stop, 11 = run-N: start now, stop after n cycles | ||
| 8:9 | RW | INST2_CONDITION2_ACTION_DO: Inst2 action selection , condition2: 00 = nothing, 01 = start, 10 = stop, 11 = run-N: start now, stop after n cycles | ||
| 10:11 | RW | INST2_C2_TIMEOUT_ACTION_DO: Inst2 action selection , c2_timeout: 00 = nothing, 01 = start, 10 = stop, 11 = run-N: start now, stop after n cycles | ||
| 12:23 | RO | constant=0b000000000000 | ||
| 24 | RW | INST1_CONDITION1_ACTION_WAITN: for wait-N | ||
| 25 | RW | INST1_CONDITION2_ACTION_WAITN: for wait-N | ||
| 26 | RW | INST1_C2_TIMEOUT_ACTION_WAITN: for wait-N | ||
| 27 | RW | INST2_CONDITION1_ACTION_WAITN: for wait-N | ||
| 28 | RW | INST2_CONDITION2_ACTION_WAITN: for wait-N | ||
| 29 | RW | INST2_C2_TIMEOUT_ACTION_WAITN: for wait-N | ||
| 30:35 | RO | constant=0b000000 | ||
| 36 | RW | INST1_CONDITION1_ACTION_BANK: trace bank switch (inst1, condition1) | ||
| 37 | RW | INST1_CONDITION2_ACTION_BANK: trace bank switch (inst1, condition2) | ||
| 38 | RW | INST1_C2_TIMEOUT_ACTION_BANK: trace bank switch (inst1, c2_timeout) | ||
| 39 | RW | INST2_CONDITION1_ACTION_BANK: trace bank switch (inst2, condition1) | ||
| 40 | RW | INST2_CONDITION2_ACTION_BANK: trace bank switch (inst2, condition2) | ||
| 41 | RW | INST2_C2_TIMEOUT_ACTION_BANK: trace bank switch (inst2, c2_timeout) | ||
| 42:47 | RO | constant=0b000000 | ||
| 48:50 | RW | INST1_CHECKSTOP_MODE_LT: Select additional condition with fir_error_lt for dbg_fir_xstop_on_trig output: 000 = inst1_condition1_lt 001 = inst1_condition2_lt 010 = inst1_condition3_lt 011 = inst1_cond2_timeout_lt 1XX = disable checkstop_mode | ||
| 51 | RW | INST1_CHECKSTOP_MODE_SELECTOR: enable_fir_trig_xstop: enable checkstop on debug trigger: 0 = disable checksop on debug trigger 1 = enable checksop on debug trigger | ||
| 52:54 | RW | INST2_CHECKSTOP_MODE_LT: Select additional condition with fir_error_lt for dbg_fir_xstop_on_trig output: 000 = inst2_condition1_lt 001 = inst2_condition2_lt 010 = inst2_condition3_lt 011 = inst2_cond2_timeout_lt 1XX = disable checkstop_mode | ||
| 55 | RW | INST2_CHECKSTOP_MODE_SELECTOR: enable_fir_error_xstop: enable checkstop on fir error: 0 = disable checkstop on fir error 1 = enable checkstop on fir error | ||
| 56:63 | RO | constant=0b00000000 | ||
| Debug Macro configuration register 12 for backend component | ||||
|---|---|---|---|---|
| Addr: |
00000000110107CF (SCOM) | |||
| Name: | TP.TCPAU1.EPS.DBG.DBG_TRACE_MODE_REG_2 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#128.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 1 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#129.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 2 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#130.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 3 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#131.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 4 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#132.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 5 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#133.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 6 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#134.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 7 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#135.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 8 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#136.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 9 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#137.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 10 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#138.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 11 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#139.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 12 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#140.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 13 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#141.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 14 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#142.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 15 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#143.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 16 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#144.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 17 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#145.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 18 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#146.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 19 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#147.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 20 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#148.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 21 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#149.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 22 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#150.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| 23 | TP.TCPAU1.EPS.DBG.CONFIG.TRAC_LAT_REQ#151.LAT.TRAC_REG_MODE.LATC.L2(0) [0] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:15 | RW | RUNN_COUNT_COMPARE_VALUE: Compare value for the run-N counter used in trace modes run-N and wait-N | ||
| 16 | RW | IMM_FREEZE_MODE: immediate freeze mode | ||
| 17 | RW | STOP_ON_ERR: stop and freeze on xstop | ||
| 18 | RW | BANK_ON_RUNN_MATCH: bank switch on runn match | ||
| 19 | RW | FORCE_TEST_MODE: force run-N condition to be true | ||
| 20 | RW | ACCUM_HIST_MODE: accumulate history mode, do not clear history mode when trace_run active | ||
| 21 | RW | FRZ_COUNT_ON_FRZ: freeze condition counters on trace freeze | ||
| 22:23 | RW | EXTEND_BANK: extends bank signal so that it can be picked up by trace if slower trace macro (0x11 = 4:1, 0x10 = 3:1, 0x01 = 2:1, else 1x | ||
| Trace start/stop/rest using scom command, use write data(0/1/2) = 1 | ||||
|---|---|---|---|---|
| Addr: |
00000000110107D0 (SCOM) | |||
| Name: | TP.TCPAU1.EPS.DBG.DEBUG_TRACE_CONTROL | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:2 | TP.TCPAU1.EPS.DBG.CONFIG.DEBUG_TRACE_CONTROL(0:2) [000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | WOX | scom_trace_start | ||
| 1 | WOX | scom_trace_stop | ||
| 2 | WOX | scom_trace_reset | ||
| xtra / dedicated trace mode register for core triggers | ||||
|---|---|---|---|---|
| Addr: |
00000000110107D1 (SCOM) | |||
| Name: | TP.TCPAU1.EPS.DBG.XTRA_TRACE_MODE | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:41 | TP.TCPAU1.EPS.DBG.CONFIG.XTRA_TRACE_MODE_LT_INST.LATC.L2(0:41) [000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:41 | RW | XTRA_TRACE_MODE_DATA: xtra / dedicated trace mode register for core triggers | ||
| CQ_SM Misc Config register #0 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010800 (SCOM) 0000000013400000 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.MCP.MISC.CONFIG0 | |||
| Constant(s): | ||||
| Comments: | Misc config register Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM0.MCP.MISC.CONFIG0_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_MA_DSA_OPT_CLAIM_UR: 0/1 = use Read.RWC/Upgrade.DN for dclaim/dcbz to GPU Mem | |
| 1 | RW | RW | CONFIG_MA_DSA_OPT_FLUSH_UR: 0/1 = use Read.RWC/Upgrade.DN for dcbf/dcbfc to GPU Mem | |
| 2 | RW | RW | CONFIG_MA_DSA_OPT_RP_MODE: 0/1 = use DMA/Read-Push for Write.NC to Proc Mem | |
| 3 | RW | RW | CONFIG_ADR_BAR_MODE: Reserved (was: PowerBus adr_bar: 0/1 = large-system-mode/small-system-mode) | |
| 4 | RW | RW | CONFIG_DISABLE_NN_RN: PowerBus scope: 0/1 = Enable Nn & Rn scopes / Disable Nn & Rn scopes | |
| 5 | RW | RW | CONFIG_DISABLE_VG_NOT_SYS: PowerBus scope: 0/1 = Enable Vg less than sys / Force all Vg to sys | |
| 6 | RW | RW | CONFIG_DISABLE_G: PowerBus scope: 0/1 = Enable G scope / Disable G scope | |
| 7 | RW | RW | CONFIG_DISABLE_LN: PowerBus scope: 0/1 = Enable Ln scope / Disable Ln scope | |
| 8 | RW | RW | CONFIG_SKIP_G: PowerBus scope: 0/1 = Allow G on rty_inc / Skip G on rty_inc | |
| 9 | RW | RW | CONFIG_MA_MCRESP_OPT_WRP: 0/1 = increase scope on rty_inc to dma_w / use write-read-push on rty_inc to dma_w | |
| 10 | RW | RW | CONFIG_USE_CL_DMA_W: 0/1 = Start cache-line DMA writes using cl_dma_inj / using cl_dma_w | |
| 11 | RW | RW | CONFIG_USE_DMA_PR_W: 0/1 = Start partial-line DMA writes using pr_dma_inj / using dma_pr_w | |
| 12:14 | RW | RW | CONFIG_INC_PRI_MASK: Mask select for priority increase due to rty_drp 0: 100% chance to increase priority 1: 50% chance to increase priority 2: 25% chance to increase priority 3: 12.5% chance to increase priority 4: 6% chance to increase priority 5: 3% chance to increase priority 6,7: 1.5% chance to increase priority | |
| 15 | RW | RW | CONFIG_MACH_CORRENAB: 0/1 = disable/enable state machine array ECC correction | |
| 16 | RW | RW | CONFIG_MACH_INJECT_ENABLE1: 0/1 = disable/enable state machine array ECC error inject bit 1 | |
| 17 | RW | RW | CONFIG_MACH_INJECT_ENABLE2: 0/1 = disable/enable state machine array ECC error inject bit 2 | |
| 18 | RW | RW | CONFIG_RXO_CORRENAB: 0/1 = disable/enable ReqRspOut array ECC correction | |
| 19 | RW | RW | CONFIG_RXO_INJECT_ENABLE1: 0/1 = disable/enable ReqRspOut array ECC error inject bit 1 | |
| 20 | RW | RW | CONFIG_RXO_INJECT_ENABLE2: 0/1 = disable/enable ReqRspOut array ECC error inject bit 2 | |
| 21 | RW | RW | CONFIG_RSI_CORRENAB: 0/1 = disable/enable PB-Rsp-In array ECC correction | |
| 22 | RW | RW | CONFIG_RSI_INJECT_ENABLE1: 0/1 = disable/enable PB-Rsp-In array ECC error inject bit 1 | |
| 23 | RW | RW | CONFIG_RSI_INJECT_ENABLE2: 0/1 = disable/enable PB-Rsp-In array ECC error inject bit 2 | |
| 24 | RW | RW | CONFIG_MA_DSA_OPT_DMA_UPG: 0/1 = non-relaxed dma_w use Read.RWC/Upgrade.DN to acquire pocket-cache state/data | |
| 25 | RW | RW | CONFIG_EVAPORATE_BY_LCO: 0/1 = just free the state-machine without lco/evaporate pocket-cache entries by lco | |
| 26 | RW | RW | CONFIG_ENABLE_PBUS: 0/1 = disable PAU PowerBus RCmd, PResp, and CResp interfaces / enable these interfaces Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 27 | RW | RW | CONFIG_ENABLE_SNARF_CPM: 0/1 = disable/enable Probe.I.MO snarfing a cp_m | |
| 28 | RW | RW | CONFIG_DISABLE_INJECT: 0/1 = enable sending cl,pr_dma_inj / disable sending cl,pr_dma_inj Note: to truly disable sending _inj commands, the following bits must also be set to '0': config_ma_dsa_opt_rp_mode | |
| 29 | RW | RW | CONFIG_DCACHE_MODE: 0/1 = drive data-bus dcache field in basic mode / CAPP mode. | |
| 30 | RW | RW | CONFIG_DCACHE_REPORTS_PHYSICAL: 0/1 = in basic mode, report local masters as near / local. | |
| 31 | RW | RW | CONFIG_RSI_DISABLE_DATIN_FASTPATH: 0/1 = enable rsi PB data-in fastpath/disable fastpath | |
| 32 | RW | RW | CONFIG_FORBID_MMIO_READ_GT_32: 0/1 = Allow GPU->PB MMIOs > 32-bytes / flag-error & brick-fence on MMIOs > 32-bytes | |
| 33 | RW | RW | CONFIG_FORBID_MMIO_ATOMIC: 0/1 = Allow GPU->PB atomics to MMIO space / flag-error & brick-fence on atomics to MMIO space | |
| 34 | RW | RW | CONFIG_DISABLE_HW555363_FASTPATH_AND_FENCE: 0/1 = enable HW555363 fix for fence happening between fastpath RCmd and CResp / disable fix. | |
| 35 | RW | RW | CONFIG0_RESERVED1: reserved | |
| 36 | RW | RW | CONFIG_ENABLE_CONTEXT_LCO: 0/1 = disable LCOing context entries into L3/enable LCOing context entries into L3 | |
| 37 | RW | RW | CONFIG_MA_DSA_OPT_FAIL_WAKE: 0/1 = send wake_host_thread to PB as asb_notify / fail all wake_host_thread w/ thread-not-found status (no PB asb_notify) | |
| 38 | RW | RW | CONFIG_ENABLE_FAST_DIR_UPDATE: 0/1 = disable directory fast update from mach pipe / enable directory fast update from mach pipe | |
| 39 | RW | RW | CONFIG_OPT_MES_USE_GO_M: 0/1 = read_mes w/ RW authority uses rd_go_s/rd_go_m to acquire the line | |
| 40 | RW | RW | CONFIG_OPT_LCO_M_USE_MU: 0/1 = use lco_m to inject a modified line into an L3 / use lco_mu | |
| 41 | RW | RW | CONFIG_OPT_SNOOP_EX_LCO: 0/1 = use cp_* when a castout.push(128B)->I is due to a snoop against an exclusive directory entry / use an lco_m,mu | |
| 42 | RW | RW | CONFIG_ENABLE_CP_ME: 0/1 = disable sending cp_me / enable cp_me when a cleaning E->I and homed off-node. | |
| 43 | RW | RW | CONFIG_FENCE_ON_DERR_MMIO: 0/1 = write SUE data to MMIO on data error from OCAPI / fence brick (note: dual NVF10/OCR7 error flagged) | |
| 44 | RW | RW | CONFIG_BRK0_OCAPI_MODE: 0/1 = Disable OpenCAPI mode / enable OpenCAPI mode for brick 0 (mutually exclusive with config_brk0_nvlink_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 45 | RW | RW | CONFIG_BRK1_OCAPI_MODE: 0/1 = Disable OpenCAPI mode / enable OpenCAPI mode for brick 1 (mutually exclusive with config_brk1_nvlink_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 46 | RW | RW | CONFIG_BRK2_OCAPI_MODE: 0/1 = Disable OpenCAPI mode / enable OpenCAPI mode for brick 2 (mutually exclusive with config_brk2_nvlink_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 47 | RW | RW | CONFIG_BRK3_OCAPI_MODE: 0/1 = Disable OpenCAPI mode / enable OpenCAPI mode for brick 3 (mutually exclusive with config_brk3_nvlink_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 48 | RW | RW | CONFIG_BRK4_OCAPI_MODE: 0/1 = Disable OpenCAPI mode / enable OpenCAPI mode for brick 4 (mutually exclusive with config_brk4_nvlink_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 49 | RW | RW | CONFIG_BRK0_NVLINK_MODE: 0/1 = Disable NVLink mode / enable NVLink mode for brick 0 (mutually exclusive with config_brk0_ocapi_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 50 | RW | RW | CONFIG_BRK1_NVLINK_MODE: 0/1 = Disable NVLink mode / enable NVLink mode for brick 1 (mutually exclusive with config_brk1_ocapi_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 51 | RW | RW | CONFIG_BRK2_NVLINK_MODE: 0/1 = Disable NVLink mode / enable NVLink mode for brick 2 (mutually exclusive with config_brk2_ocapi_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 52 | RW | RW | CONFIG_BRK3_NVLINK_MODE: 0/1 = Disable NVLink mode / enable NVLink mode for brick 3 (mutually exclusive with config_brk3_ocapi_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 53 | RW | RW | CONFIG_BRK4_NVLINK_MODE: 0/1 = Disable NVLink mode / enable NVLink mode for brick 4 (mutually exclusive with config_brk4_ocapi_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 54 | RW | RW | CONFIG_BRK0_POISON_FENCE_L2: 0/1 = write all-ones-good-ECC/all-ones-SUE to E/Ei/M L2 directory entries when brick 0 is fenced Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 55 | RW | RW | CONFIG_BRK1_POISON_FENCE_L2: 0/1 = write all-ones-good-ECC/all-ones-SUE to E/Ei/M L2 directory entries when brick 0 is fenced Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 56:58 | RW | RW | CONFIG0_RESERVED0: reserved | |
| 59 | RW | RW | CONFIG_BRK0_IMP_TAGS_MODE_ENABLE: 0/1 = disable IMP (HAPPI) iseries tags mode / enable tags mode for brick 0 Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 60 | RW | RW | CONFIG_BRK1_IMP_TAGS_MODE_ENABLE: 0/1 = disable IMP (HAPPI) iseries tags mode / enable tags mode for brick 1 Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 61 | RW | RW | CONFIG_BRK2_IMP_TAGS_MODE_ENABLE: 0/1 = disable IMP (HAPPI) iseries tags mode / enable tags mode for brick 2 Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 62 | RW | RW | CONFIG_BRK3_IMP_TAGS_MODE_ENABLE: 0/1 = disable IMP (HAPPI) iseries tags mode / enable tags mode for brick 3 Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 63 | RW | RW | CONFIG_BRK4_IMP_TAGS_MODE_ENABLE: 0/1 = disable IMP (HAPPI) iseries tags mode / enable tags mode for brick 4 Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| CQ_SM Misc Config register #1 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010801 (SCOM) 0000000013400008 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.MCP.MISC.CONFIG1 | |||
| Constant(s): | ||||
| Comments: | Misc config register Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM0.MCP.MISC.CONFIG1_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:3 | RW | RW | CONFIG_RANDOM_BACKOFF_DUR_MASK: Mask for the base random duration of a random retry backoff 0000 -> 0-15 base random duration 0001 -> 0-31 base random duration 0011 -> 0-63 base random duration 0111 -> 0-127 base random duration 1111 -> 0-255 base random duration | |
| 4:7 | RW | RW | CONFIG_CHGRATE_HANG_SLOWDOWN_REQ: Mask for for the slowdown of NTL CReq or OCAPI TLX.vc.3 credits during chgrate.hang 'n' -> 1/(2^(n+1)) cycles average rate Note that for a single PowerBus ramp, the rate is actually 8 times faster since there are 4 RCmd slice x 2 NTL Bricks that get CReq credits. This field is the rate for 1 brick receiving credit from 1 RCmd slice. | |
| 8:11 | RW | RW | CONFIG_CHGRATE_HANG_SLOWDOWN_CST: Mask for for the slowdown of OCAPI TLX.vc.2 credits during chgrate.hang 'n' -> 1/(2^(n+1)) cycles average rate Note that for a single PowerBus ramp, the rate is actually 8 times faster since there are 4 RCmd slice x 2 NTL Bricks that get CReq credits. This field is the rate for 1 brick receiving credit from 1 RCmd slice. | |
| 12:15 | RW | RW | CONFIG_CHGRATE_HANG_SLOWDOWN_PRB: Mask for for the slowdown of NTL Probe or OCAPI TLX.vc.1 credits during chgrate.hang 'n' -> 1/(2^(n+1)) cycles average rate Note that for a single PowerBus ramp, the rate is actually 8 times faster since there are 4 RCmd slice x 2 NTL Bricks that get CReq credits. This field is the rate for 1 brick receiving credit from 1 RCmd slice. | |
| 16:27 | RW | RW | CONFIG_EPSILON_WLN_COUNT: epsilon count for Ln scope CP-Write | |
| 28 | RW | RW | CONFIG_MIMIRROR_MASTER_ENABLE: 0/1 = disable MI mirroring support / enable MI mirroring | |
| 29:31 | RW | RW | CONFIG_MIMIRROR_BRICK_MODE: Primary & Secondary bricks are: 000 = Primary is brick 0, brick 1 not used 001 = Primary is brick 1, brick 0 not used 010 = Primary is brick 0, stores mirror to brick 1 011 = Primary is brick 1, stores mirror to brick 0 100 = Primary is brick 0, stores mirror to brick 1, loads can failover to brick 1 101 = Primary is brick 1, stores mirror to brick 0, loads can failover to brick 0 110 = Primary brick is addr(54), stores mirror to both bricks, loads can failover to the other brick 111 = Primary brick is random, stores mirror to both bricks, loads can failover to the other brick | |
| 32 | RW | RW | CONFIG_MIMIRROR_FENCE_ON_BAD_DATA: 0/1 = don't force fence for bad_data responses / force fence when bad_data arrives in a response. | |
| 33:34 | RW | RW | CONFIG1_RESERVED2: reserved | |
| 35 | RW | RW | CONFIG_PCKT_LONG_CL_DMA_INJ: 0/1 = allow cl_dma_inj to use short pocket-cache timer/ force cl_dma_inj to use long pocket-cache timer | |
| 36 | RW | RW | CONFIG_PCKT_LONG_PR_DMA_INJ: 0/1 = allow pr_dma_inj to use short pocket-cache timer/ force pr_dma_inj to use long pocket-cache timer | |
| 37:42 | RW | RW | CONFIG_PCKT_LONG_MIN_COUNT: Minimum number of state-machine w/ long pocket-cache timers before short timers can be used | |
| 43 | RW | RW | CONFIG_PCKT_LONG_USES_HANG: 0/1 = use config_pocket_long_rate2 / use rpt_hang.poll ticks to drive long pocket-cache timer | |
| 44 | RW | RW | CONFIG_DONT_RETRY_LCO_LONG: reserved (was config_dont_retry_lco_long) | |
| 45 | RW | RW | CONFIG_DONT_RETRY_LCO_LONG_STRESSED: reserved (was config_dont_retry_lco_long_stressed). | |
| 46 | RW | RW | CONFIG_DONT_RETRY_LCO_SHORT: reserved (was config_dont_retry_lco_short) | |
| 47 | RW | RW | CONFIG_DONT_RETRY_LCO_SHORT_STRESSED: reserved (was config_dont_retry_lco_short_stressed). | |
| 48 | RW | RW | CONFIG_STOP_ASB_AT_LN_SCOPE: 0/1 = increase to asb_notify to G scope / stop and return thread-not-found when asb_notify @ Ln scope doesn't find the thread | |
| 49 | RW | RW | CONFIG_STOP_ASB_AT_G_SCOPE: 0/1 = increase to asb_notify to Vg(sys) scope / stop and return thread-not-found when asb_notify @ G scope doesn't find the thread | |
| 50 | RW | RW | CONFIG_INITIAL_HPC_PROBE_PRIORITY: Initial drop_priority value when mastering an hpc_probe | |
| 51 | RW | RW | CONFIG_NVLINK_P10P10_MODE: 0/1 = normal NVLink mode / special lab-debug-only P10-to-P10 NVLink mode | |
| 52 | RW | RW | CONFIG_HANG_ON_ADDRESS_ERRORS: 0/1 = abort and continue on CResp=addr_error / hang state-machine on CResp=addr_error | |
| 53 | RW | RW | CONFIG_DISABLE_HW525464_CLEAN_XUE_FENCE_PB: 0/1 = enable HW525464 fix for cleaning XUE data on fence of pb cmd / disable fix. | |
| 54 | RW | RW | CONFIG_DISABLE_HW517903_BAD_SYNC: 0/1 = handle bad sync in non-4.0 mode / disable fix. | |
| 55 | RW | RW | CONFIG_DISABLE_HW526620_BAD_SYN_DONE: 0/1 = handle mis-aligned synonym_done / disable fix. | |
| 56 | RW | RW | CONFIG_ENABLE_OPENCAPI_NETWORKING: 0/1 = disable networking / enable OpenCAPI MI networking mode. | |
| 57 | RW | RW | CONFIG_NET0_TORUS_MODE: 0/1 = Dragonfly network mode / Torus network mode for brick 0 | |
| 58 | RW | RW | CONFIG_NET1_TORUS_MODE: 0/1 = Dragonfly network mode / Torus network mode for brick 1 | |
| 59 | RW | RW | CONFIG_DISABLE_HW532477_ARMWF_IMP_TAGS_RESET: 0/1 = Enable resetting itags after transmitting armwf data / disable fix | |
| 60 | RW | RW | CONFIG_DISABLE_HW536051_FENCE_HOSPICE_PRONOTE: 0/1 = Enable an extra dirscan before waiting for REQ to drain / disable fix | |
| 61 | RW | RW | CONFIG_DISABLE_HW537584_HOSPICE_QUALIFIER: 0/1 = Enable correctly qualifying hp_vec_empty with dir_allocated to indicate hospice / disable fix | |
| 62 | RW | RW | CONFIG_DISABLE_HW546460_INC_DEC_ALL_ONES: 0/1 = Enable IM-network brick4-fence causing inc/dec atomics to return all ones / disable fix | |
| 63 | RW | RW | CONFIG_ENABLE_HW555343_ALL_PTL_ARE_BE: 0/1 = disable HW555343 fix / enable fix to convert all partial writes to byte-enable writes. | |
| PowerBus Epsilon | ||||
|---|---|---|---|---|
| Addr: |
0000000011010802 (SCOM) 0000000013400010 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.MCP.MISC.EPSILON_CONFIG | |||
| Constant(s): | ||||
| Comments: | PowerBus Epsilon config register Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM0.MCP.MISC.EPSILON_CONFIG_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:3 | RW | RW | CONFIG_EPSILON_RATE: 0 = decrement epsilon count at 1:1 pau_clock_1to1 ... 15 = epsilon count at 1/16 pau_clock_1to1 | |
| 4:15 | RW | RW | CONFIG_EPSILON_W0_COUNT: epsilon count for Nn/G scope CP-Write | |
| 16:27 | RW | RW | CONFIG_EPSILON_W1_COUNT: epsilon count for Rn/Vg scope CP-Write | |
| 28:39 | RW | RW | CONFIG_EPSILON_R0_COUNT: epsilon count for Ln scope Reads | |
| 40:51 | RW | RW | CONFIG_EPSILON_R1_COUNT: epsilon count for Nn/G scope Reads | |
| 52:63 | RW | RW | CONFIG_EPSILON_R2_COUNT: epsilon count for Rn/Vg scope Reads | |
| Timer Config Reg | ||||
|---|---|---|---|---|
| Addr: |
0000000011010803 (SCOM) 0000000013400018 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.MCP.MISC.XTIMER_CONFIG | |||
| Constant(s): | ||||
| Comments: | Timer Configuration Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:59 | PAU3.CS.SM0.MCP.MISC.XTIMER_CONFIG_Q_0_INST.LATC.L2(0:59) [000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:1 | RW | RW | CONFIG_POCKET_LONG_RATE1: Rate_1 for the Long Pocket-Cache timer. The Pocket-Cache timer is used to evaporate pocket-cache entries which are not claimed. The Long timer duration is f(Rate_1)*2^(Rate_2)*5e-10 seconds Unless config_pckt_long_uses_hang=1, then it is f(Rate1)*rpt_hang.poll interval. f(0b00) = 2 f(0b01) = 3 f(0b10) = 4 f(0b11) = 5 | |
| 2:7 | RW | RW | CONFIG_POCKET_LONG_RATE2: Rate_2 for the long timer for Pocket-Cache entries (2^n cycles). | |
| 8:13 | RW | RW | CONFIG_POCKET_SHORT_RATE2: Rate_2 for the short timer for Pocket-Cache entries (2^n cycles). | |
| 14:19 | RW | RW | CONFIG_FWD_PROG_RATE2: Rate_2 for the forward-progress timer (2^n cycles). | |
| 20:25 | RW | RW | CONFIG_XTIMER_RESERVED1: Reserved (was: Rate for CTL timer tick (default 63 = off)) | |
| 26:31 | RW | RW | CONFIG_INH0_TICK: Rate for SM-Inhibit timer tick0 (default 63 = off) Note: This field can/should have different values in each instance. No MDials have been created for this field's IDials | |
| 32:37 | RW | RW | CONFIG_INH1_TICK: Rate for SM-Inhibit timer tick1 (default 63 = off) Note: This field can/should have different values in each instance. No MDials have been created for this field's IDials | |
| 38:39 | RW | RW | CONFIG_NV_RESP_RATE1: Reserved (was: Rate_1 for NV-Response timer) | |
| 40:45 | RW | RW | CONFIG_NV_RESP_RATE2: Rate_2 for the NV-Response timer (2^n cycles). Overall timeout is (3 to 4)*(2^Rate_2)*5e-10 seconds. | |
| 46:47 | RW | RW | CONFIG_POCKET_SHORT_RATE1: Rate_1 for the Short Pocket-Cache timer. The Pocket-Cache timer is used to evaporate pocket-cache entries which are not claimed. the Short timer duration is f(Rate_1)*2^(Rate_2)*5e-10 seconds where f(Rate_1) is: f(0b00) = 7 f(0b01) = 63 f(0b10) = 511 f(0b11) = 4095 | |
| 48:53 | RW | RW | CONFIG_SCAN_WAIT_RATE: Rate for directory-scanning wait-walker 2^Rate cycles per tick | |
| 54:59 | RW | RW | CONFIG_EPOCH_RATE: Rate for epoch-checks Overall timeout is (2 to 3)*(2^Rate)*5e-10 seconds. | |
| 60:63 | RO | RO | constant=0b0000 | |
| Perf Config Reg | ||||
|---|---|---|---|---|
| Addr: |
0000000011010804 (SCOM) 0000000013400020 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.MCP.MISC.PERF_CONFIG | |||
| Constant(s): | ||||
| Comments: | Performance Event selection | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM0.MCP.MISC.PERF_CONFIG_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:8 | RW | RW | PERF_CONFIG_LATSTART: Latency count start event | |
| 9:17 | RW | RW | PERF_CONFIG_LATCANCEL: Latency count abort event | |
| 18:26 | RW | RW | PERF_CONFIG_LATFINISH: Latency count finish event | |
| 27 | RW | RW | PERF_CONFIG_RESERVED1: reserved | |
| 28:35 | RW | RW | PERF_CONFIG_EVENT0: Event 0 select 0: count nothing 1: count cycles 2: count latency events (see latstart/cancel/finish fields) 3: count latency cycles (avg latency = cycles divided by events) 4: count latency aborts (start condition was detected, but finish condition was not) 5: count # Same-address checks detected a collision 6: count # Same-address checks detected no collision 7: count # CResps matching cresp + original command 8: count # of PB Cmds sent w/ matching scope 9: count # CResps matching cresp + scope + master command + original command 10: count # of PB Cmds sent w/ matching scope+command 11: count # of NV/OC Cmds sent w/ matching command 12: count # of NV/OC Resps sent w/ matching response(command) 13: count # of force_evicts sent due to dir-scan / XSL-castouts 14: count # of force_evicts sent due to sfe / PowerBus RCmd snoops 15: count # of force_evicts sent due to the other brick having state (needed by the requesting brick) 16: count # of force_evicts / EF responses sent due to capacity evicts in the L2 directory 17: count # of allocating C2 commands that update state in an existing directory entry (ie cacheline was alreayd present) 18: count # of allocating C2 commands that update state in a new directory entry (ie cacheline was not present in the directory) others: reserved (count nothing) | |
| 36:43 | RW | RW | PERF_CONFIG_EVENT1: Event 1 select See Event 0 select for encodes | |
| 44:51 | RW | RW | PERF_CONFIG_EVENT2: Event 2 select See Event 0 select for encodes | |
| 52:59 | RW | RW | PERF_CONFIG_EVENT3: Event 3 select See Event 0 select for encodes | |
| 60:61 | RW | RW | PERF_CONFIG_RESERVED2: reserved | |
| 62 | RW | RW | PERF_CONFIG_LATFILTER: 0/1 = count max latency events / filter latency events by 1/1024 for bias reduction | |
| 63 | RW | RW | PERF_CONFIG_ACT: Enable clock-gates for performance monitor latches | |
| Inhibit configuration Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010805 (SCOM) 0000000013400028 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.MCP.MISC.INHIBIT_CONFIG | |||
| Constant(s): | ||||
| Comments: | Configures Inhibits for CQ_SM | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM0.MCP.MISC.INHIBIT_CONFIG_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:3 | RW | RW | CONFIG_INHIBIT_LFREQ0: Base LFSR frequency 0: 0..11 = 1/2^(n+1) 12 = 1/2^14 13 = 1/2^16 14 = 1/2^18 15 = 1/2^20 | |
| 4:5 | RW | RW | CONFIG_INHIBIT_PFREQ0: Selects pre frequency 0: 0 = Inhibit timer tick0 1 = inverted Inhibit timer tick0 2 = LFSR 3 = inverted LFSR (-> 1/2, 3/4, 7/8, ...) | |
| 6 | RW | RW | CONFIG_INHIBIT_BLOCKY0: 0/1 = disable blocky mode / enable blocky mode | |
| 7 | RW | RW | CONFIG_INHIBIT_ONESHOT0: 0/1 = continus mode / one-shot mode | |
| 8:15 | RW | RW | CONFIG_INHIBIT_DEST0: Selects the destination of the inhibit | |
| 16:19 | RW | RW | CONFIG_INHIBIT_LFREQ1: Base LFSR frequency 0: 0..12 = 1/2^(n+1) 13 = 1/2^16 14 = 1/2^18 15 = 1/2^20 | |
| 20:21 | RW | RW | CONFIG_INHIBIT_PFREQ1: Selects pre frequency 0: 0 = Inhibit timer tick1 1 = inverted Inhibit timer tick1 2 = LFSR 3 = inverted LFSR (-> 1/2, 3/4, 7/8, ...) | |
| 22 | RW | RW | CONFIG_INHIBIT_BLOCKY1: 0/1 = disable blocky mode / enable blocky mode | |
| 23 | RW | RW | CONFIG_INHIBIT_ONESHOT1: 0/1 = continus mode / one-shot mode | |
| 24:31 | RW | RW | CONFIG_INHIBIT_DEST1: Selects the destination of the inhibit | |
| 32:35 | RW | RW | CONFIG_INHIBIT_LFREQ2: Base LFSR frequency 2: 0..11 = 1/2^(n+1) 12 = 1/2^14 13 = 1/2^16 14 = 1/2^18 15 = 1/2^20 | |
| 36:37 | RW | RW | CONFIG_INHIBIT_PFREQ2: Selects pre frequency 2: 0 = Inhibit timer tick0 1 = inverted Inhibit timer tick0 2 = LFSR 3 = inverted LFSR (-> 1/2, 3/4, 7/8, ...) | |
| 38 | RW | RW | CONFIG_INHIBIT_BLOCKY2: 0/1 = disable blocky mode / enable blocky mode | |
| 39 | RW | RW | CONFIG_INHIBIT_ONESHOT2: 0/1 = continus mode / one-shot mode | |
| 40:47 | RW | RW | CONFIG_INHIBIT_DEST2: Selects the destination of the inhibit | |
| 48:51 | RW | RW | CONFIG_INHIBIT_LFREQ3: Base LFSR frequency 3: 0..12 = 1/2^(n+1) 13 = 1/2^16 14 = 1/2^18 15 = 1/2^20 | |
| 52:53 | RW | RW | CONFIG_INHIBIT_PFREQ3: Selects pre frequency 3: 0 = Inhibit timer tick1 1 = inverted Inhibit timer tick1 2 = LFSR 3 = inverted LFSR (-> 1/2, 3/4, 7/8, ...) | |
| 54 | RW | RW | CONFIG_INHIBIT_BLOCKY3: 0/1 = disable blocky mode / enable blocky mode | |
| 55 | RW | RW | CONFIG_INHIBIT_ONESHOT3: 0/1 = continus mode / one-shot mode | |
| 56:63 | RW | RW | CONFIG_INHIBIT_DEST3: Selects the destination of the inhibit | |
| c_err_rpt Message-0 latches | ||||
|---|---|---|---|---|
| Addr: |
0000000011010806 (SCOM) 0000000013400030 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.MCP.MISC.CERR_MESSAGE0 | |||
| Constant(s): | ||||
| Comments: | Error message/capture register 0 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM0.MCP.MISC.CERR_MESSAGE0_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:63 | RWX_WCLRREG | RWX_WCLRREG | CERR_MESSAGE_BITS0: reserved | |
| c_err_rpt Message-1 latches | ||||
|---|---|---|---|---|
| Addr: |
0000000011010807 (SCOM) 0000000013400038 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.MCP.MISC.CERR_MESSAGE1 | |||
| Constant(s): | ||||
| Comments: | Error message/capture register 1 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM0.MCP.MISC.CERR_MESSAGE1_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:63 | RWX_WCLRREG | RWX_WCLRREG | CERR_MESSAGE_BITS1: reserved | |
| c_err_rpt Message-2 latches | ||||
|---|---|---|---|---|
| Addr: |
0000000011010808 (SCOM) 0000000013400040 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.MCP.MISC.CERR_MESSAGE2 | |||
| Constant(s): | ||||
| Comments: | Error message/capture register 2 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM0.MCP.MISC.CERR_MESSAGE2_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:63 | RWX_WCLRREG | RWX_WCLRREG | CERR_MESSAGE_BITS2: reserved | |
| c_err_rpt Message-3 latches | ||||
|---|---|---|---|---|
| Addr: |
0000000011010809 (SCOM) 0000000013400048 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.MCP.MISC.CERR_MESSAGE3 | |||
| Constant(s): | ||||
| Comments: | Error message/capture register 3 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM0.MCP.MISC.CERR_MESSAGE3_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:63 | RWX_WCLRREG | RWX_WCLRREG | CERR_MESSAGE_BITS3: reserved | |
| c_err_rpt Message-4 latches | ||||
|---|---|---|---|---|
| Addr: |
000000001101080A (SCOM) 0000000013400050 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.MCP.MISC.CERR_MESSAGE4 | |||
| Constant(s): | ||||
| Comments: | Error message/capture register 4 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM0.MCP.MISC.CERR_MESSAGE4_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:63 | RWX_WCLRREG | RWX_WCLRREG | CERR_MESSAGE_BITS4: reserved | |
| c_err_rpt Message-5 latches | ||||
|---|---|---|---|---|
| Addr: |
000000001101080B (SCOM) 0000000013400058 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.MCP.MISC.CERR_MESSAGE5 | |||
| Constant(s): | ||||
| Comments: | Error message/capture register 5 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM0.MCP.MISC.CERR_MESSAGE5_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:63 | RWX_WCLRREG | RWX_WCLRREG | CERR_MESSAGE_BITS5: reserved | |
| c_err_rpt Message-6 latches | ||||
|---|---|---|---|---|
| Addr: |
000000001101080C (SCOM) 0000000013400060 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.MCP.MISC.CERR_MESSAGE6 | |||
| Constant(s): | ||||
| Comments: | Error message/capture register 6 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM0.MCP.MISC.CERR_MESSAGE6_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:63 | RWX_WCLRREG | RWX_WCLRREG | CERR_MESSAGE_BITS6: reserved | |
| c_err_rpt Message-7 latches | ||||
|---|---|---|---|---|
| Addr: |
000000001101080D (SCOM) 0000000013400068 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.MCP.MISC.CERR_MESSAGE7 | |||
| Constant(s): | ||||
| Comments: | Error message/capture register 7 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:39 | PAU3.CS.SM0.MCP.MISC.CERR_MESSAGE7_Q_0_INST.LATC.L2(0:39) [0000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:39 | RWX_WCLRREG | RWX_WCLRREG | CERR_MESSAGE_BITS7: reserved | |
| 40:63 | RO | RO | constant=0b000000000000000000000000 | |
| CQ_SM status register | ||||
|---|---|---|---|---|
| Addr: |
000000001101080E (SCOM) 0000000013400070 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.MCP.MISC.SM_STATUS | |||
| Constant(s): | ||||
| Comments: | Status reporting register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM0.MCP.MISC.SM_STATUS_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:3 | ROX | ROX | SM_STATUS_MRBGP: Master-Retry backoff level for Group-Pump commands | |
| 4:7 | ROX | ROX | SM_STATUS_MRBSP: Master-Retry backoff level for System-Pump commands | |
| 8:11 | ROX | ROX | SM_STATUS_FENCE0: Brick-0 Fence sequencing state 0b0000 = Idle state, completely unfenced 0b0--- = in transition between fenced and not-fenced 0b10-- = in transition between fenced and not-fenced 0b1100 = Fenced state, fence sequencing complete 0b1101 = Flushing pocket-cache entries prior to exiting fence 0b1110 = Flushing pocket-cache entries prior to exiting fence 0b1111 = reserved | |
| 12:15 | ROX | ROX | SM_STATUS_FENCE1: Brick-1 Fence sequencing state 0b0000 = Idle state, completely unfenced 0b0--- = in transition between fenced and not-fenced 0b10-- = in transition between fenced and not-fenced 0b1100 = Fenced state, fence sequencing complete 0b1101 = Flushing pocket-cache entries prior to exiting fence 0b1110 = Flushing pocket-cache entries prior to exiting fence 0b1111 = reserved | |
| 16:19 | ROX | ROX | SM_STATUS_FENCE2: Brick-2 Fence sequencing state 0b0000 = Idle state, completely unfenced 0b0--- = in transition between fenced and not-fenced 0b10-- = in transition between fenced and not-fenced 0b1100 = Fenced state, fence sequencing complete 0b1101 = Flushing pocket-cache entries prior to exiting fence 0b1110 = Flushing pocket-cache entries prior to exiting fence 0b1111 = reserved | |
| 20:23 | ROX | ROX | SM_STATUS_FENCE3: Brick-3 Fence sequencing state 0b0000 = Idle state, completely unfenced 0b0--- = in transition between fenced and not-fenced 0b10-- = in transition between fenced and not-fenced 0b1100 = Fenced state, fence sequencing complete 0b1101 = Flushing pocket-cache entries prior to exiting fence 0b1110 = Flushing pocket-cache entries prior to exiting fence 0b1111 = reserved | |
| 24:27 | ROX | ROX | SM_STATUS_FENCE4: Brick-4 Fence sequencing state 0b0000 = Idle state, completely unfenced 0b0--- = in transition between fenced and not-fenced 0b10-- = in transition between fenced and not-fenced 0b1100 = Fenced state, fence sequencing complete 0b1101 = Flushing pocket-cache entries prior to exiting fence 0b1110 = Flushing pocket-cache entries prior to exiting fence 0b1111 = reserved | |
| 28 | ROX | ROX | SM_STATUS_PBLN: 1 when outbound Ln-scope PowerBus request queue is empty | |
| 29 | ROX | ROX | SM_STATUS_PBNNG: 1 when outbound Nn/G-scope PowerBus request queue is empty | |
| 30 | ROX | ROX | SM_STATUS_PBRNVG: 1 when outbound Rn/Vg-scope PowerBus request queue is empty | |
| 31 | ROX | ROX | SM_STATUS_B0REQ: 1 when outbound brick 0 CReq request queue is empty | |
| 32 | ROX | ROX | SM_STATUS_B0DGD: 1 when outbound brick 0 Downgrade request queue is empty | |
| 33 | ROX | ROX | SM_STATUS_B1REQ: 1 when outbound brick 1 CReq request queue is empty | |
| 34 | ROX | ROX | SM_STATUS_B1DGD: 1 when outbound brick 1 Downgrade request queue is empty | |
| 35 | ROX | ROX | SM_STATUS_B2REQ: 1 when outbound brick 2 CReq request queue is empty | |
| 36 | ROX | ROX | SM_STATUS_B2DGD: 1 when outbound brick 2 Downgrade request queue is empty | |
| 37 | ROX | ROX | SM_STATUS_B3REQ: 1 when outbound brick 3 CReq request queue is empty | |
| 38 | ROX | ROX | SM_STATUS_B3DGD: 1 when outbound brick 3 Downgrade request queue is empty | |
| 39 | ROX | ROX | SM_STATUS_B4REQ: 1 when outbound brick 4 CReq request queue is empty | |
| 40 | ROX | ROX | SM_STATUS_B4DGD: 1 when outbound brick 4 Downgrade request queue is empty | |
| 41 | ROX | ROX | SM_STATUS_MMIO: 1 when outbound MMIO/GenId request queue is empty | |
| 42 | ROX | ROX | SM_STATUS_MMIOSUE: 1 when outbound MMIO-SUE request queue is empty | |
| 43 | ROX | ROX | SM_STATUS_ATSXLATE: 1 when outbound ATS-TCE-Translation request queue is empty | |
| 44 | ROX | ROX | SM_STATUS_REPLAY: 1 when outbound replay-to-directory queue is empty | |
| 45 | ROX | ROX | SM_STATUS_PBRSP: 1 when outbound PowerBus data-response/merge-operation queue is empty | |
| 46 | ROX | ROX | SM_STATUS_B0RSP: 1 when outbound brick 0 response queue is empty | |
| 47 | ROX | ROX | SM_STATUS_B1RSP: 1 when outbound brick 1 response queue is empty | |
| 48 | ROX | ROX | SM_STATUS_B2RSP: 1 when outbound brick 2 response queue is empty | |
| 49 | ROX | ROX | SM_STATUS_B3RSP: 1 when outbound brick 3 response queue is empty | |
| 50 | ROX | ROX | SM_STATUS_B4RSP: 1 when outbound brick 4 response queue is empty | |
| 51 | ROX | ROX | SM_STATUS_XARSP: 1 when outbound ATS/MISC response queue is empty | |
| 52 | ROX | ROX | SM_STATUS_FREE: 1 when Free state machine queue is empty | |
| 53 | ROX | ROX | SM_STATUS_DIRUPD: 1 when Directory-Update queue is empty | |
| 54 | ROX | ROX | SM_STATUS_SACOLL: 1 when Same-Address Collision-Check queue is empty | |
| 55:58 | ROX | ROX | SM_STATUS_MRBCP: Master-Retry backoff level for Chip-Pump commands | |
| 59:60 | ROX | ROX | SM_STATUS_PERF_LSTATE: Performance-counter Latency state | |
| 61:63 | ROX | ROX | SM_STATUS_RESERVED2: reserved | |
| c_err_rpt first-0 latches | ||||
|---|---|---|---|---|
| Addr: |
000000001101080F (SCOM) 0000000013400078 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.MCP.MISC.CERR_FIRST0 | |||
| Constant(s): | ||||
| Comments: | c_err_rpt first latches read-write-1-clear reg | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:55 | PAU3.CS.SM0.MCP.MISC.CERR_FIRST0_Q_0_INST.LATC.L2(0:55) [00000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_0: NVF0 s4: NVLink UT=0 to MMIO space bad cmd/length/alignment | |
| 1 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_1: NVF1 s4: UT=1 to MMIO space bad cmd/length/alignment | |
| 2 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_2: NVF2 s4: Target-Error/Unsupported-Request/Reserved Rsp_Status received in NVLink Response | |
| 3 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_3: NVF3 s4: Unexpected NVLink/OCAPI Response | |
| 4 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_4: NVF4 s4: Bad NV or OC response received (fence brick) | |
| 5 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_5: NVF5 s7: MCP_M_EVAL_DSA: illegal castout/.push arrives vs L2 directory state | |
| 6 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_6: NVF6 s4: Target-Error/Unsupported-Request/Reserved Rsp_Status received in NVLink Trans-Done Response | |
| 7 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_7: NVF7 s4: NVLink or OCAPI response timeout | |
| 8 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_8: NVF8 s4: Bad synonym_done received | |
| 9 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_9: NVF9 s4: OCAPI request to MMIO space bad cmd/length/alignment | |
| 10 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_10: NVF10 s4: DMA write/atomic to MMIO space w/ Data error | |
| 11 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_11: NVF11 s7: MCP_M_EVAL_DSA: Topology-index of the Request address is not valid in the topology-index table | |
| 12 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_12: NVF12 s7: MCP_M_EVAL_DSA: addr_error CResp to posted request | |
| 13 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_13: NVF13 (reserved) | |
| 14 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_14: NVF14 (reserved) | |
| 15 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_15: NVF15 NVLink NVF error for brick 0 occurred | |
| 16 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_16: NVF16 NVLink NVF error for brick 1 occurred | |
| 17 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_17: NVF17 NVLink NVF error for brick 2 occurred | |
| 18 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_18: NVF18 NVLink NVF error for brick 3 occurred | |
| 19 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_19: NVF19 NVLink NVF error for brick 4 occurred | |
| 20 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_ASBE_0: ASBE0 SBE ECC error detected from State-machine array | |
| 21 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_ASBE_1: ASBE1 SBE ECC error detected from Rq/Rs output queue array | |
| 22 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_ASBE_2: ASBE2 SBE ECC error detected from PowerBus data flit combiner array | |
| 23 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_ASBE_3: ASBE3 (reserved) | |
| 24 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_ASBE_4: ASBE4 SBE ECC error detected from L2-Directory SRAM 0 | |
| 25 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_ASBE_5: ASBE5 SBE ECC error detected from L2-Directory SRAM 1 | |
| 26 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_ASBE_6: ASBE6 SBE ECC error detected from L2-Directory SRAM 2 | |
| 27 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_ASBE_7: ASBE7 SBE ECC error detected from L2-Directory SRAM 3 | |
| 28 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBR_0: PBR0 s4: MCP_PC_WT_CRESP: abort_trm(_ed) cresp received to PAU request | |
| 29 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBR_1: PBR1 s4: MCP_PC_BK_WT_CRESP: abort_trm cresp received to PAU BKill request | |
| 30 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBR_2: PBR2 s4: Mis-aligned dma_pr_w/pr_dma_inj to AFU-MMIO space | |
| 31 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBR_3: PBR3 s4: rpt_hang.poll signalled hang condition | |
| 32 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBR_4: PBR4 s4: MCP_PC_WT_CRESP: Addr_Error received for self-lpc command (SSF) | |
| 33 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBR_5: PBR5 (reserved) | |
| 34 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBR_6: PBR6 (reserved) | |
| 35 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBR_7: PBR7 (reserved) | |
| 36 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_REG_0: REG0 s4: Address/Length/Alignment error on MMIO/GenId/Config access | |
| 37 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_REG_1: REG1 (reserved) | |
| 38 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_REG_2: REG2 (reserved) | |
| 39 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_REG_3: REG3 (reserved) | |
| 40 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_OCR_0: OCR0 s4: UT=0 to MMIO space bad cmd/length/alignment | |
| 41 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_OCR_1: OCR1 s4: Bad OC response received | |
| 42 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_OCR_2: OCR2 s4: AFU request w/ bad data received | |
| 43 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_OCR_3: OCR3 s4: Intrp_Req ObjHandle did not map to MMIO space | |
| 44 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_OCR_4: OCR4 s4: NVLink UT=0 to MMIO space bad cmd/length/alignment | |
| 45 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_OCR_5: OCR5 s4: UT=1 to MMIO space bad cmd/length/alignment | |
| 46 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_OCR_6: OCR6 s4: OCAPI request to MMIO space bad cmd/length/alignment | |
| 47 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_OCR_7: OCR7 s4: DMA write/atomic to MMIO space w/ Data error | |
| 48 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_OCR_8: OCR8 Epoch scanning did not complete before the next tick | |
| 49 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_OCR_9: OCR9 (reserved) | |
| 50 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_OCR_10: OCR10 (reserved) | |
| 51 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_OCR_11: OCR11 NVLink OCR error for brick 0 occurred | |
| 52 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_OCR_12: OCR12 NVLink OCR error for brick 1 occurred | |
| 53 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_OCR_13: OCR13 NVLink OCR error for brick 2 occurred | |
| 54 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_OCR_14: OCR14 NVLink OCR error for brick 3 occurred | |
| 55 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_OCR_15: OCR15 NVLink OCR error for brick 4 occurred | |
| 56:63 | RO | RO | constant=0b00000000 | |
| c_err_rpt first-1 latches | ||||
|---|---|---|---|---|
| Addr: |
0000000011010810 (SCOM) 0000000013400080 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.MCP.MISC.CERR_FIRST1 | |||
| Constant(s): | ||||
| Comments: | c_err_rpt first latches read-write-1-clear reg | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:35 | PAU3.CS.SM0.MCP.MISC.CERR_FIRST1_Q_0_INST.LATC.L2(0:35) [000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLGX_0: NLGX0 Unknown xtype in stage s0r of RXO pipe | |
| 1 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLGX_1: NLGX1 Unknown xtype in stage s2r of RXO pipe | |
| 2 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLGX_2: NLGX2 (reserved) | |
| 3 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLGX_3: NLGX3 (reserved) | |
| 4 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_FWD_0: FWD0 s4: Forward progress timer expired | |
| 5 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_FWD_1: FWD1 s4: rpt_hang.data waiting-for-data timeout | |
| 6 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_FWD_2: FWD2 (reserved) | |
| 7 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_FWD_3: FWD3 (reserved) | |
| 8 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_AUE_0: AUE0 UE ECC error detected from State-machine array | |
| 9 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_AUE_1: AUE1 UE ECC error detected from Rq/Rs output queue array | |
| 10 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_AUE_2: AUE2 UE ECC error detected from PowerBus data flit combiner array | |
| 11 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_AUE_3: AUE3 (reserved) | |
| 12 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_AUE_4: AUE4 UE ECC error detected from L2-Directory SRAM 0 | |
| 13 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_AUE_5: AUE5 UE ECC error detected from L2-Directory SRAM 1 | |
| 14 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_AUE_6: AUE6 UE ECC error detected from L2-Directory SRAM 2 | |
| 15 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_AUE_7: AUE7 UE ECC error detected from L2-Directory SRAM 3 | |
| 16 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBF_0: PBF0 s5: MCP_M_WT_CRESP: error cresp received for a command | |
| 17 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBF_1: PBF1 s5: MCP_PC_WT_CRESP: error cresp received for a command | |
| 18 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBF_2: PBF2 s4: MCP_PC_WT_CRESP: Addr_Error received for self-lpc command (SSF) | |
| 19 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBF_3: PBF3 s4: MCP_PC_BK_WT_CRESP: ack_dead cresp received for a bkill | |
| 20 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBF_4: PBF4 s5: MCP_M_RCV_DATA_PTL: not all segments/OWs were received | |
| 21 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBF_5: PBF5 s4: dma_pr_w/pr_dma_inj snooped that crosses 128B boundary | |
| 22 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBF_6: PBF6 s4: SMEV_DATIN: Received data with illegal data_stat value. | |
| 23 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBF_7: PBF7 Unexpected data beat received | |
| 24 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBF_8: PBF8 s7: addr_error CResp to internal PAU request | |
| 25 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBF_9: PBF9 (reserved) | |
| 26 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBF_10: PBF10 s5: Received 64B of data but snooped command wasn't cp_*(m=1) | |
| 27 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBF_11: PBF11 s5: Received 64B of data to PAU-mastered command | |
| 28 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_LDA_0: LDA0 s4: MCP_PC_WT_CRESP: Addr_Error received for load command (LD) | |
| 29 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_LDA_1: LDA1 (reserved) | |
| 30 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_LDA_2: LDA2 (reserved) | |
| 31 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_LDA_3: LDA3 (reserved) | |
| 32 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_STA_0: STA0 s4: MCP_PC_WT_CRESP: Addr_Error received for store command (ST) | |
| 33 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_STA_1: STA1 s4: MCP_PC_BK_WT_CRESP: Addr_Error received for bkill command (ST) | |
| 34 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_STA_2: STA2 (reserved) | |
| 35 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_STA_3: STA3 (reserved) | |
| 36:63 | RO | RO | constant=0b0000000000000000000000000000 | |
| c_err_rpt first-2 latches | ||||
|---|---|---|---|---|
| Addr: |
0000000011010811 (SCOM) 0000000013400088 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.MCP.MISC.CERR_FIRST2 | |||
| Constant(s): | ||||
| Comments: | c_err_rpt first latches read-write-1-clear reg | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM0.MCP.MISC.CERR_FIRST2_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_0: NLG0 s4: Rcmd Event received but state machine is not IDLE | |
| 1 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_1: NLG1 s4: Pocket-Hit event but not in MCP_M_PCKT_WAIT_HIT/PC_* state | |
| 2 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_2: NLG2 s4: MCP_M_WT_CRESP: ma_scresp table lookup missed | |
| 3 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_3: NLG3 s4: MCP_M_WT_CRESP: start epsilon, but epsilon already in progress | |
| 4 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_4: NLG4 s5: MCP_M_WT_CRESP: ma_scresp indicated 'evaporate' but have xTL modified data | |
| 5 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_5: NLG5 s5: MCP_M_WT_CRESP: ma_scresp indicated 'evaporate' but have PB modified data | |
| 6 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_6: NLG6 s5: MCP_M_WT_CRESP: bad scenario code from ma_scresp table | |
| 7 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_7: NLG7 s4: snoop Cresp received but not in MCP_M_WT_CRESP state | |
| 8 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_8: NLG8 s4: Dir-Lock Event received but state machine is not MCP_PC_WT_CRESP/MCP_M_WAIT_SYN_PEND/MCP_M_WAIT_DIR_LOCK or bad ttype | |
| 9 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_9: NLG9 s4: MCP_PC_WT_CRESP: ma_mcresp table lookup missed | |
| 10 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_10: NLG10 s4/5: MCP_PC/_BK/_WT_CRESP: Write coll state didn't match early protection state | |
| 11 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_11: NLG11 s4: MCP_PC_WT_CRESP: start epsilon, but epsilon already in progress | |
| 12 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_12: NLG12 s5: MCP_PC_WT_CRESP: bad scenario code from ma_mcresp table | |
| 13 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_13: NLG13 s4: MCP_PC_BK_WT_CRESP: bad next-step for bkill (ack-done) | |
| 14 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_14: NLG14 s4: MCP_PC_BK_WT_CRESP: bad next-step for bkill (retry) | |
| 15 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_15: NLG15 s4: MCP_PC_BK_WT_CRESP: bad cresp for a bkill | |
| 16 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_16: NLG16 s4: master Cresp received but not in MCP_PC_WT_CRESP/MCP_PC_BK_WT_CRESP states | |
| 17 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_17: NLG17 s4: M_IDLE: Invalid DATALEN[3:0] for NVLink data command | |
| 18 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_18: NLG18 s4: M_IDLE: Invalid command type received | |
| 19 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_19: NLG19 s4: AT-translate-Response event but not in wait-translate state | |
| 20 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_20: NLG20 s4: AT-translate-Response event had bad translate status, but cmd not recognized | |
| 21 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_21: NLG21 s4: SA-Done event but not in wait-SA state | |
| 22 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_22: NLG22 s4: MCP_PC_WAIT_DATADONE: bad next-step for PB data transmit | |
| 23 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_23: NLG23 s4: MCP_TD_WAIT_DATADONE: Unknown NVLink Master Command | |
| 24 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_24: NLG24 s4: BuffDone event but not in PB/PC/MG/NR/XATS/MCP_TD_WAIT_DATADONE state | |
| 25 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_25: NLG25 s4: MCP_NC_WT_RESP: Unknown nv-master command for NVLink response | |
| 26 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_26: NLG26 s4: RG-RspIn event but not in MCP_RG_WT_RESP or MCP_NC_WT_RESP* state | |
| 27 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_27: NLG27 s4: Epsilon-In-Progress, but epsilon counter clock is not the epsilon clock | |
| 28 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_28: NLG28 s4: Epsilon counter clock is 'epsilon' but epsilon_ip is not set | |
| 29 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_29: NLG29 s4: MCP_PC_WT_BK_RBACK: bad next-step for bkill | |
| 30 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_30: NLG30 s4: M/RR_BACK timer expired but not in PC_WT(_BK)_RBACK state | |
| 31 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_31: NLG31 s4: Bad epclock value | |
| 32 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_32: NLG32 s4: coll_state is POCKET_RCOLL_ND but master state is not PCKT_WAIT_HIT | |
| 33 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_33: NLG33 s7: Did not find anything to do for a MCMD_COH response | |
| 34 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_34: NLG34 s4: Unknown Event type received | |
| 35 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_35: NLG35 s4: SMEV_DIRDONE received but sm_dir_upd_pending=0 | |
| 36 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_36: NLG36 s7: MCP_M_EVAL_DSA: Unknown merge opcode from dsa table | |
| 37 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_37: NLG37 s7: Unknown State | |
| 38 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_38: NLG38 s4: coll_state is POCKET_RCOLL_OND but master state is not PCKT_WAIT_HIT | |
| 39 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_39: NLG39 s4: Unknown sm_master_state in ESCAN_FENCE event | |
| 40 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_40: NLG40 s4: MCP_FENCE_WT_RESP_FILL: Unknown nv-master command for Fence-Fill-SUE response | |
| 41 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_41: NLG41 s4: MCP_M_WT_CRESP: impossible command/cresp | |
| 42 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_42: NLG42 s4: MCP_PC_WT_CRESP: impossible command/cresp | |
| 43 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_43: NLG43 s7: MCP_M_EVAL_DSA: impossible command/state | |
| 44 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_44: NLG44 s7: Unexpected Error State (bad sub-sequence return) | |
| 45 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_45: NLG45 s5: sfstat-retry but not in retry-abbks collision state | |
| 46 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_46: NLG46 s5: *cond*-retry but not in retry-abbks collision state | |
| 47 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_47: NLG47 s4: Request from CTL/xTL caused bad MMIO alignment, but cmd not recognized | |
| 48 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_48: NLG48 s5: MCP_NC_EXE_RESP: Unknown nv-master command for NVLink response | |
| 49 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_49: NLG49 s7: MCP_M_EVAL_DSA: Topology-index of the Request address is not valid in the topology-index table | |
| 50 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_50: NLG50 s4: Request from CTL/xTL caused bad MMIO alignment, but cmd not recognized | |
| 51 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_51: NLG51 s4: Request from CTL/xTL loaded into non-idle state-machine | |
| 52 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_52: NLG52 s4: POCKET-HIT event but coll_state is not POCKET_WINNER* | |
| 53 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_53: NLG53 s4: Unknown rspin event w/ unknown master-command in MCP_RG_WT_RESP state | |
| 54 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_54: NLG54 s7: Attempt to send PBus request but config_enable_pbus=0 | |
| 55 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_55: NLG55 s4: Invalid SrcBus on response from CTL | |
| 56 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_56: NLG56 s4: Shoulder-tap event but not in MCP_M_WT_SHOULDER_TAP state | |
| 57 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_57: NLG57 s7: MCP_M_EVAL_DSA: ma_dsasfe table lookup missed | |
| 58 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_58: NLG58 s7: MCP_M_EVAL_DSA: ma_dsac2alc table lookup missed | |
| 59 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_59: NLG59 s7: MCP_M_EVAL_DSA: ma_dsac2co table lookup missed | |
| 60 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_60: NLG60 s7: MCP_M_EVAL_DSA: ma_dsaoth table lookup missed | |
| 61 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_61: NLG61 s7: MCP_M_EVAL_DSA: ma_dsascan table lookup missed | |
| 62 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_62: NLG62 s7: Nothing to do after looking in DSA table | |
| 63 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_63: NLG63 s7: coherence update/response but directory lock is not DLOCK_MOD | |
| c_err_rpt mask-0 latches | ||||
|---|---|---|---|---|
| Addr: |
0000000011010812 (SCOM) 0000000013400090 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.MCP.MISC.CERR_MASK0 | |||
| Constant(s): | ||||
| Comments: | c_err_rpt mask reg Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:55 | PAU3.CS.SM0.MCP.MISC.CERR_MASK0_Q_0_INST.LATC.L2(0:55) [00000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | IDIAL_MCP_MASK_NVF_0: NVF0 s4: NVLink UT=0 to MMIO space bad cmd/length/alignment | |
| 1 | RW | RW | IDIAL_MCP_MASK_NVF_1: NVF1 s4: UT=1 to MMIO space bad cmd/length/alignment | |
| 2 | RW | RW | IDIAL_MCP_MASK_NVF_2: NVF2 s4: Target-Error/Unsupported-Request/Reserved Rsp_Status received in NVLink Response | |
| 3 | RW | RW | IDIAL_MCP_MASK_NVF_3: NVF3 s4: Unexpected NVLink/OCAPI Response | |
| 4 | RW | RW | IDIAL_MCP_MASK_NVF_4: NVF4 s4: Bad NV or OC response received (fence brick) | |
| 5 | RW | RW | IDIAL_MCP_MASK_NVF_5: NVF5 s7: MCP_M_EVAL_DSA: illegal castout/.push arrives vs L2 directory state | |
| 6 | RW | RW | IDIAL_MCP_MASK_NVF_6: NVF6 s4: Target-Error/Unsupported-Request/Reserved Rsp_Status received in NVLink Trans-Done Response | |
| 7 | RW | RW | IDIAL_MCP_MASK_NVF_7: NVF7 s4: NVLink or OCAPI response timeout | |
| 8 | RW | RW | IDIAL_MCP_MASK_NVF_8: NVF8 s4: Bad synonym_done received | |
| 9 | RW | RW | IDIAL_MCP_MASK_NVF_9: NVF9 s4: OCAPI request to MMIO space bad cmd/length/alignment | |
| 10 | RW | RW | IDIAL_MCP_MASK_NVF_10: NVF10 s4: DMA write/atomic to MMIO space w/ Data error | |
| 11 | RW | RW | IDIAL_MCP_MASK_NVF_11: NVF11 s7: MCP_M_EVAL_DSA: Topology-index of the Request address is not valid in the topology-index table | |
| 12 | RW | RW | IDIAL_MCP_MASK_NVF_12: NVF12 s7: MCP_M_EVAL_DSA: addr_error CResp to posted request | |
| 13 | RW | RW | IDIAL_MCP_MASK_NVF_13: NVF13 (reserved) | |
| 14 | RW | RW | IDIAL_MCP_MASK_NVF_14: NVF14 (reserved) | |
| 15 | RW | RW | IDIAL_MCP_MASK_NVF_15: NVF15 NVLink NVF error for brick 0 occurred | |
| 16 | RW | RW | IDIAL_MCP_MASK_NVF_16: NVF16 NVLink NVF error for brick 1 occurred | |
| 17 | RW | RW | IDIAL_MCP_MASK_NVF_17: NVF17 NVLink NVF error for brick 2 occurred | |
| 18 | RW | RW | IDIAL_MCP_MASK_NVF_18: NVF18 NVLink NVF error for brick 3 occurred | |
| 19 | RW | RW | IDIAL_MCP_MASK_NVF_19: NVF19 NVLink NVF error for brick 4 occurred | |
| 20 | RW | RW | IDIAL_MCP_MASK_ASBE_0: ASBE0 SBE ECC error detected from State-machine array | |
| 21 | RW | RW | IDIAL_MCP_MASK_ASBE_1: ASBE1 SBE ECC error detected from Rq/Rs output queue array | |
| 22 | RW | RW | IDIAL_MCP_MASK_ASBE_2: ASBE2 SBE ECC error detected from PowerBus data flit combiner array | |
| 23 | RW | RW | IDIAL_MCP_MASK_ASBE_3: ASBE3 (reserved) | |
| 24 | RW | RW | IDIAL_MCP_MASK_ASBE_4: ASBE4 SBE ECC error detected from L2-Directory SRAM 0 | |
| 25 | RW | RW | IDIAL_MCP_MASK_ASBE_5: ASBE5 SBE ECC error detected from L2-Directory SRAM 1 | |
| 26 | RW | RW | IDIAL_MCP_MASK_ASBE_6: ASBE6 SBE ECC error detected from L2-Directory SRAM 2 | |
| 27 | RW | RW | IDIAL_MCP_MASK_ASBE_7: ASBE7 SBE ECC error detected from L2-Directory SRAM 3 | |
| 28 | RW | RW | IDIAL_MCP_MASK_PBR_0: PBR0 s4: MCP_PC_WT_CRESP: abort_trm(_ed) cresp received to PAU request | |
| 29 | RW | RW | IDIAL_MCP_MASK_PBR_1: PBR1 s4: MCP_PC_BK_WT_CRESP: abort_trm cresp received to PAU BKill request | |
| 30 | RW | RW | IDIAL_MCP_MASK_PBR_2: PBR2 s4: Mis-aligned dma_pr_w/pr_dma_inj to AFU-MMIO space | |
| 31 | RW | RW | IDIAL_MCP_MASK_PBR_3: PBR3 s4: rpt_hang.poll signalled hang condition | |
| 32 | RW | RW | IDIAL_MCP_MASK_PBR_4: PBR4 s4: MCP_PC_WT_CRESP: Addr_Error received for self-lpc command (SSF) | |
| 33 | RW | RW | IDIAL_MCP_MASK_PBR_5: PBR5 (reserved) | |
| 34 | RW | RW | IDIAL_MCP_MASK_PBR_6: PBR6 (reserved) | |
| 35 | RW | RW | IDIAL_MCP_MASK_PBR_7: PBR7 (reserved) | |
| 36 | RW | RW | IDIAL_MCP_MASK_REG_0: REG0 s4: Address/Length/Alignment error on MMIO/GenId/Config access | |
| 37 | RW | RW | IDIAL_MCP_MASK_REG_1: REG1 (reserved) | |
| 38 | RW | RW | IDIAL_MCP_MASK_REG_2: REG2 (reserved) | |
| 39 | RW | RW | IDIAL_MCP_MASK_REG_3: REG3 (reserved) | |
| 40 | RW | RW | IDIAL_MCP_MASK_OCR_0: OCR0 s4: UT=0 to MMIO space bad cmd/length/alignment | |
| 41 | RW | RW | IDIAL_MCP_MASK_OCR_1: OCR1 s4: Bad OC response received | |
| 42 | RW | RW | IDIAL_MCP_MASK_OCR_2: OCR2 s4: AFU request w/ bad data received | |
| 43 | RW | RW | IDIAL_MCP_MASK_OCR_3: OCR3 s4: Intrp_Req ObjHandle did not map to MMIO space | |
| 44 | RW | RW | IDIAL_MCP_MASK_OCR_4: OCR4 s4: NVLink UT=0 to MMIO space bad cmd/length/alignment | |
| 45 | RW | RW | IDIAL_MCP_MASK_OCR_5: OCR5 s4: UT=1 to MMIO space bad cmd/length/alignment | |
| 46 | RW | RW | IDIAL_MCP_MASK_OCR_6: OCR6 s4: OCAPI request to MMIO space bad cmd/length/alignment | |
| 47 | RW | RW | IDIAL_MCP_MASK_OCR_7: OCR7 s4: DMA write/atomic to MMIO space w/ Data error | |
| 48 | RW | RW | IDIAL_MCP_MASK_OCR_8: OCR8 Epoch scanning did not complete before the next tick | |
| 49 | RW | RW | IDIAL_MCP_MASK_OCR_9: OCR9 (reserved) | |
| 50 | RW | RW | IDIAL_MCP_MASK_OCR_10: OCR10 (reserved) | |
| 51 | RW | RW | IDIAL_MCP_MASK_OCR_11: OCR11 NVLink OCR error for brick 0 occurred | |
| 52 | RW | RW | IDIAL_MCP_MASK_OCR_12: OCR12 NVLink OCR error for brick 1 occurred | |
| 53 | RW | RW | IDIAL_MCP_MASK_OCR_13: OCR13 NVLink OCR error for brick 2 occurred | |
| 54 | RW | RW | IDIAL_MCP_MASK_OCR_14: OCR14 NVLink OCR error for brick 3 occurred | |
| 55 | RW | RW | IDIAL_MCP_MASK_OCR_15: OCR15 NVLink OCR error for brick 4 occurred | |
| 56:63 | RO | RO | constant=0b00000000 | |
| c_err_rpt mask-1 latches | ||||
|---|---|---|---|---|
| Addr: |
0000000011010813 (SCOM) 0000000013400098 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.MCP.MISC.CERR_MASK1 | |||
| Constant(s): | ||||
| Comments: | c_err_rpt mask reg Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:35 | PAU3.CS.SM0.MCP.MISC.CERR_MASK1_Q_0_INST.LATC.L2(0:35) [000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | IDIAL_MCP_MASK_NLGX_0: NLGX0 Unknown xtype in stage s0r of RXO pipe | |
| 1 | RW | RW | IDIAL_MCP_MASK_NLGX_1: NLGX1 Unknown xtype in stage s2r of RXO pipe | |
| 2 | RW | RW | IDIAL_MCP_MASK_NLGX_2: NLGX2 (reserved) | |
| 3 | RW | RW | IDIAL_MCP_MASK_NLGX_3: NLGX3 (reserved) | |
| 4 | RW | RW | IDIAL_MCP_MASK_FWD_0: FWD0 s4: Forward progress timer expired | |
| 5 | RW | RW | IDIAL_MCP_MASK_FWD_1: FWD1 s4: rpt_hang.data waiting-for-data timeout | |
| 6 | RW | RW | IDIAL_MCP_MASK_FWD_2: FWD2 (reserved) | |
| 7 | RW | RW | IDIAL_MCP_MASK_FWD_3: FWD3 (reserved) | |
| 8 | RW | RW | IDIAL_MCP_MASK_AUE_0: AUE0 UE ECC error detected from State-machine array | |
| 9 | RW | RW | IDIAL_MCP_MASK_AUE_1: AUE1 UE ECC error detected from Rq/Rs output queue array | |
| 10 | RW | RW | IDIAL_MCP_MASK_AUE_2: AUE2 UE ECC error detected from PowerBus data flit combiner array | |
| 11 | RW | RW | IDIAL_MCP_MASK_AUE_3: AUE3 (reserved) | |
| 12 | RW | RW | IDIAL_MCP_MASK_AUE_4: AUE4 UE ECC error detected from L2-Directory SRAM 0 | |
| 13 | RW | RW | IDIAL_MCP_MASK_AUE_5: AUE5 UE ECC error detected from L2-Directory SRAM 1 | |
| 14 | RW | RW | IDIAL_MCP_MASK_AUE_6: AUE6 UE ECC error detected from L2-Directory SRAM 2 | |
| 15 | RW | RW | IDIAL_MCP_MASK_AUE_7: AUE7 UE ECC error detected from L2-Directory SRAM 3 | |
| 16 | RW | RW | IDIAL_MCP_MASK_PBF_0: PBF0 s5: MCP_M_WT_CRESP: error cresp received for a command | |
| 17 | RW | RW | IDIAL_MCP_MASK_PBF_1: PBF1 s5: MCP_PC_WT_CRESP: error cresp received for a command | |
| 18 | RW | RW | IDIAL_MCP_MASK_PBF_2: PBF2 s4: MCP_PC_WT_CRESP: Addr_Error received for self-lpc command (SSF) | |
| 19 | RW | RW | IDIAL_MCP_MASK_PBF_3: PBF3 s4: MCP_PC_BK_WT_CRESP: ack_dead cresp received for a bkill | |
| 20 | RW | RW | IDIAL_MCP_MASK_PBF_4: PBF4 s5: MCP_M_RCV_DATA_PTL: not all segments/OWs were received | |
| 21 | RW | RW | IDIAL_MCP_MASK_PBF_5: PBF5 s4: dma_pr_w/pr_dma_inj snooped that crosses 128B boundary | |
| 22 | RW | RW | IDIAL_MCP_MASK_PBF_6: PBF6 s4: SMEV_DATIN: Received data with illegal data_stat value. | |
| 23 | RW | RW | IDIAL_MCP_MASK_PBF_7: PBF7 Unexpected data beat received | |
| 24 | RW | RW | IDIAL_MCP_MASK_PBF_8: PBF8 s7: addr_error CResp to internal PAU request | |
| 25 | RW | RW | IDIAL_MCP_MASK_PBF_9: PBF9 (reserved) | |
| 26 | RW | RW | IDIAL_MCP_MASK_PBF_10: PBF10 s5: Received 64B of data but snooped command wasn't cp_*(m=1) | |
| 27 | RW | RW | IDIAL_MCP_MASK_PBF_11: PBF11 s5: Received 64B of data to PAU-mastered command | |
| 28 | RW | RW | IDIAL_MCP_MASK_LDA_0: LDA0 s4: MCP_PC_WT_CRESP: Addr_Error received for load command (LD) | |
| 29 | RW | RW | IDIAL_MCP_MASK_LDA_1: LDA1 (reserved) | |
| 30 | RW | RW | IDIAL_MCP_MASK_LDA_2: LDA2 (reserved) | |
| 31 | RW | RW | IDIAL_MCP_MASK_LDA_3: LDA3 (reserved) | |
| 32 | RW | RW | IDIAL_MCP_MASK_STA_0: STA0 s4: MCP_PC_WT_CRESP: Addr_Error received for store command (ST) | |
| 33 | RW | RW | IDIAL_MCP_MASK_STA_1: STA1 s4: MCP_PC_BK_WT_CRESP: Addr_Error received for bkill command (ST) | |
| 34 | RW | RW | IDIAL_MCP_MASK_STA_2: STA2 (reserved) | |
| 35 | RW | RW | IDIAL_MCP_MASK_STA_3: STA3 (reserved) | |
| 36:63 | RO | RO | constant=0b0000000000000000000000000000 | |
| c_err_rpt mask-2 latches | ||||
|---|---|---|---|---|
| Addr: |
0000000011010814 (SCOM) 00000000134000A0 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.MCP.MISC.CERR_MASK2 | |||
| Constant(s): | ||||
| Comments: | c_err_rpt mask reg Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM0.MCP.MISC.CERR_MASK2_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | IDIAL_MCP_MASK_NLG_0: NLG0 s4: Rcmd Event received but state machine is not IDLE | |
| 1 | RW | RW | IDIAL_MCP_MASK_NLG_1: NLG1 s4: Pocket-Hit event but not in MCP_M_PCKT_WAIT_HIT/PC_* state | |
| 2 | RW | RW | IDIAL_MCP_MASK_NLG_2: NLG2 s4: MCP_M_WT_CRESP: ma_scresp table lookup missed | |
| 3 | RW | RW | IDIAL_MCP_MASK_NLG_3: NLG3 s4: MCP_M_WT_CRESP: start epsilon, but epsilon already in progress | |
| 4 | RW | RW | IDIAL_MCP_MASK_NLG_4: NLG4 s5: MCP_M_WT_CRESP: ma_scresp indicated 'evaporate' but have xTL modified data | |
| 5 | RW | RW | IDIAL_MCP_MASK_NLG_5: NLG5 s5: MCP_M_WT_CRESP: ma_scresp indicated 'evaporate' but have PB modified data | |
| 6 | RW | RW | IDIAL_MCP_MASK_NLG_6: NLG6 s5: MCP_M_WT_CRESP: bad scenario code from ma_scresp table | |
| 7 | RW | RW | IDIAL_MCP_MASK_NLG_7: NLG7 s4: snoop Cresp received but not in MCP_M_WT_CRESP state | |
| 8 | RW | RW | IDIAL_MCP_MASK_NLG_8: NLG8 s4: Dir-Lock Event received but state machine is not MCP_PC_WT_CRESP/MCP_M_WAIT_SYN_PEND/MCP_M_WAIT_DIR_LOCK or bad ttype | |
| 9 | RW | RW | IDIAL_MCP_MASK_NLG_9: NLG9 s4: MCP_PC_WT_CRESP: ma_mcresp table lookup missed | |
| 10 | RW | RW | IDIAL_MCP_MASK_NLG_10: NLG10 s4/5: MCP_PC/_BK/_WT_CRESP: Write coll state didn't match early protection state | |
| 11 | RW | RW | IDIAL_MCP_MASK_NLG_11: NLG11 s4: MCP_PC_WT_CRESP: start epsilon, but epsilon already in progress | |
| 12 | RW | RW | IDIAL_MCP_MASK_NLG_12: NLG12 s5: MCP_PC_WT_CRESP: bad scenario code from ma_mcresp table | |
| 13 | RW | RW | IDIAL_MCP_MASK_NLG_13: NLG13 s4: MCP_PC_BK_WT_CRESP: bad next-step for bkill (ack-done) | |
| 14 | RW | RW | IDIAL_MCP_MASK_NLG_14: NLG14 s4: MCP_PC_BK_WT_CRESP: bad next-step for bkill (retry) | |
| 15 | RW | RW | IDIAL_MCP_MASK_NLG_15: NLG15 s4: MCP_PC_BK_WT_CRESP: bad cresp for a bkill | |
| 16 | RW | RW | IDIAL_MCP_MASK_NLG_16: NLG16 s4: master Cresp received but not in MCP_PC_WT_CRESP/MCP_PC_BK_WT_CRESP states | |
| 17 | RW | RW | IDIAL_MCP_MASK_NLG_17: NLG17 s4: M_IDLE: Invalid DATALEN[3:0] for NVLink data command | |
| 18 | RW | RW | IDIAL_MCP_MASK_NLG_18: NLG18 s4: M_IDLE: Invalid command type received | |
| 19 | RW | RW | IDIAL_MCP_MASK_NLG_19: NLG19 s4: AT-translate-Response event but not in wait-translate state | |
| 20 | RW | RW | IDIAL_MCP_MASK_NLG_20: NLG20 s4: AT-translate-Response event had bad translate status, but cmd not recognized | |
| 21 | RW | RW | IDIAL_MCP_MASK_NLG_21: NLG21 s4: SA-Done event but not in wait-SA state | |
| 22 | RW | RW | IDIAL_MCP_MASK_NLG_22: NLG22 s4: MCP_PC_WAIT_DATADONE: bad next-step for PB data transmit | |
| 23 | RW | RW | IDIAL_MCP_MASK_NLG_23: NLG23 s4: MCP_TD_WAIT_DATADONE: Unknown NVLink Master Command | |
| 24 | RW | RW | IDIAL_MCP_MASK_NLG_24: NLG24 s4: BuffDone event but not in PB/PC/MG/NR/XATS/MCP_TD_WAIT_DATADONE state | |
| 25 | RW | RW | IDIAL_MCP_MASK_NLG_25: NLG25 s4: MCP_NC_WT_RESP: Unknown nv-master command for NVLink response | |
| 26 | RW | RW | IDIAL_MCP_MASK_NLG_26: NLG26 s4: RG-RspIn event but not in MCP_RG_WT_RESP or MCP_NC_WT_RESP* state | |
| 27 | RW | RW | IDIAL_MCP_MASK_NLG_27: NLG27 s4: Epsilon-In-Progress, but epsilon counter clock is not the epsilon clock | |
| 28 | RW | RW | IDIAL_MCP_MASK_NLG_28: NLG28 s4: Epsilon counter clock is 'epsilon' but epsilon_ip is not set | |
| 29 | RW | RW | IDIAL_MCP_MASK_NLG_29: NLG29 s4: MCP_PC_WT_BK_RBACK: bad next-step for bkill | |
| 30 | RW | RW | IDIAL_MCP_MASK_NLG_30: NLG30 s4: M/RR_BACK timer expired but not in PC_WT(_BK)_RBACK state | |
| 31 | RW | RW | IDIAL_MCP_MASK_NLG_31: NLG31 s4: Bad epclock value | |
| 32 | RW | RW | IDIAL_MCP_MASK_NLG_32: NLG32 s4: coll_state is POCKET_RCOLL_ND but master state is not PCKT_WAIT_HIT | |
| 33 | RW | RW | IDIAL_MCP_MASK_NLG_33: NLG33 s7: Did not find anything to do for a MCMD_COH response | |
| 34 | RW | RW | IDIAL_MCP_MASK_NLG_34: NLG34 s4: Unknown Event type received | |
| 35 | RW | RW | IDIAL_MCP_MASK_NLG_35: NLG35 s4: SMEV_DIRDONE received but sm_dir_upd_pending=0 | |
| 36 | RW | RW | IDIAL_MCP_MASK_NLG_36: NLG36 s7: MCP_M_EVAL_DSA: Unknown merge opcode from dsa table | |
| 37 | RW | RW | IDIAL_MCP_MASK_NLG_37: NLG37 s7: Unknown State | |
| 38 | RW | RW | IDIAL_MCP_MASK_NLG_38: NLG38 s4: coll_state is POCKET_RCOLL_OND but master state is not PCKT_WAIT_HIT | |
| 39 | RW | RW | IDIAL_MCP_MASK_NLG_39: NLG39 s4: Unknown sm_master_state in ESCAN_FENCE event | |
| 40 | RW | RW | IDIAL_MCP_MASK_NLG_40: NLG40 s4: MCP_FENCE_WT_RESP_FILL: Unknown nv-master command for Fence-Fill-SUE response | |
| 41 | RW | RW | IDIAL_MCP_MASK_NLG_41: NLG41 s4: MCP_M_WT_CRESP: impossible command/cresp | |
| 42 | RW | RW | IDIAL_MCP_MASK_NLG_42: NLG42 s4: MCP_PC_WT_CRESP: impossible command/cresp | |
| 43 | RW | RW | IDIAL_MCP_MASK_NLG_43: NLG43 s7: MCP_M_EVAL_DSA: impossible command/state | |
| 44 | RW | RW | IDIAL_MCP_MASK_NLG_44: NLG44 s7: Unexpected Error State (bad sub-sequence return) | |
| 45 | RW | RW | IDIAL_MCP_MASK_NLG_45: NLG45 s5: sfstat-retry but not in retry-abbks collision state | |
| 46 | RW | RW | IDIAL_MCP_MASK_NLG_46: NLG46 s5: *cond*-retry but not in retry-abbks collision state | |
| 47 | RW | RW | IDIAL_MCP_MASK_NLG_47: NLG47 s4: Request from CTL/xTL caused bad MMIO alignment, but cmd not recognized | |
| 48 | RW | RW | IDIAL_MCP_MASK_NLG_48: NLG48 s5: MCP_NC_EXE_RESP: Unknown nv-master command for NVLink response | |
| 49 | RW | RW | IDIAL_MCP_MASK_NLG_49: NLG49 s7: MCP_M_EVAL_DSA: Topology-index of the Request address is not valid in the topology-index table | |
| 50 | RW | RW | IDIAL_MCP_MASK_NLG_50: NLG50 s4: Request from CTL/xTL caused bad MMIO alignment, but cmd not recognized | |
| 51 | RW | RW | IDIAL_MCP_MASK_NLG_51: NLG51 s4: Request from CTL/xTL loaded into non-idle state-machine | |
| 52 | RW | RW | IDIAL_MCP_MASK_NLG_52: NLG52 s4: POCKET-HIT event but coll_state is not POCKET_WINNER* | |
| 53 | RW | RW | IDIAL_MCP_MASK_NLG_53: NLG53 s4: Unknown rspin event w/ unknown master-command in MCP_RG_WT_RESP state | |
| 54 | RW | RW | IDIAL_MCP_MASK_NLG_54: NLG54 s7: Attempt to send PBus request but config_enable_pbus=0 | |
| 55 | RW | RW | IDIAL_MCP_MASK_NLG_55: NLG55 s4: Invalid SrcBus on response from CTL | |
| 56 | RW | RW | IDIAL_MCP_MASK_NLG_56: NLG56 s4: Shoulder-tap event but not in MCP_M_WT_SHOULDER_TAP state | |
| 57 | RW | RW | IDIAL_MCP_MASK_NLG_57: NLG57 s7: MCP_M_EVAL_DSA: ma_dsasfe table lookup missed | |
| 58 | RW | RW | IDIAL_MCP_MASK_NLG_58: NLG58 s7: MCP_M_EVAL_DSA: ma_dsac2alc table lookup missed | |
| 59 | RW | RW | IDIAL_MCP_MASK_NLG_59: NLG59 s7: MCP_M_EVAL_DSA: ma_dsac2co table lookup missed | |
| 60 | RW | RW | IDIAL_MCP_MASK_NLG_60: NLG60 s7: MCP_M_EVAL_DSA: ma_dsaoth table lookup missed | |
| 61 | RW | RW | IDIAL_MCP_MASK_NLG_61: NLG61 s7: MCP_M_EVAL_DSA: ma_dsascan table lookup missed | |
| 62 | RW | RW | IDIAL_MCP_MASK_NLG_62: NLG62 s7: Nothing to do after looking in DSA table | |
| 63 | RW | RW | IDIAL_MCP_MASK_NLG_63: NLG63 s7: coherence update/response but directory lock is not DLOCK_MOD | |
| c_err_rpt hold-0 latches | ||||
|---|---|---|---|---|
| Addr: |
0000000011010815 (SCOM) 00000000134000A8 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.MCP.MISC.CERR_HOLD0 | |||
| Constant(s): | ||||
| Comments: | c_err_rpt hold latches read-write-clear reg | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:19 | PAU3.CS.SM0.MCP.MISC.CERPT_NVF.HOLD_LATCH_INST.HOLD.LATC.L2(0:19) [00000000000000000000] | |||
| 20:27 | PAU3.CS.SM0.MCP.MISC.CERPT_ASBE.HOLD_LATCH_INST.HOLD.LATC.L2(0:7) [00000000] | |||
| 28:35 | PAU3.CS.SM0.MCP.MISC.CERPT_PBR.HOLD_LATCH_INST.HOLD.LATC.L2(0:7) [00000000] | |||
| 36:39 | PAU3.CS.SM0.MCP.MISC.CERPT_REG.HOLD_LATCH_INST.HOLD.LATC.L2(0:3) [0000] | |||
| 40:55 | PAU3.CS.SM0.MCP.MISC.CERPT_OCR.HOLD_LATCH_INST.HOLD.LATC.L2(0:15) [0000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_0: NVF0 s4: NVLink UT=0 to MMIO space bad cmd/length/alignment | |
| 1 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_1: NVF1 s4: UT=1 to MMIO space bad cmd/length/alignment | |
| 2 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_2: NVF2 s4: Target-Error/Unsupported-Request/Reserved Rsp_Status received in NVLink Response | |
| 3 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_3: NVF3 s4: Unexpected NVLink/OCAPI Response | |
| 4 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_4: NVF4 s4: Bad NV or OC response received (fence brick) | |
| 5 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_5: NVF5 s7: MCP_M_EVAL_DSA: illegal castout/.push arrives vs L2 directory state | |
| 6 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_6: NVF6 s4: Target-Error/Unsupported-Request/Reserved Rsp_Status received in NVLink Trans-Done Response | |
| 7 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_7: NVF7 s4: NVLink or OCAPI response timeout | |
| 8 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_8: NVF8 s4: Bad synonym_done received | |
| 9 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_9: NVF9 s4: OCAPI request to MMIO space bad cmd/length/alignment | |
| 10 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_10: NVF10 s4: DMA write/atomic to MMIO space w/ Data error | |
| 11 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_11: NVF11 s7: MCP_M_EVAL_DSA: Topology-index of the Request address is not valid in the topology-index table | |
| 12 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_12: NVF12 s7: MCP_M_EVAL_DSA: addr_error CResp to posted request | |
| 13 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_13: NVF13 (reserved) | |
| 14 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_14: NVF14 (reserved) | |
| 15 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_15: NVF15 NVLink NVF error for brick 0 occurred | |
| 16 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_16: NVF16 NVLink NVF error for brick 1 occurred | |
| 17 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_17: NVF17 NVLink NVF error for brick 2 occurred | |
| 18 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_18: NVF18 NVLink NVF error for brick 3 occurred | |
| 19 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_19: NVF19 NVLink NVF error for brick 4 occurred | |
| 20 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_ASBE_0: ASBE0 SBE ECC error detected from State-machine array | |
| 21 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_ASBE_1: ASBE1 SBE ECC error detected from Rq/Rs output queue array | |
| 22 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_ASBE_2: ASBE2 SBE ECC error detected from PowerBus data flit combiner array | |
| 23 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_ASBE_3: ASBE3 (reserved) | |
| 24 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_ASBE_4: ASBE4 SBE ECC error detected from L2-Directory SRAM 0 | |
| 25 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_ASBE_5: ASBE5 SBE ECC error detected from L2-Directory SRAM 1 | |
| 26 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_ASBE_6: ASBE6 SBE ECC error detected from L2-Directory SRAM 2 | |
| 27 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_ASBE_7: ASBE7 SBE ECC error detected from L2-Directory SRAM 3 | |
| 28 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBR_0: PBR0 s4: MCP_PC_WT_CRESP: abort_trm(_ed) cresp received to PAU request | |
| 29 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBR_1: PBR1 s4: MCP_PC_BK_WT_CRESP: abort_trm cresp received to PAU BKill request | |
| 30 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBR_2: PBR2 s4: Mis-aligned dma_pr_w/pr_dma_inj to AFU-MMIO space | |
| 31 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBR_3: PBR3 s4: rpt_hang.poll signalled hang condition | |
| 32 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBR_4: PBR4 s4: MCP_PC_WT_CRESP: Addr_Error received for self-lpc command (SSF) | |
| 33 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBR_5: PBR5 (reserved) | |
| 34 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBR_6: PBR6 (reserved) | |
| 35 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBR_7: PBR7 (reserved) | |
| 36 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_REG_0: REG0 s4: Address/Length/Alignment error on MMIO/GenId/Config access | |
| 37 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_REG_1: REG1 (reserved) | |
| 38 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_REG_2: REG2 (reserved) | |
| 39 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_REG_3: REG3 (reserved) | |
| 40 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_OCR_0: OCR0 s4: UT=0 to MMIO space bad cmd/length/alignment | |
| 41 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_OCR_1: OCR1 s4: Bad OC response received | |
| 42 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_OCR_2: OCR2 s4: AFU request w/ bad data received | |
| 43 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_OCR_3: OCR3 s4: Intrp_Req ObjHandle did not map to MMIO space | |
| 44 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_OCR_4: OCR4 s4: NVLink UT=0 to MMIO space bad cmd/length/alignment | |
| 45 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_OCR_5: OCR5 s4: UT=1 to MMIO space bad cmd/length/alignment | |
| 46 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_OCR_6: OCR6 s4: OCAPI request to MMIO space bad cmd/length/alignment | |
| 47 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_OCR_7: OCR7 s4: DMA write/atomic to MMIO space w/ Data error | |
| 48 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_OCR_8: OCR8 Epoch scanning did not complete before the next tick | |
| 49 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_OCR_9: OCR9 (reserved) | |
| 50 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_OCR_10: OCR10 (reserved) | |
| 51 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_OCR_11: OCR11 NVLink OCR error for brick 0 occurred | |
| 52 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_OCR_12: OCR12 NVLink OCR error for brick 1 occurred | |
| 53 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_OCR_13: OCR13 NVLink OCR error for brick 2 occurred | |
| 54 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_OCR_14: OCR14 NVLink OCR error for brick 3 occurred | |
| 55 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_OCR_15: OCR15 NVLink OCR error for brick 4 occurred | |
| 56:63 | RO | RO | constant=0b00000000 | |
| c_err_rpt hold-1 latches | ||||
|---|---|---|---|---|
| Addr: |
0000000011010816 (SCOM) 00000000134000B0 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.MCP.MISC.CERR_HOLD1 | |||
| Constant(s): | ||||
| Comments: | c_err_rpt hold latches read-write-clear reg | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:3 | PAU3.CS.SM0.MCP.MISC.CERPT_NLGX.HOLD_LATCH_INST.HOLD.LATC.L2(0:3) [0000] | |||
| 4:7 | PAU3.CS.SM0.MCP.MISC.CERPT_FWD.HOLD_LATCH_INST.HOLD.LATC.L2(0:3) [0000] | |||
| 8:15 | PAU3.CS.SM0.MCP.MISC.CERPT_AUE.HOLD_LATCH_INST.HOLD.LATC.L2(0:7) [00000000] | |||
| 16:27 | PAU3.CS.SM0.MCP.MISC.CERPT_PBF.HOLD_LATCH_INST.HOLD.LATC.L2(0:11) [000000000000] | |||
| 28:31 | PAU3.CS.SM0.MCP.MISC.CERPT_LDA.HOLD_LATCH_INST.HOLD.LATC.L2(0:3) [0000] | |||
| 32:35 | PAU3.CS.SM0.MCP.MISC.CERPT_STA.HOLD_LATCH_INST.HOLD.LATC.L2(0:3) [0000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLGX_0: NLGX0 Unknown xtype in stage s0r of RXO pipe | |
| 1 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLGX_1: NLGX1 Unknown xtype in stage s2r of RXO pipe | |
| 2 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLGX_2: NLGX2 (reserved) | |
| 3 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLGX_3: NLGX3 (reserved) | |
| 4 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_FWD_0: FWD0 s4: Forward progress timer expired | |
| 5 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_FWD_1: FWD1 s4: rpt_hang.data waiting-for-data timeout | |
| 6 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_FWD_2: FWD2 (reserved) | |
| 7 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_FWD_3: FWD3 (reserved) | |
| 8 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_AUE_0: AUE0 UE ECC error detected from State-machine array | |
| 9 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_AUE_1: AUE1 UE ECC error detected from Rq/Rs output queue array | |
| 10 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_AUE_2: AUE2 UE ECC error detected from PowerBus data flit combiner array | |
| 11 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_AUE_3: AUE3 (reserved) | |
| 12 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_AUE_4: AUE4 UE ECC error detected from L2-Directory SRAM 0 | |
| 13 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_AUE_5: AUE5 UE ECC error detected from L2-Directory SRAM 1 | |
| 14 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_AUE_6: AUE6 UE ECC error detected from L2-Directory SRAM 2 | |
| 15 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_AUE_7: AUE7 UE ECC error detected from L2-Directory SRAM 3 | |
| 16 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBF_0: PBF0 s5: MCP_M_WT_CRESP: error cresp received for a command | |
| 17 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBF_1: PBF1 s5: MCP_PC_WT_CRESP: error cresp received for a command | |
| 18 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBF_2: PBF2 s4: MCP_PC_WT_CRESP: Addr_Error received for self-lpc command (SSF) | |
| 19 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBF_3: PBF3 s4: MCP_PC_BK_WT_CRESP: ack_dead cresp received for a bkill | |
| 20 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBF_4: PBF4 s5: MCP_M_RCV_DATA_PTL: not all segments/OWs were received | |
| 21 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBF_5: PBF5 s4: dma_pr_w/pr_dma_inj snooped that crosses 128B boundary | |
| 22 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBF_6: PBF6 s4: SMEV_DATIN: Received data with illegal data_stat value. | |
| 23 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBF_7: PBF7 Unexpected data beat received | |
| 24 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBF_8: PBF8 s7: addr_error CResp to internal PAU request | |
| 25 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBF_9: PBF9 (reserved) | |
| 26 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBF_10: PBF10 s5: Received 64B of data but snooped command wasn't cp_*(m=1) | |
| 27 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBF_11: PBF11 s5: Received 64B of data to PAU-mastered command | |
| 28 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_LDA_0: LDA0 s4: MCP_PC_WT_CRESP: Addr_Error received for load command (LD) | |
| 29 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_LDA_1: LDA1 (reserved) | |
| 30 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_LDA_2: LDA2 (reserved) | |
| 31 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_LDA_3: LDA3 (reserved) | |
| 32 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_STA_0: STA0 s4: MCP_PC_WT_CRESP: Addr_Error received for store command (ST) | |
| 33 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_STA_1: STA1 s4: MCP_PC_BK_WT_CRESP: Addr_Error received for bkill command (ST) | |
| 34 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_STA_2: STA2 (reserved) | |
| 35 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_STA_3: STA3 (reserved) | |
| 36:63 | RO | RO | constant=0b0000000000000000000000000000 | |
| c_err_rpt hold-2 latches | ||||
|---|---|---|---|---|
| Addr: |
0000000011010817 (SCOM) 00000000134000B8 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.MCP.MISC.CERR_HOLD2 | |||
| Constant(s): | ||||
| Comments: | c_err_rpt hold latches read-write-clear reg | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM0.MCP.MISC.CERPT_NLG.HOLD_LATCH_INST.HOLD.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_0: NLG0 s4: Rcmd Event received but state machine is not IDLE | |
| 1 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_1: NLG1 s4: Pocket-Hit event but not in MCP_M_PCKT_WAIT_HIT/PC_* state | |
| 2 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_2: NLG2 s4: MCP_M_WT_CRESP: ma_scresp table lookup missed | |
| 3 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_3: NLG3 s4: MCP_M_WT_CRESP: start epsilon, but epsilon already in progress | |
| 4 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_4: NLG4 s5: MCP_M_WT_CRESP: ma_scresp indicated 'evaporate' but have xTL modified data | |
| 5 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_5: NLG5 s5: MCP_M_WT_CRESP: ma_scresp indicated 'evaporate' but have PB modified data | |
| 6 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_6: NLG6 s5: MCP_M_WT_CRESP: bad scenario code from ma_scresp table | |
| 7 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_7: NLG7 s4: snoop Cresp received but not in MCP_M_WT_CRESP state | |
| 8 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_8: NLG8 s4: Dir-Lock Event received but state machine is not MCP_PC_WT_CRESP/MCP_M_WAIT_SYN_PEND/MCP_M_WAIT_DIR_LOCK or bad ttype | |
| 9 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_9: NLG9 s4: MCP_PC_WT_CRESP: ma_mcresp table lookup missed | |
| 10 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_10: NLG10 s4/5: MCP_PC/_BK/_WT_CRESP: Write coll state didn't match early protection state | |
| 11 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_11: NLG11 s4: MCP_PC_WT_CRESP: start epsilon, but epsilon already in progress | |
| 12 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_12: NLG12 s5: MCP_PC_WT_CRESP: bad scenario code from ma_mcresp table | |
| 13 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_13: NLG13 s4: MCP_PC_BK_WT_CRESP: bad next-step for bkill (ack-done) | |
| 14 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_14: NLG14 s4: MCP_PC_BK_WT_CRESP: bad next-step for bkill (retry) | |
| 15 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_15: NLG15 s4: MCP_PC_BK_WT_CRESP: bad cresp for a bkill | |
| 16 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_16: NLG16 s4: master Cresp received but not in MCP_PC_WT_CRESP/MCP_PC_BK_WT_CRESP states | |
| 17 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_17: NLG17 s4: M_IDLE: Invalid DATALEN[3:0] for NVLink data command | |
| 18 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_18: NLG18 s4: M_IDLE: Invalid command type received | |
| 19 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_19: NLG19 s4: AT-translate-Response event but not in wait-translate state | |
| 20 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_20: NLG20 s4: AT-translate-Response event had bad translate status, but cmd not recognized | |
| 21 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_21: NLG21 s4: SA-Done event but not in wait-SA state | |
| 22 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_22: NLG22 s4: MCP_PC_WAIT_DATADONE: bad next-step for PB data transmit | |
| 23 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_23: NLG23 s4: MCP_TD_WAIT_DATADONE: Unknown NVLink Master Command | |
| 24 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_24: NLG24 s4: BuffDone event but not in PB/PC/MG/NR/XATS/MCP_TD_WAIT_DATADONE state | |
| 25 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_25: NLG25 s4: MCP_NC_WT_RESP: Unknown nv-master command for NVLink response | |
| 26 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_26: NLG26 s4: RG-RspIn event but not in MCP_RG_WT_RESP or MCP_NC_WT_RESP* state | |
| 27 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_27: NLG27 s4: Epsilon-In-Progress, but epsilon counter clock is not the epsilon clock | |
| 28 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_28: NLG28 s4: Epsilon counter clock is 'epsilon' but epsilon_ip is not set | |
| 29 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_29: NLG29 s4: MCP_PC_WT_BK_RBACK: bad next-step for bkill | |
| 30 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_30: NLG30 s4: M/RR_BACK timer expired but not in PC_WT(_BK)_RBACK state | |
| 31 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_31: NLG31 s4: Bad epclock value | |
| 32 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_32: NLG32 s4: coll_state is POCKET_RCOLL_ND but master state is not PCKT_WAIT_HIT | |
| 33 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_33: NLG33 s7: Did not find anything to do for a MCMD_COH response | |
| 34 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_34: NLG34 s4: Unknown Event type received | |
| 35 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_35: NLG35 s4: SMEV_DIRDONE received but sm_dir_upd_pending=0 | |
| 36 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_36: NLG36 s7: MCP_M_EVAL_DSA: Unknown merge opcode from dsa table | |
| 37 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_37: NLG37 s7: Unknown State | |
| 38 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_38: NLG38 s4: coll_state is POCKET_RCOLL_OND but master state is not PCKT_WAIT_HIT | |
| 39 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_39: NLG39 s4: Unknown sm_master_state in ESCAN_FENCE event | |
| 40 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_40: NLG40 s4: MCP_FENCE_WT_RESP_FILL: Unknown nv-master command for Fence-Fill-SUE response | |
| 41 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_41: NLG41 s4: MCP_M_WT_CRESP: impossible command/cresp | |
| 42 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_42: NLG42 s4: MCP_PC_WT_CRESP: impossible command/cresp | |
| 43 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_43: NLG43 s7: MCP_M_EVAL_DSA: impossible command/state | |
| 44 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_44: NLG44 s7: Unexpected Error State (bad sub-sequence return) | |
| 45 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_45: NLG45 s5: sfstat-retry but not in retry-abbks collision state | |
| 46 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_46: NLG46 s5: *cond*-retry but not in retry-abbks collision state | |
| 47 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_47: NLG47 s4: Request from CTL/xTL caused bad MMIO alignment, but cmd not recognized | |
| 48 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_48: NLG48 s5: MCP_NC_EXE_RESP: Unknown nv-master command for NVLink response | |
| 49 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_49: NLG49 s7: MCP_M_EVAL_DSA: Topology-index of the Request address is not valid in the topology-index table | |
| 50 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_50: NLG50 s4: Request from CTL/xTL caused bad MMIO alignment, but cmd not recognized | |
| 51 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_51: NLG51 s4: Request from CTL/xTL loaded into non-idle state-machine | |
| 52 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_52: NLG52 s4: POCKET-HIT event but coll_state is not POCKET_WINNER* | |
| 53 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_53: NLG53 s4: Unknown rspin event w/ unknown master-command in MCP_RG_WT_RESP state | |
| 54 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_54: NLG54 s7: Attempt to send PBus request but config_enable_pbus=0 | |
| 55 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_55: NLG55 s4: Invalid SrcBus on response from CTL | |
| 56 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_56: NLG56 s4: Shoulder-tap event but not in MCP_M_WT_SHOULDER_TAP state | |
| 57 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_57: NLG57 s7: MCP_M_EVAL_DSA: ma_dsasfe table lookup missed | |
| 58 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_58: NLG58 s7: MCP_M_EVAL_DSA: ma_dsac2alc table lookup missed | |
| 59 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_59: NLG59 s7: MCP_M_EVAL_DSA: ma_dsac2co table lookup missed | |
| 60 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_60: NLG60 s7: MCP_M_EVAL_DSA: ma_dsaoth table lookup missed | |
| 61 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_61: NLG61 s7: MCP_M_EVAL_DSA: ma_dsascan table lookup missed | |
| 62 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_62: NLG62 s7: Nothing to do after looking in DSA table | |
| 63 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_63: NLG63 s7: coherence update/response but directory lock is not DLOCK_MOD | |
| Perf Match Reg | ||||
|---|---|---|---|---|
| Addr: |
0000000011010818 (SCOM) 00000000134000C0 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.MCP.MISC.PERF_MATCH_CONFIG | |||
| Constant(s): | ||||
| Comments: | Performance Event Field Match | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:43 | PAU3.CS.SM0.MCP.MISC.PERF_MATCH_CONFIG_Q_0_INST.LATC.L2(0:43) [00000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:23 | RW | RW | PERF_MATCH_RESERVED2: reserved | |
| 24:28 | RW | RW | PERF_MATCH_CRESP: CResp | |
| 29:31 | RW | RW | PERF_MATCH_SCOPE: Scope | |
| 32:41 | RW | RW | PERF_MATCH_MCMD: MCmd | |
| 42:43 | RW | RW | PERF_MATCH_RESERVED1: reserved | |
| 44:63 | RO | RO | constant=0b00000000000000000000 | |
| Perf Mask Reg | ||||
|---|---|---|---|---|
| Addr: |
0000000011010819 (SCOM) 00000000134000C8 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.MCP.MISC.PERF_MASK_CONFIG | |||
| Constant(s): | ||||
| Comments: | Performance Event Field Mask | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:43 | PAU3.CS.SM0.MCP.MISC.PERF_MASK_CONFIG_Q_0_INST.LATC.L2(0:43) [00000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:23 | RW | RW | PERF_MASK_RESERVED2: reserved | |
| 24:28 | RW | RW | PERF_MASK_CRESP: CResp | |
| 29:31 | RW | RW | PERF_MASK_SCOPE: Scope | |
| 32:41 | RW | RW | PERF_MASK_MCMD: MCmd | |
| 42:43 | RW | RW | PERF_MASK_RESERVED1: reserved | |
| 44:63 | RO | RO | constant=0b00000000000000000000 | |
| Debug0 Config Reg | ||||
|---|---|---|---|---|
| Addr: |
000000001101081A (SCOM) 00000000134000D0 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.MCP.MISC.DEBUG0_CONFIG | |||
| Constant(s): | ||||
| Comments: | Config register for trace-0 chain | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM0.MCP.MISC.DEBUG0_CONFIG_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:4 | RW | RW | DEBUG0_CONFIG_POD0: Mux control for byte 0 of trace-0 | |
| 5:9 | RW | RW | DEBUG0_CONFIG_POD1: Mux control for byte 1 of trace-0 | |
| 10:14 | RW | RW | DEBUG0_CONFIG_POD2: Mux control for byte 2 of trace-0 | |
| 15:19 | RW | RW | DEBUG0_CONFIG_POD3: Mux control for byte 3 of trace-0 | |
| 20:24 | RW | RW | DEBUG0_CONFIG_POD4: Mux control for byte 4 of trace-0 | |
| 25:29 | RW | RW | DEBUG0_CONFIG_POD5: Mux control for byte 5 of trace-0 | |
| 30:34 | RW | RW | DEBUG0_CONFIG_POD6: Mux control for byte 6 of trace-0 | |
| 35:39 | RW | RW | DEBUG0_CONFIG_POD7: Mux control for byte 7 of trace-0 | |
| 40:44 | RW | RW | DEBUG0_CONFIG_POD8: Mux control for byte 8 of trace-0 | |
| 45:49 | RW | RW | DEBUG0_CONFIG_POD9: Mux control for byte 9 of trace-0 | |
| 50:54 | RW | RW | DEBUG0_CONFIG_POD10: Mux control for byte 10 of trace-0 | |
| 55:62 | RW | RW | DEBUG0_CONFIG_RESERVED1: reserved | |
| 63 | RW | RW | DEBUG0_CONFIG_ACT: Enable clock-gates for debug trace latches | |
| Debug1 Config Reg | ||||
|---|---|---|---|---|
| Addr: |
000000001101081B (SCOM) 00000000134000D8 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.MCP.MISC.DEBUG1_CONFIG | |||
| Constant(s): | ||||
| Comments: | Config register for trace-1 chain | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM0.MCP.MISC.DEBUG1_CONFIG_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:4 | RW | RW | DEBUG1_CONFIG_POD0: Mux control for byte 0 of trace-1 | |
| 5:9 | RW | RW | DEBUG1_CONFIG_POD1: Mux control for byte 1 of trace-1 | |
| 10:14 | RW | RW | DEBUG1_CONFIG_POD2: Mux control for byte 2 of trace-1 | |
| 15:19 | RW | RW | DEBUG1_CONFIG_POD3: Mux control for byte 3 of trace-1 | |
| 20:24 | RW | RW | DEBUG1_CONFIG_POD4: Mux control for byte 4 of trace-1 | |
| 25:29 | RW | RW | DEBUG1_CONFIG_POD5: Mux control for byte 5 of trace-1 | |
| 30:34 | RW | RW | DEBUG1_CONFIG_POD6: Mux control for byte 6 of trace-1 | |
| 35:39 | RW | RW | DEBUG1_CONFIG_POD7: Mux control for byte 7 of trace-1 | |
| 40:44 | RW | RW | DEBUG1_CONFIG_POD8: Mux control for byte 8 of trace-1 | |
| 45:49 | RW | RW | DEBUG1_CONFIG_POD9: Mux control for byte 9 of trace-1 | |
| 50:54 | RW | RW | DEBUG1_CONFIG_POD10: Mux control for byte 10 of trace-1 | |
| 55:62 | RW | RW | DEBUG1_CONFIG_RESERVED1: reserved | |
| 63 | RW | RW | DEBUG1_CONFIG_ACT: Enable clock-gates for debug trace latches | |
| Debug Machine-Pipe config 3 | ||||
|---|---|---|---|---|
| Addr: |
000000001101081C (SCOM) 00000000134000E0 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.MCP.MISC.DEBUG3_CONFIG | |||
| Constant(s): | ||||
| Comments: | Config register for machine-pipe fields into internal-group 4 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM0.MCP.MISC.DEBUG3_CONFIG_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:6 | RW | RW | DEBUG_CONFIG_MACH_BYTE0: Mux control for mach byte 0 | |
| 7:13 | RW | RW | DEBUG_CONFIG_MACH_BYTE1: Mux control for mach byte 1 | |
| 14:20 | RW | RW | DEBUG_CONFIG_MACH_BYTE2: Mux control for mach byte 2 | |
| 21:27 | RW | RW | DEBUG_CONFIG_MACH_BYTE3: Mux control for mach byte 3 | |
| 28:34 | RW | RW | DEBUG_CONFIG_MACH_BYTE4: Mux control for mach byte 4 | |
| 35:41 | RW | RW | DEBUG_CONFIG_MACH_BYTE5: Mux control for mach byte 5 | |
| 42:48 | RW | RW | DEBUG_CONFIG_MACH_BYTE6: Mux control for mach byte 6 | |
| 49:55 | RW | RW | DEBUG_CONFIG_MACH_BYTE7: Mux control for mach byte 7 | |
| 56:62 | RW | RW | DEBUG_CONFIG_MACH_BYTE8: Mux control for mach byte 8 | |
| 63 | RW | RW | DEBUG_CONFIG_MACH_ACT: Clock-gate enable for mach byte latches | |
| Debug Machine-Pipe config 4 | ||||
|---|---|---|---|---|
| Addr: |
000000001101081D (SCOM) 00000000134000E8 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.MCP.MISC.DEBUG4_CONFIG | |||
| Constant(s): | ||||
| Comments: | Config register for machine-pipe fields into internal-group 4 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:51 | PAU3.CS.SM0.MCP.MISC.DEBUG4_CONFIG_Q_0_INST.LATC.L2(0:51) [0000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:6 | RW | RW | DEBUG_CONFIG_MACH_BYTE9: Mux control for mach byte 9 | |
| 7:13 | RW | RW | DEBUG_CONFIG_MACH_BYTE10: Mux control for mach byte 10 | |
| 14:20 | RW | RW | DEBUG_CONFIG_MACH_BYTE11: Mux control for mach byte 11 | |
| 21:27 | RW | RW | DEBUG_CONFIG_MACH_BYTE12: Mux control for mach byte 12 | |
| 28:34 | RW | RW | DEBUG_CONFIG_MACH_BYTE13: Mux control for mach byte 13 | |
| 35:41 | RW | RW | DEBUG_CONFIG_MACH_BYTE14: Mux control for mach byte 14 | |
| 42:48 | RW | RW | DEBUG_CONFIG_MACH_BYTE15: Mux control for mach byte 15 | |
| 49:51 | RW | RW | DEBUG_CONFIG_MACH_RESERVED1: reserved | |
| 52:63 | RO | RO | constant=0b000000000000 | |
| CQ_SM Misc Config register #2 | ||||
|---|---|---|---|---|
| Addr: |
000000001101081E (SCOM) 00000000134000F0 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.MCP.MISC.CONFIG2 | |||
| Constant(s): | ||||
| Comments: | Misc config register Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM0.MCP.MISC.CONFIG2_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:11 | RW | RW | CONFIG_MCP_FIR_TO_INHIBIT_MASK: Mask of FIR bits that should force inhibit-all Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 12 | RW | RW | CONFIG_BRK0_FENCE_TO_INHIBIT_MASK: 0/1 = brick-0 fence operates normally / brick-0 fence inhibits everything Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 13 | RW | RW | CONFIG_BRK1_FENCE_TO_INHIBIT_MASK: 0/1 = brick-1 fence operates normally / brick-1 fence inhibits everything Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 14 | RW | RW | CONFIG_BRK2_FENCE_TO_INHIBIT_MASK: 0/1 = brick-2 fence operates normally / brick-2 fence inhibits everything Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 15 | RW | RW | CONFIG_BRK3_FENCE_TO_INHIBIT_MASK: 0/1 = brick-3 fence operates normally / brick-3 fence inhibits everything Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 16 | RW | RW | CONFIG_BRK4_FENCE_TO_INHIBIT_MASK: 0/1 = brick-4 fence operates normally / brick-4 fence inhibits everything Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 17 | RW | RW | CONFIG_ENABLE_PHASE1_DCBF: 0/1 = disable DCARM (PB V5 arch sec 9.6) protocol for dcbf,dcbfc,dcbfps (group 1) / enable dcarm protocol | |
| 18 | RW | RW | CONFIG_ENABLE_PHASE1_CLEAN: 0/1 = disable DCARM (PB V5 arch sec 9.6) protocol for dcbfstp (group 2) / enable dcarm protocol | |
| 19 | RW | RW | CONFIG_ENABLE_PHASE1_AMO: 0/1 = disable DCARM (PB V5 arch sec 9.6) protocol for armw*,armwf* (group 3) / enable dcarm protocol | |
| 20:31 | RW | RW | CONFIG_DCARM_TIMER: timeout value for DCARM phase-2 measured in PowerBus epsilon steps | |
| 32:33 | RW | RW | CONFIG_BRK0_EXT_MEM_TAGS: Even and Odd iSeries tag bits for brick-0 OCAPI 128B dma_w (Extended memory) | |
| 34:35 | RW | RW | CONFIG_BRK1_EXT_MEM_TAGS: Even and Odd iSeries tag bits for brick-1 OCAPI 128B dma_w (Extended memory) | |
| 36:37 | RW | RW | CONFIG_BRK2_EXT_MEM_TAGS: Even and Odd iSeries tag bits for brick-2 OCAPI 128B dma_w (Extended memory) | |
| 38:39 | RW | RW | CONFIG_BRK3_EXT_MEM_TAGS: Even and Odd iSeries tag bits for brick-3 OCAPI 128B dma_w (Extended memory) | |
| 40:41 | RW | RW | CONFIG_BRK4_EXT_MEM_TAGS: Even and Odd iSeries tag bits for brick-4 OCAPI 128B dma_w (Extended memory) | |
| 42 | RW | RW | CONFIG_PB_TO_OC_FASTPATH_MASTER_ENABLE: 0/1 = disable sending OC read request at RCmd / enable sending early OC read request before CResp | |
| 43 | RW | RW | CONFIG_PB_TO_OC_FASTPATH_ENABLE_READ: 0/1 = disable sending fastpath oc read for rd_go_s, rd_go_m, rd_larx / enable fastpath. | |
| 44 | RW | RW | CONFIG_PB_TO_OC_FASTPATH_ENABLE_PREF: 0/1 = disable sending fastpath oc read for pref_go_s, pref_go_m / enable fastpath. | |
| 45 | RW | RW | CONFIG_PB_TO_OC_FASTPATH_ENABLE_DMA: 0/1 = disable sending fastpath oc read for cl_dma_rd, cl_rd_nc / enable fastpath. | |
| 46 | RW | RW | CONFIG_PB_TO_OC_FASTPATH_ENABLE_RWITM: 0/1 = disable sending fastpath oc read for rwitm, rwitm_stwx / enable fastpath. | |
| 47 | RW | RW | CONFIG_PB_TO_OC_FASTPATH_ENABLE_CI: 0/1 = disable sending fastpath oc read for ci_pr_rd / enable fastpath. | |
| 48 | RW | RW | CONFIG_PB_TO_OC_FASTPATH_REQUIRE_QOS_1: 0/1 = for fastpath oc reads, don't-care the q (QoS) bit in reads / require the q bit to be '1' if it exists. | |
| 49 | RW | RW | CONFIG_PB_TO_OC_FASTPATH_REQUIRE_HINT_0: 0/1 = for fastpath oc reads, don't-care the h (hint) bit in reads / require the h bit to be '0' if it exists. | |
| 50:51 | RW | RW | CONFIG_PB_TO_OC_FASTPATH_REQUIRE_CL: for fastpath oc reads, require the cl0/cl1 field (if it exists) to be >= this value. | |
| 52 | RW | RW | CONFIG_PB_TO_OC_FASTPATH_REQUIRE_LD_PR_1: 0/1 = for fastpath oc reads, don't-care the ld_pr (load promote) bit in reads / require the ld_pr bit to be '1' if it exists. | |
| 53 | RW | RW | CONFIG_PB_TO_OC_FASTPATH_REQUIRE_RXO_EMPTY: 0/1 = for fastpath oc reads, don't require the RXO queue to be empty / require the RXO request-out queue to be empty | |
| 54 | RW | RW | CONFIG_DISABLE_HW551717_PTLA_TO_UCI: 0/1 = enable swapping pr_wr_mem_ptla_uco to pr_wr_mem_ptla_uci / disable fix | |
| 55 | RW | RW | CONFIG_DISABLE_HW552185_BKRETRY_TO_RMA: 0/1 = enable using COLL_RMA in place of bkretry / disable fix | |
| 56 | RW | RW | CONFIG_ENABLE_HW549830_MI_RETRY_NON_CP: 0/1 = disable hw549830 fix / enable retrying non-cp commands back to requesting PAU when retried on the PowerBus. | |
| 57:60 | RW | RW | CONFIG_HW549830_MI_RETRY_THRESH: Number of retries on the PowerBus before retrying the non-cp command back to the source PAU. | |
| 61:63 | RW | RW | CONFIG2_RESERVED: Reserved | |
| Timer Config Reg 2 | ||||
|---|---|---|---|---|
| Addr: |
000000001101081F (SCOM) 00000000134000F8 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.MCP.MISC.XTIMER2_CONFIG | |||
| Constant(s): | ||||
| Comments: | Timer Configuration Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:11 | PAU3.CS.SM0.MCP.MISC.XTIMER2_CONFIG_Q_0_INST.LATC.L2(0:11) [000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:5 | RW | RW | CONFIG_INH2_TICK: Rate for SM-Inhibit timer tick 2 (default 63=off) | |
| 6:11 | RW | RW | CONFIG_INH3_TICK: Rate for SM-Inhibit timer tick 3 (default 63=off) | |
| 12:63 | RO | RO | constant=0b0000000000000000000000000000000000000000000000000000 | |
| CQ_DIR Misc Config register #0 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010828 (SCOM) 0000000013400140 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.DIR.MISC.CONFIG0 | |||
| Constant(s): | ||||
| Comments: | Misc config register Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM0.DIR.MISC.CONFIG0Q.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:3 | RW | RW | CONFIG_HOST_TAG_SIZE: Configured host tag size (in bits) Must be less than or equal to the maximum host tag size supported by the AFUs connected to this PAU. 15 = maximum host tag size supported 6 = minimum host tag size supported 5..0 = reserved values, do not use | |
| 4:62 | RW | RW | CONFIG0_RESERVED: Reserved | |
| 63 | RW | RW | CONFIG_DEBUG0_ACT: Clock-gate enable for debug0 latches | |
| Perf Config Reg | ||||
|---|---|---|---|---|
| Addr: |
0000000011010829 (SCOM) 0000000013400148 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.DIR.MISC.PERF_CONFIG | |||
| Constant(s): | ||||
| Comments: | Performance Event selection | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM0.DIR.MISC.PERF_CONFIGQ.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:27 | RW | RW | PERF_CONFIG_RESERVED1: reserved | |
| 28:35 | RW | RW | PERF_CONFIG_EVENT0: Event 0 select 0: count nothing 1: count cycles others: reserved (count nothing) | |
| 36:43 | RW | RW | PERF_CONFIG_EVENT1: Event 1 select See Event 0 select for encodes | |
| 44:51 | RW | RW | PERF_CONFIG_EVENT2: Event 2 select See Event 0 select for encodes | |
| 52:59 | RW | RW | PERF_CONFIG_EVENT3: Event 3 select See Event 0 select for encodes | |
| 60:62 | RW | RW | PERF_CONFIG_RESERVED2: reserved | |
| 63 | RW | RW | PERF_CONFIG_ACT: Enable clock-gates for performance monitor latches | |
| Debug0 Config Reg | ||||
|---|---|---|---|---|
| Addr: |
000000001101082A (SCOM) 0000000013400150 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.DIR.MISC.DEBUG0_CONFIG | |||
| Constant(s): | ||||
| Comments: | Config register for trace-0 chain | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM0.DIR.MISC.DEBUG0_CONFIGQ.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:4 | RW | RW | DEBUG0_CONFIG_POD0: Mux control for byte 0 of trace-0 | |
| 5:9 | RW | RW | DEBUG0_CONFIG_POD1: Mux control for byte 1 of trace-0 | |
| 10:14 | RW | RW | DEBUG0_CONFIG_POD2: Mux control for byte 2 of trace-0 | |
| 15:19 | RW | RW | DEBUG0_CONFIG_POD3: Mux control for byte 3 of trace-0 | |
| 20:24 | RW | RW | DEBUG0_CONFIG_POD4: Mux control for byte 4 of trace-0 | |
| 25:29 | RW | RW | DEBUG0_CONFIG_POD5: Mux control for byte 5 of trace-0 | |
| 30:34 | RW | RW | DEBUG0_CONFIG_POD6: Mux control for byte 6 of trace-0 | |
| 35:39 | RW | RW | DEBUG0_CONFIG_POD7: Mux control for byte 7 of trace-0 | |
| 40:44 | RW | RW | DEBUG0_CONFIG_POD8: Mux control for byte 8 of trace-0 | |
| 45:49 | RW | RW | DEBUG0_CONFIG_POD9: Mux control for byte 9 of trace-0 | |
| 50:54 | RW | RW | DEBUG0_CONFIG_POD10: Mux control for byte 10 of trace-0 | |
| 55:62 | RW | RW | DEBUG0_CONFIG_RESERVED1: reserved | |
| 63 | RW | RW | DEBUG0_CONFIG_ACT: Enable clock-gates for debug trace latches | |
| Debug1 Config Reg | ||||
|---|---|---|---|---|
| Addr: |
000000001101082B (SCOM) 0000000013400158 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.DIR.MISC.DEBUG1_CONFIG | |||
| Constant(s): | ||||
| Comments: | Config register for trace-1 chain | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM0.DIR.MISC.DEBUG1_CONFIGQ.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:4 | RW | RW | DEBUG1_CONFIG_POD0: Mux control for byte 0 of trace-1 | |
| 5:9 | RW | RW | DEBUG1_CONFIG_POD1: Mux control for byte 1 of trace-1 | |
| 10:14 | RW | RW | DEBUG1_CONFIG_POD2: Mux control for byte 2 of trace-1 | |
| 15:19 | RW | RW | DEBUG1_CONFIG_POD3: Mux control for byte 3 of trace-1 | |
| 20:24 | RW | RW | DEBUG1_CONFIG_POD4: Mux control for byte 4 of trace-1 | |
| 25:29 | RW | RW | DEBUG1_CONFIG_POD5: Mux control for byte 5 of trace-1 | |
| 30:34 | RW | RW | DEBUG1_CONFIG_POD6: Mux control for byte 6 of trace-1 | |
| 35:39 | RW | RW | DEBUG1_CONFIG_POD7: Mux control for byte 7 of trace-1 | |
| 40:44 | RW | RW | DEBUG1_CONFIG_POD8: Mux control for byte 8 of trace-1 | |
| 45:49 | RW | RW | DEBUG1_CONFIG_POD9: Mux control for byte 9 of trace-1 | |
| 50:54 | RW | RW | DEBUG1_CONFIG_POD10: Mux control for byte 10 of trace-1 | |
| 55:62 | RW | RW | DEBUG1_CONFIG_RESERVED1: reserved | |
| 63 | RW | RW | DEBUG1_CONFIG_ACT: Enable clock-gates for debug trace latches | |
| SCOM L2 Data Reg | ||||
|---|---|---|---|---|
| Addr: |
000000001101082C (SCOM) 0000000013400160 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.DIR.MISC.SCOM_L2_DATA | |||
| Constant(s): | ||||
| Comments: | Read-only register for SCOM reads of the L2 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM0.DIR.MISC.SCOM_L2_DATAQ.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:63 | ROX | ROX | L2_SCOM_READ_DATA: Data read out of the L2 directory by the SCOM interface | |
| CQ_SM Misc Config register #0 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010830 (SCOM) 0000000013400180 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.SNP.MISC.CONFIG0 | |||
| Constant(s): | ||||
| Comments: | Misc config register Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM0.SNP.MISC.CONFIG0_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:1 | RW | RW | CONFIG_MA_RSNOOP_OPT_DCLAIM: 0 = partial-respond to dclaim to GPU Mem with lpc_ack 1 = (deprecated - do not use) partial-respond to dclaim to GPU Mem with lpc_ack+rty_lost_claim Nv: 2 = partial-respond to dclaim to GPU Mem with lpc_ack+rty_lpc+start pocket cache Oc: 2 = reserved (must not be set when config_ocapi_mode=1 for this stack) 3 = reserved | |
| 2 | RW | RW | CONFIG_ENABLE_PBUS: 0/1 = disable PAU PowerBus RCmd, PResp, and CResp interfaces / enable these interfaces Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 3 | RW | RW | CONFIG_BRAZOS_MODE: Reserved (was: brazos_mode 0/1 = non-brazos 4-group;2-chip mode / brazos 2-group;4-chip mode) | |
| 4 | RW | RW | CONFIG_PCKT_BLK_PRB: 0/1 = valid pocket-cache entries do not block probes / probes are blocked | |
| 5 | RW | RW | CONFIG_ADR_BAR_MODE: Reserved (was: PowerBus adr_bar: 0/1 = large-system-mode/small-system-mode) | |
| 6 | RW | RW | CONFIG_RESTRICT_CHIP_GROUP: Reserved (was: 0/1 = support all 16 groups and all 8 chips / restrict chip/group to 4/2 or 2/4) | |
| 7 | RW | RW | CONFIG_DISABLE_HW552185_BKRETRY_TO_RMA: 0/1 = 'or' hit_rma into hit_bk_rty_abbk and hit_pckt_win signals / disable fix | |
| 8 | RW | RW | CONFIG0_RESERVED3: reserved | |
| 9:15 | RW | RW | CONFIG_SNP_FIR_TO_INHIBIT_MASK: Mask of FIR bits that should force inhibit-all Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 16 | RW | RW | CONFIG_BRK0_FENCE_TO_INHIBIT_MASK: 0/1 = brick-0 fence operates normally / brick-0 fence inhibits everything Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 17 | RW | RW | CONFIG_BRK1_FENCE_TO_INHIBIT_MASK: 0/1 = brick-1 fence operates normally / brick-1 fence inhibits everything Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 18 | RW | RW | CONFIG_BRK2_FENCE_TO_INHIBIT_MASK: 0/1 = brick-2 fence operates normally / brick-2 fence inhibits everything Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 19 | RW | RW | CONFIG_BRK3_FENCE_TO_INHIBIT_MASK: 0/1 = brick-3 fence operates normally / brick-3 fence inhibits everything Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 20 | RW | RW | CONFIG_BRK4_FENCE_TO_INHIBIT_MASK: 0/1 = brick-4 fence operates normally / brick-4 fence inhibits everything Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 21 | RW | RW | CONFIG_MRBGP_TRACK_ALL: 0/1 = master-retry-backoff group-pump track only this stack's/all-this-chips retry responses | |
| 22 | RW | RW | CONFIG_MRBSP_TRACK_ALL: 0/1 = master-retry-backoff system-pump track only this stack's/all-this-chips retry responses | |
| 23 | RW | RW | CONFIG_MRBCP_TRACK_ALL: 0/1 = master-retry-backoff chip-pump track only this stack's/all-this-chips retry responses | |
| 24:30 | RW | RW | CONFIG_ADDR_EX_MASK_ENA: Reserved (was: Mask for address bits to ignore when checking for different-group/different-chip when calculating initial scope.) aka config_chip_address_extension_mask_enable(15:21) | |
| 31 | RW | RW | CONFIG_SINGLE_AFU_DUAL_BRICK: 0/1 = AFU(s) use only one brick / 1 AFU is using both bricks on this ramp (the only effect of this bit is to 'wildcard' brick numbers when processing XSL-castouts) | |
| 32 | RW | RW | CONFIG_BRK0_OCAPI_MODE: 0/1 = Disable OpenCAPI mode / enable OpenCAPI mode for brick 0 (mutually exclusive with config_brk0_nvlink_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 33 | RW | RW | CONFIG_BRK1_OCAPI_MODE: 0/1 = Disable OpenCAPI mode / enable OpenCAPI mode for brick 1 (mutually exclusive with config_brk1_nvlink_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 34 | RW | RW | CONFIG_BRK2_OCAPI_MODE: 0/1 = Disable OpenCAPI mode / enable OpenCAPI mode for brick 2 (mutually exclusive with config_brk2_nvlink_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 35 | RW | RW | CONFIG_BRK3_OCAPI_MODE: 0/1 = Disable OpenCAPI mode / enable OpenCAPI mode for brick 3 (mutually exclusive with config_brk3_nvlink_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 36 | RW | RW | CONFIG_BRK4_OCAPI_MODE: 0/1 = Disable OpenCAPI mode / enable OpenCAPI mode for brick 4 (mutually exclusive with config_brk4_nvlink_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 37 | RW | RW | CONFIG_BRK0_NVLINK_MODE: 0/1 = Disable NVLink mode / enable NVLink mode for brick 0 (mutually exclusive with config_brk0_ocapi_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 38 | RW | RW | CONFIG_BRK1_NVLINK_MODE: 0/1 = Disable NVLink mode / enable NVLink mode for brick 1 (mutually exclusive with config_brk1_ocapi_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 39 | RW | RW | CONFIG_BRK2_NVLINK_MODE: 0/1 = Disable NVLink mode / enable NVLink mode for brick 2 (mutually exclusive with config_brk2_ocapi_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 40 | RW | RW | CONFIG_BRK3_NVLINK_MODE: 0/1 = Disable NVLink mode / enable NVLink mode for brick 3 (mutually exclusive with config_brk3_ocapi_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 41 | RW | RW | CONFIG_BRK4_NVLINK_MODE: 0/1 = Disable NVLink mode / enable NVLink mode for brick 4 (mutually exclusive with config_brk4_ocapi_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 42 | RW | RW | CONFIG_ENABLE_BLOCKING_RCMD_DIR: 0/1 = disable blocking RCmd dir lookups to give bandwidth to internal accesses / enable blocking | |
| 43 | RW | RW | CONFIG_DISABLE_DIR_POWERSAVE: 0/1 = allow clock-gating empty directory lookups to save power / disable clock-gating | |
| 44 | RW | RW | CONFIG_DISABLE_PRESP_POWERSAVE: 0/1 = allow clock-gating empty CAM+DIR PResps to save power / disable clock-gating | |
| 45 | RW | RW | CONFIG_ENABLE_BRK0_OCAPI_C2: 0/1 = disable receiving OCAPI C2 opcodes / enable receiving on brick 0 | |
| 46 | RW | RW | CONFIG_ENABLE_BRK1_OCAPI_C2: 0/1 = disable receiving OCAPI C2 opcodes / enable receiving on brick 1 | |
| 47 | RW | RW | CONFIG_ENABLE_BRK2_OCAPI_C2: 0/1 = disable receiving OCAPI C2 opcodes / enable receiving on brick 2 | |
| 48 | RW | RW | CONFIG_ENABLE_BRK3_OCAPI_C2: 0/1 = disable receiving OCAPI C2 opcodes / enable receiving on brick 3 | |
| 49 | RW | RW | CONFIG_ENABLE_BRK4_OCAPI_C2: 0/1 = disable receiving OCAPI C2 opcodes / enable receiving on brick 4 | |
| 50 | RW | RW | CONFIG_DISABLE_CAN_BY_CP: 0/1 = enable cancel-by-cp logic / disable cancel-by-cp logic | |
| 51 | RW | RW | CONFIG0_RESERVED1: reserved (was: chicken switch hw483005) | |
| 52 | RW | RW | CONFIG0_RESERVED2: reserved (was: chicken switch hw484205) | |
| 53 | RW | RW | CONFIG0_RESERVED4: reserved (was: chicken switch hw484205) | |
| 54 | RW | RW | CONFIG0_RESERVED5: reserved (was: chicken switch hw484205) | |
| 55 | RW | RW | CONFIG0_RESERVED6: reserved (was: chicken switch hw484099) | |
| 56 | RW | RW | CONFIG0_RESERVED7: reserved (was: chicken switch hw484668) | |
| 57 | RW | RW | CONFIG0_RESERVED8: reserved (was: chicken switch hw484695) | |
| 58 | RW | RW | CONFIG0_RESERVED9: reserved (was: chicken switch hw484972) | |
| 59 | RW | RW | CONFIG0_RESERVED10: reserved (was: chicken switch hw485798) | |
| 60 | RW | RW | CONFIG_DISABLE_CAN_BY_PROBE: 0/1 = enable cancel-by-probe logic / disable cancel-by-probe logic | |
| 61 | RW | RW | CONFIG_HANG_ON_ADDRESS_ERRORS: 0/1 = abort and continue on CResp=addr_error / hang state-machine on CResp=addr_error | |
| 62 | RW | RW | CONFIG_DISABLE_HW521165_SFE_BLOCKS_CASTOUT: 0/1 = enable hw521165 fix / disable and allow SFE to block castouts | |
| 63 | RW | RW | CONFIG_DISABLE_HW517982_PSNOOP_MISS_PRESP_NULL: 0/1 = enable hw517982 fix to force PResp=null for psnoop table miss / disable fix. | |
| CQ_SM Misc Config register #1 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010831 (SCOM) 0000000013400188 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.SNP.MISC.CONFIG1 | |||
| Constant(s): | ||||
| Comments: | Misc config register Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM0.SNP.MISC.CONFIG1_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:3 | RW | RW | CONFIG_SCALE_RPT_HANG_POLL: Scaling factor for rpt_hang.poll 0 = 1:1 PowerBus rpt_hang.polls received 1 = 1:2 PowerBus rpt_hang.polls received ... 15 = 1:16 PowerBus rpt_hang.polls received | |
| 4:7 | RW | RW | CONFIG_SCALE_RPT_HANG_DATA: Scaling factor for rpt_hang.data 0 = 1:1 PowerBus rpt_hang.datas received 1 = 1:2 PowerBus rpt_hang.datas received ... 15 = 1:16 PowerBus rpt_hang.datas received | |
| 8:11 | RW | RW | CONFIG_HOST_TAG_SIZE: Configured host tag size (in bits) Must be less than or equal to the maximum host tag size supported by the AFUs connected to this PAU. 15 = maximum host tag size supported 6 = minimum host tag size supported 5..0 = reserved values, do not use | |
| 12:15 | RW | RW | CONFIG_ARB_NONCRR_SAFETY: Safety valve for non-cresp/non-reqin events going down the arb pipe. after N+1 reqin events go through the arbiter while a non-crr event is waiting, reqin events are blocked to give non-crr events a chance. | |
| 16:18 | RW | RW | CONFIG_REPLAY_IP_LIMIT: Limit on number of replays in-progress in the snoop/directory pipe. Must not be set to zero | |
| 19 | RW | RW | CONFIG1_RESERVED1: Reserved | |
| 20:23 | RW | RW | CONFIG_BLOCK_FOR_REPLAY_TIME: Controls the # of cycles to count before forcing an opportunity for a 'replay' to access the directory 0 = 16 cycles 1 = 15 cycles ... 15 = 1 cycle | |
| 24:27 | RW | RW | CONFIG_BLOCK_FOR_DIRSCAN_TIME: Controls the # of cycles to count before forcing an opportunity for a directory-scan to access the directory 0 = 16 cycles 1 = 15 cycles ... 15 = 1 cycle | |
| 28:29 | RW | RW | CONFIG_THROT_ADDR_HASH: select the addr hash crc function used for PWR0/1/2 throttling | |
| 30 | RW | RW | CONFIG_DISABLE_HW510185_DIR_WALKER_REF_COUNT: 0/1 = enable hw510185 dir walker ref counts / disable and return to single-threaded evicts. | |
| 31 | RW | RW | CONFIG_ENABLE_OPENCAPI_NETWORKING: 0/1 = disable networking / enable OpenCAPI MI networking mode. | |
| 32 | RW | RW | CONFIG_NETWORKING_GVC_LOCATION: 0/1 = GVC in PowerBus RA(8:11) / GVC in PowerBus RA(20:23) | |
| 33 | RW | RW | CONFIG_TORUS_ENABLE_E_TO_A: 0/1 = Disable Torus from transferring VC-E into VC-A / Enable Torus to tranfer VC-E into VC-A. | |
| 34 | RW | RW | CONFIG_NETWORKING_SUPPRESS_CAM: 0/1 = Allow CAM results to retry networking RCmds / Disable CAM results for networking RCmds. | |
| 35 | RW | RW | CONFIG_DISABLE_HW532135_FENCE_SHARED_C2_ALC: 0/1 = enable shared state for c2-allocating requests when fenced / disable fix | |
| 36 | RW | RW | CONFIG_TORUS_ENABLE_VC_A: 0/1 = disable torus mode using VC-A (only use VC-E & VC-HP) / enable torus using VC-A | |
| 37 | RW | RW | CONFIG_TORUS_ENABLE_FAIRNESS: 0/1 = disable torus continuation vs new-insertion fairness / enable fairness mechanism | |
| 38:39 | RW | RW | CONFIG1_RESERVED2: Reserved | |
| 40:43 | RW | RW | CONFIG_BRK0_TORUS_NEW_INS_ACC_DEC: (brick 0) Amount to subtract (x4+3) from the fairness counter when a new-insertion is accepted. | |
| 44:47 | RW | RW | CONFIG_BRK0_TORUS_NEW_INS_REJ_INC: (brick 0) Amount to add to the fairness counter when a new-insertion is rejected and the counter is primed. | |
| 48:51 | RW | RW | CONFIG_BRK0_TORUS_CONT_ACC_INC: (brick 0) Amount to add to the fairness counter when a continuation is accepted in the forward-progress state. | |
| 52:55 | RW | RW | CONFIG_BRK1_TORUS_NEW_INS_ACC_DEC: (brick 1) Amount to subtract (x4+3) from the fairness counter when a new-insertion is accepted. | |
| 56:59 | RW | RW | CONFIG_BRK1_TORUS_NEW_INS_REJ_INC: (brick 1) Amount to add to the fairness counter when a new-insertion is rejected and the counter is primed. | |
| 60:63 | RW | RW | CONFIG_BRK1_TORUS_CONT_ACC_INC: (brick 1) Amount to add to the fairness counter when a continuation is accepted in the forward-progress state. | |
| GPU0-Memory BAR | ||||
|---|---|---|---|---|
| Addr: |
0000000011010832 (SCOM) 0000000013400190 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.SNP.MISC.GPU0_BAR | |||
| Constant(s): | ||||
| Comments: | BAR register defining GPU Mem addresses serviced by brick 0 connected to this stack. Note: This register should be set to the same value for each brick/stack. MDials have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:51 | PAU3.CS.SM0.SNP.MISC.GPU0_BAR_Q_0_INST.LATC.L2(0:51) [0000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_GPU0_BAR_ENABLE: Enable for this BAR (0=disabled, 1=enabled) for brick 0 | |
| 1:35 | RW | RW | CONFIG_GPU0_BAR_ADDR_MASK: BAR Address/Mask bits 1:35 for brick 0 In Small-BAR mode (see bit 36): 1:7 = Base_Addr(13:19) = 16T slice 8:21 = Base_Addr(20:33) = 1G address in slice 22:35 = Base_Mask(20:33) = 1G...16T BAR size. (Note: Mask limited to 1G...4T in Axone and P10 w/ GPU systems) In Large-BAR mode (see bit 36): 1 = '1' to match MemSel = addr(13:14) = 0b00 2 = '1' to match MemSel = addr(13:14) = 0b01 3 = '1' to match MemSel = addr(13:14) = 0b10 4:35 = Topology_Id_Mask(0:31) when chip_eq_group=0, TIM(0:31) bit 'i' corresponds to addr(15:19) = 'i' when chip_eq_group=1, TIM(0:31) bit 'i' corresponds to (addr(15:16) & addr(19:21)) = 'i' | |
| 36 | RW | RW | CONFIG_GPU0_BAR_SL_MODE: 0/1 = Small-BAR/Large-BAR Mode selector | |
| 37 | RW | RW | CONFIG_GPU0_BAR_4T_LIMIT: 0 = no limit, 16T slices can be used. 1 = limit slices to 4T. -> when chip_eq_group=0, addr(20:21) must match bar_4t_select -> when chip_eq_group=1, addr(17:18) must match bar_4t_select limit=1 is used in P10 systems w/ a GPU or in Axone systems | |
| 38:39 | RW | RW | CONFIG_GPU0_BAR_4T_SELECT: when bar_4t_limit=1 this field selects the value in addr(20:21) to match | |
| 40:43 | RW | RW | CONFIG_GPU0_BAR_MODE: Hash mode of the BAR for brick 0: if bar_extended_mode == 0: 0 = (single) match on all address in addr/size 1 = (dual.0) match if hashbits(7)=0 2 = (dual.1) match if hashbits(7)=1 3 = (triple.0) match if hashbits%3=0 4 = (triple.1) match if hashbits%3=1 5 = (triple.2) match if hashbits%3=2 6 = (quad.0) match if hashbits(6:7)=0 7 = (quad.1) match if hashbits(6:7)=1 8 = (quad.2) match if hashbits(6:7)=2 9 = (quad.3) match if hashbits(6:7)=3 10 = (six.0) match if hashbits%3=0 and hashbits(7)=0 11 = (six.1) match if hashbits%3=0 and hashbits(7)=1 12 = (six.2) match if hashbits%3=1 and hashbits(7)=0 13 = (six.3) match if hashbits%3=1 and hashbits(7)=1 14 = (six.4) match if hashbits%3=2 and hashbits(7)=0 15 = (six.5) match if hashbits%3=2 and hashbits(7)=1 if bar_extended_mode == 1: 0 = (oct.0) match if hashbits(5:7)=0 1 = (oct.1) match if hashbits(5:7)=1 2 = (oct.2) match if hashbits(5:7)=2 3 = (oct.3) match if hashbits(5:7)=3 4 = (oct.4) match if hashbits(5:7)=4 5 = (oct.5) match if hashbits(5:7)=5 6 = (oct.6) match if hashbits(5:7)=6 7 = (oct.7) match if hashbits(5:7)=7 others = reserved | |
| 44 | RW | RW | CONFIG_GPU0_BAR_GRANULE: Hash boundary for brick 0: 0 = hash on 512B boundary (hashbits(0:7)=addr(47:54)) 1 = hash on 1024B boundary (hashbits(0:7)=addr(46:53)) | |
| 45 | RW | RW | CONFIG_GPU0_BAR_POISON: on failed access return all ones 0/1 = with good ECC / with SUE ECC. | |
| 46 | RW | RW | CONFIG_GPU0_BAR_M2MODE: 0 = OpenCAPI AFU M1 mode / 1 = OpenCAPI AFU M2 mode Has no effect when in NVLink mode | |
| 47 | RW | RW | CONFIG_GPU0_BAR_PA_IGNORE_MODE: Set to '1' for RA-to-PA conversion to ignore the mode field | |
| 48 | RW | RW | CONFIG_GPU0_BAR_SECURE_A12: P10 Only: this specifies the addr(12) value to match for this BAR. Can only be set to one in P10 and only when SMF_CONFIG=0b11. | |
| 49 | RW | RW | CONFIG_GPU0_BAR_CHIP_EQ_GROUP: Axone Only: this specifies that the system is in chip=group mode. This bit should only be set when sl_mode=1 and 4t_limit=1. 0/1 = TIM(0:31) applies to addr(15:19) / TIM(0:31) applies to (addr(15:16) & addr(19:21)). | |
| 50 | RW | RW | CONFIG_GPU0_BAR_EXTENDED_MODE: 0/1 = bar_mode selects 1,2,3,4,6 way hashing / bar_mode selects 8-way hashing | |
| 51 | RW | RW | CONFIG_GPU0_BAR_RESERVED: reserved | |
| 52:63 | RO | RO | constant=0b000000000000 | |
| GPU1-Memory BAR | ||||
|---|---|---|---|---|
| Addr: |
0000000011010833 (SCOM) 0000000013400198 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.SNP.MISC.GPU1_BAR | |||
| Constant(s): | ||||
| Comments: | BAR register defining GPU Mem addresses serviced by brick 1 connected to this stack. Note: This register should be set to the same value for each brick/stack. MDials have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:51 | PAU3.CS.SM0.SNP.MISC.GPU1_BAR_Q_0_INST.LATC.L2(0:51) [0000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_GPU1_BAR_ENABLE: Enable for this BAR (0=disabled, 1=enabled) for brick 1 | |
| 1:35 | RW | RW | CONFIG_GPU1_BAR_ADDR_MASK: BAR Address/Mask bits 1:35 for brick 1 In Small-BAR mode (see bit 36): 1:7 = Base_Addr(13:19) = 16T slice 8:21 = Base_Addr(20:33) = 1G address in slice 22:35 = Base_Mask(20:33) = 1G...16T BAR size. (Note: Mask limited to 1G...4T in Axone and P10 w/ GPU systems) In Large-BAR mode (see bit 36): 1 = '1' to match MemSel = addr(13:14) = 0b00 2 = '1' to match MemSel = addr(13:14) = 0b01 3 = '1' to match MemSel = addr(13:14) = 0b10 4:35 = Topology_Id_Mask(0:31) when chip_eq_group=0, TIM(0:31) bit 'i' corresponds to addr(15:19) = 'i' when chip_eq_group=1, TIM(0:31) bit 'i' corresponds to (addr(15:16) & addr(19:21)) = 'i' | |
| 36 | RW | RW | CONFIG_GPU1_BAR_SL_MODE: 0/1 = Small-BAR/Large-BAR Mode selector | |
| 37 | RW | RW | CONFIG_GPU1_BAR_4T_LIMIT: 0 = no limit, 16T slices can be used. 1 = limit slices to 4T. -> when chip_eq_group=0, addr(20:21) must match bar_4t_select -> when chip_eq_group=1, addr(17:18) must match bar_4t_select limit=1 is used in P10 systems w/ a GPU or in Axone systems | |
| 38:39 | RW | RW | CONFIG_GPU1_BAR_4T_SELECT: when bar_4t_limit=1 this field selects the value in addr(20:21) to match | |
| 40:43 | RW | RW | CONFIG_GPU1_BAR_MODE: Hash mode of the BAR for brick 1: if bar_extended_mode == 0: 0 = (single) match on all address in addr/size 1 = (dual.0) match if hashbits(7)=0 2 = (dual.1) match if hashbits(7)=1 3 = (triple.0) match if hashbits%3=0 4 = (triple.1) match if hashbits%3=1 5 = (triple.2) match if hashbits%3=2 6 = (quad.0) match if hashbits(6:7)=0 7 = (quad.1) match if hashbits(6:7)=1 8 = (quad.2) match if hashbits(6:7)=2 9 = (quad.3) match if hashbits(6:7)=3 10 = (six.0) match if hashbits%3=0 and hashbits(7)=0 11 = (six.1) match if hashbits%3=0 and hashbits(7)=1 12 = (six.2) match if hashbits%3=1 and hashbits(7)=0 13 = (six.3) match if hashbits%3=1 and hashbits(7)=1 14 = (six.4) match if hashbits%3=2 and hashbits(7)=0 15 = (six.5) match if hashbits%3=2 and hashbits(7)=1 if bar_extended_mode == 1: 0 = (oct.0) match if hashbits(5:7)=0 1 = (oct.1) match if hashbits(5:7)=1 2 = (oct.2) match if hashbits(5:7)=2 3 = (oct.3) match if hashbits(5:7)=3 4 = (oct.4) match if hashbits(5:7)=4 5 = (oct.5) match if hashbits(5:7)=5 6 = (oct.6) match if hashbits(5:7)=6 7 = (oct.7) match if hashbits(5:7)=7 others = reserved | |
| 44 | RW | RW | CONFIG_GPU1_BAR_GRANULE: Hash boundary for brick 1: 0 = hash on 512B boundary (hashbits(0:7)=addr(47:54)) 1 = hash on 1024B boundary (hashbits(0:7)=addr(46:53)) | |
| 45 | RW | RW | CONFIG_GPU1_BAR_POISON: on failed access return all ones 0/1 = with good ECC / with SUE ECC. | |
| 46 | RW | RW | CONFIG_GPU1_BAR_M2MODE: 0 = OpenCAPI AFU M1 mode / 1 = OpenCAPI AFU M2 mode Has no effect when in NVLink mode | |
| 47 | RW | RW | CONFIG_GPU1_BAR_PA_IGNORE_MODE: Set to '1' for RA-to-PA conversion to ignore the mode field | |
| 48 | RW | RW | CONFIG_GPU1_BAR_SECURE_A12: P10 Only: this specifies the addr(12) value to match for this BAR. Can only be set to one in P10 and only when SMF_CONFIG=0b11. | |
| 49 | RW | RW | CONFIG_GPU1_BAR_CHIP_EQ_GROUP: Axone Only: this specifies that the system is in chip=group mode. This bit should only be set when sl_mode=1 and 4t_limit=1. 0/1 = TIM(0:31) applies to addr(15:19) / TIM(0:31) applies to (addr(15:16) & addr(19:21)). | |
| 50 | RW | RW | CONFIG_GPU1_BAR_EXTENDED_MODE: 0/1 = bar_mode selects 1,2,3,4,6 way hashing / bar_mode selects 8-way hashing | |
| 51 | RW | RW | CONFIG_GPU1_BAR_RESERVED: reserved | |
| 52:63 | RO | RO | constant=0b000000000000 | |
| GPU2-Memory BAR | ||||
|---|---|---|---|---|
| Addr: |
0000000011010834 (SCOM) 00000000134001A0 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.SNP.MISC.GPU2_BAR | |||
| Constant(s): | ||||
| Comments: | BAR register defining GPU Mem addresses serviced by brick 2 connected to this stack. Note: This register should be set to the same value for each brick/stack. MDials have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:51 | PAU3.CS.SM0.SNP.MISC.GPU2_BAR_Q_0_INST.LATC.L2(0:51) [0000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_GPU2_BAR_ENABLE: Enable for this BAR (0=disabled, 1=enabled) for brick 2 | |
| 1:35 | RW | RW | CONFIG_GPU2_BAR_ADDR_MASK: BAR Address/Mask bits 1:35 for brick 2 In Small-BAR mode (see bit 36): 1:7 = Base_Addr(13:19) = 16T slice 8:21 = Base_Addr(20:33) = 1G address in slice 22:35 = Base_Mask(20:33) = 1G...16T BAR size. (Note: Mask limited to 1G...4T in Axone and P10 w/ GPU systems) In Large-BAR mode (see bit 36): 1 = '1' to match MemSel = addr(13:14) = 0b00 2 = '1' to match MemSel = addr(13:14) = 0b01 3 = '1' to match MemSel = addr(13:14) = 0b10 4:35 = Topology_Id_Mask(0:31) when chip_eq_group=0, TIM(0:31) bit 'i' corresponds to addr(15:19) = 'i' when chip_eq_group=1, TIM(0:31) bit 'i' corresponds to (addr(15:16) & addr(19:21)) = 'i' | |
| 36 | RW | RW | CONFIG_GPU2_BAR_SL_MODE: 0/1 = Small-BAR/Large-BAR Mode selector | |
| 37 | RW | RW | CONFIG_GPU2_BAR_4T_LIMIT: 0 = no limit, 16T slices can be used. 1 = limit slices to 4T. -> when chip_eq_group=0, addr(20:21) must match bar_4t_select -> when chip_eq_group=1, addr(17:18) must match bar_4t_select limit=1 is used in P10 systems w/ a GPU or in Axone systems | |
| 38:39 | RW | RW | CONFIG_GPU2_BAR_4T_SELECT: when bar_4t_limit=1 this field selects the value in addr(20:21) to match | |
| 40:43 | RW | RW | CONFIG_GPU2_BAR_MODE: Hash mode of the BAR for brick 2: if bar_extended_mode == 0: 0 = (single) match on all address in addr/size 1 = (dual.0) match if hashbits(7)=0 2 = (dual.1) match if hashbits(7)=1 3 = (triple.0) match if hashbits%3=0 4 = (triple.1) match if hashbits%3=1 5 = (triple.2) match if hashbits%3=2 6 = (quad.0) match if hashbits(6:7)=0 7 = (quad.1) match if hashbits(6:7)=1 8 = (quad.2) match if hashbits(6:7)=2 9 = (quad.3) match if hashbits(6:7)=3 10 = (six.0) match if hashbits%3=0 and hashbits(7)=0 11 = (six.1) match if hashbits%3=0 and hashbits(7)=1 12 = (six.2) match if hashbits%3=1 and hashbits(7)=0 13 = (six.3) match if hashbits%3=1 and hashbits(7)=1 14 = (six.4) match if hashbits%3=2 and hashbits(7)=0 15 = (six.5) match if hashbits%3=2 and hashbits(7)=1 if bar_extended_mode == 1: 0 = (oct.0) match if hashbits(5:7)=0 1 = (oct.1) match if hashbits(5:7)=1 2 = (oct.2) match if hashbits(5:7)=2 3 = (oct.3) match if hashbits(5:7)=3 4 = (oct.4) match if hashbits(5:7)=4 5 = (oct.5) match if hashbits(5:7)=5 6 = (oct.6) match if hashbits(5:7)=6 7 = (oct.7) match if hashbits(5:7)=7 others = reserved | |
| 44 | RW | RW | CONFIG_GPU2_BAR_GRANULE: Hash boundary for brick 2: 0 = hash on 512B boundary (hashbits(0:7)=addr(47:54)) 1 = hash on 1024B boundary (hashbits(0:7)=addr(46:53)) | |
| 45 | RW | RW | CONFIG_GPU2_BAR_POISON: on failed access return all ones 0/1 = with good ECC / with SUE ECC. | |
| 46 | RW | RW | CONFIG_GPU2_BAR_M2MODE: 0 = OpenCAPI AFU M1 mode / 1 = OpenCAPI AFU M2 mode Has no effect when in NVLink mode | |
| 47 | RW | RW | CONFIG_GPU2_BAR_PA_IGNORE_MODE: Set to '1' for RA-to-PA conversion to ignore the mode field | |
| 48 | RW | RW | CONFIG_GPU2_BAR_SECURE_A12: P10 Only: this specifies the addr(12) value to match for this BAR. Can only be set to one in P10 and only when SMF_CONFIG=0b11. | |
| 49 | RW | RW | CONFIG_GPU2_BAR_CHIP_EQ_GROUP: Axone Only: this specifies that the system is in chip=group mode. This bit should only be set when sl_mode=1 and 4t_limit=1. 0/1 = TIM(0:31) applies to addr(15:19) / TIM(0:31) applies to (addr(15:16) & addr(19:21)). | |
| 50 | RW | RW | CONFIG_GPU2_BAR_EXTENDED_MODE: 0/1 = bar_mode selects 1,2,3,4,6 way hashing / bar_mode selects 8-way hashing | |
| 51 | RW | RW | CONFIG_GPU2_BAR_RESERVED: reserved | |
| 52:63 | RO | RO | constant=0b000000000000 | |
| GPU3-Memory BAR | ||||
|---|---|---|---|---|
| Addr: |
0000000011010835 (SCOM) 00000000134001A8 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.SNP.MISC.GPU3_BAR | |||
| Constant(s): | ||||
| Comments: | BAR register defining GPU Mem addresses serviced by brick 3 connected to this stack. Note: This register should be set to the same value for each brick/stack. MDials have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:51 | PAU3.CS.SM0.SNP.MISC.GPU3_BAR_Q_0_INST.LATC.L2(0:51) [0000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_GPU3_BAR_ENABLE: Enable for this BAR (0=disabled, 1=enabled) for brick 3 | |
| 1:35 | RW | RW | CONFIG_GPU3_BAR_ADDR_MASK: BAR Address/Mask bits 1:35 for brick 3 In Small-BAR mode (see bit 36): 1:7 = Base_Addr(13:19) = 16T slice 8:21 = Base_Addr(20:33) = 1G address in slice 22:35 = Base_Mask(20:33) = 1G...16T BAR size. (Note: Mask limited to 1G...4T in Axone and P10 w/ GPU systems) In Large-BAR mode (see bit 36): 1 = '1' to match MemSel = addr(13:14) = 0b00 2 = '1' to match MemSel = addr(13:14) = 0b01 3 = '1' to match MemSel = addr(13:14) = 0b10 4:35 = Topology_Id_Mask(0:31) when chip_eq_group=0, TIM(0:31) bit 'i' corresponds to addr(15:19) = 'i' when chip_eq_group=1, TIM(0:31) bit 'i' corresponds to (addr(15:16) & addr(19:21)) = 'i' | |
| 36 | RW | RW | CONFIG_GPU3_BAR_SL_MODE: 0/1 = Small-BAR/Large-BAR Mode selector | |
| 37 | RW | RW | CONFIG_GPU3_BAR_4T_LIMIT: 0 = no limit, 16T slices can be used. 1 = limit slices to 4T. -> when chip_eq_group=0, addr(20:21) must match bar_4t_select -> when chip_eq_group=1, addr(17:18) must match bar_4t_select limit=1 is used in P10 systems w/ a GPU or in Axone systems | |
| 38:39 | RW | RW | CONFIG_GPU3_BAR_4T_SELECT: when bar_4t_limit=1 this field selects the value in addr(20:21) to match | |
| 40:43 | RW | RW | CONFIG_GPU3_BAR_MODE: Hash mode of the BAR for brick 3: if bar_extended_mode == 0: 0 = (single) match on all address in addr/size 1 = (dual.0) match if hashbits(7)=0 2 = (dual.1) match if hashbits(7)=1 3 = (triple.0) match if hashbits%3=0 4 = (triple.1) match if hashbits%3=1 5 = (triple.2) match if hashbits%3=2 6 = (quad.0) match if hashbits(6:7)=0 7 = (quad.1) match if hashbits(6:7)=1 8 = (quad.2) match if hashbits(6:7)=2 9 = (quad.3) match if hashbits(6:7)=3 10 = (six.0) match if hashbits%3=0 and hashbits(7)=0 11 = (six.1) match if hashbits%3=0 and hashbits(7)=1 12 = (six.2) match if hashbits%3=1 and hashbits(7)=0 13 = (six.3) match if hashbits%3=1 and hashbits(7)=1 14 = (six.4) match if hashbits%3=2 and hashbits(7)=0 15 = (six.5) match if hashbits%3=2 and hashbits(7)=1 if bar_extended_mode == 1: 0 = (oct.0) match if hashbits(5:7)=0 1 = (oct.1) match if hashbits(5:7)=1 2 = (oct.2) match if hashbits(5:7)=2 3 = (oct.3) match if hashbits(5:7)=3 4 = (oct.4) match if hashbits(5:7)=4 5 = (oct.5) match if hashbits(5:7)=5 6 = (oct.6) match if hashbits(5:7)=6 7 = (oct.7) match if hashbits(5:7)=7 others = reserved | |
| 44 | RW | RW | CONFIG_GPU3_BAR_GRANULE: Hash boundary for brick 3: 0 = hash on 512B boundary (hashbits(0:7)=addr(47:54)) 1 = hash on 1024B boundary (hashbits(0:7)=addr(46:53)) | |
| 45 | RW | RW | CONFIG_GPU3_BAR_POISON: on failed access return all ones 0/1 = with good ECC / with SUE ECC. | |
| 46 | RW | RW | CONFIG_GPU3_BAR_M2MODE: 0 = OpenCAPI AFU M1 mode / 1 = OpenCAPI AFU M2 mode Has no effect when in NVLink mode | |
| 47 | RW | RW | CONFIG_GPU3_BAR_PA_IGNORE_MODE: Set to '1' for RA-to-PA conversion to ignore the mode field | |
| 48 | RW | RW | CONFIG_GPU3_BAR_SECURE_A12: P10 Only: this specifies the addr(12) value to match for this BAR. Can only be set to one in P10 and only when SMF_CONFIG=0b11. | |
| 49 | RW | RW | CONFIG_GPU3_BAR_CHIP_EQ_GROUP: Axone Only: this specifies that the system is in chip=group mode. This bit should only be set when sl_mode=1 and 4t_limit=1. 0/1 = TIM(0:31) applies to addr(15:19) / TIM(0:31) applies to (addr(15:16) & addr(19:21)). | |
| 50 | RW | RW | CONFIG_GPU3_BAR_EXTENDED_MODE: 0/1 = bar_mode selects 1,2,3,4,6 way hashing / bar_mode selects 8-way hashing | |
| 51 | RW | RW | CONFIG_GPU3_BAR_RESERVED: reserved | |
| 52:63 | RO | RO | constant=0b000000000000 | |
| GPU4-Memory BAR | ||||
|---|---|---|---|---|
| Addr: |
0000000011010836 (SCOM) 00000000134001B0 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.SNP.MISC.GPU4_BAR | |||
| Constant(s): | ||||
| Comments: | BAR register defining GPU Mem addresses serviced by brick 4 connected to this stack. Note: This register should be set to the same value for each brick/stack. MDials have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:51 | PAU3.CS.SM0.SNP.MISC.GPU4_BAR_Q_0_INST.LATC.L2(0:51) [0000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_GPU4_BAR_ENABLE: Enable for this BAR (0=disabled, 1=enabled) for brick 4 | |
| 1:35 | RW | RW | CONFIG_GPU4_BAR_ADDR_MASK: BAR Address/Mask bits 1:35 for brick 4 In Small-BAR mode (see bit 36): 1:7 = Base_Addr(13:19) = 16T slice 8:21 = Base_Addr(20:33) = 1G address in slice 22:35 = Base_Mask(20:33) = 1G...16T BAR size. (Note: Mask limited to 1G...4T in Axone and P10 w/ GPU systems) In Large-BAR mode (see bit 36): 1 = '1' to match MemSel = addr(13:14) = 0b00 2 = '1' to match MemSel = addr(13:14) = 0b01 3 = '1' to match MemSel = addr(13:14) = 0b10 4:35 = Topology_Id_Mask(0:31) when chip_eq_group=0, TIM(0:31) bit 'i' corresponds to addr(15:19) = 'i' when chip_eq_group=1, TIM(0:31) bit 'i' corresponds to (addr(15:16) & addr(19:21)) = 'i' | |
| 36 | RW | RW | CONFIG_GPU4_BAR_SL_MODE: 0/1 = Small-BAR/Large-BAR Mode selector | |
| 37 | RW | RW | CONFIG_GPU4_BAR_4T_LIMIT: 0 = no limit, 16T slices can be used. 1 = limit slices to 4T. -> when chip_eq_group=0, addr(20:21) must match bar_4t_select -> when chip_eq_group=1, addr(17:18) must match bar_4t_select limit=1 is used in P10 systems w/ a GPU or in Axone systems | |
| 38:39 | RW | RW | CONFIG_GPU4_BAR_4T_SELECT: when bar_4t_limit=1 this field selects the value in addr(20:21) to match | |
| 40:43 | RW | RW | CONFIG_GPU4_BAR_MODE: Hash mode of the BAR for brick 4: if bar_extended_mode == 0: 0 = (single) match on all address in addr/size 1 = (dual.0) match if hashbits(7)=0 2 = (dual.1) match if hashbits(7)=1 3 = (triple.0) match if hashbits%3=0 4 = (triple.1) match if hashbits%3=1 5 = (triple.2) match if hashbits%3=2 6 = (quad.0) match if hashbits(6:7)=0 7 = (quad.1) match if hashbits(6:7)=1 8 = (quad.2) match if hashbits(6:7)=2 9 = (quad.3) match if hashbits(6:7)=3 10 = (six.0) match if hashbits%3=0 and hashbits(7)=0 11 = (six.1) match if hashbits%3=0 and hashbits(7)=1 12 = (six.2) match if hashbits%3=1 and hashbits(7)=0 13 = (six.3) match if hashbits%3=1 and hashbits(7)=1 14 = (six.4) match if hashbits%3=2 and hashbits(7)=0 15 = (six.5) match if hashbits%3=2 and hashbits(7)=1 if bar_extended_mode == 1: 0 = (oct.0) match if hashbits(5:7)=0 1 = (oct.1) match if hashbits(5:7)=1 2 = (oct.2) match if hashbits(5:7)=2 3 = (oct.3) match if hashbits(5:7)=3 4 = (oct.4) match if hashbits(5:7)=4 5 = (oct.5) match if hashbits(5:7)=5 6 = (oct.6) match if hashbits(5:7)=6 7 = (oct.7) match if hashbits(5:7)=7 others = reserved | |
| 44 | RW | RW | CONFIG_GPU4_BAR_GRANULE: Hash boundary for brick 4: 0 = hash on 512B boundary (hashbits(0:7)=addr(47:54)) 1 = hash on 1024B boundary (hashbits(0:7)=addr(46:53)) | |
| 45 | RW | RW | CONFIG_GPU4_BAR_POISON: on failed access return all ones 0/1 = with good ECC / with SUE ECC. | |
| 46 | RW | RW | CONFIG_GPU4_BAR_M2MODE: 0 = OpenCAPI AFU M1 mode / 1 = OpenCAPI AFU M2 mode Has no effect when in NVLink mode | |
| 47 | RW | RW | CONFIG_GPU4_BAR_PA_IGNORE_MODE: Set to '1' for RA-to-PA conversion to ignore the mode field | |
| 48 | RW | RW | CONFIG_GPU4_BAR_SECURE_A12: P10 Only: this specifies the addr(12) value to match for this BAR. Can only be set to one in P10 and only when SMF_CONFIG=0b11. | |
| 49 | RW | RW | CONFIG_GPU4_BAR_CHIP_EQ_GROUP: Axone Only: this specifies that the system is in chip=group mode. This bit should only be set when sl_mode=1 and 4t_limit=1. 0/1 = TIM(0:31) applies to addr(15:19) / TIM(0:31) applies to (addr(15:16) & addr(19:21)). | |
| 50 | RW | RW | CONFIG_GPU4_BAR_EXTENDED_MODE: 0/1 = bar_mode selects 1,2,3,4,6 way hashing / bar_mode selects 8-way hashing | |
| 51 | RW | RW | CONFIG_GPU4_BAR_RESERVED: reserved | |
| 52:63 | RO | RO | constant=0b000000000000 | |
| NTL0/NDL0 MMIO BAR | ||||
|---|---|---|---|---|
| Addr: |
0000000011010837 (SCOM) 00000000134001B8 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.SNP.MISC.NDT0_BAR | |||
| Constant(s): | ||||
| Comments: | BAR register defining NDL/NTL MMIO (NVLink) or AFU MMIO (OpenCAPI) range for brick 0 connected to this stack Note: This register should be set to the same value for each brick/stack. MDials have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:43 | PAU3.CS.SM0.SNP.MISC.NDT0_BAR_Q_0_INST.LATC.L2(0:43) [00000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_NDT0_BAR_ENABLE: 0/1 = disable/enable BAR for brick 0 | |
| 1 | RW | RW | CONFIG_NDT0_BAR_SECURE_A12: P10 Only: this specifies the addr(12) value to match for this BAR. Can only be set to one in P10 and only when SMF_CONFIG=0b11. | |
| 2 | RW | RW | NDT0_RESERVED1: reserved | |
| 3:35 | RW | RW | CONFIG_NDT0_BAR_ADDR: 64K aligned address of BAR for brick 0's 64K range | |
| 36 | RW | RW | CONFIG_NDT0_BAR_POISON: on failed access return all ones 0/1 = with good ECC / with SUE ECC. | |
| 37:38 | RW | RW | NDT0_RESERVED2: reserved | |
| 39:43 | RW | RW | CONFIG_NDT0_BAR_SIZE: Size of BAR region. 0 = 64K 1 = 128K (NVLink must select this size) 2 = 256K ... 26 = 4T others = reserved | |
| 44:63 | RO | RO | constant=0b00000000000000000000 | |
| NTL1/NDL1 MMIO BAR | ||||
|---|---|---|---|---|
| Addr: |
0000000011010838 (SCOM) 00000000134001C0 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.SNP.MISC.NDT1_BAR | |||
| Constant(s): | ||||
| Comments: | BAR register defining NDL/NTL MMIO (NVLink) or AFU MMIO (OpenCAPI) range for brick 1 connected to this stack Note: This register should be set to the same value for each brick/stack. MDials have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:43 | PAU3.CS.SM0.SNP.MISC.NDT1_BAR_Q_0_INST.LATC.L2(0:43) [00000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_NDT1_BAR_ENABLE: 0/1 = disable/enable BAR for brick 1 | |
| 1 | RW | RW | CONFIG_NDT1_BAR_SECURE_A12: P10 Only: this specifies the addr(12) value to match for this BAR. Can only be set to one in P10 and only when SMF_CONFIG=0b11. | |
| 2 | RW | RW | NDT1_RESERVED1: reserved | |
| 3:35 | RW | RW | CONFIG_NDT1_BAR_ADDR: 64K aligned address of BAR for brick 1's 64K range | |
| 36 | RW | RW | CONFIG_NDT1_BAR_POISON: on failed access return all ones 0/1 = with good ECC / with SUE ECC. | |
| 37:38 | RW | RW | NDT1_RESERVED2: reserved | |
| 39:43 | RW | RW | CONFIG_NDT1_BAR_SIZE: Size of BAR region. 0 = 64K 1 = 128K (NVLink must select this size) 2 = 256K ... 26 = 4T others = reserved | |
| 44:63 | RO | RO | constant=0b00000000000000000000 | |
| NTL2/NDL2 MMIO BAR | ||||
|---|---|---|---|---|
| Addr: |
0000000011010839 (SCOM) 00000000134001C8 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.SNP.MISC.NDT2_BAR | |||
| Constant(s): | ||||
| Comments: | BAR register defining NDL/NTL MMIO (NVLink) or AFU MMIO (OpenCAPI) range for brick 2 connected to this stack Note: This register should be set to the same value for each brick/stack. MDials have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:43 | PAU3.CS.SM0.SNP.MISC.NDT2_BAR_Q_0_INST.LATC.L2(0:43) [00000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_NDT2_BAR_ENABLE: 0/1 = disable/enable BAR for brick 2 | |
| 1 | RW | RW | CONFIG_NDT2_BAR_SECURE_A12: P10 Only: this specifies the addr(12) value to match for this BAR. Can only be set to one in P10 and only when SMF_CONFIG=0b11. | |
| 2 | RW | RW | NDT2_RESERVED1: reserved | |
| 3:35 | RW | RW | CONFIG_NDT2_BAR_ADDR: 64K aligned address of BAR for brick 2's 64K range | |
| 36 | RW | RW | CONFIG_NDT2_BAR_POISON: on failed access return all ones 0/1 = with good ECC / with SUE ECC. | |
| 37:38 | RW | RW | NDT2_RESERVED2: reserved | |
| 39:43 | RW | RW | CONFIG_NDT2_BAR_SIZE: Size of BAR region. 0 = 64K 1 = 128K (NVLink must select this size) 2 = 256K ... 26 = 4T others = reserved | |
| 44:63 | RO | RO | constant=0b00000000000000000000 | |
| NTL3/NDL3 MMIO BAR | ||||
|---|---|---|---|---|
| Addr: |
000000001101083A (SCOM) 00000000134001D0 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.SNP.MISC.NDT3_BAR | |||
| Constant(s): | ||||
| Comments: | BAR register defining NDL/NTL MMIO (NVLink) or AFU MMIO (OpenCAPI) range for brick 3 connected to this stack Note: This register should be set to the same value for each brick/stack. MDials have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:43 | PAU3.CS.SM0.SNP.MISC.NDT3_BAR_Q_0_INST.LATC.L2(0:43) [00000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_NDT3_BAR_ENABLE: 0/1 = disable/enable BAR for brick 3 | |
| 1 | RW | RW | CONFIG_NDT3_BAR_SECURE_A12: P10 Only: this specifies the addr(12) value to match for this BAR. Can only be set to one in P10 and only when SMF_CONFIG=0b11. | |
| 2 | RW | RW | NDT3_RESERVED1: reserved | |
| 3:35 | RW | RW | CONFIG_NDT3_BAR_ADDR: 64K aligned address of BAR for brick 3's 64K range | |
| 36 | RW | RW | CONFIG_NDT3_BAR_POISON: on failed access return all ones 0/1 = with good ECC / with SUE ECC. | |
| 37:38 | RW | RW | NDT3_RESERVED2: reserved | |
| 39:43 | RW | RW | CONFIG_NDT3_BAR_SIZE: Size of BAR region. 0 = 64K 1 = 128K (NVLink must select this size) 2 = 256K ... 26 = 4T others = reserved | |
| 44:63 | RO | RO | constant=0b00000000000000000000 | |
| NTL4/NDL4 MMIO BAR | ||||
|---|---|---|---|---|
| Addr: |
000000001101083B (SCOM) 00000000134001D8 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.SNP.MISC.NDT4_BAR | |||
| Constant(s): | ||||
| Comments: | BAR register defining NDL/NTL MMIO (NVLink) or AFU MMIO (OpenCAPI) range for brick 4 connected to this stack Note: This register should be set to the same value for each brick/stack. MDials have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:43 | PAU3.CS.SM0.SNP.MISC.NDT4_BAR_Q_0_INST.LATC.L2(0:43) [00000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_NDT4_BAR_ENABLE: 0/1 = disable/enable BAR for brick 4 | |
| 1 | RW | RW | CONFIG_NDT4_BAR_SECURE_A12: P10 Only: this specifies the addr(12) value to match for this BAR. Can only be set to one in P10 and only when SMF_CONFIG=0b11. | |
| 2 | RW | RW | NDT4_RESERVED1: reserved | |
| 3:35 | RW | RW | CONFIG_NDT4_BAR_ADDR: 64K aligned address of BAR for brick 4's 64K range | |
| 36 | RW | RW | CONFIG_NDT4_BAR_POISON: on failed access return all ones 0/1 = with good ECC / with SUE ECC. | |
| 37:38 | RW | RW | NDT4_RESERVED2: reserved | |
| 39:43 | RW | RW | CONFIG_NDT4_BAR_SIZE: Size of BAR region. 0 = 64K 1 = 128K (NVLink must select this size) 2 = 256K ... 26 = 4T others = reserved | |
| 44:63 | RO | RO | constant=0b00000000000000000000 | |
| PAU MMIO BAR | ||||
|---|---|---|---|---|
| Addr: |
000000001101083C (SCOM) 00000000134001E0 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.SNP.MISC.PAUMMIO_BAR | |||
| Constant(s): | ||||
| Comments: | BAR register definingPAU MMIO range Note: This register should be set to the same value for each brick/stack. MDials have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:31 | PAU3.CS.SM0.SNP.MISC.PAUMMIO_BAR_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_PAUMMIO_BAR_ENABLE: 0/1 = disable/enable PAUMMIO_BAR | |
| 1 | RW | RW | CONFIG_PAUMMIO_BAR_SECURE_A12: P10 Only: this specifies the addr(12) value to match for this BAR. Can only be set to one in P10 and only when SMF_CONFIG=0b11. | |
| 2 | RW | RW | PAUMMIO_RESERVED1: reserved | |
| 3:27 | RW | RW | CONFIG_PAUMMIO_BAR_ADDR: 16M aligned address of this PAUMMIO_BAR's 16M range. Bits 15:39 of the RA | |
| 28:30 | RW | RW | PAUMMIO_RESERVED2: reserved | |
| 31 | RW | RW | CONFIG_PAUMMIO_BAR_POISON: On failed access return all ones 0/1 = with good ECC / with SUE ECC. | |
| 32:63 | RO | RO | constant=0b00000000000000000000000000000000 | |
| Generation-ID Registers MMIO BAR | ||||
|---|---|---|---|---|
| Addr: |
000000001101083D (SCOM) 00000000134001E8 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.SNP.MISC.GENID_BAR | |||
| Constant(s): | ||||
| Comments: | NVLink mode: BAR register defining Generation-ID registers for this stack/ramp OCAPI mode: BAR register defining Config space + Generation-ID registers registers for this stack/ramp Note: This register should be set to the same value for each brick/stack. MDials have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:35 | PAU3.CS.SM0.SNP.MISC.GENID_BAR_Q_0_INST.LATC.L2(0:35) [000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_GENID_BAR_ENABLE: 0/1 = disable/enable this BAR | |
| 1 | RW | RW | CONFIG_GENID_BAR_SECURE_A12: P10 Only: this specifies the addr(12) value to match for this BAR. Can only be set to one in P10 and only when SMF_CONFIG=0b11. | |
| 2 | RW | RW | GENID_RESERVED1: reserved | |
| 3:32 | RW | RW | CONFIG_GENID_BAR_ADDR: 512K aligned address +0K = Brick 0 Gen-Id Registers +64K = Brick 1 Gen-Id Registers +128K = Brick 2 Gen-Id Registers +192K = Brick 3 Gen-Id Registers +256K = Brick 4 Gen-Id Registers +320K = Bricks 0-4 Config Addr/Data registers for OCAPI links +384K = reserved +448K = reserved | |
| 33:34 | RW | RW | GENID_RESERVED2: reserved | |
| 35 | RW | RW | CONFIG_GENID_BAR_POISON: on failed access return all ones 0/1 = with good ECC / with SUE ECC. | |
| 36:63 | RO | RO | constant=0b0000000000000000000000000000 | |
| Relexed-Ordering Source 0 Config | ||||
|---|---|---|---|---|
| Addr: |
000000001101083E (SCOM) 00000000134001F0 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.SNP.MISC.CONFIG_RELAXED_SRC0 | |||
| Constant(s): | ||||
| Comments: | Configure relaxed-ordering source Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM0.SNP.MISC.CONFIG_RELAXED_SRC0_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:13 | RW | RW | CONFIG_RELAXED_SOURCE0_TAG: P10: Match against ('00' & ttag(0:11)). | |
| 14:27 | RW | RW | CONFIG_RELAXED_SOURCE0_TAGMASK: Mask on tag(0:13). 0=must-match, 1=don't-care. | |
| 28 | RW | RW | CONFIG_RELAXED_SOURCE0_MASK_PAU: P10: match ttag(7:9)=000,001,111 | |
| 29 | RW | RW | CONFIG_RELAXED_SOURCE0_MASK_PCIE: P10: reserved | |
| 30 | RW | RW | CONFIG_RELAXED_SOURCE0_MASK_L2L3: P10: reserved | |
| 31 | RW | RW | CONFIG_RELAXED_SOURCE0_RESERVED1: reserved | |
| 32:39 | RW | RW | CONFIG_RELAXED_SOURCE0_RDSTART: P10: ttag(12:19) start-of-read-tags value (first tag) | |
| 40:47 | RW | RW | CONFIG_RELAXED_SOURCE0_RDEND: P10: ttag(12:19) end-of-read-tags value (last tag) | |
| 48:55 | RW | RW | CONFIG_RELAXED_SOURCE0_WRSTART: P10: ttag(12:19) start-of-write-tags value (first tag) | |
| 56:63 | RW | RW | CONFIG_RELAXED_SOURCE0_WREND: P10: ttag(12:19) end-of-write-tags value (last tag) | |
| Relexed-Ordering Source 1 Config | ||||
|---|---|---|---|---|
| Addr: |
000000001101083F (SCOM) 00000000134001F8 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.SNP.MISC.CONFIG_RELAXED_SRC1 | |||
| Constant(s): | ||||
| Comments: | Configure relaxed-ordering source Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM0.SNP.MISC.CONFIG_RELAXED_SRC1_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:13 | RW | RW | CONFIG_RELAXED_SOURCE1_TAG: P10: Match against ('00' & ttag(0:11)). | |
| 14:27 | RW | RW | CONFIG_RELAXED_SOURCE1_TAGMASK: Mask on tag(0:13). 0=must-match, 1=don't-care. | |
| 28 | RW | RW | CONFIG_RELAXED_SOURCE1_MASK_PAU: P10: match ttag(7:9)=000,001,111 | |
| 29 | RW | RW | CONFIG_RELAXED_SOURCE1_MASK_PCIE: P10: reserved | |
| 30 | RW | RW | CONFIG_RELAXED_SOURCE1_MASK_L2L3: P10: reserved | |
| 31 | RW | RW | CONFIG_RELAXED_SOURCE1_RESERVED1: reserved | |
| 32:39 | RW | RW | CONFIG_RELAXED_SOURCE1_RDSTART: P10: ttag(12:19) start-of-read-tags value (first tag) | |
| 40:47 | RW | RW | CONFIG_RELAXED_SOURCE1_RDEND: P10: ttag(12:19) end-of-read-tags value (last tag) | |
| 48:55 | RW | RW | CONFIG_RELAXED_SOURCE1_WRSTART: P10: ttag(12:19) start-of-write-tags value (first tag) | |
| 56:63 | RW | RW | CONFIG_RELAXED_SOURCE1_WREND: P10: ttag(12:19) end-of-write-tags value (last tag) | |
| Relexed-Ordering Source 2 Config | ||||
|---|---|---|---|---|
| Addr: |
0000000011010840 (SCOM) 0000000013400200 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.SNP.MISC.CONFIG_RELAXED_SRC2 | |||
| Constant(s): | ||||
| Comments: | Configure relaxed-ordering source Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM0.SNP.MISC.CONFIG_RELAXED_SRC2_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:13 | RW | RW | CONFIG_RELAXED_SOURCE2_TAG: P10: Match against ('00' & ttag(0:11)). | |
| 14:27 | RW | RW | CONFIG_RELAXED_SOURCE2_TAGMASK: Mask on tag(0:13). 0=must-match, 1=don't-care. | |
| 28 | RW | RW | CONFIG_RELAXED_SOURCE2_MASK_PAU: P10: match ttag(7:9)=000,001,111 | |
| 29 | RW | RW | CONFIG_RELAXED_SOURCE2_MASK_PCIE: P10: reserved | |
| 30 | RW | RW | CONFIG_RELAXED_SOURCE2_MASK_L2L3: P10: reserved | |
| 31 | RW | RW | CONFIG_RELAXED_SOURCE2_RESERVED1: reserved | |
| 32:39 | RW | RW | CONFIG_RELAXED_SOURCE2_RDSTART: P10: ttag(12:19) start-of-read-tags value (first tag) | |
| 40:47 | RW | RW | CONFIG_RELAXED_SOURCE2_RDEND: P10: ttag(12:19) end-of-read-tags value (last tag) | |
| 48:55 | RW | RW | CONFIG_RELAXED_SOURCE2_WRSTART: P10: ttag(12:19) start-of-write-tags value (first tag) | |
| 56:63 | RW | RW | CONFIG_RELAXED_SOURCE2_WREND: P10: ttag(12:19) end-of-write-tags value (last tag) | |
| Relexed-Ordering Source 3 Config | ||||
|---|---|---|---|---|
| Addr: |
0000000011010841 (SCOM) 0000000013400208 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.SNP.MISC.CONFIG_RELAXED_SRC3 | |||
| Constant(s): | ||||
| Comments: | Configure relaxed-ordering source Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM0.SNP.MISC.CONFIG_RELAXED_SRC3_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:13 | RW | RW | CONFIG_RELAXED_SOURCE3_TAG: P10: Match against ('00' & ttag(0:11)). | |
| 14:27 | RW | RW | CONFIG_RELAXED_SOURCE3_TAGMASK: Mask on tag(0:13). 0=must-match, 1=don't-care. | |
| 28 | RW | RW | CONFIG_RELAXED_SOURCE3_MASK_PAU: P10: match ttag(7:9)=000,001,111 | |
| 29 | RW | RW | CONFIG_RELAXED_SOURCE3_MASK_PCIE: P10: reserved | |
| 30 | RW | RW | CONFIG_RELAXED_SOURCE3_MASK_L2L3: P10: reserved | |
| 31 | RW | RW | CONFIG_RELAXED_SOURCE3_RESERVED1: reserved | |
| 32:39 | RW | RW | CONFIG_RELAXED_SOURCE3_RDSTART: P10: ttag(12:19) start-of-read-tags value (first tag) | |
| 40:47 | RW | RW | CONFIG_RELAXED_SOURCE3_RDEND: P10: ttag(12:19) end-of-read-tags value (last tag) | |
| 48:55 | RW | RW | CONFIG_RELAXED_SOURCE3_WRSTART: P10: ttag(12:19) start-of-write-tags value (first tag) | |
| 56:63 | RW | RW | CONFIG_RELAXED_SOURCE3_WREND: P10: ttag(12:19) end-of-write-tags value (last tag) | |
| Relexed-Ordering Source 4 Config | ||||
|---|---|---|---|---|
| Addr: |
0000000011010842 (SCOM) 0000000013400210 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.SNP.MISC.CONFIG_RELAXED_SRC4 | |||
| Constant(s): | ||||
| Comments: | Configure relaxed-ordering source Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM0.SNP.MISC.CONFIG_RELAXED_SRC4_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:13 | RW | RW | CONFIG_RELAXED_SOURCE4_TAG: P10: Match against ('00' & ttag(0:11)). | |
| 14:27 | RW | RW | CONFIG_RELAXED_SOURCE4_TAGMASK: Mask on tag(0:13). 0=must-match, 1=don't-care. | |
| 28 | RW | RW | CONFIG_RELAXED_SOURCE4_MASK_PAU: P10: match ttag(7:9)=000,001,111 | |
| 29 | RW | RW | CONFIG_RELAXED_SOURCE4_MASK_PCIE: P10: reserved | |
| 30 | RW | RW | CONFIG_RELAXED_SOURCE4_MASK_L2L3: P10: reserved | |
| 31 | RW | RW | CONFIG_RELAXED_SOURCE4_RESERVED1: reserved | |
| 32:39 | RW | RW | CONFIG_RELAXED_SOURCE4_RDSTART: P10: ttag(12:19) start-of-read-tags value (first tag) | |
| 40:47 | RW | RW | CONFIG_RELAXED_SOURCE4_RDEND: P10: ttag(12:19) end-of-read-tags value (last tag) | |
| 48:55 | RW | RW | CONFIG_RELAXED_SOURCE4_WRSTART: P10: ttag(12:19) start-of-write-tags value (first tag) | |
| 56:63 | RW | RW | CONFIG_RELAXED_SOURCE4_WREND: P10: ttag(12:19) end-of-write-tags value (last tag) | |
| Relexed-Ordering Source 5 Config | ||||
|---|---|---|---|---|
| Addr: |
0000000011010843 (SCOM) 0000000013400218 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.SNP.MISC.CONFIG_RELAXED_SRC5 | |||
| Constant(s): | ||||
| Comments: | Configure relaxed-ordering source Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM0.SNP.MISC.CONFIG_RELAXED_SRC5_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:13 | RW | RW | CONFIG_RELAXED_SOURCE5_TAG: P10: Match against ('00' & ttag(0:11)). | |
| 14:27 | RW | RW | CONFIG_RELAXED_SOURCE5_TAGMASK: Mask on tag(0:13). 0=must-match, 1=don't-care. | |
| 28 | RW | RW | CONFIG_RELAXED_SOURCE5_MASK_PAU: P10: match ttag(7:9)=000,001,111 | |
| 29 | RW | RW | CONFIG_RELAXED_SOURCE5_MASK_PCIE: P10: reserved | |
| 30 | RW | RW | CONFIG_RELAXED_SOURCE5_MASK_L2L3: P10: reserved | |
| 31 | RW | RW | CONFIG_RELAXED_SOURCE5_RESERVED1: reserved | |
| 32:39 | RW | RW | CONFIG_RELAXED_SOURCE5_RDSTART: P10: ttag(12:19) start-of-read-tags value (first tag) | |
| 40:47 | RW | RW | CONFIG_RELAXED_SOURCE5_RDEND: P10: ttag(12:19) end-of-read-tags value (last tag) | |
| 48:55 | RW | RW | CONFIG_RELAXED_SOURCE5_WRSTART: P10: ttag(12:19) start-of-write-tags value (first tag) | |
| 56:63 | RW | RW | CONFIG_RELAXED_SOURCE5_WREND: P10: ttag(12:19) end-of-write-tags value (last tag) | |
| Relexed-Ordering Source 6 Config | ||||
|---|---|---|---|---|
| Addr: |
0000000011010844 (SCOM) 0000000013400220 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.SNP.MISC.CONFIG_RELAXED_SRC6 | |||
| Constant(s): | ||||
| Comments: | Configure relaxed-ordering source Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM0.SNP.MISC.CONFIG_RELAXED_SRC6_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:13 | RW | RW | CONFIG_RELAXED_SOURCE6_TAG: P10: Match against ('00' & ttag(0:11)). | |
| 14:27 | RW | RW | CONFIG_RELAXED_SOURCE6_TAGMASK: Mask on tag(0:13). 0=must-match, 1=don't-care. | |
| 28 | RW | RW | CONFIG_RELAXED_SOURCE6_MASK_PAU: P10: match ttag(7:9)=000,001,111 | |
| 29 | RW | RW | CONFIG_RELAXED_SOURCE6_MASK_PCIE: P10: reserved | |
| 30 | RW | RW | CONFIG_RELAXED_SOURCE6_MASK_L2L3: P10: reserved | |
| 31 | RW | RW | CONFIG_RELAXED_SOURCE6_RESERVED1: reserved | |
| 32:39 | RW | RW | CONFIG_RELAXED_SOURCE6_RDSTART: P10: ttag(12:19) start-of-read-tags value (first tag) | |
| 40:47 | RW | RW | CONFIG_RELAXED_SOURCE6_RDEND: P10: ttag(12:19) end-of-read-tags value (last tag) | |
| 48:55 | RW | RW | CONFIG_RELAXED_SOURCE6_WRSTART: P10: ttag(12:19) start-of-write-tags value (first tag) | |
| 56:63 | RW | RW | CONFIG_RELAXED_SOURCE6_WREND: P10: ttag(12:19) end-of-write-tags value (last tag) | |
| Relexed-Ordering Source 7 Config | ||||
|---|---|---|---|---|
| Addr: |
0000000011010845 (SCOM) 0000000013400228 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.SNP.MISC.CONFIG_RELAXED_SRC7 | |||
| Constant(s): | ||||
| Comments: | Configure relaxed-ordering source Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM0.SNP.MISC.CONFIG_RELAXED_SRC7_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:13 | RW | RW | CONFIG_RELAXED_SOURCE7_TAG: P10: Match against ('00' & ttag(0:11)). | |
| 14:27 | RW | RW | CONFIG_RELAXED_SOURCE7_TAGMASK: Mask on tag(0:13). 0=must-match, 1=don't-care. | |
| 28 | RW | RW | CONFIG_RELAXED_SOURCE7_MASK_PAU: P10: match ttag(7:9)=000,001,111 | |
| 29 | RW | RW | CONFIG_RELAXED_SOURCE7_MASK_PCIE: P10: reserved | |
| 30 | RW | RW | CONFIG_RELAXED_SOURCE7_MASK_L2L3: P10: reserved | |
| 31 | RW | RW | CONFIG_RELAXED_SOURCE7_RESERVED1: reserved | |
| 32:39 | RW | RW | CONFIG_RELAXED_SOURCE7_RDSTART: P10: ttag(12:19) start-of-read-tags value (first tag) | |
| 40:47 | RW | RW | CONFIG_RELAXED_SOURCE7_RDEND: P10: ttag(12:19) end-of-read-tags value (last tag) | |
| 48:55 | RW | RW | CONFIG_RELAXED_SOURCE7_WRSTART: P10: ttag(12:19) start-of-write-tags value (first tag) | |
| 56:63 | RW | RW | CONFIG_RELAXED_SOURCE7_WREND: P10: ttag(12:19) end-of-write-tags value (last tag) | |
| Relaxed-Ordering Config2 brick 0 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010846 (SCOM) 0000000013400230 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.SNP.MISC.CONFIG_RELAXED_BRK0 | |||
| Constant(s): | ||||
| Comments: | Configure relaxed-ordering Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM0.SNP.MISC.CONFIG_RELAXED_BRK0_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_RELAXED_BRK0_CMD_CL_DMA_W: enable relaxed ordering for (non-atomic write) cl_dma_w (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 1 | RW | RW | CONFIG_RELAXED_BRK0_CMD_CL_DMA_W_HP: Reserved. (was: enable relaxed ordering for (non-atomic write) cl_dma_w_hp (only valid for GPU and AFU-M2 memory)) | |
| 2 | RW | RW | CONFIG_RELAXED_BRK0_CMD_CL_DMA_INJ: enable relaxed ordering for (non-atomic write) cl_dma_inj (only valid for GPU and AFU-M2 memory) | |
| 3 | RW | RW | CONFIG_RELAXED_BRK0_CMD_PR_DMA_INJ: enable relaxed ordering for (non-atomic write) pr_dma_inj (only valid for GPU and AFU-M2 memory) | |
| 4 | RW | RW | CONFIG_RELAXED_BRK0_CMD_DMA_PR_W: enable relaxed ordering for (non-atomic write) dma_pr_w (only valid for GPU and AFU-M2 memory) | |
| 5 | RW | RW | CONFIG_RELAXED_BRK0_CMD_CL_RD_NC_F0: enable relaxed ordering for (non-atomic read) cl_rd_nc(F=0) (only valid for GPU and AFU-M2 memory) | |
| 6 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMW_CAS_IMAX_U: enable relaxed ordering for (atomic write) armw_cas_imax_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 7 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMW_CAS_IMAX_S: enable relaxed ordering for (atomic write) armw_cas_imax_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 8 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMW_CAS_IMIN_U: enable relaxed ordering for (atomic write) armw_cas_imin_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 9 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMW_CAS_IMIN_S: enable relaxed ordering for (atomic write) armw_cas_imin_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 10 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMW_ADD: enable relaxed ordering for (atomic write) armw_add (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 11 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMW_AND: enable relaxed ordering for (atomic write) armw_and (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 12 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMW_OR: enable relaxed ordering for (atomic write) armw_or (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 13 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMW_XOR: enable relaxed ordering for (atomic write) armw_xor (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 14 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMWF_CAS_IMAX_U: enable relaxed ordering for (atomic read) armwf_cas_imax_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 15 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMWF_CAS_IMAX_S: enable relaxed ordering for (atomic read) armwf_cas_imax_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 16 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMWF_CAS_IMIN_U: enable relaxed ordering for (atomic read) armwf_cas_imin_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 17 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMWF_CAS_IMIN_S: enable relaxed ordering for (atomic read) armwf_cas_imin_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 18 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMWF_ADD: enable relaxed ordering for (atomic read) armwf_add (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 19 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMWF_AND: enable relaxed ordering for (atomic read) armwf_and (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 20 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMWF_OR: enable relaxed ordering for (atomic read) armwf_or (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 21 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMWF_XOR: enable relaxed ordering for (atomic read) armwf_xor (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 22 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMWF_CAS_E: enable relaxed ordering for (atomic read) armwf_cas_e (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 23 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMWF_CAS_U: enable relaxed ordering for (atomic read) armwf_cas_u (only valid for OCAPI AFU-M1 or AFU-M2 memory) (errata HW367501 requires this bit to be 0 for GPU memory) | |
| 24 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMW_CAS_T: enable relaxed ordering for (atomic write) armw_cas_t (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 25 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMWF_CAS_NE: enable relaxed ordering for (atomic read) armwf_cas_ne (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 26 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMWF_INC_B: enable relaxed ordering for (atomic read) armwf_inc_b (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 27 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMWF_INC_E: enable relaxed ordering for (atomic read) armwf_inc_e (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 28 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMWF_DEC_B: enable relaxed ordering for (atomic read) armwf_dec_b (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 29:31 | RW | RW | CONFIG_RELAXED_BRK0_RESERVED1: reserved | |
| 32 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE0_WRENA: 0/1 = disable/enable relaxed source 0 for (non-atomic) write operations | |
| 33 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE0_RDENA: 0/1 = disable/enable relaxed source 0 for (non-atomic) read operations | |
| 34 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE0_AWENA: 0/1 = disable/enable relaxed source 0 for atomic (write) operations | |
| 35 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE0_ARENA: 0/1 = disable/enable relaxed source 0 for atomic (read) operations | |
| 36 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE1_WRENA: 0/1 = disable/enable relaxed source 1 for (non-atomic) write operations | |
| 37 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE1_RDENA: 0/1 = disable/enable relaxed source 1 for (non-atomic) read operations | |
| 38 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE1_AWENA: 0/1 = disable/enable relaxed source 1 for atomic (write) operations | |
| 39 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE1_ARENA: 0/1 = disable/enable relaxed source 1 for atomic (read) operations | |
| 40 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE2_WRENA: 0/1 = disable/enable relaxed source 2 for (non-atomic) write operations | |
| 41 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE2_RDENA: 0/1 = disable/enable relaxed source 2 for (non-atomic) read operations | |
| 42 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE2_AWENA: 0/1 = disable/enable relaxed source 2 for atomic (write) operations | |
| 43 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE2_ARENA: 0/1 = disable/enable relaxed source 2 for atomic (read) operations | |
| 44 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE3_WRENA: 0/1 = disable/enable relaxed source 3 for (non-atomic) write operations | |
| 45 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE3_RDENA: 0/1 = disable/enable relaxed source 3 for (non-atomic) read operations | |
| 46 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE3_AWENA: 0/1 = disable/enable relaxed source 3 for atomic (write) operations | |
| 47 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE3_ARENA: 0/1 = disable/enable relaxed source 3 for atomic (read) operations | |
| 48 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE4_WRENA: 0/1 = disable/enable relaxed source 4 for (non-atomic) write operations | |
| 49 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE4_RDENA: 0/1 = disable/enable relaxed source 4 for (non-atomic) read operations | |
| 50 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE4_AWENA: 0/1 = disable/enable relaxed source 4 for atomic (write) operations | |
| 51 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE4_ARENA: 0/1 = disable/enable relaxed source 4 for atomic (read) operations | |
| 52 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE5_WRENA: 0/1 = disable/enable relaxed source 5 for (non-atomic) write operations | |
| 53 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE5_RDENA: 0/1 = disable/enable relaxed source 5 for (non-atomic) read operations | |
| 54 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE5_AWENA: 0/1 = disable/enable relaxed source 5 for atomic (write) operations | |
| 55 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE5_ARENA: 0/1 = disable/enable relaxed source 5 for atomic (read) operations | |
| 56 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE6_WRENA: 0/1 = disable/enable relaxed source 6 for (non-atomic) write operations | |
| 57 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE6_RDENA: 0/1 = disable/enable relaxed source 6 for (non-atomic) read operations | |
| 58 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE6_AWENA: 0/1 = disable/enable relaxed source 6 for atomic (write) operations | |
| 59 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE6_ARENA: 0/1 = disable/enable relaxed source 6 for atomic (read) operations | |
| 60 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE7_WRENA: 0/1 = disable/enable relaxed source 7 for (non-atomic) write operations | |
| 61 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE7_RDENA: 0/1 = disable/enable relaxed source 7 for (non-atomic) read operations | |
| 62 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE7_AWENA: 0/1 = disable/enable relaxed source 7 for atomic (write) operations | |
| 63 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE7_ARENA: 0/1 = disable/enable relaxed source 7 for atomic (read) operations | |
| Relaxed-Ordering Config2 brick 1 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010847 (SCOM) 0000000013400238 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.SNP.MISC.CONFIG_RELAXED_BRK1 | |||
| Constant(s): | ||||
| Comments: | Configure relaxed-ordering Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM0.SNP.MISC.CONFIG_RELAXED_BRK1_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_RELAXED_BRK1_CMD_CL_DMA_W: enable relaxed ordering for (non-atomic write) cl_dma_w (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 1 | RW | RW | CONFIG_RELAXED_BRK1_CMD_CL_DMA_W_HP: Reserved. (was: enable relaxed ordering for (non-atomic write) cl_dma_w_hp (only valid for GPU and AFU-M2 memory)) | |
| 2 | RW | RW | CONFIG_RELAXED_BRK1_CMD_CL_DMA_INJ: enable relaxed ordering for (non-atomic write) cl_dma_inj (only valid for GPU and AFU-M2 memory) | |
| 3 | RW | RW | CONFIG_RELAXED_BRK1_CMD_PR_DMA_INJ: enable relaxed ordering for (non-atomic write) pr_dma_inj (only valid for GPU and AFU-M2 memory) | |
| 4 | RW | RW | CONFIG_RELAXED_BRK1_CMD_DMA_PR_W: enable relaxed ordering for (non-atomic write) dma_pr_w (only valid for GPU and AFU-M2 memory) | |
| 5 | RW | RW | CONFIG_RELAXED_BRK1_CMD_CL_RD_NC_F0: enable relaxed ordering for (non-atomic read) cl_rd_nc(F=0) (only valid for GPU and AFU-M2 memory) | |
| 6 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMW_CAS_IMAX_U: enable relaxed ordering for (atomic write) armw_cas_imax_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 7 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMW_CAS_IMAX_S: enable relaxed ordering for (atomic write) armw_cas_imax_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 8 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMW_CAS_IMIN_U: enable relaxed ordering for (atomic write) armw_cas_imin_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 9 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMW_CAS_IMIN_S: enable relaxed ordering for (atomic write) armw_cas_imin_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 10 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMW_ADD: enable relaxed ordering for (atomic write) armw_add (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 11 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMW_AND: enable relaxed ordering for (atomic write) armw_and (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 12 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMW_OR: enable relaxed ordering for (atomic write) armw_or (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 13 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMW_XOR: enable relaxed ordering for (atomic write) armw_xor (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 14 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMWF_CAS_IMAX_U: enable relaxed ordering for (atomic read) armwf_cas_imax_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 15 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMWF_CAS_IMAX_S: enable relaxed ordering for (atomic read) armwf_cas_imax_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 16 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMWF_CAS_IMIN_U: enable relaxed ordering for (atomic read) armwf_cas_imin_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 17 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMWF_CAS_IMIN_S: enable relaxed ordering for (atomic read) armwf_cas_imin_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 18 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMWF_ADD: enable relaxed ordering for (atomic read) armwf_add (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 19 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMWF_AND: enable relaxed ordering for (atomic read) armwf_and (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 20 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMWF_OR: enable relaxed ordering for (atomic read) armwf_or (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 21 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMWF_XOR: enable relaxed ordering for (atomic read) armwf_xor (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 22 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMWF_CAS_E: enable relaxed ordering for (atomic read) armwf_cas_e (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 23 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMWF_CAS_U: enable relaxed ordering for (atomic read) armwf_cas_u (only valid for OCAPI AFU-M1 or AFU-M2 memory) (errata HW367501 requires this bit to be 0 for GPU memory) | |
| 24 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMW_CAS_T: enable relaxed ordering for (atomic write) armw_cas_t (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 25 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMWF_CAS_NE: enable relaxed ordering for (atomic read) armwf_cas_ne (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 26 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMWF_INC_B: enable relaxed ordering for (atomic read) armwf_inc_b (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 27 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMWF_INC_E: enable relaxed ordering for (atomic read) armwf_inc_e (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 28 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMWF_DEC_B: enable relaxed ordering for (atomic read) armwf_dec_b (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 29:31 | RW | RW | CONFIG_RELAXED_BRK1_RESERVED1: reserved | |
| 32 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE0_WRENA: 0/1 = disable/enable relaxed source 0 for (non-atomic) write operations | |
| 33 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE0_RDENA: 0/1 = disable/enable relaxed source 0 for (non-atomic) read operations | |
| 34 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE0_AWENA: 0/1 = disable/enable relaxed source 0 for atomic (write) operations | |
| 35 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE0_ARENA: 0/1 = disable/enable relaxed source 0 for atomic (read) operations | |
| 36 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE1_WRENA: 0/1 = disable/enable relaxed source 1 for (non-atomic) write operations | |
| 37 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE1_RDENA: 0/1 = disable/enable relaxed source 1 for (non-atomic) read operations | |
| 38 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE1_AWENA: 0/1 = disable/enable relaxed source 1 for atomic (write) operations | |
| 39 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE1_ARENA: 0/1 = disable/enable relaxed source 1 for atomic (read) operations | |
| 40 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE2_WRENA: 0/1 = disable/enable relaxed source 2 for (non-atomic) write operations | |
| 41 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE2_RDENA: 0/1 = disable/enable relaxed source 2 for (non-atomic) read operations | |
| 42 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE2_AWENA: 0/1 = disable/enable relaxed source 2 for atomic (write) operations | |
| 43 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE2_ARENA: 0/1 = disable/enable relaxed source 2 for atomic (read) operations | |
| 44 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE3_WRENA: 0/1 = disable/enable relaxed source 3 for (non-atomic) write operations | |
| 45 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE3_RDENA: 0/1 = disable/enable relaxed source 3 for (non-atomic) read operations | |
| 46 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE3_AWENA: 0/1 = disable/enable relaxed source 3 for atomic (write) operations | |
| 47 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE3_ARENA: 0/1 = disable/enable relaxed source 3 for atomic (read) operations | |
| 48 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE4_WRENA: 0/1 = disable/enable relaxed source 4 for (non-atomic) write operations | |
| 49 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE4_RDENA: 0/1 = disable/enable relaxed source 4 for (non-atomic) read operations | |
| 50 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE4_AWENA: 0/1 = disable/enable relaxed source 4 for atomic (write) operations | |
| 51 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE4_ARENA: 0/1 = disable/enable relaxed source 4 for atomic (read) operations | |
| 52 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE5_WRENA: 0/1 = disable/enable relaxed source 5 for (non-atomic) write operations | |
| 53 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE5_RDENA: 0/1 = disable/enable relaxed source 5 for (non-atomic) read operations | |
| 54 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE5_AWENA: 0/1 = disable/enable relaxed source 5 for atomic (write) operations | |
| 55 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE5_ARENA: 0/1 = disable/enable relaxed source 5 for atomic (read) operations | |
| 56 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE6_WRENA: 0/1 = disable/enable relaxed source 6 for (non-atomic) write operations | |
| 57 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE6_RDENA: 0/1 = disable/enable relaxed source 6 for (non-atomic) read operations | |
| 58 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE6_AWENA: 0/1 = disable/enable relaxed source 6 for atomic (write) operations | |
| 59 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE6_ARENA: 0/1 = disable/enable relaxed source 6 for atomic (read) operations | |
| 60 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE7_WRENA: 0/1 = disable/enable relaxed source 7 for (non-atomic) write operations | |
| 61 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE7_RDENA: 0/1 = disable/enable relaxed source 7 for (non-atomic) read operations | |
| 62 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE7_AWENA: 0/1 = disable/enable relaxed source 7 for atomic (write) operations | |
| 63 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE7_ARENA: 0/1 = disable/enable relaxed source 7 for atomic (read) operations | |
| Relaxed-Ordering Config2 brick 2 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010848 (SCOM) 0000000013400240 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.SNP.MISC.CONFIG_RELAXED_BRK2 | |||
| Constant(s): | ||||
| Comments: | Configure relaxed-ordering Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM0.SNP.MISC.CONFIG_RELAXED_BRK2_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_RELAXED_BRK2_CMD_CL_DMA_W: enable relaxed ordering for (non-atomic write) cl_dma_w (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 1 | RW | RW | CONFIG_RELAXED_BRK2_CMD_CL_DMA_W_HP: Reserved. (was: enable relaxed ordering for (non-atomic write) cl_dma_w_hp (only valid for GPU and AFU-M2 memory)) | |
| 2 | RW | RW | CONFIG_RELAXED_BRK2_CMD_CL_DMA_INJ: enable relaxed ordering for (non-atomic write) cl_dma_inj (only valid for GPU and AFU-M2 memory) | |
| 3 | RW | RW | CONFIG_RELAXED_BRK2_CMD_PR_DMA_INJ: enable relaxed ordering for (non-atomic write) pr_dma_inj (only valid for GPU and AFU-M2 memory) | |
| 4 | RW | RW | CONFIG_RELAXED_BRK2_CMD_DMA_PR_W: enable relaxed ordering for (non-atomic write) dma_pr_w (only valid for GPU and AFU-M2 memory) | |
| 5 | RW | RW | CONFIG_RELAXED_BRK2_CMD_CL_RD_NC_F0: enable relaxed ordering for (non-atomic read) cl_rd_nc(F=0) (only valid for GPU and AFU-M2 memory) | |
| 6 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMW_CAS_IMAX_U: enable relaxed ordering for (atomic write) armw_cas_imax_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 7 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMW_CAS_IMAX_S: enable relaxed ordering for (atomic write) armw_cas_imax_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 8 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMW_CAS_IMIN_U: enable relaxed ordering for (atomic write) armw_cas_imin_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 9 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMW_CAS_IMIN_S: enable relaxed ordering for (atomic write) armw_cas_imin_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 10 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMW_ADD: enable relaxed ordering for (atomic write) armw_add (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 11 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMW_AND: enable relaxed ordering for (atomic write) armw_and (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 12 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMW_OR: enable relaxed ordering for (atomic write) armw_or (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 13 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMW_XOR: enable relaxed ordering for (atomic write) armw_xor (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 14 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMWF_CAS_IMAX_U: enable relaxed ordering for (atomic read) armwf_cas_imax_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 15 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMWF_CAS_IMAX_S: enable relaxed ordering for (atomic read) armwf_cas_imax_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 16 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMWF_CAS_IMIN_U: enable relaxed ordering for (atomic read) armwf_cas_imin_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 17 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMWF_CAS_IMIN_S: enable relaxed ordering for (atomic read) armwf_cas_imin_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 18 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMWF_ADD: enable relaxed ordering for (atomic read) armwf_add (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 19 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMWF_AND: enable relaxed ordering for (atomic read) armwf_and (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 20 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMWF_OR: enable relaxed ordering for (atomic read) armwf_or (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 21 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMWF_XOR: enable relaxed ordering for (atomic read) armwf_xor (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 22 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMWF_CAS_E: enable relaxed ordering for (atomic read) armwf_cas_e (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 23 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMWF_CAS_U: enable relaxed ordering for (atomic read) armwf_cas_u (only valid for OCAPI AFU-M1 or AFU-M2 memory) (errata HW367501 requires this bit to be 0 for GPU memory) | |
| 24 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMW_CAS_T: enable relaxed ordering for (atomic write) armw_cas_t (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 25 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMWF_CAS_NE: enable relaxed ordering for (atomic read) armwf_cas_ne (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 26 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMWF_INC_B: enable relaxed ordering for (atomic read) armwf_inc_b (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 27 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMWF_INC_E: enable relaxed ordering for (atomic read) armwf_inc_e (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 28 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMWF_DEC_B: enable relaxed ordering for (atomic read) armwf_dec_b (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 29:31 | RW | RW | CONFIG_RELAXED_BRK2_RESERVED1: reserved | |
| 32 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE0_WRENA: 0/1 = disable/enable relaxed source 0 for (non-atomic) write operations | |
| 33 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE0_RDENA: 0/1 = disable/enable relaxed source 0 for (non-atomic) read operations | |
| 34 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE0_AWENA: 0/1 = disable/enable relaxed source 0 for atomic (write) operations | |
| 35 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE0_ARENA: 0/1 = disable/enable relaxed source 0 for atomic (read) operations | |
| 36 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE1_WRENA: 0/1 = disable/enable relaxed source 1 for (non-atomic) write operations | |
| 37 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE1_RDENA: 0/1 = disable/enable relaxed source 1 for (non-atomic) read operations | |
| 38 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE1_AWENA: 0/1 = disable/enable relaxed source 1 for atomic (write) operations | |
| 39 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE1_ARENA: 0/1 = disable/enable relaxed source 1 for atomic (read) operations | |
| 40 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE2_WRENA: 0/1 = disable/enable relaxed source 2 for (non-atomic) write operations | |
| 41 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE2_RDENA: 0/1 = disable/enable relaxed source 2 for (non-atomic) read operations | |
| 42 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE2_AWENA: 0/1 = disable/enable relaxed source 2 for atomic (write) operations | |
| 43 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE2_ARENA: 0/1 = disable/enable relaxed source 2 for atomic (read) operations | |
| 44 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE3_WRENA: 0/1 = disable/enable relaxed source 3 for (non-atomic) write operations | |
| 45 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE3_RDENA: 0/1 = disable/enable relaxed source 3 for (non-atomic) read operations | |
| 46 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE3_AWENA: 0/1 = disable/enable relaxed source 3 for atomic (write) operations | |
| 47 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE3_ARENA: 0/1 = disable/enable relaxed source 3 for atomic (read) operations | |
| 48 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE4_WRENA: 0/1 = disable/enable relaxed source 4 for (non-atomic) write operations | |
| 49 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE4_RDENA: 0/1 = disable/enable relaxed source 4 for (non-atomic) read operations | |
| 50 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE4_AWENA: 0/1 = disable/enable relaxed source 4 for atomic (write) operations | |
| 51 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE4_ARENA: 0/1 = disable/enable relaxed source 4 for atomic (read) operations | |
| 52 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE5_WRENA: 0/1 = disable/enable relaxed source 5 for (non-atomic) write operations | |
| 53 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE5_RDENA: 0/1 = disable/enable relaxed source 5 for (non-atomic) read operations | |
| 54 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE5_AWENA: 0/1 = disable/enable relaxed source 5 for atomic (write) operations | |
| 55 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE5_ARENA: 0/1 = disable/enable relaxed source 5 for atomic (read) operations | |
| 56 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE6_WRENA: 0/1 = disable/enable relaxed source 6 for (non-atomic) write operations | |
| 57 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE6_RDENA: 0/1 = disable/enable relaxed source 6 for (non-atomic) read operations | |
| 58 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE6_AWENA: 0/1 = disable/enable relaxed source 6 for atomic (write) operations | |
| 59 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE6_ARENA: 0/1 = disable/enable relaxed source 6 for atomic (read) operations | |
| 60 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE7_WRENA: 0/1 = disable/enable relaxed source 7 for (non-atomic) write operations | |
| 61 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE7_RDENA: 0/1 = disable/enable relaxed source 7 for (non-atomic) read operations | |
| 62 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE7_AWENA: 0/1 = disable/enable relaxed source 7 for atomic (write) operations | |
| 63 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE7_ARENA: 0/1 = disable/enable relaxed source 7 for atomic (read) operations | |
| Relaxed-Ordering Config2 brick 3 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010849 (SCOM) 0000000013400248 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.SNP.MISC.CONFIG_RELAXED_BRK3 | |||
| Constant(s): | ||||
| Comments: | Configure relaxed-ordering Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM0.SNP.MISC.CONFIG_RELAXED_BRK3_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_RELAXED_BRK3_CMD_CL_DMA_W: enable relaxed ordering for (non-atomic write) cl_dma_w (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 1 | RW | RW | CONFIG_RELAXED_BRK3_CMD_CL_DMA_W_HP: Reserved. (was: enable relaxed ordering for (non-atomic write) cl_dma_w_hp (only valid for GPU and AFU-M2 memory)) | |
| 2 | RW | RW | CONFIG_RELAXED_BRK3_CMD_CL_DMA_INJ: enable relaxed ordering for (non-atomic write) cl_dma_inj (only valid for GPU and AFU-M2 memory) | |
| 3 | RW | RW | CONFIG_RELAXED_BRK3_CMD_PR_DMA_INJ: enable relaxed ordering for (non-atomic write) pr_dma_inj (only valid for GPU and AFU-M2 memory) | |
| 4 | RW | RW | CONFIG_RELAXED_BRK3_CMD_DMA_PR_W: enable relaxed ordering for (non-atomic write) dma_pr_w (only valid for GPU and AFU-M2 memory) | |
| 5 | RW | RW | CONFIG_RELAXED_BRK3_CMD_CL_RD_NC_F0: enable relaxed ordering for (non-atomic read) cl_rd_nc(F=0) (only valid for GPU and AFU-M2 memory) | |
| 6 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMW_CAS_IMAX_U: enable relaxed ordering for (atomic write) armw_cas_imax_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 7 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMW_CAS_IMAX_S: enable relaxed ordering for (atomic write) armw_cas_imax_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 8 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMW_CAS_IMIN_U: enable relaxed ordering for (atomic write) armw_cas_imin_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 9 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMW_CAS_IMIN_S: enable relaxed ordering for (atomic write) armw_cas_imin_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 10 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMW_ADD: enable relaxed ordering for (atomic write) armw_add (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 11 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMW_AND: enable relaxed ordering for (atomic write) armw_and (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 12 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMW_OR: enable relaxed ordering for (atomic write) armw_or (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 13 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMW_XOR: enable relaxed ordering for (atomic write) armw_xor (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 14 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMWF_CAS_IMAX_U: enable relaxed ordering for (atomic read) armwf_cas_imax_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 15 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMWF_CAS_IMAX_S: enable relaxed ordering for (atomic read) armwf_cas_imax_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 16 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMWF_CAS_IMIN_U: enable relaxed ordering for (atomic read) armwf_cas_imin_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 17 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMWF_CAS_IMIN_S: enable relaxed ordering for (atomic read) armwf_cas_imin_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 18 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMWF_ADD: enable relaxed ordering for (atomic read) armwf_add (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 19 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMWF_AND: enable relaxed ordering for (atomic read) armwf_and (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 20 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMWF_OR: enable relaxed ordering for (atomic read) armwf_or (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 21 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMWF_XOR: enable relaxed ordering for (atomic read) armwf_xor (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 22 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMWF_CAS_E: enable relaxed ordering for (atomic read) armwf_cas_e (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 23 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMWF_CAS_U: enable relaxed ordering for (atomic read) armwf_cas_u (only valid for OCAPI AFU-M1 or AFU-M2 memory) (errata HW367501 requires this bit to be 0 for GPU memory) | |
| 24 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMW_CAS_T: enable relaxed ordering for (atomic write) armw_cas_t (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 25 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMWF_CAS_NE: enable relaxed ordering for (atomic read) armwf_cas_ne (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 26 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMWF_INC_B: enable relaxed ordering for (atomic read) armwf_inc_b (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 27 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMWF_INC_E: enable relaxed ordering for (atomic read) armwf_inc_e (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 28 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMWF_DEC_B: enable relaxed ordering for (atomic read) armwf_dec_b (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 29:31 | RW | RW | CONFIG_RELAXED_BRK3_RESERVED1: reserved | |
| 32 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE0_WRENA: 0/1 = disable/enable relaxed source 0 for (non-atomic) write operations | |
| 33 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE0_RDENA: 0/1 = disable/enable relaxed source 0 for (non-atomic) read operations | |
| 34 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE0_AWENA: 0/1 = disable/enable relaxed source 0 for atomic (write) operations | |
| 35 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE0_ARENA: 0/1 = disable/enable relaxed source 0 for atomic (read) operations | |
| 36 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE1_WRENA: 0/1 = disable/enable relaxed source 1 for (non-atomic) write operations | |
| 37 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE1_RDENA: 0/1 = disable/enable relaxed source 1 for (non-atomic) read operations | |
| 38 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE1_AWENA: 0/1 = disable/enable relaxed source 1 for atomic (write) operations | |
| 39 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE1_ARENA: 0/1 = disable/enable relaxed source 1 for atomic (read) operations | |
| 40 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE2_WRENA: 0/1 = disable/enable relaxed source 2 for (non-atomic) write operations | |
| 41 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE2_RDENA: 0/1 = disable/enable relaxed source 2 for (non-atomic) read operations | |
| 42 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE2_AWENA: 0/1 = disable/enable relaxed source 2 for atomic (write) operations | |
| 43 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE2_ARENA: 0/1 = disable/enable relaxed source 2 for atomic (read) operations | |
| 44 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE3_WRENA: 0/1 = disable/enable relaxed source 3 for (non-atomic) write operations | |
| 45 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE3_RDENA: 0/1 = disable/enable relaxed source 3 for (non-atomic) read operations | |
| 46 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE3_AWENA: 0/1 = disable/enable relaxed source 3 for atomic (write) operations | |
| 47 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE3_ARENA: 0/1 = disable/enable relaxed source 3 for atomic (read) operations | |
| 48 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE4_WRENA: 0/1 = disable/enable relaxed source 4 for (non-atomic) write operations | |
| 49 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE4_RDENA: 0/1 = disable/enable relaxed source 4 for (non-atomic) read operations | |
| 50 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE4_AWENA: 0/1 = disable/enable relaxed source 4 for atomic (write) operations | |
| 51 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE4_ARENA: 0/1 = disable/enable relaxed source 4 for atomic (read) operations | |
| 52 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE5_WRENA: 0/1 = disable/enable relaxed source 5 for (non-atomic) write operations | |
| 53 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE5_RDENA: 0/1 = disable/enable relaxed source 5 for (non-atomic) read operations | |
| 54 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE5_AWENA: 0/1 = disable/enable relaxed source 5 for atomic (write) operations | |
| 55 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE5_ARENA: 0/1 = disable/enable relaxed source 5 for atomic (read) operations | |
| 56 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE6_WRENA: 0/1 = disable/enable relaxed source 6 for (non-atomic) write operations | |
| 57 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE6_RDENA: 0/1 = disable/enable relaxed source 6 for (non-atomic) read operations | |
| 58 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE6_AWENA: 0/1 = disable/enable relaxed source 6 for atomic (write) operations | |
| 59 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE6_ARENA: 0/1 = disable/enable relaxed source 6 for atomic (read) operations | |
| 60 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE7_WRENA: 0/1 = disable/enable relaxed source 7 for (non-atomic) write operations | |
| 61 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE7_RDENA: 0/1 = disable/enable relaxed source 7 for (non-atomic) read operations | |
| 62 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE7_AWENA: 0/1 = disable/enable relaxed source 7 for atomic (write) operations | |
| 63 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE7_ARENA: 0/1 = disable/enable relaxed source 7 for atomic (read) operations | |
| Relaxed-Ordering Config2 brick 4 | ||||
|---|---|---|---|---|
| Addr: |
000000001101084A (SCOM) 0000000013400250 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.SNP.MISC.CONFIG_RELAXED_BRK4 | |||
| Constant(s): | ||||
| Comments: | Configure relaxed-ordering Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM0.SNP.MISC.CONFIG_RELAXED_BRK4_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_RELAXED_BRK4_CMD_CL_DMA_W: enable relaxed ordering for (non-atomic write) cl_dma_w (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 1 | RW | RW | CONFIG_RELAXED_BRK4_CMD_CL_DMA_W_HP: Reserved. (was: enable relaxed ordering for (non-atomic write) cl_dma_w_hp (only valid for GPU and AFU-M2 memory)) | |
| 2 | RW | RW | CONFIG_RELAXED_BRK4_CMD_CL_DMA_INJ: enable relaxed ordering for (non-atomic write) cl_dma_inj (only valid for GPU and AFU-M2 memory) | |
| 3 | RW | RW | CONFIG_RELAXED_BRK4_CMD_PR_DMA_INJ: enable relaxed ordering for (non-atomic write) pr_dma_inj (only valid for GPU and AFU-M2 memory) | |
| 4 | RW | RW | CONFIG_RELAXED_BRK4_CMD_DMA_PR_W: enable relaxed ordering for (non-atomic write) dma_pr_w (only valid for GPU and AFU-M2 memory) | |
| 5 | RW | RW | CONFIG_RELAXED_BRK4_CMD_CL_RD_NC_F0: enable relaxed ordering for (non-atomic read) cl_rd_nc(F=0) (only valid for GPU and AFU-M2 memory) | |
| 6 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMW_CAS_IMAX_U: enable relaxed ordering for (atomic write) armw_cas_imax_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 7 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMW_CAS_IMAX_S: enable relaxed ordering for (atomic write) armw_cas_imax_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 8 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMW_CAS_IMIN_U: enable relaxed ordering for (atomic write) armw_cas_imin_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 9 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMW_CAS_IMIN_S: enable relaxed ordering for (atomic write) armw_cas_imin_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 10 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMW_ADD: enable relaxed ordering for (atomic write) armw_add (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 11 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMW_AND: enable relaxed ordering for (atomic write) armw_and (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 12 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMW_OR: enable relaxed ordering for (atomic write) armw_or (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 13 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMW_XOR: enable relaxed ordering for (atomic write) armw_xor (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 14 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMWF_CAS_IMAX_U: enable relaxed ordering for (atomic read) armwf_cas_imax_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 15 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMWF_CAS_IMAX_S: enable relaxed ordering for (atomic read) armwf_cas_imax_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 16 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMWF_CAS_IMIN_U: enable relaxed ordering for (atomic read) armwf_cas_imin_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 17 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMWF_CAS_IMIN_S: enable relaxed ordering for (atomic read) armwf_cas_imin_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 18 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMWF_ADD: enable relaxed ordering for (atomic read) armwf_add (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 19 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMWF_AND: enable relaxed ordering for (atomic read) armwf_and (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 20 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMWF_OR: enable relaxed ordering for (atomic read) armwf_or (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 21 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMWF_XOR: enable relaxed ordering for (atomic read) armwf_xor (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 22 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMWF_CAS_E: enable relaxed ordering for (atomic read) armwf_cas_e (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 23 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMWF_CAS_U: enable relaxed ordering for (atomic read) armwf_cas_u (only valid for OCAPI AFU-M1 or AFU-M2 memory) (errata HW367501 requires this bit to be 0 for GPU memory) | |
| 24 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMW_CAS_T: enable relaxed ordering for (atomic write) armw_cas_t (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 25 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMWF_CAS_NE: enable relaxed ordering for (atomic read) armwf_cas_ne (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 26 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMWF_INC_B: enable relaxed ordering for (atomic read) armwf_inc_b (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 27 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMWF_INC_E: enable relaxed ordering for (atomic read) armwf_inc_e (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 28 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMWF_DEC_B: enable relaxed ordering for (atomic read) armwf_dec_b (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 29:31 | RW | RW | CONFIG_RELAXED_BRK4_RESERVED1: reserved | |
| 32 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE0_WRENA: 0/1 = disable/enable relaxed source 0 for (non-atomic) write operations | |
| 33 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE0_RDENA: 0/1 = disable/enable relaxed source 0 for (non-atomic) read operations | |
| 34 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE0_AWENA: 0/1 = disable/enable relaxed source 0 for atomic (write) operations | |
| 35 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE0_ARENA: 0/1 = disable/enable relaxed source 0 for atomic (read) operations | |
| 36 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE1_WRENA: 0/1 = disable/enable relaxed source 1 for (non-atomic) write operations | |
| 37 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE1_RDENA: 0/1 = disable/enable relaxed source 1 for (non-atomic) read operations | |
| 38 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE1_AWENA: 0/1 = disable/enable relaxed source 1 for atomic (write) operations | |
| 39 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE1_ARENA: 0/1 = disable/enable relaxed source 1 for atomic (read) operations | |
| 40 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE2_WRENA: 0/1 = disable/enable relaxed source 2 for (non-atomic) write operations | |
| 41 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE2_RDENA: 0/1 = disable/enable relaxed source 2 for (non-atomic) read operations | |
| 42 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE2_AWENA: 0/1 = disable/enable relaxed source 2 for atomic (write) operations | |
| 43 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE2_ARENA: 0/1 = disable/enable relaxed source 2 for atomic (read) operations | |
| 44 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE3_WRENA: 0/1 = disable/enable relaxed source 3 for (non-atomic) write operations | |
| 45 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE3_RDENA: 0/1 = disable/enable relaxed source 3 for (non-atomic) read operations | |
| 46 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE3_AWENA: 0/1 = disable/enable relaxed source 3 for atomic (write) operations | |
| 47 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE3_ARENA: 0/1 = disable/enable relaxed source 3 for atomic (read) operations | |
| 48 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE4_WRENA: 0/1 = disable/enable relaxed source 4 for (non-atomic) write operations | |
| 49 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE4_RDENA: 0/1 = disable/enable relaxed source 4 for (non-atomic) read operations | |
| 50 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE4_AWENA: 0/1 = disable/enable relaxed source 4 for atomic (write) operations | |
| 51 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE4_ARENA: 0/1 = disable/enable relaxed source 4 for atomic (read) operations | |
| 52 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE5_WRENA: 0/1 = disable/enable relaxed source 5 for (non-atomic) write operations | |
| 53 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE5_RDENA: 0/1 = disable/enable relaxed source 5 for (non-atomic) read operations | |
| 54 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE5_AWENA: 0/1 = disable/enable relaxed source 5 for atomic (write) operations | |
| 55 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE5_ARENA: 0/1 = disable/enable relaxed source 5 for atomic (read) operations | |
| 56 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE6_WRENA: 0/1 = disable/enable relaxed source 6 for (non-atomic) write operations | |
| 57 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE6_RDENA: 0/1 = disable/enable relaxed source 6 for (non-atomic) read operations | |
| 58 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE6_AWENA: 0/1 = disable/enable relaxed source 6 for atomic (write) operations | |
| 59 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE6_ARENA: 0/1 = disable/enable relaxed source 6 for atomic (read) operations | |
| 60 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE7_WRENA: 0/1 = disable/enable relaxed source 7 for (non-atomic) write operations | |
| 61 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE7_RDENA: 0/1 = disable/enable relaxed source 7 for (non-atomic) read operations | |
| 62 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE7_AWENA: 0/1 = disable/enable relaxed source 7 for atomic (write) operations | |
| 63 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE7_ARENA: 0/1 = disable/enable relaxed source 7 for atomic (read) operations | |
| Low-Water Marks | ||||
|---|---|---|---|---|
| Addr: |
000000001101084B (SCOM) 0000000013400258 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.SNP.MISC.LOW_WATER | |||
| Constant(s): | ||||
| Comments: | State-Machine allocation Low-Water Marks the sum of the Low-Water marks must be less than config_max_machines Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM0.SNP.MISC.LOW_WATER_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_LOW_WATER_PWR0: Low-Water mark for PowerBus rd/dclaim/atomic/etc. requests | |
| 1 | RW | RW | CONFIG_LOW_WATER_PWR1: Low-Water mark for PowerBus cp (castout-push) requests. | |
| 2 | RW | RW | CONFIG_LOW_WATER_PWR2: Low-Water mark for PowerBus snoops for force-evict requests. | |
| 3 | RW | RW | CONFIG_LOW_WATER_XATS: Low-Water mark for ATS/XSL PowerBus requests | |
| 4 | RW | RW | CONFIG_LOW_WATER_INTS: Low-Water mark for MISC Interrupt requests | |
| 5 | RW | RW | CONFIG_LOW_WATER_REQ0: Low-Water mark for brick-0 NVLink brick-0 Req channel or OCAPI TLX.vc.3 requests | |
| 6 | RW | RW | CONFIG_LOW_WATER_CST0: Low-Water mark for brick-0 OCAPI Castout requests | |
| 7 | RW | RW | CONFIG_LOW_WATER_PRB0: Low-Water mark for brick-0 NVLink Probe or OCAPI mem_pa_flush requests | |
| 8 | RW | RW | CONFIG_LOW_WATER_REQ1: Low-Water mark for brick-1 NVLink Req channel or OCAPI TLX.vc.3 requests | |
| 9 | RW | RW | CONFIG_LOW_WATER_CST1: Low-Water mark for brick-1 OCAPI Castout requests | |
| 10 | RW | RW | CONFIG_LOW_WATER_PRB1: Low-Water mark for brick-1 NVLink Probe or OCAPI mem_pa_flush requests | |
| 11 | RW | RW | CONFIG_LOW_WATER_REQ2: Low-Water mark for brick-2 NVLink brick-0 Req channel or OCAPI TLX.vc.3 requests | |
| 12 | RW | RW | CONFIG_LOW_WATER_CST2: Low-Water mark for brick-2 OCAPI Castout requests | |
| 13 | RW | RW | CONFIG_LOW_WATER_PRB2: Low-Water mark for brick-2 NVLink Probe or OCAPI mem_pa_flush requests | |
| 14 | RW | RW | CONFIG_LOW_WATER_REQ3: Low-Water mark for brick-3 NVLink Req channel or OCAPI TLX.vc.3 requests | |
| 15 | RW | RW | CONFIG_LOW_WATER_CST3: Low-Water mark for brick-3 OCAPI Castout requests | |
| 16 | RW | RW | CONFIG_LOW_WATER_PRB3: Low-Water mark for brick-3 NVLink Probe or OCAPI mem_pa_flush requests | |
| 17 | RW | RW | CONFIG_LOW_WATER_REQ4: Low-Water mark for brick-4 NVLink brick-0 Req channel or OCAPI TLX.vc.3 requests | |
| 18 | RW | RW | CONFIG_LOW_WATER_CST4: Low-Water mark for brick-4 OCAPI Castout requests | |
| 19 | RW | RW | CONFIG_LOW_WATER_PRB4: Low-Water mark for brick-4 NVLink Probe or OCAPI mem_pa_flush requests | |
| 20 | RW | RW | CONFIG_LOW_WATER_XI_SHARED: shared Low-Water mark for ATS/XSL/MISC-INT requests if set to 1, the only one of config_low_water_{xats,ints} should be set to 1 | |
| 21 | RW | RW | CONFIG_LOW_WATER_REQX_SHARED: shared Low-Water mark for req0...req4 if set to 1, the only one of config_low_water_{req0...req4} should be set to 1 | |
| 22 | RW | RW | CONFIG_LOW_WATER_CSTX_SHARED: shared Low-Water mark for cst0...cst4 if set to 1, the only one of config_low_water_{cst0...cst4} should be set to 1 | |
| 23 | RW | RW | CONFIG_LOW_WATER_PRBX_SHARED: shared Low-Water mark for prb0...prb4 if set to 1, the only one of config_low_water_{prb0...prb4} should be set to 1 | |
| 24:25 | RW | RW | CONFIG_WEIGHT_PWR0: 0...3 -> weight 1..4 when balancing PWR0 against other classes | |
| 26:27 | RW | RW | CONFIG_WEIGHT_PWR1: 0...3 -> weight 1..4 when balancing PWR1 against other classes | |
| 28:29 | RW | RW | CONFIG_WEIGHT_PWR2: 0...3 -> weight 1..4 when balancing PWR2 against other classes | |
| 30:31 | RW | RW | CONFIG_WEIGHT_XATS: 0...3 -> weight 1..4 when balancing XATS against other classes | |
| 32:33 | RW | RW | CONFIG_WEIGHT_INTS: 0...3 -> weight 1..4 when balancing INTS against other classes | |
| 34:35 | RW | RW | CONFIG_WEIGHT_REQ0: 0...3 -> weight 1..4 when balancing REQ0 against other classes | |
| 36:37 | RW | RW | CONFIG_WEIGHT_CST0: 0...3 -> weight 1..4 when balancing CST0 against other classes | |
| 38:39 | RW | RW | CONFIG_WEIGHT_PRB0: 0...3 -> weight 1..4 when balancing PRB0 against other classes | |
| 40:41 | RW | RW | CONFIG_WEIGHT_REQ1: 0...3 -> weight 1..4 when balancing REQ1 against other classes | |
| 42:43 | RW | RW | CONFIG_WEIGHT_CST1: 0...3 -> weight 1..4 when balancing CST1 against other classes | |
| 44:45 | RW | RW | CONFIG_WEIGHT_PRB1: 0...3 -> weight 1..4 when balancing PRB1 against other classes | |
| 46:47 | RW | RW | CONFIG_WEIGHT_REQ2: 0...3 -> weight 1..4 when balancing REQ2 against other classes | |
| 48:49 | RW | RW | CONFIG_WEIGHT_CST2: 0...3 -> weight 1..4 when balancing CST2 against other classes | |
| 50:51 | RW | RW | CONFIG_WEIGHT_PRB2: 0...3 -> weight 1..4 when balancing PRB2 against other classes | |
| 52:53 | RW | RW | CONFIG_WEIGHT_REQ3: 0...3 -> weight 1..4 when balancing REQ3 against other classes | |
| 54:55 | RW | RW | CONFIG_WEIGHT_CST3: 0...3 -> weight 1..4 when balancing CST3 against other classes | |
| 56:57 | RW | RW | CONFIG_WEIGHT_PRB3: 0...3 -> weight 1..4 when balancing PRB3 against other classes | |
| 58:59 | RW | RW | CONFIG_WEIGHT_REQ4: 0...3 -> weight 1..4 when balancing REQ4 against other classes | |
| 60:61 | RW | RW | CONFIG_WEIGHT_CST4: 0...3 -> weight 1..4 when balancing CST4 against other classes | |
| 62:63 | RW | RW | CONFIG_WEIGHT_PRB4: 0...3 -> weight 1..4 when balancing PRB4 against other classes | |
| Machine Allocation configuration | ||||
|---|---|---|---|---|
| Addr: |
000000001101084D (SCOM) 0000000013400268 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.SNP.MISC.MACHINE_ALLOC | |||
| Constant(s): | ||||
| Comments: | State-Machine configuration and control Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM0.SNP.MISC.MACHINE_ALLOC_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_ENABLE_MACHINE_ALLOC: Enable state-machine allocation Can only be changed 0->1, must stay 1 once set | |
| 1 | RW | RW | CONFIG_ENABLE_EXCEED_HIGH: Enable exceeding high water marks | |
| 2:7 | RW | RW | CONFIG_MAX_MACHINES: Maximum number of state-machines to be used. Must be >= 20 and <= 62 | |
| 8:13 | RW | RW | CONFIG_HIGH_WATER_IDLE: High-water mark for 'Idle' allocation classes | |
| 14:19 | RW | RW | CONFIG_HIGH_BONUS1: Signed 6-bit bonus value to apply to the available machines count prior to division | |
| 20:29 | RW | RW | CONFIG_HIGH_MIN_SHARE: Minimum share after division (machines * 8) | |
| 30:39 | RW | RW | CONFIG_HIGH_BONUS2: Signed 10-bit bonus value to apply to machines count after division (signed machines * 8) | |
| 40:43 | RW | RW | CONFIG_MAX_HIGH_RESERVED: Maximum of state-machines reserved for classes below their high-water marks | |
| 44:48 | RW | RW | CONFIG_SMAL_DEBUG_SEL0: Debug select mux for state-machine-allocation debug output 0 | |
| 49:53 | RW | RW | CONFIG_SMAL_DEBUG_SEL1: Debug select mux for state-machine-allocation debug output 1 | |
| 54:58 | RW | RW | CONFIG_SMAL_DEBUG_SEL2: Debug select mux for state-machine-allocation debug output 2 | |
| 59:63 | RW | RW | CONFIG_SMAL_DEBUG_SEL3: Debug select mux for state-machine-allocation debug output 3 | |
| Perf Config Reg | ||||
|---|---|---|---|---|
| Addr: |
000000001101084E (SCOM) 0000000013400270 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.SNP.MISC.PERF_CONFIG | |||
| Constant(s): | ||||
| Comments: | Performance Event selection | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:35 | PAU3.CS.SM0.SNP.MISC.PERF_CONFIG_Q_0_INST.LATC.L2(0:35) [000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:7 | RW | RW | PERF_CONFIG_EVENT0: Event 0 select 0: count nothing 1: count cycles 2: count # of cycles REQ0 count matches perf_mask/match_alloc 3: count # of cycles CST0 count matches perf_mask/match_alloc 4: count # of cycles PRB0 count matches perf_mask/match_alloc 5: count # of cycles REQ1 count matches perf_mask/match_alloc 6: count # of cycles CST1 count matches perf_mask/match_alloc 7: count # of cycles PRB1 count matches perf_mask/match_alloc 8: count # of cycles REQ2 count matches perf_mask/match_alloc 9: count # of cycles CST2 count matches perf_mask/match_alloc 10: count # of cycles PRB2 count matches perf_mask/match_alloc 11: count # of cycles REQ3 count matches perf_mask/match_alloc 12: count # of cycles CST3 count matches perf_mask/match_alloc 13: count # of cycles PRB3 count matches perf_mask/match_alloc 14: count # of cycles REQ4 count matches perf_mask/match_alloc 15: count # of cycles CST4 count matches perf_mask/match_alloc 16: count # of cycles PRB4 count matches perf_mask/match_alloc 17: count # of cycles PWR0 count matches perf_mask/match_alloc 18: count # of cycles PWR1 count matches perf_mask/match_alloc 19: count # of cycles PWR2 count matches perf_mask/match_alloc 20: count # of cycles XATS count matches perf_mask/match_alloc 21: count # of cycles reserved count matches perf_mask/match_alloc 22: count # of cycles free count matches perf_mask/match_alloc 23: count # of cycles INTS count matches perf_mask/match_alloc 24: count # of RCmds received matching perf_mask/match 25: count # of times PResp=rty_dinc was driven 26: count # of RCmds received from PAU/PAU 27: count # of perf-select RCmds that had cam_hit_pckt_vld_d asserted as an input to the fsnoop_coll table 28: count # of perf-select RCmds that had cam_hit_pckt_vld_nd asserted as an input to the fsnoop_coll table 29: count # of perf-select RCmds that had cam_hit_pckt_vld_ond asserted as an input to the fsnoop_coll table 30: count # of perf-select RCmds that had cam_hit_pckt_win asserted as an input to the fsnoop_coll table 31: count # of perf-select RCmds that had cam_hit_rty_dif asserted as an input to the fsnoop_coll table 32: count # of perf-select RCmds that had cam_hit_rty_dif_mpf asserted as an input to the fsnoop_coll table 33: count # of perf-select RCmds that had cam_hit_pckt_poison asserted as an input to the fsnoop_coll table 34: count # of perf-select RCmds that had cam_hit_rty_lco asserted as an input to the fsnoop_coll table 35: count # of perf-select RCmds that had cam_hit_rty_abbk asserted as an input to the fsnoop_coll table 36: count # of perf-select RCmds that had cam_hit_rty_abbks asserted as an input to the fsnoop_coll table 37: count # of perf-select RCmds that had cam_hit_rty_all asserted as an input to the fsnoop_coll table 38: count # of perf-select RCmds that had cam_hit_snarf_cpm asserted as an input to the fsnoop_coll table 39: count # of perf-select RCmds that had cam_hit_pb_req asserted as an input to the fsnoop_coll table 40: count # of perf-select RCmds that had presp_rty_spec asserted as an output from the fsnoop_coll table 41: count # of perf-select RCmds that had presp_rty_hpc asserted as an output from the fsnoop_coll table 42: count # of perf-select RCmds that had presp_rty_prot asserted as an output from the fsnoop_coll table 43: count # of perf-select RCmds that had presp_rty_r_coll asserted as an output from the fsnoop_coll table 44: count # of perf-select RCmds that had presp_pckt_hit asserted as an output from the fsnoop_coll table 45: count # of perf-select RCmds that had presp_accept asserted as an output from the fsnoop_coll table 46: count # of perf-select RCmds that had cam_hit_mod_addr asserted as an input to the fsnoop_dir table 47: count # of perf-select RCmds that had cam_hit_mod_lock asserted as an input to the fsnoop_dir table 48: count # of perf-select RCmds that had cam_hit_syn_pend asserted as an input to the fsnoop_dir table 49: count # of perf-select RCmds that had cam_hit_sfe_addr asserted as an input to the fsnoop_dir table 50: count # of perf-select RCmds that had cam_hit_sfe_pend asserted as an input to the fsnoop_dir table 51: count # of perf-select RCmds that had cam_hit_co_pend asserted as an input to the fsnoop_dir table 52: count # of perf-select RCmds that had cam_hit_rs_pend asserted as an input to the fsnoop_dir table 53: count # of perf-select RCmds that had cam_hit_row_not_head asserted as an input to the fsnoop_dir table 54: count # of perf-select RCmds that had l2_dir_valid_or_alloc asserted as an input to the fsnoop_dir table 55: count # of perf-select RCmds that had l2_dir_any_pro_note asserted as an input to the fsnoop_dir table 56: count # of perf-select RCmds that had l2_dir_max_e asserted as an input to the fsnoop_dir table 57: count # of perf-select RCmds that had l2_dir_has_s asserted as an input to the fsnoop_dir table 58: count # of perf-select RCmds that had l2_dir_any_cmd_i asserted as an input to the fsnoop_dir table 59: count # of perf-select RCmds that had l2_dir_other_brick_s asserted as an input to the fsnoop_dir table 60: count # of perf-select RCmds that had l2_dir_other_brick_e asserted as an input to the fsnoop_dir table 61: count # of perf-select RCmds that had presp_shd asserted as an output from the fsnoop_dir table 62: count # of perf-select RCmds that had presp_rty asserted as an output from the fsnoop_dir table 63: count # of perf-select RCmds that had presp_m_mu_ix asserted as an output from the fsnoop_dir table 64: count # of perf-select RCmds that had presp_rty_lost_claim asserted as an output from the fsnoop_dir table 65: count # of perf-select RCmds that had lock_snp_sfe asserted as an output from the fsnoop_dir table 66: count # of perf-select RCmds that had lock_snp_mod asserted as an output from the fsnoop_dir table 67: count # of perf-select RCmds that had lock_mod asserted as an output from the fsnoop_dir table 68: count # of perf-select RCmds that had send_mugging asserted as an output from the fsnoop_dir table 69: count # of perf-select RCmds that had block_dir asserted as an input to the psnoop table others: reserved (count nothing) | |
| 8:15 | RW | RW | PERF_CONFIG_EVENT1: Event 1 select See Event 0 select for encodes | |
| 16:23 | RW | RW | PERF_CONFIG_EVENT2: Event 2 select See Event 0 select for encodes | |
| 24:31 | RW | RW | PERF_CONFIG_EVENT3: Event 3 select See Event 0 select for encodes | |
| 32:34 | RW | RW | PERF_CONFIG_RESERVED2: reserved | |
| 35 | RW | RW | PERF_CONFIG_ACT: Enable clock-gates for performance monitor latches | |
| 36:63 | RO | RO | constant=0b0000000000000000000000000000 | |
| Inhibit configuration Register | ||||
|---|---|---|---|---|
| Addr: |
000000001101084F (SCOM) 0000000013400278 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.SNP.MISC.INHIBIT_CONFIG | |||
| Constant(s): | ||||
| Comments: | Configures Inhibits for CQ_SM | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:31 | PAU3.CS.SM0.SNP.MISC.INHIBIT_CONFIG_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:7 | RW | RW | CONFIG_INHIBIT_DEST0: Selects the destination of the inhibit | |
| 8:15 | RW | RW | CONFIG_INHIBIT_DEST1: Selects the destination of the inhibit | |
| 16:23 | RW | RW | CONFIG_INHIBIT_DEST2: Selects the destination of the inhibit | |
| 24:31 | RW | RW | CONFIG_INHIBIT_DEST3: Selects the destination of the inhibit | |
| 32:63 | RO | RO | constant=0b00000000000000000000000000000000 | |
| c_err_rpt Message-0 latches | ||||
|---|---|---|---|---|
| Addr: |
0000000011010850 (SCOM) 0000000013400280 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.SNP.MISC.CERR_MESSAGE0 | |||
| Constant(s): | ||||
| Comments: | Error message/capture register 0 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM0.SNP.MISC.CERR_MESSAGE0_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:63 | RWX_WCLRREG | RWX_WCLRREG | CERR_MESSAGE_BITS0: reserved | |
| c_err_rpt Message-1 latches | ||||
|---|---|---|---|---|
| Addr: |
0000000011010851 (SCOM) 0000000013400288 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.SNP.MISC.CERR_MESSAGE1 | |||
| Constant(s): | ||||
| Comments: | Error message/capture register 1 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM0.SNP.MISC.CERR_MESSAGE1_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:63 | RWX_WCLRREG | RWX_WCLRREG | CERR_MESSAGE_BITS1: reserved | |
| CQ_SM status register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010852 (SCOM) 0000000013400290 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.SNP.MISC.SM_STATUS | |||
| Constant(s): | ||||
| Comments: | Status reporting register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:23 | PAU3.CS.SM0.SNP.MISC.SM_STATUS_Q_0_INST.LATC.L2(0:23) [000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | ROX | ROX | SM_STATUS_PWR0: 1 when PowerBus (non-cp*) allocation is at its idle level | |
| 1 | ROX | ROX | SM_STATUS_PWR1: 1 when PowerBus (cp*) allocation is at its idle level | |
| 2 | ROX | ROX | SM_STATUS_PWR2: 1 when PowerBus (cp*) allocation is at its idle level | |
| 3 | ROX | ROX | SM_STATUS_XATS: 1 when ATS/MISC allocation is at its idle level | |
| 4 | ROX | ROX | SM_STATUS_INTS: 1 when INTS allocation is at its idle level | |
| 5 | ROX | ROX | SM_STATUS_CREQ0: 1 when brick 0 CReq allocation is at its idle level | |
| 6 | ROX | ROX | SM_STATUS_CST0: 1 when brick 0 Castout allocation is at its idle level | |
| 7 | ROX | ROX | SM_STATUS_PRB0: 1 when brick 0 Probe allocation is at its idle level | |
| 8 | ROX | ROX | SM_STATUS_CREQ1: 1 when brick 1 CReq allocation is at its idle level | |
| 9 | ROX | ROX | SM_STATUS_CST1: 1 when brick 1 Castout allocation is at its idle level | |
| 10 | ROX | ROX | SM_STATUS_PRB1: 1 when brick 1 Probe allocation is at its idle level | |
| 11 | ROX | ROX | SM_STATUS_CREQ2: 1 when brick 1 CReq allocation is at its idle level | |
| 12 | ROX | ROX | SM_STATUS_CST2: 1 when brick 1 Castout allocation is at its idle level | |
| 13 | ROX | ROX | SM_STATUS_PRB2: 1 when brick 1 Probe allocation is at its idle level | |
| 14 | ROX | ROX | SM_STATUS_CREQ3: 1 when brick 1 CReq allocation is at its idle level | |
| 15 | ROX | ROX | SM_STATUS_CST3: 1 when brick 1 Castout allocation is at its idle level | |
| 16 | ROX | ROX | SM_STATUS_PRB3: 1 when brick 1 Probe allocation is at its idle level | |
| 17 | ROX | ROX | SM_STATUS_CREQ4: 1 when brick 1 CReq allocation is at its idle level | |
| 18 | ROX | ROX | SM_STATUS_CST4: 1 when brick 1 Castout allocation is at its idle level | |
| 19 | ROX | ROX | SM_STATUS_PRB4: 1 when brick 1 Probe allocation is at its idle level | |
| 20 | ROX | ROX | SM_STATUS_CHGRATE: 1 when chgrate.hang slowdown is being applied to machine allocation | |
| 21:23 | ROX | ROX | SM_STATUS_RESERVED1: reserved | |
| 24:63 | RO | RO | constant=0b0000000000000000000000000000000000000000 | |
| c_err_rpt first-0 latches | ||||
|---|---|---|---|---|
| Addr: |
0000000011010853 (SCOM) 0000000013400298 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.SNP.MISC.CERR_FIRST0 | |||
| Constant(s): | ||||
| Comments: | c_err_rpt first latches read-write-1-clear reg | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:7 | PAU3.CS.SM0.SNP.MISC.CERR_FIRST0_Q_0_INST.LATC.L2(0:7) [00000000] | |||
| 8:15 | PAU3.CS.SM0.SNP.MISC.CERR_FIRST0_Q_8_INST.LATC.L2(8:15) [00000000] | |||
| 16:23 | PAU3.CS.SM0.SNP.MISC.CERR_FIRST0_Q_16_INST.LATC.L2(16:23) [00000000] | |||
| 24:35 | PAU3.CS.SM0.SNP.MISC.CERR_FIRST0_Q_24_INST.LATC.L2(24:35) [000000000000] | |||
| 36:59 | PAU3.CS.SM0.SNP.MISC.CERR_FIRST0_Q_36_INST.LATC.L2(36:59) [000000000000000000000000] | |||
| 60:63 | PAU3.CS.SM0.SNP.MISC.CERR_FIRST0_Q_60_INST.LATC.L2(60:63) [0000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NCF_0: NCF0 An NVLink probe did not match its GPUBar | |
| 1 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NCF_1: NCF1 Epoch timeout while ProNoted L2-dir entry was waiting for castout | |
| 2 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NCF_2: NCF2 (reserved) | |
| 3 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NCF_3: NCF3 NVLink NCF error for brick 0 occurred | |
| 4 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NCF_4: NCF4 NVLink NCF error for brick 1 occurred | |
| 5 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NCF_5: NCF5 NVLink NCF error for brick 2 occurred | |
| 6 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NCF_6: NCF6 NVLink NCF error for brick 3 occurred | |
| 7 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NCF_7: NCF7 NVLink NCF error for brick 4 occurred | |
| 8 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBR_0: PBR0 Addr_Error received for self-lpc command (SSF) | |
| 9 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBR_1: PBR1 (reserved) | |
| 10 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBR_2: PBR2 (reserved) | |
| 11 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBR_3: PBR3 (reserved) | |
| 12 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBR_4: PBR4 Illegal Cmd to GPU Memory received | |
| 13 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBR_5: PBR5 (reserved) | |
| 14 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBR_6: PBR6 (reserved) | |
| 15 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBR_7: PBR7 (reserved) | |
| 16 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBP_0: PBP0 Parity error detected on rcmd ttag field | |
| 17 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBP_1: PBP1 Parity error detected on rcmd addr field | |
| 18 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBP_2: PBP2 Parity error detected on CResp ttag | |
| 19 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBP_3: PBP3 Parity error detected on CResp atag | |
| 20 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBP_4: PBP4 (reserved) | |
| 21 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBP_5: PBP5 (reserved) | |
| 22 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBP_6: PBP6 (reserved) | |
| 23 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBP_7: PBP7 (reserved) | |
| 24 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBC_0: PBC0 (reserved) | |
| 25 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBC_1: PBC1 (reserved) | |
| 26 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBC_2: PBC2 (reserved) | |
| 27 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBC_3: PBC3 (reserved) | |
| 28 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBC_4: PBC4 Reserved (was: RCmd TTag received with illegal group ID) | |
| 29 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBC_5: PBC5 Reserved (was: RCmd TTag received with illegal chip ID) | |
| 30 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBC_6: PBC6 Reserved (was: CResp TTag received with illegal group ID) | |
| 31 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBC_7: PBC7 Reserved (was: CResp TTag received with illegal chip ID) | |
| 32 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBC_8: PBC8 RCmd received with disabled topo-idx in address | |
| 33 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBC_9: PBC9 (reserved) | |
| 34 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBC_10: PBC10 (reserved) | |
| 35 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBC_11: PBC11 (reserved) | |
| 36 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_0: NLG0 RCmd Pre-Snoop table lookup missed the table | |
| 37 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_1: NLG1 (reserved) | |
| 38 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_2: NLG2 Req-in logic dropped an ATS-response | |
| 39 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_3: NLG3 (reserved) | |
| 40 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_4: NLG4 RCmd Final-Snoop Coll-Shd table lookup missed the table | |
| 41 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_5: NLG5 CAM lookup hit multiple snarf-cpm entries (multiple probes received from GPU) | |
| 42 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_6: NLG6 Arb request-in queue overflowed | |
| 43 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_7: NLG7 RCmd Final-Snoop coll collision/lpc table lookup missed the table | |
| 44 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_8: NLG8 RCmd Final-Snoop dir C2/L2-directory table lookup missed the table | |
| 45 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_9: NLG9 RCmd Final-Snoop Coll-Retry-Spec table lookup missed the table | |
| 46 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_10: NLG10 RCmd Final-Snoop Coll-Retry-HPC table lookup missed the table | |
| 47 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_11: NLG11 RCmd Final-Snoop Coll-Retry-Prot table lookup missed the table | |
| 48 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_12: NLG12 RCmd Final-Snoop Coll-Retry-RColl table lookup missed the table | |
| 49 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_13: NLG13 RCmd Final-Snoop Coll-Pocket-Hit table lookup missed the table | |
| 50 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_14: NLG14 RCmd Final-Snoop Coll-Accept table lookup missed the table | |
| 51 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_15: NLG15 RCmd Final-Snoop Dir-Shd table lookup missed the table | |
| 52 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_16: NLG16 RCmd Final-Snoop Dir-Rty table lookup missed the table | |
| 53 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_17: NLG17 RCmd Final-Snoop Dir-MMU(Ix) table lookup missed the table | |
| 54 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_18: NLG18 RCmd Final-Snoop Dir C2/L2 directory impossible command/state combination | |
| 55 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_19: NLG19 RCmd Final-Snoop Dir-Snoop-SFE table lookup missed the table | |
| 56 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_20: NLG20 RCmd Final-Snoop Dir-Snoop-Mod table lookup missed the table | |
| 57 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_21: NLG21 RCmd Final-Snoop Dir-Mod table lookup missed the table | |
| 58 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_22: NLG22 RCmd Final-Snoop CAM-Shared table lookup missed the table | |
| 59 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_23: NLG23 An internal sequencer had an invalid state | |
| 60 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBF_0: PBF0 Addr_Error received for self-lpc command (SSF) | |
| 61 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBF_1: PBF1 (reserved) | |
| 62 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBF_2: PBF2 (reserved) | |
| 63 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBF_3: PBF3 (reserved) | |
| c_err_rpt mask-0 latches | ||||
|---|---|---|---|---|
| Addr: |
0000000011010854 (SCOM) 00000000134002A0 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.SNP.MISC.CERR_MASK0 | |||
| Constant(s): | ||||
| Comments: | c_err_rpt mask reg Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM0.SNP.MISC.CERR_MASK0_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | IDIAL_SNP_MASK_NCF_0: NCF0 An NVLink probe did not match its GPUBar | |
| 1 | RW | RW | IDIAL_SNP_MASK_NCF_1: NCF1 Epoch timeout while ProNoted L2-dir entry was waiting for castout | |
| 2 | RW | RW | IDIAL_SNP_MASK_NCF_2: NCF2 (reserved) | |
| 3 | RW | RW | IDIAL_SNP_MASK_NCF_3: NCF3 NVLink NCF error for brick 0 occurred | |
| 4 | RW | RW | IDIAL_SNP_MASK_NCF_4: NCF4 NVLink NCF error for brick 1 occurred | |
| 5 | RW | RW | IDIAL_SNP_MASK_NCF_5: NCF5 NVLink NCF error for brick 2 occurred | |
| 6 | RW | RW | IDIAL_SNP_MASK_NCF_6: NCF6 NVLink NCF error for brick 3 occurred | |
| 7 | RW | RW | IDIAL_SNP_MASK_NCF_7: NCF7 NVLink NCF error for brick 4 occurred | |
| 8 | RW | RW | IDIAL_SNP_MASK_PBR_0: PBR0 Addr_Error received for self-lpc command (SSF) | |
| 9 | RW | RW | IDIAL_SNP_MASK_PBR_1: PBR1 (reserved) | |
| 10 | RW | RW | IDIAL_SNP_MASK_PBR_2: PBR2 (reserved) | |
| 11 | RW | RW | IDIAL_SNP_MASK_PBR_3: PBR3 (reserved) | |
| 12 | RW | RW | IDIAL_SNP_MASK_PBR_4: PBR4 Illegal Cmd to GPU Memory received | |
| 13 | RW | RW | IDIAL_SNP_MASK_PBR_5: PBR5 (reserved) | |
| 14 | RW | RW | IDIAL_SNP_MASK_PBR_6: PBR6 (reserved) | |
| 15 | RW | RW | IDIAL_SNP_MASK_PBR_7: PBR7 (reserved) | |
| 16 | RW | RW | IDIAL_SNP_MASK_PBP_0: PBP0 Parity error detected on rcmd ttag field | |
| 17 | RW | RW | IDIAL_SNP_MASK_PBP_1: PBP1 Parity error detected on rcmd addr field | |
| 18 | RW | RW | IDIAL_SNP_MASK_PBP_2: PBP2 Parity error detected on CResp ttag | |
| 19 | RW | RW | IDIAL_SNP_MASK_PBP_3: PBP3 Parity error detected on CResp atag | |
| 20 | RW | RW | IDIAL_SNP_MASK_PBP_4: PBP4 (reserved) | |
| 21 | RW | RW | IDIAL_SNP_MASK_PBP_5: PBP5 (reserved) | |
| 22 | RW | RW | IDIAL_SNP_MASK_PBP_6: PBP6 (reserved) | |
| 23 | RW | RW | IDIAL_SNP_MASK_PBP_7: PBP7 (reserved) | |
| 24 | RW | RW | IDIAL_SNP_MASK_PBC_0: PBC0 (reserved) | |
| 25 | RW | RW | IDIAL_SNP_MASK_PBC_1: PBC1 (reserved) | |
| 26 | RW | RW | IDIAL_SNP_MASK_PBC_2: PBC2 (reserved) | |
| 27 | RW | RW | IDIAL_SNP_MASK_PBC_3: PBC3 (reserved) | |
| 28 | RW | RW | IDIAL_SNP_MASK_PBC_4: PBC4 Reserved (was: RCmd TTag received with illegal group ID) | |
| 29 | RW | RW | IDIAL_SNP_MASK_PBC_5: PBC5 Reserved (was: RCmd TTag received with illegal chip ID) | |
| 30 | RW | RW | IDIAL_SNP_MASK_PBC_6: PBC6 Reserved (was: CResp TTag received with illegal group ID) | |
| 31 | RW | RW | IDIAL_SNP_MASK_PBC_7: PBC7 Reserved (was: CResp TTag received with illegal chip ID) | |
| 32 | RW | RW | IDIAL_SNP_MASK_PBC_8: PBC8 RCmd received with disabled topo-idx in address | |
| 33 | RW | RW | IDIAL_SNP_MASK_PBC_9: PBC9 (reserved) | |
| 34 | RW | RW | IDIAL_SNP_MASK_PBC_10: PBC10 (reserved) | |
| 35 | RW | RW | IDIAL_SNP_MASK_PBC_11: PBC11 (reserved) | |
| 36 | RW | RW | IDIAL_SNP_MASK_NLG_0: NLG0 RCmd Pre-Snoop table lookup missed the table | |
| 37 | RW | RW | IDIAL_SNP_MASK_NLG_1: NLG1 (reserved) | |
| 38 | RW | RW | IDIAL_SNP_MASK_NLG_2: NLG2 Req-in logic dropped an ATS-response | |
| 39 | RW | RW | IDIAL_SNP_MASK_NLG_3: NLG3 (reserved) | |
| 40 | RW | RW | IDIAL_SNP_MASK_NLG_4: NLG4 RCmd Final-Snoop Coll-Shd table lookup missed the table | |
| 41 | RW | RW | IDIAL_SNP_MASK_NLG_5: NLG5 CAM lookup hit multiple snarf-cpm entries (multiple probes received from GPU) | |
| 42 | RW | RW | IDIAL_SNP_MASK_NLG_6: NLG6 Arb request-in queue overflowed | |
| 43 | RW | RW | IDIAL_SNP_MASK_NLG_7: NLG7 RCmd Final-Snoop coll collision/lpc table lookup missed the table | |
| 44 | RW | RW | IDIAL_SNP_MASK_NLG_8: NLG8 RCmd Final-Snoop dir C2/L2-directory table lookup missed the table | |
| 45 | RW | RW | IDIAL_SNP_MASK_NLG_9: NLG9 RCmd Final-Snoop Coll-Retry-Spec table lookup missed the table | |
| 46 | RW | RW | IDIAL_SNP_MASK_NLG_10: NLG10 RCmd Final-Snoop Coll-Retry-HPC table lookup missed the table | |
| 47 | RW | RW | IDIAL_SNP_MASK_NLG_11: NLG11 RCmd Final-Snoop Coll-Retry-Prot table lookup missed the table | |
| 48 | RW | RW | IDIAL_SNP_MASK_NLG_12: NLG12 RCmd Final-Snoop Coll-Retry-RColl table lookup missed the table | |
| 49 | RW | RW | IDIAL_SNP_MASK_NLG_13: NLG13 RCmd Final-Snoop Coll-Pocket-Hit table lookup missed the table | |
| 50 | RW | RW | IDIAL_SNP_MASK_NLG_14: NLG14 RCmd Final-Snoop Coll-Accept table lookup missed the table | |
| 51 | RW | RW | IDIAL_SNP_MASK_NLG_15: NLG15 RCmd Final-Snoop Dir-Shd table lookup missed the table | |
| 52 | RW | RW | IDIAL_SNP_MASK_NLG_16: NLG16 RCmd Final-Snoop Dir-Rty table lookup missed the table | |
| 53 | RW | RW | IDIAL_SNP_MASK_NLG_17: NLG17 RCmd Final-Snoop Dir-MMU(Ix) table lookup missed the table | |
| 54 | RW | RW | IDIAL_SNP_MASK_NLG_18: NLG18 RCmd Final-Snoop Dir C2/L2 directory impossible command/state combination | |
| 55 | RW | RW | IDIAL_SNP_MASK_NLG_19: NLG19 RCmd Final-Snoop Dir-Snoop-SFE table lookup missed the table | |
| 56 | RW | RW | IDIAL_SNP_MASK_NLG_20: NLG20 RCmd Final-Snoop Dir-Snoop-Mod table lookup missed the table | |
| 57 | RW | RW | IDIAL_SNP_MASK_NLG_21: NLG21 RCmd Final-Snoop Dir-Mod table lookup missed the table | |
| 58 | RW | RW | IDIAL_SNP_MASK_NLG_22: NLG22 RCmd Final-Snoop CAM-Shared table lookup missed the table | |
| 59 | RW | RW | IDIAL_SNP_MASK_NLG_23: NLG23 An internal sequencer had an invalid state | |
| 60 | RW | RW | IDIAL_SNP_MASK_PBF_0: PBF0 Addr_Error received for self-lpc command (SSF) | |
| 61 | RW | RW | IDIAL_SNP_MASK_PBF_1: PBF1 (reserved) | |
| 62 | RW | RW | IDIAL_SNP_MASK_PBF_2: PBF2 (reserved) | |
| 63 | RW | RW | IDIAL_SNP_MASK_PBF_3: PBF3 (reserved) | |
| c_err_rpt hold-0 latches | ||||
|---|---|---|---|---|
| Addr: |
0000000011010855 (SCOM) 00000000134002A8 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.SNP.MISC.CERR_HOLD0 | |||
| Constant(s): | ||||
| Comments: | c_err_rpt hold latches read-write-clear reg | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:7 | PAU3.CS.SM0.SNP.MISC.CERPT_NCF.HOLD_LATCH_INST.HOLD.LATC.L2(0:7) [00000000] | |||
| 8:15 | PAU3.CS.SM0.SNP.MISC.CERPT_PBR.HOLD_LATCH_INST.HOLD.LATC.L2(0:7) [00000000] | |||
| 16:23 | PAU3.CS.SM0.SNP.MISC.CERPT_PBP.HOLD_LATCH_INST.HOLD.LATC.L2(0:7) [00000000] | |||
| 24:35 | PAU3.CS.SM0.SNP.MISC.CERPT_PBC.HOLD_LATCH_INST.HOLD.LATC.L2(0:11) [000000000000] | |||
| 36:59 | PAU3.CS.SM0.SNP.MISC.CERPT_NLG.HOLD_LATCH_INST.HOLD.LATC.L2(0:23) [000000000000000000000000] | |||
| 60:63 | PAU3.CS.SM0.SNP.MISC.CERPT_PBF.HOLD_LATCH_INST.HOLD.LATC.L2(0:3) [0000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NCF_0: NCF0 An NVLink probe did not match its GPUBar | |
| 1 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NCF_1: NCF1 Epoch timeout while ProNoted L2-dir entry was waiting for castout | |
| 2 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NCF_2: NCF2 (reserved) | |
| 3 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NCF_3: NCF3 NVLink NCF error for brick 0 occurred | |
| 4 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NCF_4: NCF4 NVLink NCF error for brick 1 occurred | |
| 5 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NCF_5: NCF5 NVLink NCF error for brick 2 occurred | |
| 6 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NCF_6: NCF6 NVLink NCF error for brick 3 occurred | |
| 7 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NCF_7: NCF7 NVLink NCF error for brick 4 occurred | |
| 8 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBR_0: PBR0 Addr_Error received for self-lpc command (SSF) | |
| 9 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBR_1: PBR1 (reserved) | |
| 10 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBR_2: PBR2 (reserved) | |
| 11 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBR_3: PBR3 (reserved) | |
| 12 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBR_4: PBR4 Illegal Cmd to GPU Memory received | |
| 13 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBR_5: PBR5 (reserved) | |
| 14 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBR_6: PBR6 (reserved) | |
| 15 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBR_7: PBR7 (reserved) | |
| 16 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBP_0: PBP0 Parity error detected on rcmd ttag field | |
| 17 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBP_1: PBP1 Parity error detected on rcmd addr field | |
| 18 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBP_2: PBP2 Parity error detected on CResp ttag | |
| 19 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBP_3: PBP3 Parity error detected on CResp atag | |
| 20 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBP_4: PBP4 (reserved) | |
| 21 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBP_5: PBP5 (reserved) | |
| 22 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBP_6: PBP6 (reserved) | |
| 23 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBP_7: PBP7 (reserved) | |
| 24 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBC_0: PBC0 (reserved) | |
| 25 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBC_1: PBC1 (reserved) | |
| 26 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBC_2: PBC2 (reserved) | |
| 27 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBC_3: PBC3 (reserved) | |
| 28 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBC_4: PBC4 Reserved (was: RCmd TTag received with illegal group ID) | |
| 29 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBC_5: PBC5 Reserved (was: RCmd TTag received with illegal chip ID) | |
| 30 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBC_6: PBC6 Reserved (was: CResp TTag received with illegal group ID) | |
| 31 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBC_7: PBC7 Reserved (was: CResp TTag received with illegal chip ID) | |
| 32 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBC_8: PBC8 RCmd received with disabled topo-idx in address | |
| 33 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBC_9: PBC9 (reserved) | |
| 34 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBC_10: PBC10 (reserved) | |
| 35 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBC_11: PBC11 (reserved) | |
| 36 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_0: NLG0 RCmd Pre-Snoop table lookup missed the table | |
| 37 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_1: NLG1 (reserved) | |
| 38 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_2: NLG2 Req-in logic dropped an ATS-response | |
| 39 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_3: NLG3 (reserved) | |
| 40 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_4: NLG4 RCmd Final-Snoop Coll-Shd table lookup missed the table | |
| 41 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_5: NLG5 CAM lookup hit multiple snarf-cpm entries (multiple probes received from GPU) | |
| 42 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_6: NLG6 Arb request-in queue overflowed | |
| 43 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_7: NLG7 RCmd Final-Snoop coll collision/lpc table lookup missed the table | |
| 44 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_8: NLG8 RCmd Final-Snoop dir C2/L2-directory table lookup missed the table | |
| 45 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_9: NLG9 RCmd Final-Snoop Coll-Retry-Spec table lookup missed the table | |
| 46 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_10: NLG10 RCmd Final-Snoop Coll-Retry-HPC table lookup missed the table | |
| 47 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_11: NLG11 RCmd Final-Snoop Coll-Retry-Prot table lookup missed the table | |
| 48 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_12: NLG12 RCmd Final-Snoop Coll-Retry-RColl table lookup missed the table | |
| 49 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_13: NLG13 RCmd Final-Snoop Coll-Pocket-Hit table lookup missed the table | |
| 50 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_14: NLG14 RCmd Final-Snoop Coll-Accept table lookup missed the table | |
| 51 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_15: NLG15 RCmd Final-Snoop Dir-Shd table lookup missed the table | |
| 52 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_16: NLG16 RCmd Final-Snoop Dir-Rty table lookup missed the table | |
| 53 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_17: NLG17 RCmd Final-Snoop Dir-MMU(Ix) table lookup missed the table | |
| 54 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_18: NLG18 RCmd Final-Snoop Dir C2/L2 directory impossible command/state combination | |
| 55 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_19: NLG19 RCmd Final-Snoop Dir-Snoop-SFE table lookup missed the table | |
| 56 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_20: NLG20 RCmd Final-Snoop Dir-Snoop-Mod table lookup missed the table | |
| 57 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_21: NLG21 RCmd Final-Snoop Dir-Mod table lookup missed the table | |
| 58 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_22: NLG22 RCmd Final-Snoop CAM-Shared table lookup missed the table | |
| 59 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_23: NLG23 An internal sequencer had an invalid state | |
| 60 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBF_0: PBF0 Addr_Error received for self-lpc command (SSF) | |
| 61 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBF_1: PBF1 (reserved) | |
| 62 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBF_2: PBF2 (reserved) | |
| 63 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBF_3: PBF3 (reserved) | |
| Perf Address Match | ||||
|---|---|---|---|---|
| Addr: |
0000000011010856 (SCOM) 00000000134002B0 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.SNP.MISC.PERF_ADDR_CONFIG | |||
| Constant(s): | ||||
| Comments: | Performance Address Match | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:43 | PAU3.CS.SM0.SNP.MISC.PERF_ADDR_CONFIG_Q_0_INST.LATC.L2(0:43) [00000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:5 | RW | RW | PERF_SIZE_ADDR: Size of address range to match 35 = 64K 34 = 128K ... 25 = 64M 15 = 64G 10 = 2T 0 = 2P | |
| 6:41 | RW | RW | PERF_MATCH_ADDR: Address to match | |
| 42:43 | RW | RW | PERF_ADDR_RESERVED1: reserved | |
| 44:63 | RO | RO | constant=0b00000000000000000000 | |
| Perf Match Reg | ||||
|---|---|---|---|---|
| Addr: |
0000000011010857 (SCOM) 00000000134002B8 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.SNP.MISC.PERF_MATCH_CONFIG | |||
| Constant(s): | ||||
| Comments: | Performance Event Field Match | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:39 | PAU3.CS.SM0.SNP.MISC.PERF_MATCH_CONFIG_Q_0_INST.LATC.L2(0:39) [0000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:4 | RW | RW | PERF_MATCH_ALLOC_CLASS: Allocation Class / Source bus | |
| 5:16 | RW | RW | PERF_MATCH_TTYPE: TType | |
| 17:24 | RW | RW | PERF_MATCH_TSIZE: TSize | |
| 25 | RW | RW | PERF_MATCH_NVBE: NVLink byte enables | |
| 26 | RW | RW | PERF_MATCH_UT: NVLink UT | |
| 27:33 | RW | RW | PERF_MATCH_ATYPE: Address Type | |
| 34:39 | RW | RW | PERF_MATCH_ALLOC: Alloc | |
| 40:63 | RO | RO | constant=0b000000000000000000000000 | |
| Perf Mask Reg | ||||
|---|---|---|---|---|
| Addr: |
0000000011010858 (SCOM) 00000000134002C0 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.SNP.MISC.PERF_MASK_CONFIG | |||
| Constant(s): | ||||
| Comments: | Performance Event Field Mask | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:39 | PAU3.CS.SM0.SNP.MISC.PERF_MASK_CONFIG_Q_0_INST.LATC.L2(0:39) [0000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:4 | RW | RW | PERF_MASK_ALLOC_CLASS: Allocation Class / Source bus | |
| 5:16 | RW | RW | PERF_MASK_TTYPE: TType | |
| 17:24 | RW | RW | PERF_MASK_TSIZE: TSize | |
| 25 | RW | RW | PERF_MASK_NVBE: NVLink byte enables | |
| 26 | RW | RW | PERF_MASK_UT: NVLink UT | |
| 27:33 | RW | RW | PERF_MASK_ATYPE: Address Type | |
| 34:39 | RW | RW | PERF_MASK_ALLOC: Alloc | |
| 40:63 | RO | RO | constant=0b000000000000000000000000 | |
| Debug0 Config Reg | ||||
|---|---|---|---|---|
| Addr: |
0000000011010859 (SCOM) 00000000134002C8 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.SNP.MISC.DEBUG0_CONFIG | |||
| Constant(s): | ||||
| Comments: | Config register for trace-0 chain | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM0.SNP.MISC.DEBUG0_CONFIG_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:4 | RW | RW | DEBUG0_CONFIG_POD0: Mux control for byte 0 of trace-0 | |
| 5:9 | RW | RW | DEBUG0_CONFIG_POD1: Mux control for byte 1 of trace-0 | |
| 10:14 | RW | RW | DEBUG0_CONFIG_POD2: Mux control for byte 2 of trace-0 | |
| 15:19 | RW | RW | DEBUG0_CONFIG_POD3: Mux control for byte 3 of trace-0 | |
| 20:24 | RW | RW | DEBUG0_CONFIG_POD4: Mux control for byte 4 of trace-0 | |
| 25:29 | RW | RW | DEBUG0_CONFIG_POD5: Mux control for byte 5 of trace-0 | |
| 30:34 | RW | RW | DEBUG0_CONFIG_POD6: Mux control for byte 6 of trace-0 | |
| 35:39 | RW | RW | DEBUG0_CONFIG_POD7: Mux control for byte 7 of trace-0 | |
| 40:44 | RW | RW | DEBUG0_CONFIG_POD8: Mux control for byte 8 of trace-0 | |
| 45:49 | RW | RW | DEBUG0_CONFIG_POD9: Mux control for byte 9 of trace-0 | |
| 50:54 | RW | RW | DEBUG0_CONFIG_POD10: Mux control for byte 10 of trace-0 | |
| 55:62 | RW | RW | DEBUG0_CONFIG_RESERVED1: reserved | |
| 63 | RW | RW | DEBUG0_CONFIG_ACT: Enable clock-gates for debug trace latches | |
| Debug1 Config Reg | ||||
|---|---|---|---|---|
| Addr: |
000000001101085A (SCOM) 00000000134002D0 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.SNP.MISC.DEBUG1_CONFIG | |||
| Constant(s): | ||||
| Comments: | Config register for trace-1 chain | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM0.SNP.MISC.DEBUG1_CONFIG_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:4 | RW | RW | DEBUG1_CONFIG_POD0: Mux control for byte 0 of trace-1 | |
| 5:9 | RW | RW | DEBUG1_CONFIG_POD1: Mux control for byte 1 of trace-1 | |
| 10:14 | RW | RW | DEBUG1_CONFIG_POD2: Mux control for byte 2 of trace-1 | |
| 15:19 | RW | RW | DEBUG1_CONFIG_POD3: Mux control for byte 3 of trace-1 | |
| 20:24 | RW | RW | DEBUG1_CONFIG_POD4: Mux control for byte 4 of trace-1 | |
| 25:29 | RW | RW | DEBUG1_CONFIG_POD5: Mux control for byte 5 of trace-1 | |
| 30:34 | RW | RW | DEBUG1_CONFIG_POD6: Mux control for byte 6 of trace-1 | |
| 35:39 | RW | RW | DEBUG1_CONFIG_POD7: Mux control for byte 7 of trace-1 | |
| 40:44 | RW | RW | DEBUG1_CONFIG_POD8: Mux control for byte 8 of trace-1 | |
| 45:49 | RW | RW | DEBUG1_CONFIG_POD9: Mux control for byte 9 of trace-1 | |
| 50:54 | RW | RW | DEBUG1_CONFIG_POD10: Mux control for byte 10 of trace-1 | |
| 55:62 | RW | RW | DEBUG1_CONFIG_RESERVED1: reserved | |
| 63 | RW | RW | DEBUG1_CONFIG_ACT: Enable clock-gates for debug trace latches | |
| L2 Directory SCOM address register | ||||
|---|---|---|---|---|
| Addr: |
000000001101085B (SCOM) 00000000134002D8 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.SNP.MISC.SCOM_L2_ADDR | |||
| Constant(s): | ||||
| Comments: | register to initiate SCOM reads of the L2 direcotry | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:15 | PAU3.CS.SM0.SNP.MISC.SCOM_L2_ADDR_Q_0_INST.LATC.L2(0:15) [0000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX | RWX | SCOM_L2_VALID: Valid read Write 1 initiates a SCOM access Returns to 0 when access is finished and data is available in the DIR scom_l2_data register | |
| 1:3 | RW | RW | SCOM_L2_ADDR_RESERVED1: reserved | |
| 4:13 | RW | RW | SCOM_L2_CCI: Directory Congruence Class Index (aka SRAM address) to read | |
| 14:15 | RW | RW | SCOM_L2_WAY: Directory 'way' to read | |
| 16:63 | RO | RO | constant=0b000000000000000000000000000000000000000000000000 | |
| Topology Table register 0 | ||||
|---|---|---|---|---|
| Addr: |
000000001101085C (SCOM) 00000000134002E0 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.SNP.MISC.TOPOLOGY_TABLE0 | |||
| Constant(s): | ||||
| Comments: | Defines topology mapping for toplogy indexes 0 through 7 Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:39 | PAU3.CS.SM0.SNP.MISC.TOPOLOGY_TABLE0_Q_0_INST.LATC.L2(0:39) [0000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:7 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENABLE_0_7: Enable bit for entries 0 through 7 | |
| 8:11 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY0: Topology ID(0:3) for Topology Index 0 | |
| 12:15 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY1: Topology ID(0:3) for Topology Index 1 | |
| 16:19 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY2: Topology ID(0:3) for Topology Index 2 | |
| 20:23 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY3: Topology ID(0:3) for Topology Index 3 | |
| 24:27 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY4: Topology ID(0:3) for Topology Index 4 | |
| 28:31 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY5: Topology ID(0:3) for Topology Index 5 | |
| 32:35 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY6: Topology ID(0:3) for Topology Index 6 | |
| 36:39 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY7: Topology ID(0:3) for Topology Index 7 | |
| 40:63 | RO | RO | constant=0b000000000000000000000000 | |
| Topology Table register 1 | ||||
|---|---|---|---|---|
| Addr: |
000000001101085D (SCOM) 00000000134002E8 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.SNP.MISC.TOPOLOGY_TABLE1 | |||
| Constant(s): | ||||
| Comments: | Defines topology mapping for toplogy indexes 8 through 15 Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:39 | PAU3.CS.SM0.SNP.MISC.TOPOLOGY_TABLE1_Q_0_INST.LATC.L2(0:39) [0000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:7 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENABLE_8_15: Enable bit for entries 8 through 15 | |
| 8:11 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY8: Topology ID(0:3) for Topology Index 8 | |
| 12:15 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY9: Topology ID(0:3) for Topology Index 9 | |
| 16:19 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY10: Topology ID(0:3) for Topology Index 10 | |
| 20:23 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY11: Topology ID(0:3) for Topology Index 11 | |
| 24:27 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY12: Topology ID(0:3) for Topology Index 12 | |
| 28:31 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY13: Topology ID(0:3) for Topology Index 13 | |
| 32:35 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY14: Topology ID(0:3) for Topology Index 14 | |
| 36:39 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY15: Topology ID(0:3) for Topology Index 15 | |
| 40:63 | RO | RO | constant=0b000000000000000000000000 | |
| Topology Table register 2 | ||||
|---|---|---|---|---|
| Addr: |
000000001101085E (SCOM) 00000000134002F0 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.SNP.MISC.TOPOLOGY_TABLE2 | |||
| Constant(s): | ||||
| Comments: | Defines topology mapping for toplogy indexes 16 through 23 Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:39 | PAU3.CS.SM0.SNP.MISC.TOPOLOGY_TABLE2_Q_0_INST.LATC.L2(0:39) [0000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:7 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENABLE_16_23: Enable bit for entries 16 through 23 | |
| 8:11 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY16: Topology ID(0:3) for Topology Index 16 | |
| 12:15 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY17: Topology ID(0:3) for Topology Index 17 | |
| 16:19 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY18: Topology ID(0:3) for Topology Index 18 | |
| 20:23 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY19: Topology ID(0:3) for Topology Index 19 | |
| 24:27 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY20: Topology ID(0:3) for Topology Index 20 | |
| 28:31 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY21: Topology ID(0:3) for Topology Index 21 | |
| 32:35 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY22: Topology ID(0:3) for Topology Index 22 | |
| 36:39 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY23: Topology ID(0:3) for Topology Index 23 | |
| 40:63 | RO | RO | constant=0b000000000000000000000000 | |
| Topology Table register 3 | ||||
|---|---|---|---|---|
| Addr: |
000000001101085F (SCOM) 00000000134002F8 (PAU_RING) | |||
| Name: | PAU3.CS.SM0.SNP.MISC.TOPOLOGY_TABLE3 | |||
| Constant(s): | ||||
| Comments: | Defines topology mapping for toplogy indexes 24 through 31 Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:39 | PAU3.CS.SM0.SNP.MISC.TOPOLOGY_TABLE3_Q_0_INST.LATC.L2(0:39) [0000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:7 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENABLE_24_31: Enable bit for entries 24 through 31 | |
| 8:11 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY24: Topology ID(0:3) for Topology Index 24 | |
| 12:15 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY25: Topology ID(0:3) for Topology Index 25 | |
| 16:19 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY26: Topology ID(0:3) for Topology Index 26 | |
| 20:23 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY27: Topology ID(0:3) for Topology Index 27 | |
| 24:27 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY28: Topology ID(0:3) for Topology Index 28 | |
| 28:31 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY29: Topology ID(0:3) for Topology Index 29 | |
| 32:35 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY30: Topology ID(0:3) for Topology Index 30 | |
| 36:39 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY31: Topology ID(0:3) for Topology Index 31 | |
| 40:63 | RO | RO | constant=0b000000000000000000000000 | |
| CQ_SM Misc Config register #0 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010860 (SCOM) 0000000013410000 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.MCP.MISC.CONFIG0 | |||
| Constant(s): | ||||
| Comments: | Misc config register Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM1.MCP.MISC.CONFIG0_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_MA_DSA_OPT_CLAIM_UR: 0/1 = use Read.RWC/Upgrade.DN for dclaim/dcbz to GPU Mem | |
| 1 | RW | RW | CONFIG_MA_DSA_OPT_FLUSH_UR: 0/1 = use Read.RWC/Upgrade.DN for dcbf/dcbfc to GPU Mem | |
| 2 | RW | RW | CONFIG_MA_DSA_OPT_RP_MODE: 0/1 = use DMA/Read-Push for Write.NC to Proc Mem | |
| 3 | RW | RW | CONFIG_ADR_BAR_MODE: Reserved (was: PowerBus adr_bar: 0/1 = large-system-mode/small-system-mode) | |
| 4 | RW | RW | CONFIG_DISABLE_NN_RN: PowerBus scope: 0/1 = Enable Nn & Rn scopes / Disable Nn & Rn scopes | |
| 5 | RW | RW | CONFIG_DISABLE_VG_NOT_SYS: PowerBus scope: 0/1 = Enable Vg less than sys / Force all Vg to sys | |
| 6 | RW | RW | CONFIG_DISABLE_G: PowerBus scope: 0/1 = Enable G scope / Disable G scope | |
| 7 | RW | RW | CONFIG_DISABLE_LN: PowerBus scope: 0/1 = Enable Ln scope / Disable Ln scope | |
| 8 | RW | RW | CONFIG_SKIP_G: PowerBus scope: 0/1 = Allow G on rty_inc / Skip G on rty_inc | |
| 9 | RW | RW | CONFIG_MA_MCRESP_OPT_WRP: 0/1 = increase scope on rty_inc to dma_w / use write-read-push on rty_inc to dma_w | |
| 10 | RW | RW | CONFIG_USE_CL_DMA_W: 0/1 = Start cache-line DMA writes using cl_dma_inj / using cl_dma_w | |
| 11 | RW | RW | CONFIG_USE_DMA_PR_W: 0/1 = Start partial-line DMA writes using pr_dma_inj / using dma_pr_w | |
| 12:14 | RW | RW | CONFIG_INC_PRI_MASK: Mask select for priority increase due to rty_drp 0: 100% chance to increase priority 1: 50% chance to increase priority 2: 25% chance to increase priority 3: 12.5% chance to increase priority 4: 6% chance to increase priority 5: 3% chance to increase priority 6,7: 1.5% chance to increase priority | |
| 15 | RW | RW | CONFIG_MACH_CORRENAB: 0/1 = disable/enable state machine array ECC correction | |
| 16 | RW | RW | CONFIG_MACH_INJECT_ENABLE1: 0/1 = disable/enable state machine array ECC error inject bit 1 | |
| 17 | RW | RW | CONFIG_MACH_INJECT_ENABLE2: 0/1 = disable/enable state machine array ECC error inject bit 2 | |
| 18 | RW | RW | CONFIG_RXO_CORRENAB: 0/1 = disable/enable ReqRspOut array ECC correction | |
| 19 | RW | RW | CONFIG_RXO_INJECT_ENABLE1: 0/1 = disable/enable ReqRspOut array ECC error inject bit 1 | |
| 20 | RW | RW | CONFIG_RXO_INJECT_ENABLE2: 0/1 = disable/enable ReqRspOut array ECC error inject bit 2 | |
| 21 | RW | RW | CONFIG_RSI_CORRENAB: 0/1 = disable/enable PB-Rsp-In array ECC correction | |
| 22 | RW | RW | CONFIG_RSI_INJECT_ENABLE1: 0/1 = disable/enable PB-Rsp-In array ECC error inject bit 1 | |
| 23 | RW | RW | CONFIG_RSI_INJECT_ENABLE2: 0/1 = disable/enable PB-Rsp-In array ECC error inject bit 2 | |
| 24 | RW | RW | CONFIG_MA_DSA_OPT_DMA_UPG: 0/1 = non-relaxed dma_w use Read.RWC/Upgrade.DN to acquire pocket-cache state/data | |
| 25 | RW | RW | CONFIG_EVAPORATE_BY_LCO: 0/1 = just free the state-machine without lco/evaporate pocket-cache entries by lco | |
| 26 | RW | RW | CONFIG_ENABLE_PBUS: 0/1 = disable PAU PowerBus RCmd, PResp, and CResp interfaces / enable these interfaces Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 27 | RW | RW | CONFIG_ENABLE_SNARF_CPM: 0/1 = disable/enable Probe.I.MO snarfing a cp_m | |
| 28 | RW | RW | CONFIG_DISABLE_INJECT: 0/1 = enable sending cl,pr_dma_inj / disable sending cl,pr_dma_inj Note: to truly disable sending _inj commands, the following bits must also be set to '0': config_ma_dsa_opt_rp_mode | |
| 29 | RW | RW | CONFIG_DCACHE_MODE: 0/1 = drive data-bus dcache field in basic mode / CAPP mode. | |
| 30 | RW | RW | CONFIG_DCACHE_REPORTS_PHYSICAL: 0/1 = in basic mode, report local masters as near / local. | |
| 31 | RW | RW | CONFIG_RSI_DISABLE_DATIN_FASTPATH: 0/1 = enable rsi PB data-in fastpath/disable fastpath | |
| 32 | RW | RW | CONFIG_FORBID_MMIO_READ_GT_32: 0/1 = Allow GPU->PB MMIOs > 32-bytes / flag-error & brick-fence on MMIOs > 32-bytes | |
| 33 | RW | RW | CONFIG_FORBID_MMIO_ATOMIC: 0/1 = Allow GPU->PB atomics to MMIO space / flag-error & brick-fence on atomics to MMIO space | |
| 34 | RW | RW | CONFIG_DISABLE_HW555363_FASTPATH_AND_FENCE: 0/1 = enable HW555363 fix for fence happening between fastpath RCmd and CResp / disable fix. | |
| 35 | RW | RW | CONFIG0_RESERVED1: reserved | |
| 36 | RW | RW | CONFIG_ENABLE_CONTEXT_LCO: 0/1 = disable LCOing context entries into L3/enable LCOing context entries into L3 | |
| 37 | RW | RW | CONFIG_MA_DSA_OPT_FAIL_WAKE: 0/1 = send wake_host_thread to PB as asb_notify / fail all wake_host_thread w/ thread-not-found status (no PB asb_notify) | |
| 38 | RW | RW | CONFIG_ENABLE_FAST_DIR_UPDATE: 0/1 = disable directory fast update from mach pipe / enable directory fast update from mach pipe | |
| 39 | RW | RW | CONFIG_OPT_MES_USE_GO_M: 0/1 = read_mes w/ RW authority uses rd_go_s/rd_go_m to acquire the line | |
| 40 | RW | RW | CONFIG_OPT_LCO_M_USE_MU: 0/1 = use lco_m to inject a modified line into an L3 / use lco_mu | |
| 41 | RW | RW | CONFIG_OPT_SNOOP_EX_LCO: 0/1 = use cp_* when a castout.push(128B)->I is due to a snoop against an exclusive directory entry / use an lco_m,mu | |
| 42 | RW | RW | CONFIG_ENABLE_CP_ME: 0/1 = disable sending cp_me / enable cp_me when a cleaning E->I and homed off-node. | |
| 43 | RW | RW | CONFIG_FENCE_ON_DERR_MMIO: 0/1 = write SUE data to MMIO on data error from OCAPI / fence brick (note: dual NVF10/OCR7 error flagged) | |
| 44 | RW | RW | CONFIG_BRK0_OCAPI_MODE: 0/1 = Disable OpenCAPI mode / enable OpenCAPI mode for brick 0 (mutually exclusive with config_brk0_nvlink_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 45 | RW | RW | CONFIG_BRK1_OCAPI_MODE: 0/1 = Disable OpenCAPI mode / enable OpenCAPI mode for brick 1 (mutually exclusive with config_brk1_nvlink_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 46 | RW | RW | CONFIG_BRK2_OCAPI_MODE: 0/1 = Disable OpenCAPI mode / enable OpenCAPI mode for brick 2 (mutually exclusive with config_brk2_nvlink_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 47 | RW | RW | CONFIG_BRK3_OCAPI_MODE: 0/1 = Disable OpenCAPI mode / enable OpenCAPI mode for brick 3 (mutually exclusive with config_brk3_nvlink_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 48 | RW | RW | CONFIG_BRK4_OCAPI_MODE: 0/1 = Disable OpenCAPI mode / enable OpenCAPI mode for brick 4 (mutually exclusive with config_brk4_nvlink_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 49 | RW | RW | CONFIG_BRK0_NVLINK_MODE: 0/1 = Disable NVLink mode / enable NVLink mode for brick 0 (mutually exclusive with config_brk0_ocapi_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 50 | RW | RW | CONFIG_BRK1_NVLINK_MODE: 0/1 = Disable NVLink mode / enable NVLink mode for brick 1 (mutually exclusive with config_brk1_ocapi_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 51 | RW | RW | CONFIG_BRK2_NVLINK_MODE: 0/1 = Disable NVLink mode / enable NVLink mode for brick 2 (mutually exclusive with config_brk2_ocapi_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 52 | RW | RW | CONFIG_BRK3_NVLINK_MODE: 0/1 = Disable NVLink mode / enable NVLink mode for brick 3 (mutually exclusive with config_brk3_ocapi_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 53 | RW | RW | CONFIG_BRK4_NVLINK_MODE: 0/1 = Disable NVLink mode / enable NVLink mode for brick 4 (mutually exclusive with config_brk4_ocapi_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 54 | RW | RW | CONFIG_BRK0_POISON_FENCE_L2: 0/1 = write all-ones-good-ECC/all-ones-SUE to E/Ei/M L2 directory entries when brick 0 is fenced Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 55 | RW | RW | CONFIG_BRK1_POISON_FENCE_L2: 0/1 = write all-ones-good-ECC/all-ones-SUE to E/Ei/M L2 directory entries when brick 0 is fenced Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 56:58 | RW | RW | CONFIG0_RESERVED0: reserved | |
| 59 | RW | RW | CONFIG_BRK0_IMP_TAGS_MODE_ENABLE: 0/1 = disable IMP (HAPPI) iseries tags mode / enable tags mode for brick 0 Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 60 | RW | RW | CONFIG_BRK1_IMP_TAGS_MODE_ENABLE: 0/1 = disable IMP (HAPPI) iseries tags mode / enable tags mode for brick 1 Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 61 | RW | RW | CONFIG_BRK2_IMP_TAGS_MODE_ENABLE: 0/1 = disable IMP (HAPPI) iseries tags mode / enable tags mode for brick 2 Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 62 | RW | RW | CONFIG_BRK3_IMP_TAGS_MODE_ENABLE: 0/1 = disable IMP (HAPPI) iseries tags mode / enable tags mode for brick 3 Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 63 | RW | RW | CONFIG_BRK4_IMP_TAGS_MODE_ENABLE: 0/1 = disable IMP (HAPPI) iseries tags mode / enable tags mode for brick 4 Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| CQ_SM Misc Config register #1 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010861 (SCOM) 0000000013410008 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.MCP.MISC.CONFIG1 | |||
| Constant(s): | ||||
| Comments: | Misc config register Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM1.MCP.MISC.CONFIG1_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:3 | RW | RW | CONFIG_RANDOM_BACKOFF_DUR_MASK: Mask for the base random duration of a random retry backoff 0000 -> 0-15 base random duration 0001 -> 0-31 base random duration 0011 -> 0-63 base random duration 0111 -> 0-127 base random duration 1111 -> 0-255 base random duration | |
| 4:7 | RW | RW | CONFIG_CHGRATE_HANG_SLOWDOWN_REQ: Mask for for the slowdown of NTL CReq or OCAPI TLX.vc.3 credits during chgrate.hang 'n' -> 1/(2^(n+1)) cycles average rate Note that for a single PowerBus ramp, the rate is actually 8 times faster since there are 4 RCmd slice x 2 NTL Bricks that get CReq credits. This field is the rate for 1 brick receiving credit from 1 RCmd slice. | |
| 8:11 | RW | RW | CONFIG_CHGRATE_HANG_SLOWDOWN_CST: Mask for for the slowdown of OCAPI TLX.vc.2 credits during chgrate.hang 'n' -> 1/(2^(n+1)) cycles average rate Note that for a single PowerBus ramp, the rate is actually 8 times faster since there are 4 RCmd slice x 2 NTL Bricks that get CReq credits. This field is the rate for 1 brick receiving credit from 1 RCmd slice. | |
| 12:15 | RW | RW | CONFIG_CHGRATE_HANG_SLOWDOWN_PRB: Mask for for the slowdown of NTL Probe or OCAPI TLX.vc.1 credits during chgrate.hang 'n' -> 1/(2^(n+1)) cycles average rate Note that for a single PowerBus ramp, the rate is actually 8 times faster since there are 4 RCmd slice x 2 NTL Bricks that get CReq credits. This field is the rate for 1 brick receiving credit from 1 RCmd slice. | |
| 16:27 | RW | RW | CONFIG_EPSILON_WLN_COUNT: epsilon count for Ln scope CP-Write | |
| 28 | RW | RW | CONFIG_MIMIRROR_MASTER_ENABLE: 0/1 = disable MI mirroring support / enable MI mirroring | |
| 29:31 | RW | RW | CONFIG_MIMIRROR_BRICK_MODE: Primary & Secondary bricks are: 000 = Primary is brick 0, brick 1 not used 001 = Primary is brick 1, brick 0 not used 010 = Primary is brick 0, stores mirror to brick 1 011 = Primary is brick 1, stores mirror to brick 0 100 = Primary is brick 0, stores mirror to brick 1, loads can failover to brick 1 101 = Primary is brick 1, stores mirror to brick 0, loads can failover to brick 0 110 = Primary brick is addr(54), stores mirror to both bricks, loads can failover to the other brick 111 = Primary brick is random, stores mirror to both bricks, loads can failover to the other brick | |
| 32 | RW | RW | CONFIG_MIMIRROR_FENCE_ON_BAD_DATA: 0/1 = don't force fence for bad_data responses / force fence when bad_data arrives in a response. | |
| 33:34 | RW | RW | CONFIG1_RESERVED2: reserved | |
| 35 | RW | RW | CONFIG_PCKT_LONG_CL_DMA_INJ: 0/1 = allow cl_dma_inj to use short pocket-cache timer/ force cl_dma_inj to use long pocket-cache timer | |
| 36 | RW | RW | CONFIG_PCKT_LONG_PR_DMA_INJ: 0/1 = allow pr_dma_inj to use short pocket-cache timer/ force pr_dma_inj to use long pocket-cache timer | |
| 37:42 | RW | RW | CONFIG_PCKT_LONG_MIN_COUNT: Minimum number of state-machine w/ long pocket-cache timers before short timers can be used | |
| 43 | RW | RW | CONFIG_PCKT_LONG_USES_HANG: 0/1 = use config_pocket_long_rate2 / use rpt_hang.poll ticks to drive long pocket-cache timer | |
| 44 | RW | RW | CONFIG_DONT_RETRY_LCO_LONG: reserved (was config_dont_retry_lco_long) | |
| 45 | RW | RW | CONFIG_DONT_RETRY_LCO_LONG_STRESSED: reserved (was config_dont_retry_lco_long_stressed). | |
| 46 | RW | RW | CONFIG_DONT_RETRY_LCO_SHORT: reserved (was config_dont_retry_lco_short) | |
| 47 | RW | RW | CONFIG_DONT_RETRY_LCO_SHORT_STRESSED: reserved (was config_dont_retry_lco_short_stressed). | |
| 48 | RW | RW | CONFIG_STOP_ASB_AT_LN_SCOPE: 0/1 = increase to asb_notify to G scope / stop and return thread-not-found when asb_notify @ Ln scope doesn't find the thread | |
| 49 | RW | RW | CONFIG_STOP_ASB_AT_G_SCOPE: 0/1 = increase to asb_notify to Vg(sys) scope / stop and return thread-not-found when asb_notify @ G scope doesn't find the thread | |
| 50 | RW | RW | CONFIG_INITIAL_HPC_PROBE_PRIORITY: Initial drop_priority value when mastering an hpc_probe | |
| 51 | RW | RW | CONFIG_NVLINK_P10P10_MODE: 0/1 = normal NVLink mode / special lab-debug-only P10-to-P10 NVLink mode | |
| 52 | RW | RW | CONFIG_HANG_ON_ADDRESS_ERRORS: 0/1 = abort and continue on CResp=addr_error / hang state-machine on CResp=addr_error | |
| 53 | RW | RW | CONFIG_DISABLE_HW525464_CLEAN_XUE_FENCE_PB: 0/1 = enable HW525464 fix for cleaning XUE data on fence of pb cmd / disable fix. | |
| 54 | RW | RW | CONFIG_DISABLE_HW517903_BAD_SYNC: 0/1 = handle bad sync in non-4.0 mode / disable fix. | |
| 55 | RW | RW | CONFIG_DISABLE_HW526620_BAD_SYN_DONE: 0/1 = handle mis-aligned synonym_done / disable fix. | |
| 56 | RW | RW | CONFIG_ENABLE_OPENCAPI_NETWORKING: 0/1 = disable networking / enable OpenCAPI MI networking mode. | |
| 57 | RW | RW | CONFIG_NET0_TORUS_MODE: 0/1 = Dragonfly network mode / Torus network mode for brick 0 | |
| 58 | RW | RW | CONFIG_NET1_TORUS_MODE: 0/1 = Dragonfly network mode / Torus network mode for brick 1 | |
| 59 | RW | RW | CONFIG_DISABLE_HW532477_ARMWF_IMP_TAGS_RESET: 0/1 = Enable resetting itags after transmitting armwf data / disable fix | |
| 60 | RW | RW | CONFIG_DISABLE_HW536051_FENCE_HOSPICE_PRONOTE: 0/1 = Enable an extra dirscan before waiting for REQ to drain / disable fix | |
| 61 | RW | RW | CONFIG_DISABLE_HW537584_HOSPICE_QUALIFIER: 0/1 = Enable correctly qualifying hp_vec_empty with dir_allocated to indicate hospice / disable fix | |
| 62 | RW | RW | CONFIG_DISABLE_HW546460_INC_DEC_ALL_ONES: 0/1 = Enable IM-network brick4-fence causing inc/dec atomics to return all ones / disable fix | |
| 63 | RW | RW | CONFIG_ENABLE_HW555343_ALL_PTL_ARE_BE: 0/1 = disable HW555343 fix / enable fix to convert all partial writes to byte-enable writes. | |
| PowerBus Epsilon | ||||
|---|---|---|---|---|
| Addr: |
0000000011010862 (SCOM) 0000000013410010 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.MCP.MISC.EPSILON_CONFIG | |||
| Constant(s): | ||||
| Comments: | PowerBus Epsilon config register Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM1.MCP.MISC.EPSILON_CONFIG_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:3 | RW | RW | CONFIG_EPSILON_RATE: 0 = decrement epsilon count at 1:1 pau_clock_1to1 ... 15 = epsilon count at 1/16 pau_clock_1to1 | |
| 4:15 | RW | RW | CONFIG_EPSILON_W0_COUNT: epsilon count for Nn/G scope CP-Write | |
| 16:27 | RW | RW | CONFIG_EPSILON_W1_COUNT: epsilon count for Rn/Vg scope CP-Write | |
| 28:39 | RW | RW | CONFIG_EPSILON_R0_COUNT: epsilon count for Ln scope Reads | |
| 40:51 | RW | RW | CONFIG_EPSILON_R1_COUNT: epsilon count for Nn/G scope Reads | |
| 52:63 | RW | RW | CONFIG_EPSILON_R2_COUNT: epsilon count for Rn/Vg scope Reads | |
| Timer Config Reg | ||||
|---|---|---|---|---|
| Addr: |
0000000011010863 (SCOM) 0000000013410018 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.MCP.MISC.XTIMER_CONFIG | |||
| Constant(s): | ||||
| Comments: | Timer Configuration Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:59 | PAU3.CS.SM1.MCP.MISC.XTIMER_CONFIG_Q_0_INST.LATC.L2(0:59) [000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:1 | RW | RW | CONFIG_POCKET_LONG_RATE1: Rate_1 for the Long Pocket-Cache timer. The Pocket-Cache timer is used to evaporate pocket-cache entries which are not claimed. The Long timer duration is f(Rate_1)*2^(Rate_2)*5e-10 seconds Unless config_pckt_long_uses_hang=1, then it is f(Rate1)*rpt_hang.poll interval. f(0b00) = 2 f(0b01) = 3 f(0b10) = 4 f(0b11) = 5 | |
| 2:7 | RW | RW | CONFIG_POCKET_LONG_RATE2: Rate_2 for the long timer for Pocket-Cache entries (2^n cycles). | |
| 8:13 | RW | RW | CONFIG_POCKET_SHORT_RATE2: Rate_2 for the short timer for Pocket-Cache entries (2^n cycles). | |
| 14:19 | RW | RW | CONFIG_FWD_PROG_RATE2: Rate_2 for the forward-progress timer (2^n cycles). | |
| 20:25 | RW | RW | CONFIG_XTIMER_RESERVED1: Reserved (was: Rate for CTL timer tick (default 63 = off)) | |
| 26:31 | RW | RW | CONFIG_INH0_TICK: Rate for SM-Inhibit timer tick0 (default 63 = off) Note: This field can/should have different values in each instance. No MDials have been created for this field's IDials | |
| 32:37 | RW | RW | CONFIG_INH1_TICK: Rate for SM-Inhibit timer tick1 (default 63 = off) Note: This field can/should have different values in each instance. No MDials have been created for this field's IDials | |
| 38:39 | RW | RW | CONFIG_NV_RESP_RATE1: Reserved (was: Rate_1 for NV-Response timer) | |
| 40:45 | RW | RW | CONFIG_NV_RESP_RATE2: Rate_2 for the NV-Response timer (2^n cycles). Overall timeout is (3 to 4)*(2^Rate_2)*5e-10 seconds. | |
| 46:47 | RW | RW | CONFIG_POCKET_SHORT_RATE1: Rate_1 for the Short Pocket-Cache timer. The Pocket-Cache timer is used to evaporate pocket-cache entries which are not claimed. the Short timer duration is f(Rate_1)*2^(Rate_2)*5e-10 seconds where f(Rate_1) is: f(0b00) = 7 f(0b01) = 63 f(0b10) = 511 f(0b11) = 4095 | |
| 48:53 | RW | RW | CONFIG_SCAN_WAIT_RATE: Rate for directory-scanning wait-walker 2^Rate cycles per tick | |
| 54:59 | RW | RW | CONFIG_EPOCH_RATE: Rate for epoch-checks Overall timeout is (2 to 3)*(2^Rate)*5e-10 seconds. | |
| 60:63 | RO | RO | constant=0b0000 | |
| Perf Config Reg | ||||
|---|---|---|---|---|
| Addr: |
0000000011010864 (SCOM) 0000000013410020 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.MCP.MISC.PERF_CONFIG | |||
| Constant(s): | ||||
| Comments: | Performance Event selection | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM1.MCP.MISC.PERF_CONFIG_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:8 | RW | RW | PERF_CONFIG_LATSTART: Latency count start event | |
| 9:17 | RW | RW | PERF_CONFIG_LATCANCEL: Latency count abort event | |
| 18:26 | RW | RW | PERF_CONFIG_LATFINISH: Latency count finish event | |
| 27 | RW | RW | PERF_CONFIG_RESERVED1: reserved | |
| 28:35 | RW | RW | PERF_CONFIG_EVENT0: Event 0 select 0: count nothing 1: count cycles 2: count latency events (see latstart/cancel/finish fields) 3: count latency cycles (avg latency = cycles divided by events) 4: count latency aborts (start condition was detected, but finish condition was not) 5: count # Same-address checks detected a collision 6: count # Same-address checks detected no collision 7: count # CResps matching cresp + original command 8: count # of PB Cmds sent w/ matching scope 9: count # CResps matching cresp + scope + master command + original command 10: count # of PB Cmds sent w/ matching scope+command 11: count # of NV/OC Cmds sent w/ matching command 12: count # of NV/OC Resps sent w/ matching response(command) 13: count # of force_evicts sent due to dir-scan / XSL-castouts 14: count # of force_evicts sent due to sfe / PowerBus RCmd snoops 15: count # of force_evicts sent due to the other brick having state (needed by the requesting brick) 16: count # of force_evicts / EF responses sent due to capacity evicts in the L2 directory 17: count # of allocating C2 commands that update state in an existing directory entry (ie cacheline was alreayd present) 18: count # of allocating C2 commands that update state in a new directory entry (ie cacheline was not present in the directory) others: reserved (count nothing) | |
| 36:43 | RW | RW | PERF_CONFIG_EVENT1: Event 1 select See Event 0 select for encodes | |
| 44:51 | RW | RW | PERF_CONFIG_EVENT2: Event 2 select See Event 0 select for encodes | |
| 52:59 | RW | RW | PERF_CONFIG_EVENT3: Event 3 select See Event 0 select for encodes | |
| 60:61 | RW | RW | PERF_CONFIG_RESERVED2: reserved | |
| 62 | RW | RW | PERF_CONFIG_LATFILTER: 0/1 = count max latency events / filter latency events by 1/1024 for bias reduction | |
| 63 | RW | RW | PERF_CONFIG_ACT: Enable clock-gates for performance monitor latches | |
| Inhibit configuration Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010865 (SCOM) 0000000013410028 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.MCP.MISC.INHIBIT_CONFIG | |||
| Constant(s): | ||||
| Comments: | Configures Inhibits for CQ_SM | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM1.MCP.MISC.INHIBIT_CONFIG_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:3 | RW | RW | CONFIG_INHIBIT_LFREQ0: Base LFSR frequency 0: 0..11 = 1/2^(n+1) 12 = 1/2^14 13 = 1/2^16 14 = 1/2^18 15 = 1/2^20 | |
| 4:5 | RW | RW | CONFIG_INHIBIT_PFREQ0: Selects pre frequency 0: 0 = Inhibit timer tick0 1 = inverted Inhibit timer tick0 2 = LFSR 3 = inverted LFSR (-> 1/2, 3/4, 7/8, ...) | |
| 6 | RW | RW | CONFIG_INHIBIT_BLOCKY0: 0/1 = disable blocky mode / enable blocky mode | |
| 7 | RW | RW | CONFIG_INHIBIT_ONESHOT0: 0/1 = continus mode / one-shot mode | |
| 8:15 | RW | RW | CONFIG_INHIBIT_DEST0: Selects the destination of the inhibit | |
| 16:19 | RW | RW | CONFIG_INHIBIT_LFREQ1: Base LFSR frequency 0: 0..12 = 1/2^(n+1) 13 = 1/2^16 14 = 1/2^18 15 = 1/2^20 | |
| 20:21 | RW | RW | CONFIG_INHIBIT_PFREQ1: Selects pre frequency 0: 0 = Inhibit timer tick1 1 = inverted Inhibit timer tick1 2 = LFSR 3 = inverted LFSR (-> 1/2, 3/4, 7/8, ...) | |
| 22 | RW | RW | CONFIG_INHIBIT_BLOCKY1: 0/1 = disable blocky mode / enable blocky mode | |
| 23 | RW | RW | CONFIG_INHIBIT_ONESHOT1: 0/1 = continus mode / one-shot mode | |
| 24:31 | RW | RW | CONFIG_INHIBIT_DEST1: Selects the destination of the inhibit | |
| 32:35 | RW | RW | CONFIG_INHIBIT_LFREQ2: Base LFSR frequency 2: 0..11 = 1/2^(n+1) 12 = 1/2^14 13 = 1/2^16 14 = 1/2^18 15 = 1/2^20 | |
| 36:37 | RW | RW | CONFIG_INHIBIT_PFREQ2: Selects pre frequency 2: 0 = Inhibit timer tick0 1 = inverted Inhibit timer tick0 2 = LFSR 3 = inverted LFSR (-> 1/2, 3/4, 7/8, ...) | |
| 38 | RW | RW | CONFIG_INHIBIT_BLOCKY2: 0/1 = disable blocky mode / enable blocky mode | |
| 39 | RW | RW | CONFIG_INHIBIT_ONESHOT2: 0/1 = continus mode / one-shot mode | |
| 40:47 | RW | RW | CONFIG_INHIBIT_DEST2: Selects the destination of the inhibit | |
| 48:51 | RW | RW | CONFIG_INHIBIT_LFREQ3: Base LFSR frequency 3: 0..12 = 1/2^(n+1) 13 = 1/2^16 14 = 1/2^18 15 = 1/2^20 | |
| 52:53 | RW | RW | CONFIG_INHIBIT_PFREQ3: Selects pre frequency 3: 0 = Inhibit timer tick1 1 = inverted Inhibit timer tick1 2 = LFSR 3 = inverted LFSR (-> 1/2, 3/4, 7/8, ...) | |
| 54 | RW | RW | CONFIG_INHIBIT_BLOCKY3: 0/1 = disable blocky mode / enable blocky mode | |
| 55 | RW | RW | CONFIG_INHIBIT_ONESHOT3: 0/1 = continus mode / one-shot mode | |
| 56:63 | RW | RW | CONFIG_INHIBIT_DEST3: Selects the destination of the inhibit | |
| c_err_rpt Message-0 latches | ||||
|---|---|---|---|---|
| Addr: |
0000000011010866 (SCOM) 0000000013410030 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.MCP.MISC.CERR_MESSAGE0 | |||
| Constant(s): | ||||
| Comments: | Error message/capture register 0 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM1.MCP.MISC.CERR_MESSAGE0_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:63 | RWX_WCLRREG | RWX_WCLRREG | CERR_MESSAGE_BITS0: reserved | |
| c_err_rpt Message-1 latches | ||||
|---|---|---|---|---|
| Addr: |
0000000011010867 (SCOM) 0000000013410038 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.MCP.MISC.CERR_MESSAGE1 | |||
| Constant(s): | ||||
| Comments: | Error message/capture register 1 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM1.MCP.MISC.CERR_MESSAGE1_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:63 | RWX_WCLRREG | RWX_WCLRREG | CERR_MESSAGE_BITS1: reserved | |
| c_err_rpt Message-2 latches | ||||
|---|---|---|---|---|
| Addr: |
0000000011010868 (SCOM) 0000000013410040 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.MCP.MISC.CERR_MESSAGE2 | |||
| Constant(s): | ||||
| Comments: | Error message/capture register 2 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM1.MCP.MISC.CERR_MESSAGE2_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:63 | RWX_WCLRREG | RWX_WCLRREG | CERR_MESSAGE_BITS2: reserved | |
| c_err_rpt Message-3 latches | ||||
|---|---|---|---|---|
| Addr: |
0000000011010869 (SCOM) 0000000013410048 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.MCP.MISC.CERR_MESSAGE3 | |||
| Constant(s): | ||||
| Comments: | Error message/capture register 3 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM1.MCP.MISC.CERR_MESSAGE3_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:63 | RWX_WCLRREG | RWX_WCLRREG | CERR_MESSAGE_BITS3: reserved | |
| c_err_rpt Message-4 latches | ||||
|---|---|---|---|---|
| Addr: |
000000001101086A (SCOM) 0000000013410050 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.MCP.MISC.CERR_MESSAGE4 | |||
| Constant(s): | ||||
| Comments: | Error message/capture register 4 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM1.MCP.MISC.CERR_MESSAGE4_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:63 | RWX_WCLRREG | RWX_WCLRREG | CERR_MESSAGE_BITS4: reserved | |
| c_err_rpt Message-5 latches | ||||
|---|---|---|---|---|
| Addr: |
000000001101086B (SCOM) 0000000013410058 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.MCP.MISC.CERR_MESSAGE5 | |||
| Constant(s): | ||||
| Comments: | Error message/capture register 5 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM1.MCP.MISC.CERR_MESSAGE5_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:63 | RWX_WCLRREG | RWX_WCLRREG | CERR_MESSAGE_BITS5: reserved | |
| c_err_rpt Message-6 latches | ||||
|---|---|---|---|---|
| Addr: |
000000001101086C (SCOM) 0000000013410060 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.MCP.MISC.CERR_MESSAGE6 | |||
| Constant(s): | ||||
| Comments: | Error message/capture register 6 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM1.MCP.MISC.CERR_MESSAGE6_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:63 | RWX_WCLRREG | RWX_WCLRREG | CERR_MESSAGE_BITS6: reserved | |
| c_err_rpt Message-7 latches | ||||
|---|---|---|---|---|
| Addr: |
000000001101086D (SCOM) 0000000013410068 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.MCP.MISC.CERR_MESSAGE7 | |||
| Constant(s): | ||||
| Comments: | Error message/capture register 7 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:39 | PAU3.CS.SM1.MCP.MISC.CERR_MESSAGE7_Q_0_INST.LATC.L2(0:39) [0000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:39 | RWX_WCLRREG | RWX_WCLRREG | CERR_MESSAGE_BITS7: reserved | |
| 40:63 | RO | RO | constant=0b000000000000000000000000 | |
| CQ_SM status register | ||||
|---|---|---|---|---|
| Addr: |
000000001101086E (SCOM) 0000000013410070 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.MCP.MISC.SM_STATUS | |||
| Constant(s): | ||||
| Comments: | Status reporting register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM1.MCP.MISC.SM_STATUS_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:3 | ROX | ROX | SM_STATUS_MRBGP: Master-Retry backoff level for Group-Pump commands | |
| 4:7 | ROX | ROX | SM_STATUS_MRBSP: Master-Retry backoff level for System-Pump commands | |
| 8:11 | ROX | ROX | SM_STATUS_FENCE0: Brick-0 Fence sequencing state 0b0000 = Idle state, completely unfenced 0b0--- = in transition between fenced and not-fenced 0b10-- = in transition between fenced and not-fenced 0b1100 = Fenced state, fence sequencing complete 0b1101 = Flushing pocket-cache entries prior to exiting fence 0b1110 = Flushing pocket-cache entries prior to exiting fence 0b1111 = reserved | |
| 12:15 | ROX | ROX | SM_STATUS_FENCE1: Brick-1 Fence sequencing state 0b0000 = Idle state, completely unfenced 0b0--- = in transition between fenced and not-fenced 0b10-- = in transition between fenced and not-fenced 0b1100 = Fenced state, fence sequencing complete 0b1101 = Flushing pocket-cache entries prior to exiting fence 0b1110 = Flushing pocket-cache entries prior to exiting fence 0b1111 = reserved | |
| 16:19 | ROX | ROX | SM_STATUS_FENCE2: Brick-2 Fence sequencing state 0b0000 = Idle state, completely unfenced 0b0--- = in transition between fenced and not-fenced 0b10-- = in transition between fenced and not-fenced 0b1100 = Fenced state, fence sequencing complete 0b1101 = Flushing pocket-cache entries prior to exiting fence 0b1110 = Flushing pocket-cache entries prior to exiting fence 0b1111 = reserved | |
| 20:23 | ROX | ROX | SM_STATUS_FENCE3: Brick-3 Fence sequencing state 0b0000 = Idle state, completely unfenced 0b0--- = in transition between fenced and not-fenced 0b10-- = in transition between fenced and not-fenced 0b1100 = Fenced state, fence sequencing complete 0b1101 = Flushing pocket-cache entries prior to exiting fence 0b1110 = Flushing pocket-cache entries prior to exiting fence 0b1111 = reserved | |
| 24:27 | ROX | ROX | SM_STATUS_FENCE4: Brick-4 Fence sequencing state 0b0000 = Idle state, completely unfenced 0b0--- = in transition between fenced and not-fenced 0b10-- = in transition between fenced and not-fenced 0b1100 = Fenced state, fence sequencing complete 0b1101 = Flushing pocket-cache entries prior to exiting fence 0b1110 = Flushing pocket-cache entries prior to exiting fence 0b1111 = reserved | |
| 28 | ROX | ROX | SM_STATUS_PBLN: 1 when outbound Ln-scope PowerBus request queue is empty | |
| 29 | ROX | ROX | SM_STATUS_PBNNG: 1 when outbound Nn/G-scope PowerBus request queue is empty | |
| 30 | ROX | ROX | SM_STATUS_PBRNVG: 1 when outbound Rn/Vg-scope PowerBus request queue is empty | |
| 31 | ROX | ROX | SM_STATUS_B0REQ: 1 when outbound brick 0 CReq request queue is empty | |
| 32 | ROX | ROX | SM_STATUS_B0DGD: 1 when outbound brick 0 Downgrade request queue is empty | |
| 33 | ROX | ROX | SM_STATUS_B1REQ: 1 when outbound brick 1 CReq request queue is empty | |
| 34 | ROX | ROX | SM_STATUS_B1DGD: 1 when outbound brick 1 Downgrade request queue is empty | |
| 35 | ROX | ROX | SM_STATUS_B2REQ: 1 when outbound brick 2 CReq request queue is empty | |
| 36 | ROX | ROX | SM_STATUS_B2DGD: 1 when outbound brick 2 Downgrade request queue is empty | |
| 37 | ROX | ROX | SM_STATUS_B3REQ: 1 when outbound brick 3 CReq request queue is empty | |
| 38 | ROX | ROX | SM_STATUS_B3DGD: 1 when outbound brick 3 Downgrade request queue is empty | |
| 39 | ROX | ROX | SM_STATUS_B4REQ: 1 when outbound brick 4 CReq request queue is empty | |
| 40 | ROX | ROX | SM_STATUS_B4DGD: 1 when outbound brick 4 Downgrade request queue is empty | |
| 41 | ROX | ROX | SM_STATUS_MMIO: 1 when outbound MMIO/GenId request queue is empty | |
| 42 | ROX | ROX | SM_STATUS_MMIOSUE: 1 when outbound MMIO-SUE request queue is empty | |
| 43 | ROX | ROX | SM_STATUS_ATSXLATE: 1 when outbound ATS-TCE-Translation request queue is empty | |
| 44 | ROX | ROX | SM_STATUS_REPLAY: 1 when outbound replay-to-directory queue is empty | |
| 45 | ROX | ROX | SM_STATUS_PBRSP: 1 when outbound PowerBus data-response/merge-operation queue is empty | |
| 46 | ROX | ROX | SM_STATUS_B0RSP: 1 when outbound brick 0 response queue is empty | |
| 47 | ROX | ROX | SM_STATUS_B1RSP: 1 when outbound brick 1 response queue is empty | |
| 48 | ROX | ROX | SM_STATUS_B2RSP: 1 when outbound brick 2 response queue is empty | |
| 49 | ROX | ROX | SM_STATUS_B3RSP: 1 when outbound brick 3 response queue is empty | |
| 50 | ROX | ROX | SM_STATUS_B4RSP: 1 when outbound brick 4 response queue is empty | |
| 51 | ROX | ROX | SM_STATUS_XARSP: 1 when outbound ATS/MISC response queue is empty | |
| 52 | ROX | ROX | SM_STATUS_FREE: 1 when Free state machine queue is empty | |
| 53 | ROX | ROX | SM_STATUS_DIRUPD: 1 when Directory-Update queue is empty | |
| 54 | ROX | ROX | SM_STATUS_SACOLL: 1 when Same-Address Collision-Check queue is empty | |
| 55:58 | ROX | ROX | SM_STATUS_MRBCP: Master-Retry backoff level for Chip-Pump commands | |
| 59:60 | ROX | ROX | SM_STATUS_PERF_LSTATE: Performance-counter Latency state | |
| 61:63 | ROX | ROX | SM_STATUS_RESERVED2: reserved | |
| c_err_rpt first-0 latches | ||||
|---|---|---|---|---|
| Addr: |
000000001101086F (SCOM) 0000000013410078 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.MCP.MISC.CERR_FIRST0 | |||
| Constant(s): | ||||
| Comments: | c_err_rpt first latches read-write-1-clear reg | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:55 | PAU3.CS.SM1.MCP.MISC.CERR_FIRST0_Q_0_INST.LATC.L2(0:55) [00000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_0: NVF0 s4: NVLink UT=0 to MMIO space bad cmd/length/alignment | |
| 1 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_1: NVF1 s4: UT=1 to MMIO space bad cmd/length/alignment | |
| 2 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_2: NVF2 s4: Target-Error/Unsupported-Request/Reserved Rsp_Status received in NVLink Response | |
| 3 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_3: NVF3 s4: Unexpected NVLink/OCAPI Response | |
| 4 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_4: NVF4 s4: Bad NV or OC response received (fence brick) | |
| 5 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_5: NVF5 s7: MCP_M_EVAL_DSA: illegal castout/.push arrives vs L2 directory state | |
| 6 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_6: NVF6 s4: Target-Error/Unsupported-Request/Reserved Rsp_Status received in NVLink Trans-Done Response | |
| 7 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_7: NVF7 s4: NVLink or OCAPI response timeout | |
| 8 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_8: NVF8 s4: Bad synonym_done received | |
| 9 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_9: NVF9 s4: OCAPI request to MMIO space bad cmd/length/alignment | |
| 10 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_10: NVF10 s4: DMA write/atomic to MMIO space w/ Data error | |
| 11 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_11: NVF11 s7: MCP_M_EVAL_DSA: Topology-index of the Request address is not valid in the topology-index table | |
| 12 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_12: NVF12 s7: MCP_M_EVAL_DSA: addr_error CResp to posted request | |
| 13 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_13: NVF13 (reserved) | |
| 14 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_14: NVF14 (reserved) | |
| 15 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_15: NVF15 NVLink NVF error for brick 0 occurred | |
| 16 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_16: NVF16 NVLink NVF error for brick 1 occurred | |
| 17 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_17: NVF17 NVLink NVF error for brick 2 occurred | |
| 18 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_18: NVF18 NVLink NVF error for brick 3 occurred | |
| 19 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_19: NVF19 NVLink NVF error for brick 4 occurred | |
| 20 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_ASBE_0: ASBE0 SBE ECC error detected from State-machine array | |
| 21 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_ASBE_1: ASBE1 SBE ECC error detected from Rq/Rs output queue array | |
| 22 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_ASBE_2: ASBE2 SBE ECC error detected from PowerBus data flit combiner array | |
| 23 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_ASBE_3: ASBE3 (reserved) | |
| 24 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_ASBE_4: ASBE4 SBE ECC error detected from L2-Directory SRAM 0 | |
| 25 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_ASBE_5: ASBE5 SBE ECC error detected from L2-Directory SRAM 1 | |
| 26 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_ASBE_6: ASBE6 SBE ECC error detected from L2-Directory SRAM 2 | |
| 27 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_ASBE_7: ASBE7 SBE ECC error detected from L2-Directory SRAM 3 | |
| 28 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBR_0: PBR0 s4: MCP_PC_WT_CRESP: abort_trm(_ed) cresp received to PAU request | |
| 29 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBR_1: PBR1 s4: MCP_PC_BK_WT_CRESP: abort_trm cresp received to PAU BKill request | |
| 30 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBR_2: PBR2 s4: Mis-aligned dma_pr_w/pr_dma_inj to AFU-MMIO space | |
| 31 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBR_3: PBR3 s4: rpt_hang.poll signalled hang condition | |
| 32 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBR_4: PBR4 s4: MCP_PC_WT_CRESP: Addr_Error received for self-lpc command (SSF) | |
| 33 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBR_5: PBR5 (reserved) | |
| 34 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBR_6: PBR6 (reserved) | |
| 35 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBR_7: PBR7 (reserved) | |
| 36 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_REG_0: REG0 s4: Address/Length/Alignment error on MMIO/GenId/Config access | |
| 37 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_REG_1: REG1 (reserved) | |
| 38 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_REG_2: REG2 (reserved) | |
| 39 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_REG_3: REG3 (reserved) | |
| 40 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_OCR_0: OCR0 s4: UT=0 to MMIO space bad cmd/length/alignment | |
| 41 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_OCR_1: OCR1 s4: Bad OC response received | |
| 42 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_OCR_2: OCR2 s4: AFU request w/ bad data received | |
| 43 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_OCR_3: OCR3 s4: Intrp_Req ObjHandle did not map to MMIO space | |
| 44 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_OCR_4: OCR4 s4: NVLink UT=0 to MMIO space bad cmd/length/alignment | |
| 45 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_OCR_5: OCR5 s4: UT=1 to MMIO space bad cmd/length/alignment | |
| 46 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_OCR_6: OCR6 s4: OCAPI request to MMIO space bad cmd/length/alignment | |
| 47 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_OCR_7: OCR7 s4: DMA write/atomic to MMIO space w/ Data error | |
| 48 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_OCR_8: OCR8 Epoch scanning did not complete before the next tick | |
| 49 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_OCR_9: OCR9 (reserved) | |
| 50 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_OCR_10: OCR10 (reserved) | |
| 51 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_OCR_11: OCR11 NVLink OCR error for brick 0 occurred | |
| 52 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_OCR_12: OCR12 NVLink OCR error for brick 1 occurred | |
| 53 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_OCR_13: OCR13 NVLink OCR error for brick 2 occurred | |
| 54 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_OCR_14: OCR14 NVLink OCR error for brick 3 occurred | |
| 55 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_OCR_15: OCR15 NVLink OCR error for brick 4 occurred | |
| 56:63 | RO | RO | constant=0b00000000 | |
| c_err_rpt first-1 latches | ||||
|---|---|---|---|---|
| Addr: |
0000000011010870 (SCOM) 0000000013410080 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.MCP.MISC.CERR_FIRST1 | |||
| Constant(s): | ||||
| Comments: | c_err_rpt first latches read-write-1-clear reg | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:35 | PAU3.CS.SM1.MCP.MISC.CERR_FIRST1_Q_0_INST.LATC.L2(0:35) [000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLGX_0: NLGX0 Unknown xtype in stage s0r of RXO pipe | |
| 1 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLGX_1: NLGX1 Unknown xtype in stage s2r of RXO pipe | |
| 2 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLGX_2: NLGX2 (reserved) | |
| 3 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLGX_3: NLGX3 (reserved) | |
| 4 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_FWD_0: FWD0 s4: Forward progress timer expired | |
| 5 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_FWD_1: FWD1 s4: rpt_hang.data waiting-for-data timeout | |
| 6 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_FWD_2: FWD2 (reserved) | |
| 7 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_FWD_3: FWD3 (reserved) | |
| 8 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_AUE_0: AUE0 UE ECC error detected from State-machine array | |
| 9 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_AUE_1: AUE1 UE ECC error detected from Rq/Rs output queue array | |
| 10 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_AUE_2: AUE2 UE ECC error detected from PowerBus data flit combiner array | |
| 11 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_AUE_3: AUE3 (reserved) | |
| 12 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_AUE_4: AUE4 UE ECC error detected from L2-Directory SRAM 0 | |
| 13 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_AUE_5: AUE5 UE ECC error detected from L2-Directory SRAM 1 | |
| 14 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_AUE_6: AUE6 UE ECC error detected from L2-Directory SRAM 2 | |
| 15 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_AUE_7: AUE7 UE ECC error detected from L2-Directory SRAM 3 | |
| 16 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBF_0: PBF0 s5: MCP_M_WT_CRESP: error cresp received for a command | |
| 17 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBF_1: PBF1 s5: MCP_PC_WT_CRESP: error cresp received for a command | |
| 18 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBF_2: PBF2 s4: MCP_PC_WT_CRESP: Addr_Error received for self-lpc command (SSF) | |
| 19 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBF_3: PBF3 s4: MCP_PC_BK_WT_CRESP: ack_dead cresp received for a bkill | |
| 20 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBF_4: PBF4 s5: MCP_M_RCV_DATA_PTL: not all segments/OWs were received | |
| 21 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBF_5: PBF5 s4: dma_pr_w/pr_dma_inj snooped that crosses 128B boundary | |
| 22 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBF_6: PBF6 s4: SMEV_DATIN: Received data with illegal data_stat value. | |
| 23 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBF_7: PBF7 Unexpected data beat received | |
| 24 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBF_8: PBF8 s7: addr_error CResp to internal PAU request | |
| 25 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBF_9: PBF9 (reserved) | |
| 26 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBF_10: PBF10 s5: Received 64B of data but snooped command wasn't cp_*(m=1) | |
| 27 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBF_11: PBF11 s5: Received 64B of data to PAU-mastered command | |
| 28 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_LDA_0: LDA0 s4: MCP_PC_WT_CRESP: Addr_Error received for load command (LD) | |
| 29 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_LDA_1: LDA1 (reserved) | |
| 30 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_LDA_2: LDA2 (reserved) | |
| 31 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_LDA_3: LDA3 (reserved) | |
| 32 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_STA_0: STA0 s4: MCP_PC_WT_CRESP: Addr_Error received for store command (ST) | |
| 33 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_STA_1: STA1 s4: MCP_PC_BK_WT_CRESP: Addr_Error received for bkill command (ST) | |
| 34 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_STA_2: STA2 (reserved) | |
| 35 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_STA_3: STA3 (reserved) | |
| 36:63 | RO | RO | constant=0b0000000000000000000000000000 | |
| c_err_rpt first-2 latches | ||||
|---|---|---|---|---|
| Addr: |
0000000011010871 (SCOM) 0000000013410088 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.MCP.MISC.CERR_FIRST2 | |||
| Constant(s): | ||||
| Comments: | c_err_rpt first latches read-write-1-clear reg | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM1.MCP.MISC.CERR_FIRST2_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_0: NLG0 s4: Rcmd Event received but state machine is not IDLE | |
| 1 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_1: NLG1 s4: Pocket-Hit event but not in MCP_M_PCKT_WAIT_HIT/PC_* state | |
| 2 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_2: NLG2 s4: MCP_M_WT_CRESP: ma_scresp table lookup missed | |
| 3 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_3: NLG3 s4: MCP_M_WT_CRESP: start epsilon, but epsilon already in progress | |
| 4 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_4: NLG4 s5: MCP_M_WT_CRESP: ma_scresp indicated 'evaporate' but have xTL modified data | |
| 5 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_5: NLG5 s5: MCP_M_WT_CRESP: ma_scresp indicated 'evaporate' but have PB modified data | |
| 6 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_6: NLG6 s5: MCP_M_WT_CRESP: bad scenario code from ma_scresp table | |
| 7 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_7: NLG7 s4: snoop Cresp received but not in MCP_M_WT_CRESP state | |
| 8 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_8: NLG8 s4: Dir-Lock Event received but state machine is not MCP_PC_WT_CRESP/MCP_M_WAIT_SYN_PEND/MCP_M_WAIT_DIR_LOCK or bad ttype | |
| 9 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_9: NLG9 s4: MCP_PC_WT_CRESP: ma_mcresp table lookup missed | |
| 10 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_10: NLG10 s4/5: MCP_PC/_BK/_WT_CRESP: Write coll state didn't match early protection state | |
| 11 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_11: NLG11 s4: MCP_PC_WT_CRESP: start epsilon, but epsilon already in progress | |
| 12 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_12: NLG12 s5: MCP_PC_WT_CRESP: bad scenario code from ma_mcresp table | |
| 13 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_13: NLG13 s4: MCP_PC_BK_WT_CRESP: bad next-step for bkill (ack-done) | |
| 14 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_14: NLG14 s4: MCP_PC_BK_WT_CRESP: bad next-step for bkill (retry) | |
| 15 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_15: NLG15 s4: MCP_PC_BK_WT_CRESP: bad cresp for a bkill | |
| 16 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_16: NLG16 s4: master Cresp received but not in MCP_PC_WT_CRESP/MCP_PC_BK_WT_CRESP states | |
| 17 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_17: NLG17 s4: M_IDLE: Invalid DATALEN[3:0] for NVLink data command | |
| 18 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_18: NLG18 s4: M_IDLE: Invalid command type received | |
| 19 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_19: NLG19 s4: AT-translate-Response event but not in wait-translate state | |
| 20 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_20: NLG20 s4: AT-translate-Response event had bad translate status, but cmd not recognized | |
| 21 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_21: NLG21 s4: SA-Done event but not in wait-SA state | |
| 22 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_22: NLG22 s4: MCP_PC_WAIT_DATADONE: bad next-step for PB data transmit | |
| 23 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_23: NLG23 s4: MCP_TD_WAIT_DATADONE: Unknown NVLink Master Command | |
| 24 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_24: NLG24 s4: BuffDone event but not in PB/PC/MG/NR/XATS/MCP_TD_WAIT_DATADONE state | |
| 25 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_25: NLG25 s4: MCP_NC_WT_RESP: Unknown nv-master command for NVLink response | |
| 26 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_26: NLG26 s4: RG-RspIn event but not in MCP_RG_WT_RESP or MCP_NC_WT_RESP* state | |
| 27 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_27: NLG27 s4: Epsilon-In-Progress, but epsilon counter clock is not the epsilon clock | |
| 28 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_28: NLG28 s4: Epsilon counter clock is 'epsilon' but epsilon_ip is not set | |
| 29 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_29: NLG29 s4: MCP_PC_WT_BK_RBACK: bad next-step for bkill | |
| 30 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_30: NLG30 s4: M/RR_BACK timer expired but not in PC_WT(_BK)_RBACK state | |
| 31 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_31: NLG31 s4: Bad epclock value | |
| 32 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_32: NLG32 s4: coll_state is POCKET_RCOLL_ND but master state is not PCKT_WAIT_HIT | |
| 33 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_33: NLG33 s7: Did not find anything to do for a MCMD_COH response | |
| 34 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_34: NLG34 s4: Unknown Event type received | |
| 35 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_35: NLG35 s4: SMEV_DIRDONE received but sm_dir_upd_pending=0 | |
| 36 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_36: NLG36 s7: MCP_M_EVAL_DSA: Unknown merge opcode from dsa table | |
| 37 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_37: NLG37 s7: Unknown State | |
| 38 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_38: NLG38 s4: coll_state is POCKET_RCOLL_OND but master state is not PCKT_WAIT_HIT | |
| 39 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_39: NLG39 s4: Unknown sm_master_state in ESCAN_FENCE event | |
| 40 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_40: NLG40 s4: MCP_FENCE_WT_RESP_FILL: Unknown nv-master command for Fence-Fill-SUE response | |
| 41 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_41: NLG41 s4: MCP_M_WT_CRESP: impossible command/cresp | |
| 42 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_42: NLG42 s4: MCP_PC_WT_CRESP: impossible command/cresp | |
| 43 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_43: NLG43 s7: MCP_M_EVAL_DSA: impossible command/state | |
| 44 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_44: NLG44 s7: Unexpected Error State (bad sub-sequence return) | |
| 45 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_45: NLG45 s5: sfstat-retry but not in retry-abbks collision state | |
| 46 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_46: NLG46 s5: *cond*-retry but not in retry-abbks collision state | |
| 47 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_47: NLG47 s4: Request from CTL/xTL caused bad MMIO alignment, but cmd not recognized | |
| 48 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_48: NLG48 s5: MCP_NC_EXE_RESP: Unknown nv-master command for NVLink response | |
| 49 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_49: NLG49 s7: MCP_M_EVAL_DSA: Topology-index of the Request address is not valid in the topology-index table | |
| 50 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_50: NLG50 s4: Request from CTL/xTL caused bad MMIO alignment, but cmd not recognized | |
| 51 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_51: NLG51 s4: Request from CTL/xTL loaded into non-idle state-machine | |
| 52 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_52: NLG52 s4: POCKET-HIT event but coll_state is not POCKET_WINNER* | |
| 53 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_53: NLG53 s4: Unknown rspin event w/ unknown master-command in MCP_RG_WT_RESP state | |
| 54 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_54: NLG54 s7: Attempt to send PBus request but config_enable_pbus=0 | |
| 55 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_55: NLG55 s4: Invalid SrcBus on response from CTL | |
| 56 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_56: NLG56 s4: Shoulder-tap event but not in MCP_M_WT_SHOULDER_TAP state | |
| 57 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_57: NLG57 s7: MCP_M_EVAL_DSA: ma_dsasfe table lookup missed | |
| 58 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_58: NLG58 s7: MCP_M_EVAL_DSA: ma_dsac2alc table lookup missed | |
| 59 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_59: NLG59 s7: MCP_M_EVAL_DSA: ma_dsac2co table lookup missed | |
| 60 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_60: NLG60 s7: MCP_M_EVAL_DSA: ma_dsaoth table lookup missed | |
| 61 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_61: NLG61 s7: MCP_M_EVAL_DSA: ma_dsascan table lookup missed | |
| 62 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_62: NLG62 s7: Nothing to do after looking in DSA table | |
| 63 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_63: NLG63 s7: coherence update/response but directory lock is not DLOCK_MOD | |
| c_err_rpt mask-0 latches | ||||
|---|---|---|---|---|
| Addr: |
0000000011010872 (SCOM) 0000000013410090 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.MCP.MISC.CERR_MASK0 | |||
| Constant(s): | ||||
| Comments: | c_err_rpt mask reg Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:55 | PAU3.CS.SM1.MCP.MISC.CERR_MASK0_Q_0_INST.LATC.L2(0:55) [00000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | IDIAL_MCP_MASK_NVF_0: NVF0 s4: NVLink UT=0 to MMIO space bad cmd/length/alignment | |
| 1 | RW | RW | IDIAL_MCP_MASK_NVF_1: NVF1 s4: UT=1 to MMIO space bad cmd/length/alignment | |
| 2 | RW | RW | IDIAL_MCP_MASK_NVF_2: NVF2 s4: Target-Error/Unsupported-Request/Reserved Rsp_Status received in NVLink Response | |
| 3 | RW | RW | IDIAL_MCP_MASK_NVF_3: NVF3 s4: Unexpected NVLink/OCAPI Response | |
| 4 | RW | RW | IDIAL_MCP_MASK_NVF_4: NVF4 s4: Bad NV or OC response received (fence brick) | |
| 5 | RW | RW | IDIAL_MCP_MASK_NVF_5: NVF5 s7: MCP_M_EVAL_DSA: illegal castout/.push arrives vs L2 directory state | |
| 6 | RW | RW | IDIAL_MCP_MASK_NVF_6: NVF6 s4: Target-Error/Unsupported-Request/Reserved Rsp_Status received in NVLink Trans-Done Response | |
| 7 | RW | RW | IDIAL_MCP_MASK_NVF_7: NVF7 s4: NVLink or OCAPI response timeout | |
| 8 | RW | RW | IDIAL_MCP_MASK_NVF_8: NVF8 s4: Bad synonym_done received | |
| 9 | RW | RW | IDIAL_MCP_MASK_NVF_9: NVF9 s4: OCAPI request to MMIO space bad cmd/length/alignment | |
| 10 | RW | RW | IDIAL_MCP_MASK_NVF_10: NVF10 s4: DMA write/atomic to MMIO space w/ Data error | |
| 11 | RW | RW | IDIAL_MCP_MASK_NVF_11: NVF11 s7: MCP_M_EVAL_DSA: Topology-index of the Request address is not valid in the topology-index table | |
| 12 | RW | RW | IDIAL_MCP_MASK_NVF_12: NVF12 s7: MCP_M_EVAL_DSA: addr_error CResp to posted request | |
| 13 | RW | RW | IDIAL_MCP_MASK_NVF_13: NVF13 (reserved) | |
| 14 | RW | RW | IDIAL_MCP_MASK_NVF_14: NVF14 (reserved) | |
| 15 | RW | RW | IDIAL_MCP_MASK_NVF_15: NVF15 NVLink NVF error for brick 0 occurred | |
| 16 | RW | RW | IDIAL_MCP_MASK_NVF_16: NVF16 NVLink NVF error for brick 1 occurred | |
| 17 | RW | RW | IDIAL_MCP_MASK_NVF_17: NVF17 NVLink NVF error for brick 2 occurred | |
| 18 | RW | RW | IDIAL_MCP_MASK_NVF_18: NVF18 NVLink NVF error for brick 3 occurred | |
| 19 | RW | RW | IDIAL_MCP_MASK_NVF_19: NVF19 NVLink NVF error for brick 4 occurred | |
| 20 | RW | RW | IDIAL_MCP_MASK_ASBE_0: ASBE0 SBE ECC error detected from State-machine array | |
| 21 | RW | RW | IDIAL_MCP_MASK_ASBE_1: ASBE1 SBE ECC error detected from Rq/Rs output queue array | |
| 22 | RW | RW | IDIAL_MCP_MASK_ASBE_2: ASBE2 SBE ECC error detected from PowerBus data flit combiner array | |
| 23 | RW | RW | IDIAL_MCP_MASK_ASBE_3: ASBE3 (reserved) | |
| 24 | RW | RW | IDIAL_MCP_MASK_ASBE_4: ASBE4 SBE ECC error detected from L2-Directory SRAM 0 | |
| 25 | RW | RW | IDIAL_MCP_MASK_ASBE_5: ASBE5 SBE ECC error detected from L2-Directory SRAM 1 | |
| 26 | RW | RW | IDIAL_MCP_MASK_ASBE_6: ASBE6 SBE ECC error detected from L2-Directory SRAM 2 | |
| 27 | RW | RW | IDIAL_MCP_MASK_ASBE_7: ASBE7 SBE ECC error detected from L2-Directory SRAM 3 | |
| 28 | RW | RW | IDIAL_MCP_MASK_PBR_0: PBR0 s4: MCP_PC_WT_CRESP: abort_trm(_ed) cresp received to PAU request | |
| 29 | RW | RW | IDIAL_MCP_MASK_PBR_1: PBR1 s4: MCP_PC_BK_WT_CRESP: abort_trm cresp received to PAU BKill request | |
| 30 | RW | RW | IDIAL_MCP_MASK_PBR_2: PBR2 s4: Mis-aligned dma_pr_w/pr_dma_inj to AFU-MMIO space | |
| 31 | RW | RW | IDIAL_MCP_MASK_PBR_3: PBR3 s4: rpt_hang.poll signalled hang condition | |
| 32 | RW | RW | IDIAL_MCP_MASK_PBR_4: PBR4 s4: MCP_PC_WT_CRESP: Addr_Error received for self-lpc command (SSF) | |
| 33 | RW | RW | IDIAL_MCP_MASK_PBR_5: PBR5 (reserved) | |
| 34 | RW | RW | IDIAL_MCP_MASK_PBR_6: PBR6 (reserved) | |
| 35 | RW | RW | IDIAL_MCP_MASK_PBR_7: PBR7 (reserved) | |
| 36 | RW | RW | IDIAL_MCP_MASK_REG_0: REG0 s4: Address/Length/Alignment error on MMIO/GenId/Config access | |
| 37 | RW | RW | IDIAL_MCP_MASK_REG_1: REG1 (reserved) | |
| 38 | RW | RW | IDIAL_MCP_MASK_REG_2: REG2 (reserved) | |
| 39 | RW | RW | IDIAL_MCP_MASK_REG_3: REG3 (reserved) | |
| 40 | RW | RW | IDIAL_MCP_MASK_OCR_0: OCR0 s4: UT=0 to MMIO space bad cmd/length/alignment | |
| 41 | RW | RW | IDIAL_MCP_MASK_OCR_1: OCR1 s4: Bad OC response received | |
| 42 | RW | RW | IDIAL_MCP_MASK_OCR_2: OCR2 s4: AFU request w/ bad data received | |
| 43 | RW | RW | IDIAL_MCP_MASK_OCR_3: OCR3 s4: Intrp_Req ObjHandle did not map to MMIO space | |
| 44 | RW | RW | IDIAL_MCP_MASK_OCR_4: OCR4 s4: NVLink UT=0 to MMIO space bad cmd/length/alignment | |
| 45 | RW | RW | IDIAL_MCP_MASK_OCR_5: OCR5 s4: UT=1 to MMIO space bad cmd/length/alignment | |
| 46 | RW | RW | IDIAL_MCP_MASK_OCR_6: OCR6 s4: OCAPI request to MMIO space bad cmd/length/alignment | |
| 47 | RW | RW | IDIAL_MCP_MASK_OCR_7: OCR7 s4: DMA write/atomic to MMIO space w/ Data error | |
| 48 | RW | RW | IDIAL_MCP_MASK_OCR_8: OCR8 Epoch scanning did not complete before the next tick | |
| 49 | RW | RW | IDIAL_MCP_MASK_OCR_9: OCR9 (reserved) | |
| 50 | RW | RW | IDIAL_MCP_MASK_OCR_10: OCR10 (reserved) | |
| 51 | RW | RW | IDIAL_MCP_MASK_OCR_11: OCR11 NVLink OCR error for brick 0 occurred | |
| 52 | RW | RW | IDIAL_MCP_MASK_OCR_12: OCR12 NVLink OCR error for brick 1 occurred | |
| 53 | RW | RW | IDIAL_MCP_MASK_OCR_13: OCR13 NVLink OCR error for brick 2 occurred | |
| 54 | RW | RW | IDIAL_MCP_MASK_OCR_14: OCR14 NVLink OCR error for brick 3 occurred | |
| 55 | RW | RW | IDIAL_MCP_MASK_OCR_15: OCR15 NVLink OCR error for brick 4 occurred | |
| 56:63 | RO | RO | constant=0b00000000 | |
| c_err_rpt mask-1 latches | ||||
|---|---|---|---|---|
| Addr: |
0000000011010873 (SCOM) 0000000013410098 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.MCP.MISC.CERR_MASK1 | |||
| Constant(s): | ||||
| Comments: | c_err_rpt mask reg Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:35 | PAU3.CS.SM1.MCP.MISC.CERR_MASK1_Q_0_INST.LATC.L2(0:35) [000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | IDIAL_MCP_MASK_NLGX_0: NLGX0 Unknown xtype in stage s0r of RXO pipe | |
| 1 | RW | RW | IDIAL_MCP_MASK_NLGX_1: NLGX1 Unknown xtype in stage s2r of RXO pipe | |
| 2 | RW | RW | IDIAL_MCP_MASK_NLGX_2: NLGX2 (reserved) | |
| 3 | RW | RW | IDIAL_MCP_MASK_NLGX_3: NLGX3 (reserved) | |
| 4 | RW | RW | IDIAL_MCP_MASK_FWD_0: FWD0 s4: Forward progress timer expired | |
| 5 | RW | RW | IDIAL_MCP_MASK_FWD_1: FWD1 s4: rpt_hang.data waiting-for-data timeout | |
| 6 | RW | RW | IDIAL_MCP_MASK_FWD_2: FWD2 (reserved) | |
| 7 | RW | RW | IDIAL_MCP_MASK_FWD_3: FWD3 (reserved) | |
| 8 | RW | RW | IDIAL_MCP_MASK_AUE_0: AUE0 UE ECC error detected from State-machine array | |
| 9 | RW | RW | IDIAL_MCP_MASK_AUE_1: AUE1 UE ECC error detected from Rq/Rs output queue array | |
| 10 | RW | RW | IDIAL_MCP_MASK_AUE_2: AUE2 UE ECC error detected from PowerBus data flit combiner array | |
| 11 | RW | RW | IDIAL_MCP_MASK_AUE_3: AUE3 (reserved) | |
| 12 | RW | RW | IDIAL_MCP_MASK_AUE_4: AUE4 UE ECC error detected from L2-Directory SRAM 0 | |
| 13 | RW | RW | IDIAL_MCP_MASK_AUE_5: AUE5 UE ECC error detected from L2-Directory SRAM 1 | |
| 14 | RW | RW | IDIAL_MCP_MASK_AUE_6: AUE6 UE ECC error detected from L2-Directory SRAM 2 | |
| 15 | RW | RW | IDIAL_MCP_MASK_AUE_7: AUE7 UE ECC error detected from L2-Directory SRAM 3 | |
| 16 | RW | RW | IDIAL_MCP_MASK_PBF_0: PBF0 s5: MCP_M_WT_CRESP: error cresp received for a command | |
| 17 | RW | RW | IDIAL_MCP_MASK_PBF_1: PBF1 s5: MCP_PC_WT_CRESP: error cresp received for a command | |
| 18 | RW | RW | IDIAL_MCP_MASK_PBF_2: PBF2 s4: MCP_PC_WT_CRESP: Addr_Error received for self-lpc command (SSF) | |
| 19 | RW | RW | IDIAL_MCP_MASK_PBF_3: PBF3 s4: MCP_PC_BK_WT_CRESP: ack_dead cresp received for a bkill | |
| 20 | RW | RW | IDIAL_MCP_MASK_PBF_4: PBF4 s5: MCP_M_RCV_DATA_PTL: not all segments/OWs were received | |
| 21 | RW | RW | IDIAL_MCP_MASK_PBF_5: PBF5 s4: dma_pr_w/pr_dma_inj snooped that crosses 128B boundary | |
| 22 | RW | RW | IDIAL_MCP_MASK_PBF_6: PBF6 s4: SMEV_DATIN: Received data with illegal data_stat value. | |
| 23 | RW | RW | IDIAL_MCP_MASK_PBF_7: PBF7 Unexpected data beat received | |
| 24 | RW | RW | IDIAL_MCP_MASK_PBF_8: PBF8 s7: addr_error CResp to internal PAU request | |
| 25 | RW | RW | IDIAL_MCP_MASK_PBF_9: PBF9 (reserved) | |
| 26 | RW | RW | IDIAL_MCP_MASK_PBF_10: PBF10 s5: Received 64B of data but snooped command wasn't cp_*(m=1) | |
| 27 | RW | RW | IDIAL_MCP_MASK_PBF_11: PBF11 s5: Received 64B of data to PAU-mastered command | |
| 28 | RW | RW | IDIAL_MCP_MASK_LDA_0: LDA0 s4: MCP_PC_WT_CRESP: Addr_Error received for load command (LD) | |
| 29 | RW | RW | IDIAL_MCP_MASK_LDA_1: LDA1 (reserved) | |
| 30 | RW | RW | IDIAL_MCP_MASK_LDA_2: LDA2 (reserved) | |
| 31 | RW | RW | IDIAL_MCP_MASK_LDA_3: LDA3 (reserved) | |
| 32 | RW | RW | IDIAL_MCP_MASK_STA_0: STA0 s4: MCP_PC_WT_CRESP: Addr_Error received for store command (ST) | |
| 33 | RW | RW | IDIAL_MCP_MASK_STA_1: STA1 s4: MCP_PC_BK_WT_CRESP: Addr_Error received for bkill command (ST) | |
| 34 | RW | RW | IDIAL_MCP_MASK_STA_2: STA2 (reserved) | |
| 35 | RW | RW | IDIAL_MCP_MASK_STA_3: STA3 (reserved) | |
| 36:63 | RO | RO | constant=0b0000000000000000000000000000 | |
| c_err_rpt mask-2 latches | ||||
|---|---|---|---|---|
| Addr: |
0000000011010874 (SCOM) 00000000134100A0 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.MCP.MISC.CERR_MASK2 | |||
| Constant(s): | ||||
| Comments: | c_err_rpt mask reg Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM1.MCP.MISC.CERR_MASK2_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | IDIAL_MCP_MASK_NLG_0: NLG0 s4: Rcmd Event received but state machine is not IDLE | |
| 1 | RW | RW | IDIAL_MCP_MASK_NLG_1: NLG1 s4: Pocket-Hit event but not in MCP_M_PCKT_WAIT_HIT/PC_* state | |
| 2 | RW | RW | IDIAL_MCP_MASK_NLG_2: NLG2 s4: MCP_M_WT_CRESP: ma_scresp table lookup missed | |
| 3 | RW | RW | IDIAL_MCP_MASK_NLG_3: NLG3 s4: MCP_M_WT_CRESP: start epsilon, but epsilon already in progress | |
| 4 | RW | RW | IDIAL_MCP_MASK_NLG_4: NLG4 s5: MCP_M_WT_CRESP: ma_scresp indicated 'evaporate' but have xTL modified data | |
| 5 | RW | RW | IDIAL_MCP_MASK_NLG_5: NLG5 s5: MCP_M_WT_CRESP: ma_scresp indicated 'evaporate' but have PB modified data | |
| 6 | RW | RW | IDIAL_MCP_MASK_NLG_6: NLG6 s5: MCP_M_WT_CRESP: bad scenario code from ma_scresp table | |
| 7 | RW | RW | IDIAL_MCP_MASK_NLG_7: NLG7 s4: snoop Cresp received but not in MCP_M_WT_CRESP state | |
| 8 | RW | RW | IDIAL_MCP_MASK_NLG_8: NLG8 s4: Dir-Lock Event received but state machine is not MCP_PC_WT_CRESP/MCP_M_WAIT_SYN_PEND/MCP_M_WAIT_DIR_LOCK or bad ttype | |
| 9 | RW | RW | IDIAL_MCP_MASK_NLG_9: NLG9 s4: MCP_PC_WT_CRESP: ma_mcresp table lookup missed | |
| 10 | RW | RW | IDIAL_MCP_MASK_NLG_10: NLG10 s4/5: MCP_PC/_BK/_WT_CRESP: Write coll state didn't match early protection state | |
| 11 | RW | RW | IDIAL_MCP_MASK_NLG_11: NLG11 s4: MCP_PC_WT_CRESP: start epsilon, but epsilon already in progress | |
| 12 | RW | RW | IDIAL_MCP_MASK_NLG_12: NLG12 s5: MCP_PC_WT_CRESP: bad scenario code from ma_mcresp table | |
| 13 | RW | RW | IDIAL_MCP_MASK_NLG_13: NLG13 s4: MCP_PC_BK_WT_CRESP: bad next-step for bkill (ack-done) | |
| 14 | RW | RW | IDIAL_MCP_MASK_NLG_14: NLG14 s4: MCP_PC_BK_WT_CRESP: bad next-step for bkill (retry) | |
| 15 | RW | RW | IDIAL_MCP_MASK_NLG_15: NLG15 s4: MCP_PC_BK_WT_CRESP: bad cresp for a bkill | |
| 16 | RW | RW | IDIAL_MCP_MASK_NLG_16: NLG16 s4: master Cresp received but not in MCP_PC_WT_CRESP/MCP_PC_BK_WT_CRESP states | |
| 17 | RW | RW | IDIAL_MCP_MASK_NLG_17: NLG17 s4: M_IDLE: Invalid DATALEN[3:0] for NVLink data command | |
| 18 | RW | RW | IDIAL_MCP_MASK_NLG_18: NLG18 s4: M_IDLE: Invalid command type received | |
| 19 | RW | RW | IDIAL_MCP_MASK_NLG_19: NLG19 s4: AT-translate-Response event but not in wait-translate state | |
| 20 | RW | RW | IDIAL_MCP_MASK_NLG_20: NLG20 s4: AT-translate-Response event had bad translate status, but cmd not recognized | |
| 21 | RW | RW | IDIAL_MCP_MASK_NLG_21: NLG21 s4: SA-Done event but not in wait-SA state | |
| 22 | RW | RW | IDIAL_MCP_MASK_NLG_22: NLG22 s4: MCP_PC_WAIT_DATADONE: bad next-step for PB data transmit | |
| 23 | RW | RW | IDIAL_MCP_MASK_NLG_23: NLG23 s4: MCP_TD_WAIT_DATADONE: Unknown NVLink Master Command | |
| 24 | RW | RW | IDIAL_MCP_MASK_NLG_24: NLG24 s4: BuffDone event but not in PB/PC/MG/NR/XATS/MCP_TD_WAIT_DATADONE state | |
| 25 | RW | RW | IDIAL_MCP_MASK_NLG_25: NLG25 s4: MCP_NC_WT_RESP: Unknown nv-master command for NVLink response | |
| 26 | RW | RW | IDIAL_MCP_MASK_NLG_26: NLG26 s4: RG-RspIn event but not in MCP_RG_WT_RESP or MCP_NC_WT_RESP* state | |
| 27 | RW | RW | IDIAL_MCP_MASK_NLG_27: NLG27 s4: Epsilon-In-Progress, but epsilon counter clock is not the epsilon clock | |
| 28 | RW | RW | IDIAL_MCP_MASK_NLG_28: NLG28 s4: Epsilon counter clock is 'epsilon' but epsilon_ip is not set | |
| 29 | RW | RW | IDIAL_MCP_MASK_NLG_29: NLG29 s4: MCP_PC_WT_BK_RBACK: bad next-step for bkill | |
| 30 | RW | RW | IDIAL_MCP_MASK_NLG_30: NLG30 s4: M/RR_BACK timer expired but not in PC_WT(_BK)_RBACK state | |
| 31 | RW | RW | IDIAL_MCP_MASK_NLG_31: NLG31 s4: Bad epclock value | |
| 32 | RW | RW | IDIAL_MCP_MASK_NLG_32: NLG32 s4: coll_state is POCKET_RCOLL_ND but master state is not PCKT_WAIT_HIT | |
| 33 | RW | RW | IDIAL_MCP_MASK_NLG_33: NLG33 s7: Did not find anything to do for a MCMD_COH response | |
| 34 | RW | RW | IDIAL_MCP_MASK_NLG_34: NLG34 s4: Unknown Event type received | |
| 35 | RW | RW | IDIAL_MCP_MASK_NLG_35: NLG35 s4: SMEV_DIRDONE received but sm_dir_upd_pending=0 | |
| 36 | RW | RW | IDIAL_MCP_MASK_NLG_36: NLG36 s7: MCP_M_EVAL_DSA: Unknown merge opcode from dsa table | |
| 37 | RW | RW | IDIAL_MCP_MASK_NLG_37: NLG37 s7: Unknown State | |
| 38 | RW | RW | IDIAL_MCP_MASK_NLG_38: NLG38 s4: coll_state is POCKET_RCOLL_OND but master state is not PCKT_WAIT_HIT | |
| 39 | RW | RW | IDIAL_MCP_MASK_NLG_39: NLG39 s4: Unknown sm_master_state in ESCAN_FENCE event | |
| 40 | RW | RW | IDIAL_MCP_MASK_NLG_40: NLG40 s4: MCP_FENCE_WT_RESP_FILL: Unknown nv-master command for Fence-Fill-SUE response | |
| 41 | RW | RW | IDIAL_MCP_MASK_NLG_41: NLG41 s4: MCP_M_WT_CRESP: impossible command/cresp | |
| 42 | RW | RW | IDIAL_MCP_MASK_NLG_42: NLG42 s4: MCP_PC_WT_CRESP: impossible command/cresp | |
| 43 | RW | RW | IDIAL_MCP_MASK_NLG_43: NLG43 s7: MCP_M_EVAL_DSA: impossible command/state | |
| 44 | RW | RW | IDIAL_MCP_MASK_NLG_44: NLG44 s7: Unexpected Error State (bad sub-sequence return) | |
| 45 | RW | RW | IDIAL_MCP_MASK_NLG_45: NLG45 s5: sfstat-retry but not in retry-abbks collision state | |
| 46 | RW | RW | IDIAL_MCP_MASK_NLG_46: NLG46 s5: *cond*-retry but not in retry-abbks collision state | |
| 47 | RW | RW | IDIAL_MCP_MASK_NLG_47: NLG47 s4: Request from CTL/xTL caused bad MMIO alignment, but cmd not recognized | |
| 48 | RW | RW | IDIAL_MCP_MASK_NLG_48: NLG48 s5: MCP_NC_EXE_RESP: Unknown nv-master command for NVLink response | |
| 49 | RW | RW | IDIAL_MCP_MASK_NLG_49: NLG49 s7: MCP_M_EVAL_DSA: Topology-index of the Request address is not valid in the topology-index table | |
| 50 | RW | RW | IDIAL_MCP_MASK_NLG_50: NLG50 s4: Request from CTL/xTL caused bad MMIO alignment, but cmd not recognized | |
| 51 | RW | RW | IDIAL_MCP_MASK_NLG_51: NLG51 s4: Request from CTL/xTL loaded into non-idle state-machine | |
| 52 | RW | RW | IDIAL_MCP_MASK_NLG_52: NLG52 s4: POCKET-HIT event but coll_state is not POCKET_WINNER* | |
| 53 | RW | RW | IDIAL_MCP_MASK_NLG_53: NLG53 s4: Unknown rspin event w/ unknown master-command in MCP_RG_WT_RESP state | |
| 54 | RW | RW | IDIAL_MCP_MASK_NLG_54: NLG54 s7: Attempt to send PBus request but config_enable_pbus=0 | |
| 55 | RW | RW | IDIAL_MCP_MASK_NLG_55: NLG55 s4: Invalid SrcBus on response from CTL | |
| 56 | RW | RW | IDIAL_MCP_MASK_NLG_56: NLG56 s4: Shoulder-tap event but not in MCP_M_WT_SHOULDER_TAP state | |
| 57 | RW | RW | IDIAL_MCP_MASK_NLG_57: NLG57 s7: MCP_M_EVAL_DSA: ma_dsasfe table lookup missed | |
| 58 | RW | RW | IDIAL_MCP_MASK_NLG_58: NLG58 s7: MCP_M_EVAL_DSA: ma_dsac2alc table lookup missed | |
| 59 | RW | RW | IDIAL_MCP_MASK_NLG_59: NLG59 s7: MCP_M_EVAL_DSA: ma_dsac2co table lookup missed | |
| 60 | RW | RW | IDIAL_MCP_MASK_NLG_60: NLG60 s7: MCP_M_EVAL_DSA: ma_dsaoth table lookup missed | |
| 61 | RW | RW | IDIAL_MCP_MASK_NLG_61: NLG61 s7: MCP_M_EVAL_DSA: ma_dsascan table lookup missed | |
| 62 | RW | RW | IDIAL_MCP_MASK_NLG_62: NLG62 s7: Nothing to do after looking in DSA table | |
| 63 | RW | RW | IDIAL_MCP_MASK_NLG_63: NLG63 s7: coherence update/response but directory lock is not DLOCK_MOD | |
| c_err_rpt hold-0 latches | ||||
|---|---|---|---|---|
| Addr: |
0000000011010875 (SCOM) 00000000134100A8 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.MCP.MISC.CERR_HOLD0 | |||
| Constant(s): | ||||
| Comments: | c_err_rpt hold latches read-write-clear reg | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:19 | PAU3.CS.SM1.MCP.MISC.CERPT_NVF.HOLD_LATCH_INST.HOLD.LATC.L2(0:19) [00000000000000000000] | |||
| 20:27 | PAU3.CS.SM1.MCP.MISC.CERPT_ASBE.HOLD_LATCH_INST.HOLD.LATC.L2(0:7) [00000000] | |||
| 28:35 | PAU3.CS.SM1.MCP.MISC.CERPT_PBR.HOLD_LATCH_INST.HOLD.LATC.L2(0:7) [00000000] | |||
| 36:39 | PAU3.CS.SM1.MCP.MISC.CERPT_REG.HOLD_LATCH_INST.HOLD.LATC.L2(0:3) [0000] | |||
| 40:55 | PAU3.CS.SM1.MCP.MISC.CERPT_OCR.HOLD_LATCH_INST.HOLD.LATC.L2(0:15) [0000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_0: NVF0 s4: NVLink UT=0 to MMIO space bad cmd/length/alignment | |
| 1 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_1: NVF1 s4: UT=1 to MMIO space bad cmd/length/alignment | |
| 2 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_2: NVF2 s4: Target-Error/Unsupported-Request/Reserved Rsp_Status received in NVLink Response | |
| 3 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_3: NVF3 s4: Unexpected NVLink/OCAPI Response | |
| 4 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_4: NVF4 s4: Bad NV or OC response received (fence brick) | |
| 5 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_5: NVF5 s7: MCP_M_EVAL_DSA: illegal castout/.push arrives vs L2 directory state | |
| 6 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_6: NVF6 s4: Target-Error/Unsupported-Request/Reserved Rsp_Status received in NVLink Trans-Done Response | |
| 7 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_7: NVF7 s4: NVLink or OCAPI response timeout | |
| 8 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_8: NVF8 s4: Bad synonym_done received | |
| 9 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_9: NVF9 s4: OCAPI request to MMIO space bad cmd/length/alignment | |
| 10 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_10: NVF10 s4: DMA write/atomic to MMIO space w/ Data error | |
| 11 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_11: NVF11 s7: MCP_M_EVAL_DSA: Topology-index of the Request address is not valid in the topology-index table | |
| 12 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_12: NVF12 s7: MCP_M_EVAL_DSA: addr_error CResp to posted request | |
| 13 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_13: NVF13 (reserved) | |
| 14 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_14: NVF14 (reserved) | |
| 15 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_15: NVF15 NVLink NVF error for brick 0 occurred | |
| 16 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_16: NVF16 NVLink NVF error for brick 1 occurred | |
| 17 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_17: NVF17 NVLink NVF error for brick 2 occurred | |
| 18 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_18: NVF18 NVLink NVF error for brick 3 occurred | |
| 19 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_19: NVF19 NVLink NVF error for brick 4 occurred | |
| 20 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_ASBE_0: ASBE0 SBE ECC error detected from State-machine array | |
| 21 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_ASBE_1: ASBE1 SBE ECC error detected from Rq/Rs output queue array | |
| 22 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_ASBE_2: ASBE2 SBE ECC error detected from PowerBus data flit combiner array | |
| 23 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_ASBE_3: ASBE3 (reserved) | |
| 24 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_ASBE_4: ASBE4 SBE ECC error detected from L2-Directory SRAM 0 | |
| 25 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_ASBE_5: ASBE5 SBE ECC error detected from L2-Directory SRAM 1 | |
| 26 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_ASBE_6: ASBE6 SBE ECC error detected from L2-Directory SRAM 2 | |
| 27 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_ASBE_7: ASBE7 SBE ECC error detected from L2-Directory SRAM 3 | |
| 28 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBR_0: PBR0 s4: MCP_PC_WT_CRESP: abort_trm(_ed) cresp received to PAU request | |
| 29 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBR_1: PBR1 s4: MCP_PC_BK_WT_CRESP: abort_trm cresp received to PAU BKill request | |
| 30 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBR_2: PBR2 s4: Mis-aligned dma_pr_w/pr_dma_inj to AFU-MMIO space | |
| 31 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBR_3: PBR3 s4: rpt_hang.poll signalled hang condition | |
| 32 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBR_4: PBR4 s4: MCP_PC_WT_CRESP: Addr_Error received for self-lpc command (SSF) | |
| 33 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBR_5: PBR5 (reserved) | |
| 34 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBR_6: PBR6 (reserved) | |
| 35 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBR_7: PBR7 (reserved) | |
| 36 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_REG_0: REG0 s4: Address/Length/Alignment error on MMIO/GenId/Config access | |
| 37 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_REG_1: REG1 (reserved) | |
| 38 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_REG_2: REG2 (reserved) | |
| 39 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_REG_3: REG3 (reserved) | |
| 40 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_OCR_0: OCR0 s4: UT=0 to MMIO space bad cmd/length/alignment | |
| 41 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_OCR_1: OCR1 s4: Bad OC response received | |
| 42 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_OCR_2: OCR2 s4: AFU request w/ bad data received | |
| 43 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_OCR_3: OCR3 s4: Intrp_Req ObjHandle did not map to MMIO space | |
| 44 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_OCR_4: OCR4 s4: NVLink UT=0 to MMIO space bad cmd/length/alignment | |
| 45 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_OCR_5: OCR5 s4: UT=1 to MMIO space bad cmd/length/alignment | |
| 46 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_OCR_6: OCR6 s4: OCAPI request to MMIO space bad cmd/length/alignment | |
| 47 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_OCR_7: OCR7 s4: DMA write/atomic to MMIO space w/ Data error | |
| 48 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_OCR_8: OCR8 Epoch scanning did not complete before the next tick | |
| 49 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_OCR_9: OCR9 (reserved) | |
| 50 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_OCR_10: OCR10 (reserved) | |
| 51 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_OCR_11: OCR11 NVLink OCR error for brick 0 occurred | |
| 52 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_OCR_12: OCR12 NVLink OCR error for brick 1 occurred | |
| 53 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_OCR_13: OCR13 NVLink OCR error for brick 2 occurred | |
| 54 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_OCR_14: OCR14 NVLink OCR error for brick 3 occurred | |
| 55 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_OCR_15: OCR15 NVLink OCR error for brick 4 occurred | |
| 56:63 | RO | RO | constant=0b00000000 | |
| c_err_rpt hold-1 latches | ||||
|---|---|---|---|---|
| Addr: |
0000000011010876 (SCOM) 00000000134100B0 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.MCP.MISC.CERR_HOLD1 | |||
| Constant(s): | ||||
| Comments: | c_err_rpt hold latches read-write-clear reg | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:3 | PAU3.CS.SM1.MCP.MISC.CERPT_NLGX.HOLD_LATCH_INST.HOLD.LATC.L2(0:3) [0000] | |||
| 4:7 | PAU3.CS.SM1.MCP.MISC.CERPT_FWD.HOLD_LATCH_INST.HOLD.LATC.L2(0:3) [0000] | |||
| 8:15 | PAU3.CS.SM1.MCP.MISC.CERPT_AUE.HOLD_LATCH_INST.HOLD.LATC.L2(0:7) [00000000] | |||
| 16:27 | PAU3.CS.SM1.MCP.MISC.CERPT_PBF.HOLD_LATCH_INST.HOLD.LATC.L2(0:11) [000000000000] | |||
| 28:31 | PAU3.CS.SM1.MCP.MISC.CERPT_LDA.HOLD_LATCH_INST.HOLD.LATC.L2(0:3) [0000] | |||
| 32:35 | PAU3.CS.SM1.MCP.MISC.CERPT_STA.HOLD_LATCH_INST.HOLD.LATC.L2(0:3) [0000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLGX_0: NLGX0 Unknown xtype in stage s0r of RXO pipe | |
| 1 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLGX_1: NLGX1 Unknown xtype in stage s2r of RXO pipe | |
| 2 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLGX_2: NLGX2 (reserved) | |
| 3 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLGX_3: NLGX3 (reserved) | |
| 4 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_FWD_0: FWD0 s4: Forward progress timer expired | |
| 5 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_FWD_1: FWD1 s4: rpt_hang.data waiting-for-data timeout | |
| 6 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_FWD_2: FWD2 (reserved) | |
| 7 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_FWD_3: FWD3 (reserved) | |
| 8 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_AUE_0: AUE0 UE ECC error detected from State-machine array | |
| 9 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_AUE_1: AUE1 UE ECC error detected from Rq/Rs output queue array | |
| 10 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_AUE_2: AUE2 UE ECC error detected from PowerBus data flit combiner array | |
| 11 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_AUE_3: AUE3 (reserved) | |
| 12 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_AUE_4: AUE4 UE ECC error detected from L2-Directory SRAM 0 | |
| 13 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_AUE_5: AUE5 UE ECC error detected from L2-Directory SRAM 1 | |
| 14 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_AUE_6: AUE6 UE ECC error detected from L2-Directory SRAM 2 | |
| 15 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_AUE_7: AUE7 UE ECC error detected from L2-Directory SRAM 3 | |
| 16 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBF_0: PBF0 s5: MCP_M_WT_CRESP: error cresp received for a command | |
| 17 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBF_1: PBF1 s5: MCP_PC_WT_CRESP: error cresp received for a command | |
| 18 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBF_2: PBF2 s4: MCP_PC_WT_CRESP: Addr_Error received for self-lpc command (SSF) | |
| 19 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBF_3: PBF3 s4: MCP_PC_BK_WT_CRESP: ack_dead cresp received for a bkill | |
| 20 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBF_4: PBF4 s5: MCP_M_RCV_DATA_PTL: not all segments/OWs were received | |
| 21 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBF_5: PBF5 s4: dma_pr_w/pr_dma_inj snooped that crosses 128B boundary | |
| 22 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBF_6: PBF6 s4: SMEV_DATIN: Received data with illegal data_stat value. | |
| 23 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBF_7: PBF7 Unexpected data beat received | |
| 24 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBF_8: PBF8 s7: addr_error CResp to internal PAU request | |
| 25 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBF_9: PBF9 (reserved) | |
| 26 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBF_10: PBF10 s5: Received 64B of data but snooped command wasn't cp_*(m=1) | |
| 27 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBF_11: PBF11 s5: Received 64B of data to PAU-mastered command | |
| 28 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_LDA_0: LDA0 s4: MCP_PC_WT_CRESP: Addr_Error received for load command (LD) | |
| 29 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_LDA_1: LDA1 (reserved) | |
| 30 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_LDA_2: LDA2 (reserved) | |
| 31 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_LDA_3: LDA3 (reserved) | |
| 32 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_STA_0: STA0 s4: MCP_PC_WT_CRESP: Addr_Error received for store command (ST) | |
| 33 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_STA_1: STA1 s4: MCP_PC_BK_WT_CRESP: Addr_Error received for bkill command (ST) | |
| 34 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_STA_2: STA2 (reserved) | |
| 35 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_STA_3: STA3 (reserved) | |
| 36:63 | RO | RO | constant=0b0000000000000000000000000000 | |
| c_err_rpt hold-2 latches | ||||
|---|---|---|---|---|
| Addr: |
0000000011010877 (SCOM) 00000000134100B8 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.MCP.MISC.CERR_HOLD2 | |||
| Constant(s): | ||||
| Comments: | c_err_rpt hold latches read-write-clear reg | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM1.MCP.MISC.CERPT_NLG.HOLD_LATCH_INST.HOLD.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_0: NLG0 s4: Rcmd Event received but state machine is not IDLE | |
| 1 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_1: NLG1 s4: Pocket-Hit event but not in MCP_M_PCKT_WAIT_HIT/PC_* state | |
| 2 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_2: NLG2 s4: MCP_M_WT_CRESP: ma_scresp table lookup missed | |
| 3 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_3: NLG3 s4: MCP_M_WT_CRESP: start epsilon, but epsilon already in progress | |
| 4 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_4: NLG4 s5: MCP_M_WT_CRESP: ma_scresp indicated 'evaporate' but have xTL modified data | |
| 5 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_5: NLG5 s5: MCP_M_WT_CRESP: ma_scresp indicated 'evaporate' but have PB modified data | |
| 6 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_6: NLG6 s5: MCP_M_WT_CRESP: bad scenario code from ma_scresp table | |
| 7 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_7: NLG7 s4: snoop Cresp received but not in MCP_M_WT_CRESP state | |
| 8 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_8: NLG8 s4: Dir-Lock Event received but state machine is not MCP_PC_WT_CRESP/MCP_M_WAIT_SYN_PEND/MCP_M_WAIT_DIR_LOCK or bad ttype | |
| 9 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_9: NLG9 s4: MCP_PC_WT_CRESP: ma_mcresp table lookup missed | |
| 10 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_10: NLG10 s4/5: MCP_PC/_BK/_WT_CRESP: Write coll state didn't match early protection state | |
| 11 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_11: NLG11 s4: MCP_PC_WT_CRESP: start epsilon, but epsilon already in progress | |
| 12 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_12: NLG12 s5: MCP_PC_WT_CRESP: bad scenario code from ma_mcresp table | |
| 13 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_13: NLG13 s4: MCP_PC_BK_WT_CRESP: bad next-step for bkill (ack-done) | |
| 14 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_14: NLG14 s4: MCP_PC_BK_WT_CRESP: bad next-step for bkill (retry) | |
| 15 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_15: NLG15 s4: MCP_PC_BK_WT_CRESP: bad cresp for a bkill | |
| 16 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_16: NLG16 s4: master Cresp received but not in MCP_PC_WT_CRESP/MCP_PC_BK_WT_CRESP states | |
| 17 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_17: NLG17 s4: M_IDLE: Invalid DATALEN[3:0] for NVLink data command | |
| 18 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_18: NLG18 s4: M_IDLE: Invalid command type received | |
| 19 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_19: NLG19 s4: AT-translate-Response event but not in wait-translate state | |
| 20 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_20: NLG20 s4: AT-translate-Response event had bad translate status, but cmd not recognized | |
| 21 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_21: NLG21 s4: SA-Done event but not in wait-SA state | |
| 22 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_22: NLG22 s4: MCP_PC_WAIT_DATADONE: bad next-step for PB data transmit | |
| 23 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_23: NLG23 s4: MCP_TD_WAIT_DATADONE: Unknown NVLink Master Command | |
| 24 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_24: NLG24 s4: BuffDone event but not in PB/PC/MG/NR/XATS/MCP_TD_WAIT_DATADONE state | |
| 25 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_25: NLG25 s4: MCP_NC_WT_RESP: Unknown nv-master command for NVLink response | |
| 26 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_26: NLG26 s4: RG-RspIn event but not in MCP_RG_WT_RESP or MCP_NC_WT_RESP* state | |
| 27 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_27: NLG27 s4: Epsilon-In-Progress, but epsilon counter clock is not the epsilon clock | |
| 28 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_28: NLG28 s4: Epsilon counter clock is 'epsilon' but epsilon_ip is not set | |
| 29 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_29: NLG29 s4: MCP_PC_WT_BK_RBACK: bad next-step for bkill | |
| 30 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_30: NLG30 s4: M/RR_BACK timer expired but not in PC_WT(_BK)_RBACK state | |
| 31 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_31: NLG31 s4: Bad epclock value | |
| 32 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_32: NLG32 s4: coll_state is POCKET_RCOLL_ND but master state is not PCKT_WAIT_HIT | |
| 33 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_33: NLG33 s7: Did not find anything to do for a MCMD_COH response | |
| 34 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_34: NLG34 s4: Unknown Event type received | |
| 35 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_35: NLG35 s4: SMEV_DIRDONE received but sm_dir_upd_pending=0 | |
| 36 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_36: NLG36 s7: MCP_M_EVAL_DSA: Unknown merge opcode from dsa table | |
| 37 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_37: NLG37 s7: Unknown State | |
| 38 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_38: NLG38 s4: coll_state is POCKET_RCOLL_OND but master state is not PCKT_WAIT_HIT | |
| 39 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_39: NLG39 s4: Unknown sm_master_state in ESCAN_FENCE event | |
| 40 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_40: NLG40 s4: MCP_FENCE_WT_RESP_FILL: Unknown nv-master command for Fence-Fill-SUE response | |
| 41 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_41: NLG41 s4: MCP_M_WT_CRESP: impossible command/cresp | |
| 42 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_42: NLG42 s4: MCP_PC_WT_CRESP: impossible command/cresp | |
| 43 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_43: NLG43 s7: MCP_M_EVAL_DSA: impossible command/state | |
| 44 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_44: NLG44 s7: Unexpected Error State (bad sub-sequence return) | |
| 45 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_45: NLG45 s5: sfstat-retry but not in retry-abbks collision state | |
| 46 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_46: NLG46 s5: *cond*-retry but not in retry-abbks collision state | |
| 47 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_47: NLG47 s4: Request from CTL/xTL caused bad MMIO alignment, but cmd not recognized | |
| 48 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_48: NLG48 s5: MCP_NC_EXE_RESP: Unknown nv-master command for NVLink response | |
| 49 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_49: NLG49 s7: MCP_M_EVAL_DSA: Topology-index of the Request address is not valid in the topology-index table | |
| 50 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_50: NLG50 s4: Request from CTL/xTL caused bad MMIO alignment, but cmd not recognized | |
| 51 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_51: NLG51 s4: Request from CTL/xTL loaded into non-idle state-machine | |
| 52 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_52: NLG52 s4: POCKET-HIT event but coll_state is not POCKET_WINNER* | |
| 53 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_53: NLG53 s4: Unknown rspin event w/ unknown master-command in MCP_RG_WT_RESP state | |
| 54 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_54: NLG54 s7: Attempt to send PBus request but config_enable_pbus=0 | |
| 55 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_55: NLG55 s4: Invalid SrcBus on response from CTL | |
| 56 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_56: NLG56 s4: Shoulder-tap event but not in MCP_M_WT_SHOULDER_TAP state | |
| 57 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_57: NLG57 s7: MCP_M_EVAL_DSA: ma_dsasfe table lookup missed | |
| 58 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_58: NLG58 s7: MCP_M_EVAL_DSA: ma_dsac2alc table lookup missed | |
| 59 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_59: NLG59 s7: MCP_M_EVAL_DSA: ma_dsac2co table lookup missed | |
| 60 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_60: NLG60 s7: MCP_M_EVAL_DSA: ma_dsaoth table lookup missed | |
| 61 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_61: NLG61 s7: MCP_M_EVAL_DSA: ma_dsascan table lookup missed | |
| 62 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_62: NLG62 s7: Nothing to do after looking in DSA table | |
| 63 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_63: NLG63 s7: coherence update/response but directory lock is not DLOCK_MOD | |
| Perf Match Reg | ||||
|---|---|---|---|---|
| Addr: |
0000000011010878 (SCOM) 00000000134100C0 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.MCP.MISC.PERF_MATCH_CONFIG | |||
| Constant(s): | ||||
| Comments: | Performance Event Field Match | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:43 | PAU3.CS.SM1.MCP.MISC.PERF_MATCH_CONFIG_Q_0_INST.LATC.L2(0:43) [00000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:23 | RW | RW | PERF_MATCH_RESERVED2: reserved | |
| 24:28 | RW | RW | PERF_MATCH_CRESP: CResp | |
| 29:31 | RW | RW | PERF_MATCH_SCOPE: Scope | |
| 32:41 | RW | RW | PERF_MATCH_MCMD: MCmd | |
| 42:43 | RW | RW | PERF_MATCH_RESERVED1: reserved | |
| 44:63 | RO | RO | constant=0b00000000000000000000 | |
| Perf Mask Reg | ||||
|---|---|---|---|---|
| Addr: |
0000000011010879 (SCOM) 00000000134100C8 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.MCP.MISC.PERF_MASK_CONFIG | |||
| Constant(s): | ||||
| Comments: | Performance Event Field Mask | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:43 | PAU3.CS.SM1.MCP.MISC.PERF_MASK_CONFIG_Q_0_INST.LATC.L2(0:43) [00000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:23 | RW | RW | PERF_MASK_RESERVED2: reserved | |
| 24:28 | RW | RW | PERF_MASK_CRESP: CResp | |
| 29:31 | RW | RW | PERF_MASK_SCOPE: Scope | |
| 32:41 | RW | RW | PERF_MASK_MCMD: MCmd | |
| 42:43 | RW | RW | PERF_MASK_RESERVED1: reserved | |
| 44:63 | RO | RO | constant=0b00000000000000000000 | |
| Debug0 Config Reg | ||||
|---|---|---|---|---|
| Addr: |
000000001101087A (SCOM) 00000000134100D0 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.MCP.MISC.DEBUG0_CONFIG | |||
| Constant(s): | ||||
| Comments: | Config register for trace-0 chain | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM1.MCP.MISC.DEBUG0_CONFIG_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:4 | RW | RW | DEBUG0_CONFIG_POD0: Mux control for byte 0 of trace-0 | |
| 5:9 | RW | RW | DEBUG0_CONFIG_POD1: Mux control for byte 1 of trace-0 | |
| 10:14 | RW | RW | DEBUG0_CONFIG_POD2: Mux control for byte 2 of trace-0 | |
| 15:19 | RW | RW | DEBUG0_CONFIG_POD3: Mux control for byte 3 of trace-0 | |
| 20:24 | RW | RW | DEBUG0_CONFIG_POD4: Mux control for byte 4 of trace-0 | |
| 25:29 | RW | RW | DEBUG0_CONFIG_POD5: Mux control for byte 5 of trace-0 | |
| 30:34 | RW | RW | DEBUG0_CONFIG_POD6: Mux control for byte 6 of trace-0 | |
| 35:39 | RW | RW | DEBUG0_CONFIG_POD7: Mux control for byte 7 of trace-0 | |
| 40:44 | RW | RW | DEBUG0_CONFIG_POD8: Mux control for byte 8 of trace-0 | |
| 45:49 | RW | RW | DEBUG0_CONFIG_POD9: Mux control for byte 9 of trace-0 | |
| 50:54 | RW | RW | DEBUG0_CONFIG_POD10: Mux control for byte 10 of trace-0 | |
| 55:62 | RW | RW | DEBUG0_CONFIG_RESERVED1: reserved | |
| 63 | RW | RW | DEBUG0_CONFIG_ACT: Enable clock-gates for debug trace latches | |
| Debug1 Config Reg | ||||
|---|---|---|---|---|
| Addr: |
000000001101087B (SCOM) 00000000134100D8 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.MCP.MISC.DEBUG1_CONFIG | |||
| Constant(s): | ||||
| Comments: | Config register for trace-1 chain | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM1.MCP.MISC.DEBUG1_CONFIG_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:4 | RW | RW | DEBUG1_CONFIG_POD0: Mux control for byte 0 of trace-1 | |
| 5:9 | RW | RW | DEBUG1_CONFIG_POD1: Mux control for byte 1 of trace-1 | |
| 10:14 | RW | RW | DEBUG1_CONFIG_POD2: Mux control for byte 2 of trace-1 | |
| 15:19 | RW | RW | DEBUG1_CONFIG_POD3: Mux control for byte 3 of trace-1 | |
| 20:24 | RW | RW | DEBUG1_CONFIG_POD4: Mux control for byte 4 of trace-1 | |
| 25:29 | RW | RW | DEBUG1_CONFIG_POD5: Mux control for byte 5 of trace-1 | |
| 30:34 | RW | RW | DEBUG1_CONFIG_POD6: Mux control for byte 6 of trace-1 | |
| 35:39 | RW | RW | DEBUG1_CONFIG_POD7: Mux control for byte 7 of trace-1 | |
| 40:44 | RW | RW | DEBUG1_CONFIG_POD8: Mux control for byte 8 of trace-1 | |
| 45:49 | RW | RW | DEBUG1_CONFIG_POD9: Mux control for byte 9 of trace-1 | |
| 50:54 | RW | RW | DEBUG1_CONFIG_POD10: Mux control for byte 10 of trace-1 | |
| 55:62 | RW | RW | DEBUG1_CONFIG_RESERVED1: reserved | |
| 63 | RW | RW | DEBUG1_CONFIG_ACT: Enable clock-gates for debug trace latches | |
| Debug Machine-Pipe config 3 | ||||
|---|---|---|---|---|
| Addr: |
000000001101087C (SCOM) 00000000134100E0 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.MCP.MISC.DEBUG3_CONFIG | |||
| Constant(s): | ||||
| Comments: | Config register for machine-pipe fields into internal-group 4 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM1.MCP.MISC.DEBUG3_CONFIG_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:6 | RW | RW | DEBUG_CONFIG_MACH_BYTE0: Mux control for mach byte 0 | |
| 7:13 | RW | RW | DEBUG_CONFIG_MACH_BYTE1: Mux control for mach byte 1 | |
| 14:20 | RW | RW | DEBUG_CONFIG_MACH_BYTE2: Mux control for mach byte 2 | |
| 21:27 | RW | RW | DEBUG_CONFIG_MACH_BYTE3: Mux control for mach byte 3 | |
| 28:34 | RW | RW | DEBUG_CONFIG_MACH_BYTE4: Mux control for mach byte 4 | |
| 35:41 | RW | RW | DEBUG_CONFIG_MACH_BYTE5: Mux control for mach byte 5 | |
| 42:48 | RW | RW | DEBUG_CONFIG_MACH_BYTE6: Mux control for mach byte 6 | |
| 49:55 | RW | RW | DEBUG_CONFIG_MACH_BYTE7: Mux control for mach byte 7 | |
| 56:62 | RW | RW | DEBUG_CONFIG_MACH_BYTE8: Mux control for mach byte 8 | |
| 63 | RW | RW | DEBUG_CONFIG_MACH_ACT: Clock-gate enable for mach byte latches | |
| Debug Machine-Pipe config 4 | ||||
|---|---|---|---|---|
| Addr: |
000000001101087D (SCOM) 00000000134100E8 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.MCP.MISC.DEBUG4_CONFIG | |||
| Constant(s): | ||||
| Comments: | Config register for machine-pipe fields into internal-group 4 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:51 | PAU3.CS.SM1.MCP.MISC.DEBUG4_CONFIG_Q_0_INST.LATC.L2(0:51) [0000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:6 | RW | RW | DEBUG_CONFIG_MACH_BYTE9: Mux control for mach byte 9 | |
| 7:13 | RW | RW | DEBUG_CONFIG_MACH_BYTE10: Mux control for mach byte 10 | |
| 14:20 | RW | RW | DEBUG_CONFIG_MACH_BYTE11: Mux control for mach byte 11 | |
| 21:27 | RW | RW | DEBUG_CONFIG_MACH_BYTE12: Mux control for mach byte 12 | |
| 28:34 | RW | RW | DEBUG_CONFIG_MACH_BYTE13: Mux control for mach byte 13 | |
| 35:41 | RW | RW | DEBUG_CONFIG_MACH_BYTE14: Mux control for mach byte 14 | |
| 42:48 | RW | RW | DEBUG_CONFIG_MACH_BYTE15: Mux control for mach byte 15 | |
| 49:51 | RW | RW | DEBUG_CONFIG_MACH_RESERVED1: reserved | |
| 52:63 | RO | RO | constant=0b000000000000 | |
| CQ_SM Misc Config register #2 | ||||
|---|---|---|---|---|
| Addr: |
000000001101087E (SCOM) 00000000134100F0 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.MCP.MISC.CONFIG2 | |||
| Constant(s): | ||||
| Comments: | Misc config register Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM1.MCP.MISC.CONFIG2_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:11 | RW | RW | CONFIG_MCP_FIR_TO_INHIBIT_MASK: Mask of FIR bits that should force inhibit-all Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 12 | RW | RW | CONFIG_BRK0_FENCE_TO_INHIBIT_MASK: 0/1 = brick-0 fence operates normally / brick-0 fence inhibits everything Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 13 | RW | RW | CONFIG_BRK1_FENCE_TO_INHIBIT_MASK: 0/1 = brick-1 fence operates normally / brick-1 fence inhibits everything Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 14 | RW | RW | CONFIG_BRK2_FENCE_TO_INHIBIT_MASK: 0/1 = brick-2 fence operates normally / brick-2 fence inhibits everything Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 15 | RW | RW | CONFIG_BRK3_FENCE_TO_INHIBIT_MASK: 0/1 = brick-3 fence operates normally / brick-3 fence inhibits everything Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 16 | RW | RW | CONFIG_BRK4_FENCE_TO_INHIBIT_MASK: 0/1 = brick-4 fence operates normally / brick-4 fence inhibits everything Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 17 | RW | RW | CONFIG_ENABLE_PHASE1_DCBF: 0/1 = disable DCARM (PB V5 arch sec 9.6) protocol for dcbf,dcbfc,dcbfps (group 1) / enable dcarm protocol | |
| 18 | RW | RW | CONFIG_ENABLE_PHASE1_CLEAN: 0/1 = disable DCARM (PB V5 arch sec 9.6) protocol for dcbfstp (group 2) / enable dcarm protocol | |
| 19 | RW | RW | CONFIG_ENABLE_PHASE1_AMO: 0/1 = disable DCARM (PB V5 arch sec 9.6) protocol for armw*,armwf* (group 3) / enable dcarm protocol | |
| 20:31 | RW | RW | CONFIG_DCARM_TIMER: timeout value for DCARM phase-2 measured in PowerBus epsilon steps | |
| 32:33 | RW | RW | CONFIG_BRK0_EXT_MEM_TAGS: Even and Odd iSeries tag bits for brick-0 OCAPI 128B dma_w (Extended memory) | |
| 34:35 | RW | RW | CONFIG_BRK1_EXT_MEM_TAGS: Even and Odd iSeries tag bits for brick-1 OCAPI 128B dma_w (Extended memory) | |
| 36:37 | RW | RW | CONFIG_BRK2_EXT_MEM_TAGS: Even and Odd iSeries tag bits for brick-2 OCAPI 128B dma_w (Extended memory) | |
| 38:39 | RW | RW | CONFIG_BRK3_EXT_MEM_TAGS: Even and Odd iSeries tag bits for brick-3 OCAPI 128B dma_w (Extended memory) | |
| 40:41 | RW | RW | CONFIG_BRK4_EXT_MEM_TAGS: Even and Odd iSeries tag bits for brick-4 OCAPI 128B dma_w (Extended memory) | |
| 42 | RW | RW | CONFIG_PB_TO_OC_FASTPATH_MASTER_ENABLE: 0/1 = disable sending OC read request at RCmd / enable sending early OC read request before CResp | |
| 43 | RW | RW | CONFIG_PB_TO_OC_FASTPATH_ENABLE_READ: 0/1 = disable sending fastpath oc read for rd_go_s, rd_go_m, rd_larx / enable fastpath. | |
| 44 | RW | RW | CONFIG_PB_TO_OC_FASTPATH_ENABLE_PREF: 0/1 = disable sending fastpath oc read for pref_go_s, pref_go_m / enable fastpath. | |
| 45 | RW | RW | CONFIG_PB_TO_OC_FASTPATH_ENABLE_DMA: 0/1 = disable sending fastpath oc read for cl_dma_rd, cl_rd_nc / enable fastpath. | |
| 46 | RW | RW | CONFIG_PB_TO_OC_FASTPATH_ENABLE_RWITM: 0/1 = disable sending fastpath oc read for rwitm, rwitm_stwx / enable fastpath. | |
| 47 | RW | RW | CONFIG_PB_TO_OC_FASTPATH_ENABLE_CI: 0/1 = disable sending fastpath oc read for ci_pr_rd / enable fastpath. | |
| 48 | RW | RW | CONFIG_PB_TO_OC_FASTPATH_REQUIRE_QOS_1: 0/1 = for fastpath oc reads, don't-care the q (QoS) bit in reads / require the q bit to be '1' if it exists. | |
| 49 | RW | RW | CONFIG_PB_TO_OC_FASTPATH_REQUIRE_HINT_0: 0/1 = for fastpath oc reads, don't-care the h (hint) bit in reads / require the h bit to be '0' if it exists. | |
| 50:51 | RW | RW | CONFIG_PB_TO_OC_FASTPATH_REQUIRE_CL: for fastpath oc reads, require the cl0/cl1 field (if it exists) to be >= this value. | |
| 52 | RW | RW | CONFIG_PB_TO_OC_FASTPATH_REQUIRE_LD_PR_1: 0/1 = for fastpath oc reads, don't-care the ld_pr (load promote) bit in reads / require the ld_pr bit to be '1' if it exists. | |
| 53 | RW | RW | CONFIG_PB_TO_OC_FASTPATH_REQUIRE_RXO_EMPTY: 0/1 = for fastpath oc reads, don't require the RXO queue to be empty / require the RXO request-out queue to be empty | |
| 54 | RW | RW | CONFIG_DISABLE_HW551717_PTLA_TO_UCI: 0/1 = enable swapping pr_wr_mem_ptla_uco to pr_wr_mem_ptla_uci / disable fix | |
| 55 | RW | RW | CONFIG_DISABLE_HW552185_BKRETRY_TO_RMA: 0/1 = enable using COLL_RMA in place of bkretry / disable fix | |
| 56 | RW | RW | CONFIG_ENABLE_HW549830_MI_RETRY_NON_CP: 0/1 = disable hw549830 fix / enable retrying non-cp commands back to requesting PAU when retried on the PowerBus. | |
| 57:60 | RW | RW | CONFIG_HW549830_MI_RETRY_THRESH: Number of retries on the PowerBus before retrying the non-cp command back to the source PAU. | |
| 61:63 | RW | RW | CONFIG2_RESERVED: Reserved | |
| Timer Config Reg 2 | ||||
|---|---|---|---|---|
| Addr: |
000000001101087F (SCOM) 00000000134100F8 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.MCP.MISC.XTIMER2_CONFIG | |||
| Constant(s): | ||||
| Comments: | Timer Configuration Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:11 | PAU3.CS.SM1.MCP.MISC.XTIMER2_CONFIG_Q_0_INST.LATC.L2(0:11) [000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:5 | RW | RW | CONFIG_INH2_TICK: Rate for SM-Inhibit timer tick 2 (default 63=off) | |
| 6:11 | RW | RW | CONFIG_INH3_TICK: Rate for SM-Inhibit timer tick 3 (default 63=off) | |
| 12:63 | RO | RO | constant=0b0000000000000000000000000000000000000000000000000000 | |
| CQ_DIR Misc Config register #0 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010888 (SCOM) 0000000013410140 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.DIR.MISC.CONFIG0 | |||
| Constant(s): | ||||
| Comments: | Misc config register Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM1.DIR.MISC.CONFIG0Q.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:3 | RW | RW | CONFIG_HOST_TAG_SIZE: Configured host tag size (in bits) Must be less than or equal to the maximum host tag size supported by the AFUs connected to this PAU. 15 = maximum host tag size supported 6 = minimum host tag size supported 5..0 = reserved values, do not use | |
| 4:62 | RW | RW | CONFIG0_RESERVED: Reserved | |
| 63 | RW | RW | CONFIG_DEBUG0_ACT: Clock-gate enable for debug0 latches | |
| Perf Config Reg | ||||
|---|---|---|---|---|
| Addr: |
0000000011010889 (SCOM) 0000000013410148 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.DIR.MISC.PERF_CONFIG | |||
| Constant(s): | ||||
| Comments: | Performance Event selection | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM1.DIR.MISC.PERF_CONFIGQ.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:27 | RW | RW | PERF_CONFIG_RESERVED1: reserved | |
| 28:35 | RW | RW | PERF_CONFIG_EVENT0: Event 0 select 0: count nothing 1: count cycles others: reserved (count nothing) | |
| 36:43 | RW | RW | PERF_CONFIG_EVENT1: Event 1 select See Event 0 select for encodes | |
| 44:51 | RW | RW | PERF_CONFIG_EVENT2: Event 2 select See Event 0 select for encodes | |
| 52:59 | RW | RW | PERF_CONFIG_EVENT3: Event 3 select See Event 0 select for encodes | |
| 60:62 | RW | RW | PERF_CONFIG_RESERVED2: reserved | |
| 63 | RW | RW | PERF_CONFIG_ACT: Enable clock-gates for performance monitor latches | |
| Debug0 Config Reg | ||||
|---|---|---|---|---|
| Addr: |
000000001101088A (SCOM) 0000000013410150 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.DIR.MISC.DEBUG0_CONFIG | |||
| Constant(s): | ||||
| Comments: | Config register for trace-0 chain | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM1.DIR.MISC.DEBUG0_CONFIGQ.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:4 | RW | RW | DEBUG0_CONFIG_POD0: Mux control for byte 0 of trace-0 | |
| 5:9 | RW | RW | DEBUG0_CONFIG_POD1: Mux control for byte 1 of trace-0 | |
| 10:14 | RW | RW | DEBUG0_CONFIG_POD2: Mux control for byte 2 of trace-0 | |
| 15:19 | RW | RW | DEBUG0_CONFIG_POD3: Mux control for byte 3 of trace-0 | |
| 20:24 | RW | RW | DEBUG0_CONFIG_POD4: Mux control for byte 4 of trace-0 | |
| 25:29 | RW | RW | DEBUG0_CONFIG_POD5: Mux control for byte 5 of trace-0 | |
| 30:34 | RW | RW | DEBUG0_CONFIG_POD6: Mux control for byte 6 of trace-0 | |
| 35:39 | RW | RW | DEBUG0_CONFIG_POD7: Mux control for byte 7 of trace-0 | |
| 40:44 | RW | RW | DEBUG0_CONFIG_POD8: Mux control for byte 8 of trace-0 | |
| 45:49 | RW | RW | DEBUG0_CONFIG_POD9: Mux control for byte 9 of trace-0 | |
| 50:54 | RW | RW | DEBUG0_CONFIG_POD10: Mux control for byte 10 of trace-0 | |
| 55:62 | RW | RW | DEBUG0_CONFIG_RESERVED1: reserved | |
| 63 | RW | RW | DEBUG0_CONFIG_ACT: Enable clock-gates for debug trace latches | |
| Debug1 Config Reg | ||||
|---|---|---|---|---|
| Addr: |
000000001101088B (SCOM) 0000000013410158 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.DIR.MISC.DEBUG1_CONFIG | |||
| Constant(s): | ||||
| Comments: | Config register for trace-1 chain | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM1.DIR.MISC.DEBUG1_CONFIGQ.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:4 | RW | RW | DEBUG1_CONFIG_POD0: Mux control for byte 0 of trace-1 | |
| 5:9 | RW | RW | DEBUG1_CONFIG_POD1: Mux control for byte 1 of trace-1 | |
| 10:14 | RW | RW | DEBUG1_CONFIG_POD2: Mux control for byte 2 of trace-1 | |
| 15:19 | RW | RW | DEBUG1_CONFIG_POD3: Mux control for byte 3 of trace-1 | |
| 20:24 | RW | RW | DEBUG1_CONFIG_POD4: Mux control for byte 4 of trace-1 | |
| 25:29 | RW | RW | DEBUG1_CONFIG_POD5: Mux control for byte 5 of trace-1 | |
| 30:34 | RW | RW | DEBUG1_CONFIG_POD6: Mux control for byte 6 of trace-1 | |
| 35:39 | RW | RW | DEBUG1_CONFIG_POD7: Mux control for byte 7 of trace-1 | |
| 40:44 | RW | RW | DEBUG1_CONFIG_POD8: Mux control for byte 8 of trace-1 | |
| 45:49 | RW | RW | DEBUG1_CONFIG_POD9: Mux control for byte 9 of trace-1 | |
| 50:54 | RW | RW | DEBUG1_CONFIG_POD10: Mux control for byte 10 of trace-1 | |
| 55:62 | RW | RW | DEBUG1_CONFIG_RESERVED1: reserved | |
| 63 | RW | RW | DEBUG1_CONFIG_ACT: Enable clock-gates for debug trace latches | |
| SCOM L2 Data Reg | ||||
|---|---|---|---|---|
| Addr: |
000000001101088C (SCOM) 0000000013410160 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.DIR.MISC.SCOM_L2_DATA | |||
| Constant(s): | ||||
| Comments: | Read-only register for SCOM reads of the L2 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM1.DIR.MISC.SCOM_L2_DATAQ.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:63 | ROX | ROX | L2_SCOM_READ_DATA: Data read out of the L2 directory by the SCOM interface | |
| CQ_SM Misc Config register #0 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010890 (SCOM) 0000000013410180 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.SNP.MISC.CONFIG0 | |||
| Constant(s): | ||||
| Comments: | Misc config register Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM1.SNP.MISC.CONFIG0_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:1 | RW | RW | CONFIG_MA_RSNOOP_OPT_DCLAIM: 0 = partial-respond to dclaim to GPU Mem with lpc_ack 1 = (deprecated - do not use) partial-respond to dclaim to GPU Mem with lpc_ack+rty_lost_claim Nv: 2 = partial-respond to dclaim to GPU Mem with lpc_ack+rty_lpc+start pocket cache Oc: 2 = reserved (must not be set when config_ocapi_mode=1 for this stack) 3 = reserved | |
| 2 | RW | RW | CONFIG_ENABLE_PBUS: 0/1 = disable PAU PowerBus RCmd, PResp, and CResp interfaces / enable these interfaces Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 3 | RW | RW | CONFIG_BRAZOS_MODE: Reserved (was: brazos_mode 0/1 = non-brazos 4-group;2-chip mode / brazos 2-group;4-chip mode) | |
| 4 | RW | RW | CONFIG_PCKT_BLK_PRB: 0/1 = valid pocket-cache entries do not block probes / probes are blocked | |
| 5 | RW | RW | CONFIG_ADR_BAR_MODE: Reserved (was: PowerBus adr_bar: 0/1 = large-system-mode/small-system-mode) | |
| 6 | RW | RW | CONFIG_RESTRICT_CHIP_GROUP: Reserved (was: 0/1 = support all 16 groups and all 8 chips / restrict chip/group to 4/2 or 2/4) | |
| 7 | RW | RW | CONFIG_DISABLE_HW552185_BKRETRY_TO_RMA: 0/1 = 'or' hit_rma into hit_bk_rty_abbk and hit_pckt_win signals / disable fix | |
| 8 | RW | RW | CONFIG0_RESERVED3: reserved | |
| 9:15 | RW | RW | CONFIG_SNP_FIR_TO_INHIBIT_MASK: Mask of FIR bits that should force inhibit-all Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 16 | RW | RW | CONFIG_BRK0_FENCE_TO_INHIBIT_MASK: 0/1 = brick-0 fence operates normally / brick-0 fence inhibits everything Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 17 | RW | RW | CONFIG_BRK1_FENCE_TO_INHIBIT_MASK: 0/1 = brick-1 fence operates normally / brick-1 fence inhibits everything Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 18 | RW | RW | CONFIG_BRK2_FENCE_TO_INHIBIT_MASK: 0/1 = brick-2 fence operates normally / brick-2 fence inhibits everything Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 19 | RW | RW | CONFIG_BRK3_FENCE_TO_INHIBIT_MASK: 0/1 = brick-3 fence operates normally / brick-3 fence inhibits everything Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 20 | RW | RW | CONFIG_BRK4_FENCE_TO_INHIBIT_MASK: 0/1 = brick-4 fence operates normally / brick-4 fence inhibits everything Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 21 | RW | RW | CONFIG_MRBGP_TRACK_ALL: 0/1 = master-retry-backoff group-pump track only this stack's/all-this-chips retry responses | |
| 22 | RW | RW | CONFIG_MRBSP_TRACK_ALL: 0/1 = master-retry-backoff system-pump track only this stack's/all-this-chips retry responses | |
| 23 | RW | RW | CONFIG_MRBCP_TRACK_ALL: 0/1 = master-retry-backoff chip-pump track only this stack's/all-this-chips retry responses | |
| 24:30 | RW | RW | CONFIG_ADDR_EX_MASK_ENA: Reserved (was: Mask for address bits to ignore when checking for different-group/different-chip when calculating initial scope.) aka config_chip_address_extension_mask_enable(15:21) | |
| 31 | RW | RW | CONFIG_SINGLE_AFU_DUAL_BRICK: 0/1 = AFU(s) use only one brick / 1 AFU is using both bricks on this ramp (the only effect of this bit is to 'wildcard' brick numbers when processing XSL-castouts) | |
| 32 | RW | RW | CONFIG_BRK0_OCAPI_MODE: 0/1 = Disable OpenCAPI mode / enable OpenCAPI mode for brick 0 (mutually exclusive with config_brk0_nvlink_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 33 | RW | RW | CONFIG_BRK1_OCAPI_MODE: 0/1 = Disable OpenCAPI mode / enable OpenCAPI mode for brick 1 (mutually exclusive with config_brk1_nvlink_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 34 | RW | RW | CONFIG_BRK2_OCAPI_MODE: 0/1 = Disable OpenCAPI mode / enable OpenCAPI mode for brick 2 (mutually exclusive with config_brk2_nvlink_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 35 | RW | RW | CONFIG_BRK3_OCAPI_MODE: 0/1 = Disable OpenCAPI mode / enable OpenCAPI mode for brick 3 (mutually exclusive with config_brk3_nvlink_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 36 | RW | RW | CONFIG_BRK4_OCAPI_MODE: 0/1 = Disable OpenCAPI mode / enable OpenCAPI mode for brick 4 (mutually exclusive with config_brk4_nvlink_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 37 | RW | RW | CONFIG_BRK0_NVLINK_MODE: 0/1 = Disable NVLink mode / enable NVLink mode for brick 0 (mutually exclusive with config_brk0_ocapi_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 38 | RW | RW | CONFIG_BRK1_NVLINK_MODE: 0/1 = Disable NVLink mode / enable NVLink mode for brick 1 (mutually exclusive with config_brk1_ocapi_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 39 | RW | RW | CONFIG_BRK2_NVLINK_MODE: 0/1 = Disable NVLink mode / enable NVLink mode for brick 2 (mutually exclusive with config_brk2_ocapi_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 40 | RW | RW | CONFIG_BRK3_NVLINK_MODE: 0/1 = Disable NVLink mode / enable NVLink mode for brick 3 (mutually exclusive with config_brk3_ocapi_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 41 | RW | RW | CONFIG_BRK4_NVLINK_MODE: 0/1 = Disable NVLink mode / enable NVLink mode for brick 4 (mutually exclusive with config_brk4_ocapi_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 42 | RW | RW | CONFIG_ENABLE_BLOCKING_RCMD_DIR: 0/1 = disable blocking RCmd dir lookups to give bandwidth to internal accesses / enable blocking | |
| 43 | RW | RW | CONFIG_DISABLE_DIR_POWERSAVE: 0/1 = allow clock-gating empty directory lookups to save power / disable clock-gating | |
| 44 | RW | RW | CONFIG_DISABLE_PRESP_POWERSAVE: 0/1 = allow clock-gating empty CAM+DIR PResps to save power / disable clock-gating | |
| 45 | RW | RW | CONFIG_ENABLE_BRK0_OCAPI_C2: 0/1 = disable receiving OCAPI C2 opcodes / enable receiving on brick 0 | |
| 46 | RW | RW | CONFIG_ENABLE_BRK1_OCAPI_C2: 0/1 = disable receiving OCAPI C2 opcodes / enable receiving on brick 1 | |
| 47 | RW | RW | CONFIG_ENABLE_BRK2_OCAPI_C2: 0/1 = disable receiving OCAPI C2 opcodes / enable receiving on brick 2 | |
| 48 | RW | RW | CONFIG_ENABLE_BRK3_OCAPI_C2: 0/1 = disable receiving OCAPI C2 opcodes / enable receiving on brick 3 | |
| 49 | RW | RW | CONFIG_ENABLE_BRK4_OCAPI_C2: 0/1 = disable receiving OCAPI C2 opcodes / enable receiving on brick 4 | |
| 50 | RW | RW | CONFIG_DISABLE_CAN_BY_CP: 0/1 = enable cancel-by-cp logic / disable cancel-by-cp logic | |
| 51 | RW | RW | CONFIG0_RESERVED1: reserved (was: chicken switch hw483005) | |
| 52 | RW | RW | CONFIG0_RESERVED2: reserved (was: chicken switch hw484205) | |
| 53 | RW | RW | CONFIG0_RESERVED4: reserved (was: chicken switch hw484205) | |
| 54 | RW | RW | CONFIG0_RESERVED5: reserved (was: chicken switch hw484205) | |
| 55 | RW | RW | CONFIG0_RESERVED6: reserved (was: chicken switch hw484099) | |
| 56 | RW | RW | CONFIG0_RESERVED7: reserved (was: chicken switch hw484668) | |
| 57 | RW | RW | CONFIG0_RESERVED8: reserved (was: chicken switch hw484695) | |
| 58 | RW | RW | CONFIG0_RESERVED9: reserved (was: chicken switch hw484972) | |
| 59 | RW | RW | CONFIG0_RESERVED10: reserved (was: chicken switch hw485798) | |
| 60 | RW | RW | CONFIG_DISABLE_CAN_BY_PROBE: 0/1 = enable cancel-by-probe logic / disable cancel-by-probe logic | |
| 61 | RW | RW | CONFIG_HANG_ON_ADDRESS_ERRORS: 0/1 = abort and continue on CResp=addr_error / hang state-machine on CResp=addr_error | |
| 62 | RW | RW | CONFIG_DISABLE_HW521165_SFE_BLOCKS_CASTOUT: 0/1 = enable hw521165 fix / disable and allow SFE to block castouts | |
| 63 | RW | RW | CONFIG_DISABLE_HW517982_PSNOOP_MISS_PRESP_NULL: 0/1 = enable hw517982 fix to force PResp=null for psnoop table miss / disable fix. | |
| CQ_SM Misc Config register #1 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010891 (SCOM) 0000000013410188 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.SNP.MISC.CONFIG1 | |||
| Constant(s): | ||||
| Comments: | Misc config register Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM1.SNP.MISC.CONFIG1_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:3 | RW | RW | CONFIG_SCALE_RPT_HANG_POLL: Scaling factor for rpt_hang.poll 0 = 1:1 PowerBus rpt_hang.polls received 1 = 1:2 PowerBus rpt_hang.polls received ... 15 = 1:16 PowerBus rpt_hang.polls received | |
| 4:7 | RW | RW | CONFIG_SCALE_RPT_HANG_DATA: Scaling factor for rpt_hang.data 0 = 1:1 PowerBus rpt_hang.datas received 1 = 1:2 PowerBus rpt_hang.datas received ... 15 = 1:16 PowerBus rpt_hang.datas received | |
| 8:11 | RW | RW | CONFIG_HOST_TAG_SIZE: Configured host tag size (in bits) Must be less than or equal to the maximum host tag size supported by the AFUs connected to this PAU. 15 = maximum host tag size supported 6 = minimum host tag size supported 5..0 = reserved values, do not use | |
| 12:15 | RW | RW | CONFIG_ARB_NONCRR_SAFETY: Safety valve for non-cresp/non-reqin events going down the arb pipe. after N+1 reqin events go through the arbiter while a non-crr event is waiting, reqin events are blocked to give non-crr events a chance. | |
| 16:18 | RW | RW | CONFIG_REPLAY_IP_LIMIT: Limit on number of replays in-progress in the snoop/directory pipe. Must not be set to zero | |
| 19 | RW | RW | CONFIG1_RESERVED1: Reserved | |
| 20:23 | RW | RW | CONFIG_BLOCK_FOR_REPLAY_TIME: Controls the # of cycles to count before forcing an opportunity for a 'replay' to access the directory 0 = 16 cycles 1 = 15 cycles ... 15 = 1 cycle | |
| 24:27 | RW | RW | CONFIG_BLOCK_FOR_DIRSCAN_TIME: Controls the # of cycles to count before forcing an opportunity for a directory-scan to access the directory 0 = 16 cycles 1 = 15 cycles ... 15 = 1 cycle | |
| 28:29 | RW | RW | CONFIG_THROT_ADDR_HASH: select the addr hash crc function used for PWR0/1/2 throttling | |
| 30 | RW | RW | CONFIG_DISABLE_HW510185_DIR_WALKER_REF_COUNT: 0/1 = enable hw510185 dir walker ref counts / disable and return to single-threaded evicts. | |
| 31 | RW | RW | CONFIG_ENABLE_OPENCAPI_NETWORKING: 0/1 = disable networking / enable OpenCAPI MI networking mode. | |
| 32 | RW | RW | CONFIG_NETWORKING_GVC_LOCATION: 0/1 = GVC in PowerBus RA(8:11) / GVC in PowerBus RA(20:23) | |
| 33 | RW | RW | CONFIG_TORUS_ENABLE_E_TO_A: 0/1 = Disable Torus from transferring VC-E into VC-A / Enable Torus to tranfer VC-E into VC-A. | |
| 34 | RW | RW | CONFIG_NETWORKING_SUPPRESS_CAM: 0/1 = Allow CAM results to retry networking RCmds / Disable CAM results for networking RCmds. | |
| 35 | RW | RW | CONFIG_DISABLE_HW532135_FENCE_SHARED_C2_ALC: 0/1 = enable shared state for c2-allocating requests when fenced / disable fix | |
| 36 | RW | RW | CONFIG_TORUS_ENABLE_VC_A: 0/1 = disable torus mode using VC-A (only use VC-E & VC-HP) / enable torus using VC-A | |
| 37 | RW | RW | CONFIG_TORUS_ENABLE_FAIRNESS: 0/1 = disable torus continuation vs new-insertion fairness / enable fairness mechanism | |
| 38:39 | RW | RW | CONFIG1_RESERVED2: Reserved | |
| 40:43 | RW | RW | CONFIG_BRK0_TORUS_NEW_INS_ACC_DEC: (brick 0) Amount to subtract (x4+3) from the fairness counter when a new-insertion is accepted. | |
| 44:47 | RW | RW | CONFIG_BRK0_TORUS_NEW_INS_REJ_INC: (brick 0) Amount to add to the fairness counter when a new-insertion is rejected and the counter is primed. | |
| 48:51 | RW | RW | CONFIG_BRK0_TORUS_CONT_ACC_INC: (brick 0) Amount to add to the fairness counter when a continuation is accepted in the forward-progress state. | |
| 52:55 | RW | RW | CONFIG_BRK1_TORUS_NEW_INS_ACC_DEC: (brick 1) Amount to subtract (x4+3) from the fairness counter when a new-insertion is accepted. | |
| 56:59 | RW | RW | CONFIG_BRK1_TORUS_NEW_INS_REJ_INC: (brick 1) Amount to add to the fairness counter when a new-insertion is rejected and the counter is primed. | |
| 60:63 | RW | RW | CONFIG_BRK1_TORUS_CONT_ACC_INC: (brick 1) Amount to add to the fairness counter when a continuation is accepted in the forward-progress state. | |
| GPU0-Memory BAR | ||||
|---|---|---|---|---|
| Addr: |
0000000011010892 (SCOM) 0000000013410190 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.SNP.MISC.GPU0_BAR | |||
| Constant(s): | ||||
| Comments: | BAR register defining GPU Mem addresses serviced by brick 0 connected to this stack. Note: This register should be set to the same value for each brick/stack. MDials have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:51 | PAU3.CS.SM1.SNP.MISC.GPU0_BAR_Q_0_INST.LATC.L2(0:51) [0000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_GPU0_BAR_ENABLE: Enable for this BAR (0=disabled, 1=enabled) for brick 0 | |
| 1:35 | RW | RW | CONFIG_GPU0_BAR_ADDR_MASK: BAR Address/Mask bits 1:35 for brick 0 In Small-BAR mode (see bit 36): 1:7 = Base_Addr(13:19) = 16T slice 8:21 = Base_Addr(20:33) = 1G address in slice 22:35 = Base_Mask(20:33) = 1G...16T BAR size. (Note: Mask limited to 1G...4T in Axone and P10 w/ GPU systems) In Large-BAR mode (see bit 36): 1 = '1' to match MemSel = addr(13:14) = 0b00 2 = '1' to match MemSel = addr(13:14) = 0b01 3 = '1' to match MemSel = addr(13:14) = 0b10 4:35 = Topology_Id_Mask(0:31) when chip_eq_group=0, TIM(0:31) bit 'i' corresponds to addr(15:19) = 'i' when chip_eq_group=1, TIM(0:31) bit 'i' corresponds to (addr(15:16) & addr(19:21)) = 'i' | |
| 36 | RW | RW | CONFIG_GPU0_BAR_SL_MODE: 0/1 = Small-BAR/Large-BAR Mode selector | |
| 37 | RW | RW | CONFIG_GPU0_BAR_4T_LIMIT: 0 = no limit, 16T slices can be used. 1 = limit slices to 4T. -> when chip_eq_group=0, addr(20:21) must match bar_4t_select -> when chip_eq_group=1, addr(17:18) must match bar_4t_select limit=1 is used in P10 systems w/ a GPU or in Axone systems | |
| 38:39 | RW | RW | CONFIG_GPU0_BAR_4T_SELECT: when bar_4t_limit=1 this field selects the value in addr(20:21) to match | |
| 40:43 | RW | RW | CONFIG_GPU0_BAR_MODE: Hash mode of the BAR for brick 0: if bar_extended_mode == 0: 0 = (single) match on all address in addr/size 1 = (dual.0) match if hashbits(7)=0 2 = (dual.1) match if hashbits(7)=1 3 = (triple.0) match if hashbits%3=0 4 = (triple.1) match if hashbits%3=1 5 = (triple.2) match if hashbits%3=2 6 = (quad.0) match if hashbits(6:7)=0 7 = (quad.1) match if hashbits(6:7)=1 8 = (quad.2) match if hashbits(6:7)=2 9 = (quad.3) match if hashbits(6:7)=3 10 = (six.0) match if hashbits%3=0 and hashbits(7)=0 11 = (six.1) match if hashbits%3=0 and hashbits(7)=1 12 = (six.2) match if hashbits%3=1 and hashbits(7)=0 13 = (six.3) match if hashbits%3=1 and hashbits(7)=1 14 = (six.4) match if hashbits%3=2 and hashbits(7)=0 15 = (six.5) match if hashbits%3=2 and hashbits(7)=1 if bar_extended_mode == 1: 0 = (oct.0) match if hashbits(5:7)=0 1 = (oct.1) match if hashbits(5:7)=1 2 = (oct.2) match if hashbits(5:7)=2 3 = (oct.3) match if hashbits(5:7)=3 4 = (oct.4) match if hashbits(5:7)=4 5 = (oct.5) match if hashbits(5:7)=5 6 = (oct.6) match if hashbits(5:7)=6 7 = (oct.7) match if hashbits(5:7)=7 others = reserved | |
| 44 | RW | RW | CONFIG_GPU0_BAR_GRANULE: Hash boundary for brick 0: 0 = hash on 512B boundary (hashbits(0:7)=addr(47:54)) 1 = hash on 1024B boundary (hashbits(0:7)=addr(46:53)) | |
| 45 | RW | RW | CONFIG_GPU0_BAR_POISON: on failed access return all ones 0/1 = with good ECC / with SUE ECC. | |
| 46 | RW | RW | CONFIG_GPU0_BAR_M2MODE: 0 = OpenCAPI AFU M1 mode / 1 = OpenCAPI AFU M2 mode Has no effect when in NVLink mode | |
| 47 | RW | RW | CONFIG_GPU0_BAR_PA_IGNORE_MODE: Set to '1' for RA-to-PA conversion to ignore the mode field | |
| 48 | RW | RW | CONFIG_GPU0_BAR_SECURE_A12: P10 Only: this specifies the addr(12) value to match for this BAR. Can only be set to one in P10 and only when SMF_CONFIG=0b11. | |
| 49 | RW | RW | CONFIG_GPU0_BAR_CHIP_EQ_GROUP: Axone Only: this specifies that the system is in chip=group mode. This bit should only be set when sl_mode=1 and 4t_limit=1. 0/1 = TIM(0:31) applies to addr(15:19) / TIM(0:31) applies to (addr(15:16) & addr(19:21)). | |
| 50 | RW | RW | CONFIG_GPU0_BAR_EXTENDED_MODE: 0/1 = bar_mode selects 1,2,3,4,6 way hashing / bar_mode selects 8-way hashing | |
| 51 | RW | RW | CONFIG_GPU0_BAR_RESERVED: reserved | |
| 52:63 | RO | RO | constant=0b000000000000 | |
| GPU1-Memory BAR | ||||
|---|---|---|---|---|
| Addr: |
0000000011010893 (SCOM) 0000000013410198 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.SNP.MISC.GPU1_BAR | |||
| Constant(s): | ||||
| Comments: | BAR register defining GPU Mem addresses serviced by brick 1 connected to this stack. Note: This register should be set to the same value for each brick/stack. MDials have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:51 | PAU3.CS.SM1.SNP.MISC.GPU1_BAR_Q_0_INST.LATC.L2(0:51) [0000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_GPU1_BAR_ENABLE: Enable for this BAR (0=disabled, 1=enabled) for brick 1 | |
| 1:35 | RW | RW | CONFIG_GPU1_BAR_ADDR_MASK: BAR Address/Mask bits 1:35 for brick 1 In Small-BAR mode (see bit 36): 1:7 = Base_Addr(13:19) = 16T slice 8:21 = Base_Addr(20:33) = 1G address in slice 22:35 = Base_Mask(20:33) = 1G...16T BAR size. (Note: Mask limited to 1G...4T in Axone and P10 w/ GPU systems) In Large-BAR mode (see bit 36): 1 = '1' to match MemSel = addr(13:14) = 0b00 2 = '1' to match MemSel = addr(13:14) = 0b01 3 = '1' to match MemSel = addr(13:14) = 0b10 4:35 = Topology_Id_Mask(0:31) when chip_eq_group=0, TIM(0:31) bit 'i' corresponds to addr(15:19) = 'i' when chip_eq_group=1, TIM(0:31) bit 'i' corresponds to (addr(15:16) & addr(19:21)) = 'i' | |
| 36 | RW | RW | CONFIG_GPU1_BAR_SL_MODE: 0/1 = Small-BAR/Large-BAR Mode selector | |
| 37 | RW | RW | CONFIG_GPU1_BAR_4T_LIMIT: 0 = no limit, 16T slices can be used. 1 = limit slices to 4T. -> when chip_eq_group=0, addr(20:21) must match bar_4t_select -> when chip_eq_group=1, addr(17:18) must match bar_4t_select limit=1 is used in P10 systems w/ a GPU or in Axone systems | |
| 38:39 | RW | RW | CONFIG_GPU1_BAR_4T_SELECT: when bar_4t_limit=1 this field selects the value in addr(20:21) to match | |
| 40:43 | RW | RW | CONFIG_GPU1_BAR_MODE: Hash mode of the BAR for brick 1: if bar_extended_mode == 0: 0 = (single) match on all address in addr/size 1 = (dual.0) match if hashbits(7)=0 2 = (dual.1) match if hashbits(7)=1 3 = (triple.0) match if hashbits%3=0 4 = (triple.1) match if hashbits%3=1 5 = (triple.2) match if hashbits%3=2 6 = (quad.0) match if hashbits(6:7)=0 7 = (quad.1) match if hashbits(6:7)=1 8 = (quad.2) match if hashbits(6:7)=2 9 = (quad.3) match if hashbits(6:7)=3 10 = (six.0) match if hashbits%3=0 and hashbits(7)=0 11 = (six.1) match if hashbits%3=0 and hashbits(7)=1 12 = (six.2) match if hashbits%3=1 and hashbits(7)=0 13 = (six.3) match if hashbits%3=1 and hashbits(7)=1 14 = (six.4) match if hashbits%3=2 and hashbits(7)=0 15 = (six.5) match if hashbits%3=2 and hashbits(7)=1 if bar_extended_mode == 1: 0 = (oct.0) match if hashbits(5:7)=0 1 = (oct.1) match if hashbits(5:7)=1 2 = (oct.2) match if hashbits(5:7)=2 3 = (oct.3) match if hashbits(5:7)=3 4 = (oct.4) match if hashbits(5:7)=4 5 = (oct.5) match if hashbits(5:7)=5 6 = (oct.6) match if hashbits(5:7)=6 7 = (oct.7) match if hashbits(5:7)=7 others = reserved | |
| 44 | RW | RW | CONFIG_GPU1_BAR_GRANULE: Hash boundary for brick 1: 0 = hash on 512B boundary (hashbits(0:7)=addr(47:54)) 1 = hash on 1024B boundary (hashbits(0:7)=addr(46:53)) | |
| 45 | RW | RW | CONFIG_GPU1_BAR_POISON: on failed access return all ones 0/1 = with good ECC / with SUE ECC. | |
| 46 | RW | RW | CONFIG_GPU1_BAR_M2MODE: 0 = OpenCAPI AFU M1 mode / 1 = OpenCAPI AFU M2 mode Has no effect when in NVLink mode | |
| 47 | RW | RW | CONFIG_GPU1_BAR_PA_IGNORE_MODE: Set to '1' for RA-to-PA conversion to ignore the mode field | |
| 48 | RW | RW | CONFIG_GPU1_BAR_SECURE_A12: P10 Only: this specifies the addr(12) value to match for this BAR. Can only be set to one in P10 and only when SMF_CONFIG=0b11. | |
| 49 | RW | RW | CONFIG_GPU1_BAR_CHIP_EQ_GROUP: Axone Only: this specifies that the system is in chip=group mode. This bit should only be set when sl_mode=1 and 4t_limit=1. 0/1 = TIM(0:31) applies to addr(15:19) / TIM(0:31) applies to (addr(15:16) & addr(19:21)). | |
| 50 | RW | RW | CONFIG_GPU1_BAR_EXTENDED_MODE: 0/1 = bar_mode selects 1,2,3,4,6 way hashing / bar_mode selects 8-way hashing | |
| 51 | RW | RW | CONFIG_GPU1_BAR_RESERVED: reserved | |
| 52:63 | RO | RO | constant=0b000000000000 | |
| GPU2-Memory BAR | ||||
|---|---|---|---|---|
| Addr: |
0000000011010894 (SCOM) 00000000134101A0 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.SNP.MISC.GPU2_BAR | |||
| Constant(s): | ||||
| Comments: | BAR register defining GPU Mem addresses serviced by brick 2 connected to this stack. Note: This register should be set to the same value for each brick/stack. MDials have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:51 | PAU3.CS.SM1.SNP.MISC.GPU2_BAR_Q_0_INST.LATC.L2(0:51) [0000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_GPU2_BAR_ENABLE: Enable for this BAR (0=disabled, 1=enabled) for brick 2 | |
| 1:35 | RW | RW | CONFIG_GPU2_BAR_ADDR_MASK: BAR Address/Mask bits 1:35 for brick 2 In Small-BAR mode (see bit 36): 1:7 = Base_Addr(13:19) = 16T slice 8:21 = Base_Addr(20:33) = 1G address in slice 22:35 = Base_Mask(20:33) = 1G...16T BAR size. (Note: Mask limited to 1G...4T in Axone and P10 w/ GPU systems) In Large-BAR mode (see bit 36): 1 = '1' to match MemSel = addr(13:14) = 0b00 2 = '1' to match MemSel = addr(13:14) = 0b01 3 = '1' to match MemSel = addr(13:14) = 0b10 4:35 = Topology_Id_Mask(0:31) when chip_eq_group=0, TIM(0:31) bit 'i' corresponds to addr(15:19) = 'i' when chip_eq_group=1, TIM(0:31) bit 'i' corresponds to (addr(15:16) & addr(19:21)) = 'i' | |
| 36 | RW | RW | CONFIG_GPU2_BAR_SL_MODE: 0/1 = Small-BAR/Large-BAR Mode selector | |
| 37 | RW | RW | CONFIG_GPU2_BAR_4T_LIMIT: 0 = no limit, 16T slices can be used. 1 = limit slices to 4T. -> when chip_eq_group=0, addr(20:21) must match bar_4t_select -> when chip_eq_group=1, addr(17:18) must match bar_4t_select limit=1 is used in P10 systems w/ a GPU or in Axone systems | |
| 38:39 | RW | RW | CONFIG_GPU2_BAR_4T_SELECT: when bar_4t_limit=1 this field selects the value in addr(20:21) to match | |
| 40:43 | RW | RW | CONFIG_GPU2_BAR_MODE: Hash mode of the BAR for brick 2: if bar_extended_mode == 0: 0 = (single) match on all address in addr/size 1 = (dual.0) match if hashbits(7)=0 2 = (dual.1) match if hashbits(7)=1 3 = (triple.0) match if hashbits%3=0 4 = (triple.1) match if hashbits%3=1 5 = (triple.2) match if hashbits%3=2 6 = (quad.0) match if hashbits(6:7)=0 7 = (quad.1) match if hashbits(6:7)=1 8 = (quad.2) match if hashbits(6:7)=2 9 = (quad.3) match if hashbits(6:7)=3 10 = (six.0) match if hashbits%3=0 and hashbits(7)=0 11 = (six.1) match if hashbits%3=0 and hashbits(7)=1 12 = (six.2) match if hashbits%3=1 and hashbits(7)=0 13 = (six.3) match if hashbits%3=1 and hashbits(7)=1 14 = (six.4) match if hashbits%3=2 and hashbits(7)=0 15 = (six.5) match if hashbits%3=2 and hashbits(7)=1 if bar_extended_mode == 1: 0 = (oct.0) match if hashbits(5:7)=0 1 = (oct.1) match if hashbits(5:7)=1 2 = (oct.2) match if hashbits(5:7)=2 3 = (oct.3) match if hashbits(5:7)=3 4 = (oct.4) match if hashbits(5:7)=4 5 = (oct.5) match if hashbits(5:7)=5 6 = (oct.6) match if hashbits(5:7)=6 7 = (oct.7) match if hashbits(5:7)=7 others = reserved | |
| 44 | RW | RW | CONFIG_GPU2_BAR_GRANULE: Hash boundary for brick 2: 0 = hash on 512B boundary (hashbits(0:7)=addr(47:54)) 1 = hash on 1024B boundary (hashbits(0:7)=addr(46:53)) | |
| 45 | RW | RW | CONFIG_GPU2_BAR_POISON: on failed access return all ones 0/1 = with good ECC / with SUE ECC. | |
| 46 | RW | RW | CONFIG_GPU2_BAR_M2MODE: 0 = OpenCAPI AFU M1 mode / 1 = OpenCAPI AFU M2 mode Has no effect when in NVLink mode | |
| 47 | RW | RW | CONFIG_GPU2_BAR_PA_IGNORE_MODE: Set to '1' for RA-to-PA conversion to ignore the mode field | |
| 48 | RW | RW | CONFIG_GPU2_BAR_SECURE_A12: P10 Only: this specifies the addr(12) value to match for this BAR. Can only be set to one in P10 and only when SMF_CONFIG=0b11. | |
| 49 | RW | RW | CONFIG_GPU2_BAR_CHIP_EQ_GROUP: Axone Only: this specifies that the system is in chip=group mode. This bit should only be set when sl_mode=1 and 4t_limit=1. 0/1 = TIM(0:31) applies to addr(15:19) / TIM(0:31) applies to (addr(15:16) & addr(19:21)). | |
| 50 | RW | RW | CONFIG_GPU2_BAR_EXTENDED_MODE: 0/1 = bar_mode selects 1,2,3,4,6 way hashing / bar_mode selects 8-way hashing | |
| 51 | RW | RW | CONFIG_GPU2_BAR_RESERVED: reserved | |
| 52:63 | RO | RO | constant=0b000000000000 | |
| GPU3-Memory BAR | ||||
|---|---|---|---|---|
| Addr: |
0000000011010895 (SCOM) 00000000134101A8 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.SNP.MISC.GPU3_BAR | |||
| Constant(s): | ||||
| Comments: | BAR register defining GPU Mem addresses serviced by brick 3 connected to this stack. Note: This register should be set to the same value for each brick/stack. MDials have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:51 | PAU3.CS.SM1.SNP.MISC.GPU3_BAR_Q_0_INST.LATC.L2(0:51) [0000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_GPU3_BAR_ENABLE: Enable for this BAR (0=disabled, 1=enabled) for brick 3 | |
| 1:35 | RW | RW | CONFIG_GPU3_BAR_ADDR_MASK: BAR Address/Mask bits 1:35 for brick 3 In Small-BAR mode (see bit 36): 1:7 = Base_Addr(13:19) = 16T slice 8:21 = Base_Addr(20:33) = 1G address in slice 22:35 = Base_Mask(20:33) = 1G...16T BAR size. (Note: Mask limited to 1G...4T in Axone and P10 w/ GPU systems) In Large-BAR mode (see bit 36): 1 = '1' to match MemSel = addr(13:14) = 0b00 2 = '1' to match MemSel = addr(13:14) = 0b01 3 = '1' to match MemSel = addr(13:14) = 0b10 4:35 = Topology_Id_Mask(0:31) when chip_eq_group=0, TIM(0:31) bit 'i' corresponds to addr(15:19) = 'i' when chip_eq_group=1, TIM(0:31) bit 'i' corresponds to (addr(15:16) & addr(19:21)) = 'i' | |
| 36 | RW | RW | CONFIG_GPU3_BAR_SL_MODE: 0/1 = Small-BAR/Large-BAR Mode selector | |
| 37 | RW | RW | CONFIG_GPU3_BAR_4T_LIMIT: 0 = no limit, 16T slices can be used. 1 = limit slices to 4T. -> when chip_eq_group=0, addr(20:21) must match bar_4t_select -> when chip_eq_group=1, addr(17:18) must match bar_4t_select limit=1 is used in P10 systems w/ a GPU or in Axone systems | |
| 38:39 | RW | RW | CONFIG_GPU3_BAR_4T_SELECT: when bar_4t_limit=1 this field selects the value in addr(20:21) to match | |
| 40:43 | RW | RW | CONFIG_GPU3_BAR_MODE: Hash mode of the BAR for brick 3: if bar_extended_mode == 0: 0 = (single) match on all address in addr/size 1 = (dual.0) match if hashbits(7)=0 2 = (dual.1) match if hashbits(7)=1 3 = (triple.0) match if hashbits%3=0 4 = (triple.1) match if hashbits%3=1 5 = (triple.2) match if hashbits%3=2 6 = (quad.0) match if hashbits(6:7)=0 7 = (quad.1) match if hashbits(6:7)=1 8 = (quad.2) match if hashbits(6:7)=2 9 = (quad.3) match if hashbits(6:7)=3 10 = (six.0) match if hashbits%3=0 and hashbits(7)=0 11 = (six.1) match if hashbits%3=0 and hashbits(7)=1 12 = (six.2) match if hashbits%3=1 and hashbits(7)=0 13 = (six.3) match if hashbits%3=1 and hashbits(7)=1 14 = (six.4) match if hashbits%3=2 and hashbits(7)=0 15 = (six.5) match if hashbits%3=2 and hashbits(7)=1 if bar_extended_mode == 1: 0 = (oct.0) match if hashbits(5:7)=0 1 = (oct.1) match if hashbits(5:7)=1 2 = (oct.2) match if hashbits(5:7)=2 3 = (oct.3) match if hashbits(5:7)=3 4 = (oct.4) match if hashbits(5:7)=4 5 = (oct.5) match if hashbits(5:7)=5 6 = (oct.6) match if hashbits(5:7)=6 7 = (oct.7) match if hashbits(5:7)=7 others = reserved | |
| 44 | RW | RW | CONFIG_GPU3_BAR_GRANULE: Hash boundary for brick 3: 0 = hash on 512B boundary (hashbits(0:7)=addr(47:54)) 1 = hash on 1024B boundary (hashbits(0:7)=addr(46:53)) | |
| 45 | RW | RW | CONFIG_GPU3_BAR_POISON: on failed access return all ones 0/1 = with good ECC / with SUE ECC. | |
| 46 | RW | RW | CONFIG_GPU3_BAR_M2MODE: 0 = OpenCAPI AFU M1 mode / 1 = OpenCAPI AFU M2 mode Has no effect when in NVLink mode | |
| 47 | RW | RW | CONFIG_GPU3_BAR_PA_IGNORE_MODE: Set to '1' for RA-to-PA conversion to ignore the mode field | |
| 48 | RW | RW | CONFIG_GPU3_BAR_SECURE_A12: P10 Only: this specifies the addr(12) value to match for this BAR. Can only be set to one in P10 and only when SMF_CONFIG=0b11. | |
| 49 | RW | RW | CONFIG_GPU3_BAR_CHIP_EQ_GROUP: Axone Only: this specifies that the system is in chip=group mode. This bit should only be set when sl_mode=1 and 4t_limit=1. 0/1 = TIM(0:31) applies to addr(15:19) / TIM(0:31) applies to (addr(15:16) & addr(19:21)). | |
| 50 | RW | RW | CONFIG_GPU3_BAR_EXTENDED_MODE: 0/1 = bar_mode selects 1,2,3,4,6 way hashing / bar_mode selects 8-way hashing | |
| 51 | RW | RW | CONFIG_GPU3_BAR_RESERVED: reserved | |
| 52:63 | RO | RO | constant=0b000000000000 | |
| GPU4-Memory BAR | ||||
|---|---|---|---|---|
| Addr: |
0000000011010896 (SCOM) 00000000134101B0 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.SNP.MISC.GPU4_BAR | |||
| Constant(s): | ||||
| Comments: | BAR register defining GPU Mem addresses serviced by brick 4 connected to this stack. Note: This register should be set to the same value for each brick/stack. MDials have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:51 | PAU3.CS.SM1.SNP.MISC.GPU4_BAR_Q_0_INST.LATC.L2(0:51) [0000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_GPU4_BAR_ENABLE: Enable for this BAR (0=disabled, 1=enabled) for brick 4 | |
| 1:35 | RW | RW | CONFIG_GPU4_BAR_ADDR_MASK: BAR Address/Mask bits 1:35 for brick 4 In Small-BAR mode (see bit 36): 1:7 = Base_Addr(13:19) = 16T slice 8:21 = Base_Addr(20:33) = 1G address in slice 22:35 = Base_Mask(20:33) = 1G...16T BAR size. (Note: Mask limited to 1G...4T in Axone and P10 w/ GPU systems) In Large-BAR mode (see bit 36): 1 = '1' to match MemSel = addr(13:14) = 0b00 2 = '1' to match MemSel = addr(13:14) = 0b01 3 = '1' to match MemSel = addr(13:14) = 0b10 4:35 = Topology_Id_Mask(0:31) when chip_eq_group=0, TIM(0:31) bit 'i' corresponds to addr(15:19) = 'i' when chip_eq_group=1, TIM(0:31) bit 'i' corresponds to (addr(15:16) & addr(19:21)) = 'i' | |
| 36 | RW | RW | CONFIG_GPU4_BAR_SL_MODE: 0/1 = Small-BAR/Large-BAR Mode selector | |
| 37 | RW | RW | CONFIG_GPU4_BAR_4T_LIMIT: 0 = no limit, 16T slices can be used. 1 = limit slices to 4T. -> when chip_eq_group=0, addr(20:21) must match bar_4t_select -> when chip_eq_group=1, addr(17:18) must match bar_4t_select limit=1 is used in P10 systems w/ a GPU or in Axone systems | |
| 38:39 | RW | RW | CONFIG_GPU4_BAR_4T_SELECT: when bar_4t_limit=1 this field selects the value in addr(20:21) to match | |
| 40:43 | RW | RW | CONFIG_GPU4_BAR_MODE: Hash mode of the BAR for brick 4: if bar_extended_mode == 0: 0 = (single) match on all address in addr/size 1 = (dual.0) match if hashbits(7)=0 2 = (dual.1) match if hashbits(7)=1 3 = (triple.0) match if hashbits%3=0 4 = (triple.1) match if hashbits%3=1 5 = (triple.2) match if hashbits%3=2 6 = (quad.0) match if hashbits(6:7)=0 7 = (quad.1) match if hashbits(6:7)=1 8 = (quad.2) match if hashbits(6:7)=2 9 = (quad.3) match if hashbits(6:7)=3 10 = (six.0) match if hashbits%3=0 and hashbits(7)=0 11 = (six.1) match if hashbits%3=0 and hashbits(7)=1 12 = (six.2) match if hashbits%3=1 and hashbits(7)=0 13 = (six.3) match if hashbits%3=1 and hashbits(7)=1 14 = (six.4) match if hashbits%3=2 and hashbits(7)=0 15 = (six.5) match if hashbits%3=2 and hashbits(7)=1 if bar_extended_mode == 1: 0 = (oct.0) match if hashbits(5:7)=0 1 = (oct.1) match if hashbits(5:7)=1 2 = (oct.2) match if hashbits(5:7)=2 3 = (oct.3) match if hashbits(5:7)=3 4 = (oct.4) match if hashbits(5:7)=4 5 = (oct.5) match if hashbits(5:7)=5 6 = (oct.6) match if hashbits(5:7)=6 7 = (oct.7) match if hashbits(5:7)=7 others = reserved | |
| 44 | RW | RW | CONFIG_GPU4_BAR_GRANULE: Hash boundary for brick 4: 0 = hash on 512B boundary (hashbits(0:7)=addr(47:54)) 1 = hash on 1024B boundary (hashbits(0:7)=addr(46:53)) | |
| 45 | RW | RW | CONFIG_GPU4_BAR_POISON: on failed access return all ones 0/1 = with good ECC / with SUE ECC. | |
| 46 | RW | RW | CONFIG_GPU4_BAR_M2MODE: 0 = OpenCAPI AFU M1 mode / 1 = OpenCAPI AFU M2 mode Has no effect when in NVLink mode | |
| 47 | RW | RW | CONFIG_GPU4_BAR_PA_IGNORE_MODE: Set to '1' for RA-to-PA conversion to ignore the mode field | |
| 48 | RW | RW | CONFIG_GPU4_BAR_SECURE_A12: P10 Only: this specifies the addr(12) value to match for this BAR. Can only be set to one in P10 and only when SMF_CONFIG=0b11. | |
| 49 | RW | RW | CONFIG_GPU4_BAR_CHIP_EQ_GROUP: Axone Only: this specifies that the system is in chip=group mode. This bit should only be set when sl_mode=1 and 4t_limit=1. 0/1 = TIM(0:31) applies to addr(15:19) / TIM(0:31) applies to (addr(15:16) & addr(19:21)). | |
| 50 | RW | RW | CONFIG_GPU4_BAR_EXTENDED_MODE: 0/1 = bar_mode selects 1,2,3,4,6 way hashing / bar_mode selects 8-way hashing | |
| 51 | RW | RW | CONFIG_GPU4_BAR_RESERVED: reserved | |
| 52:63 | RO | RO | constant=0b000000000000 | |
| NTL0/NDL0 MMIO BAR | ||||
|---|---|---|---|---|
| Addr: |
0000000011010897 (SCOM) 00000000134101B8 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.SNP.MISC.NDT0_BAR | |||
| Constant(s): | ||||
| Comments: | BAR register defining NDL/NTL MMIO (NVLink) or AFU MMIO (OpenCAPI) range for brick 0 connected to this stack Note: This register should be set to the same value for each brick/stack. MDials have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:43 | PAU3.CS.SM1.SNP.MISC.NDT0_BAR_Q_0_INST.LATC.L2(0:43) [00000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_NDT0_BAR_ENABLE: 0/1 = disable/enable BAR for brick 0 | |
| 1 | RW | RW | CONFIG_NDT0_BAR_SECURE_A12: P10 Only: this specifies the addr(12) value to match for this BAR. Can only be set to one in P10 and only when SMF_CONFIG=0b11. | |
| 2 | RW | RW | NDT0_RESERVED1: reserved | |
| 3:35 | RW | RW | CONFIG_NDT0_BAR_ADDR: 64K aligned address of BAR for brick 0's 64K range | |
| 36 | RW | RW | CONFIG_NDT0_BAR_POISON: on failed access return all ones 0/1 = with good ECC / with SUE ECC. | |
| 37:38 | RW | RW | NDT0_RESERVED2: reserved | |
| 39:43 | RW | RW | CONFIG_NDT0_BAR_SIZE: Size of BAR region. 0 = 64K 1 = 128K (NVLink must select this size) 2 = 256K ... 26 = 4T others = reserved | |
| 44:63 | RO | RO | constant=0b00000000000000000000 | |
| NTL1/NDL1 MMIO BAR | ||||
|---|---|---|---|---|
| Addr: |
0000000011010898 (SCOM) 00000000134101C0 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.SNP.MISC.NDT1_BAR | |||
| Constant(s): | ||||
| Comments: | BAR register defining NDL/NTL MMIO (NVLink) or AFU MMIO (OpenCAPI) range for brick 1 connected to this stack Note: This register should be set to the same value for each brick/stack. MDials have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:43 | PAU3.CS.SM1.SNP.MISC.NDT1_BAR_Q_0_INST.LATC.L2(0:43) [00000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_NDT1_BAR_ENABLE: 0/1 = disable/enable BAR for brick 1 | |
| 1 | RW | RW | CONFIG_NDT1_BAR_SECURE_A12: P10 Only: this specifies the addr(12) value to match for this BAR. Can only be set to one in P10 and only when SMF_CONFIG=0b11. | |
| 2 | RW | RW | NDT1_RESERVED1: reserved | |
| 3:35 | RW | RW | CONFIG_NDT1_BAR_ADDR: 64K aligned address of BAR for brick 1's 64K range | |
| 36 | RW | RW | CONFIG_NDT1_BAR_POISON: on failed access return all ones 0/1 = with good ECC / with SUE ECC. | |
| 37:38 | RW | RW | NDT1_RESERVED2: reserved | |
| 39:43 | RW | RW | CONFIG_NDT1_BAR_SIZE: Size of BAR region. 0 = 64K 1 = 128K (NVLink must select this size) 2 = 256K ... 26 = 4T others = reserved | |
| 44:63 | RO | RO | constant=0b00000000000000000000 | |
| NTL2/NDL2 MMIO BAR | ||||
|---|---|---|---|---|
| Addr: |
0000000011010899 (SCOM) 00000000134101C8 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.SNP.MISC.NDT2_BAR | |||
| Constant(s): | ||||
| Comments: | BAR register defining NDL/NTL MMIO (NVLink) or AFU MMIO (OpenCAPI) range for brick 2 connected to this stack Note: This register should be set to the same value for each brick/stack. MDials have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:43 | PAU3.CS.SM1.SNP.MISC.NDT2_BAR_Q_0_INST.LATC.L2(0:43) [00000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_NDT2_BAR_ENABLE: 0/1 = disable/enable BAR for brick 2 | |
| 1 | RW | RW | CONFIG_NDT2_BAR_SECURE_A12: P10 Only: this specifies the addr(12) value to match for this BAR. Can only be set to one in P10 and only when SMF_CONFIG=0b11. | |
| 2 | RW | RW | NDT2_RESERVED1: reserved | |
| 3:35 | RW | RW | CONFIG_NDT2_BAR_ADDR: 64K aligned address of BAR for brick 2's 64K range | |
| 36 | RW | RW | CONFIG_NDT2_BAR_POISON: on failed access return all ones 0/1 = with good ECC / with SUE ECC. | |
| 37:38 | RW | RW | NDT2_RESERVED2: reserved | |
| 39:43 | RW | RW | CONFIG_NDT2_BAR_SIZE: Size of BAR region. 0 = 64K 1 = 128K (NVLink must select this size) 2 = 256K ... 26 = 4T others = reserved | |
| 44:63 | RO | RO | constant=0b00000000000000000000 | |
| NTL3/NDL3 MMIO BAR | ||||
|---|---|---|---|---|
| Addr: |
000000001101089A (SCOM) 00000000134101D0 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.SNP.MISC.NDT3_BAR | |||
| Constant(s): | ||||
| Comments: | BAR register defining NDL/NTL MMIO (NVLink) or AFU MMIO (OpenCAPI) range for brick 3 connected to this stack Note: This register should be set to the same value for each brick/stack. MDials have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:43 | PAU3.CS.SM1.SNP.MISC.NDT3_BAR_Q_0_INST.LATC.L2(0:43) [00000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_NDT3_BAR_ENABLE: 0/1 = disable/enable BAR for brick 3 | |
| 1 | RW | RW | CONFIG_NDT3_BAR_SECURE_A12: P10 Only: this specifies the addr(12) value to match for this BAR. Can only be set to one in P10 and only when SMF_CONFIG=0b11. | |
| 2 | RW | RW | NDT3_RESERVED1: reserved | |
| 3:35 | RW | RW | CONFIG_NDT3_BAR_ADDR: 64K aligned address of BAR for brick 3's 64K range | |
| 36 | RW | RW | CONFIG_NDT3_BAR_POISON: on failed access return all ones 0/1 = with good ECC / with SUE ECC. | |
| 37:38 | RW | RW | NDT3_RESERVED2: reserved | |
| 39:43 | RW | RW | CONFIG_NDT3_BAR_SIZE: Size of BAR region. 0 = 64K 1 = 128K (NVLink must select this size) 2 = 256K ... 26 = 4T others = reserved | |
| 44:63 | RO | RO | constant=0b00000000000000000000 | |
| NTL4/NDL4 MMIO BAR | ||||
|---|---|---|---|---|
| Addr: |
000000001101089B (SCOM) 00000000134101D8 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.SNP.MISC.NDT4_BAR | |||
| Constant(s): | ||||
| Comments: | BAR register defining NDL/NTL MMIO (NVLink) or AFU MMIO (OpenCAPI) range for brick 4 connected to this stack Note: This register should be set to the same value for each brick/stack. MDials have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:43 | PAU3.CS.SM1.SNP.MISC.NDT4_BAR_Q_0_INST.LATC.L2(0:43) [00000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_NDT4_BAR_ENABLE: 0/1 = disable/enable BAR for brick 4 | |
| 1 | RW | RW | CONFIG_NDT4_BAR_SECURE_A12: P10 Only: this specifies the addr(12) value to match for this BAR. Can only be set to one in P10 and only when SMF_CONFIG=0b11. | |
| 2 | RW | RW | NDT4_RESERVED1: reserved | |
| 3:35 | RW | RW | CONFIG_NDT4_BAR_ADDR: 64K aligned address of BAR for brick 4's 64K range | |
| 36 | RW | RW | CONFIG_NDT4_BAR_POISON: on failed access return all ones 0/1 = with good ECC / with SUE ECC. | |
| 37:38 | RW | RW | NDT4_RESERVED2: reserved | |
| 39:43 | RW | RW | CONFIG_NDT4_BAR_SIZE: Size of BAR region. 0 = 64K 1 = 128K (NVLink must select this size) 2 = 256K ... 26 = 4T others = reserved | |
| 44:63 | RO | RO | constant=0b00000000000000000000 | |
| PAU MMIO BAR | ||||
|---|---|---|---|---|
| Addr: |
000000001101089C (SCOM) 00000000134101E0 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.SNP.MISC.PAUMMIO_BAR | |||
| Constant(s): | ||||
| Comments: | BAR register definingPAU MMIO range Note: This register should be set to the same value for each brick/stack. MDials have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:31 | PAU3.CS.SM1.SNP.MISC.PAUMMIO_BAR_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_PAUMMIO_BAR_ENABLE: 0/1 = disable/enable PAUMMIO_BAR | |
| 1 | RW | RW | CONFIG_PAUMMIO_BAR_SECURE_A12: P10 Only: this specifies the addr(12) value to match for this BAR. Can only be set to one in P10 and only when SMF_CONFIG=0b11. | |
| 2 | RW | RW | PAUMMIO_RESERVED1: reserved | |
| 3:27 | RW | RW | CONFIG_PAUMMIO_BAR_ADDR: 16M aligned address of this PAUMMIO_BAR's 16M range. Bits 15:39 of the RA | |
| 28:30 | RW | RW | PAUMMIO_RESERVED2: reserved | |
| 31 | RW | RW | CONFIG_PAUMMIO_BAR_POISON: On failed access return all ones 0/1 = with good ECC / with SUE ECC. | |
| 32:63 | RO | RO | constant=0b00000000000000000000000000000000 | |
| Generation-ID Registers MMIO BAR | ||||
|---|---|---|---|---|
| Addr: |
000000001101089D (SCOM) 00000000134101E8 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.SNP.MISC.GENID_BAR | |||
| Constant(s): | ||||
| Comments: | NVLink mode: BAR register defining Generation-ID registers for this stack/ramp OCAPI mode: BAR register defining Config space + Generation-ID registers registers for this stack/ramp Note: This register should be set to the same value for each brick/stack. MDials have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:35 | PAU3.CS.SM1.SNP.MISC.GENID_BAR_Q_0_INST.LATC.L2(0:35) [000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_GENID_BAR_ENABLE: 0/1 = disable/enable this BAR | |
| 1 | RW | RW | CONFIG_GENID_BAR_SECURE_A12: P10 Only: this specifies the addr(12) value to match for this BAR. Can only be set to one in P10 and only when SMF_CONFIG=0b11. | |
| 2 | RW | RW | GENID_RESERVED1: reserved | |
| 3:32 | RW | RW | CONFIG_GENID_BAR_ADDR: 512K aligned address +0K = Brick 0 Gen-Id Registers +64K = Brick 1 Gen-Id Registers +128K = Brick 2 Gen-Id Registers +192K = Brick 3 Gen-Id Registers +256K = Brick 4 Gen-Id Registers +320K = Bricks 0-4 Config Addr/Data registers for OCAPI links +384K = reserved +448K = reserved | |
| 33:34 | RW | RW | GENID_RESERVED2: reserved | |
| 35 | RW | RW | CONFIG_GENID_BAR_POISON: on failed access return all ones 0/1 = with good ECC / with SUE ECC. | |
| 36:63 | RO | RO | constant=0b0000000000000000000000000000 | |
| Relexed-Ordering Source 0 Config | ||||
|---|---|---|---|---|
| Addr: |
000000001101089E (SCOM) 00000000134101F0 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.SNP.MISC.CONFIG_RELAXED_SRC0 | |||
| Constant(s): | ||||
| Comments: | Configure relaxed-ordering source Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM1.SNP.MISC.CONFIG_RELAXED_SRC0_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:13 | RW | RW | CONFIG_RELAXED_SOURCE0_TAG: P10: Match against ('00' & ttag(0:11)). | |
| 14:27 | RW | RW | CONFIG_RELAXED_SOURCE0_TAGMASK: Mask on tag(0:13). 0=must-match, 1=don't-care. | |
| 28 | RW | RW | CONFIG_RELAXED_SOURCE0_MASK_PAU: P10: match ttag(7:9)=000,001,111 | |
| 29 | RW | RW | CONFIG_RELAXED_SOURCE0_MASK_PCIE: P10: reserved | |
| 30 | RW | RW | CONFIG_RELAXED_SOURCE0_MASK_L2L3: P10: reserved | |
| 31 | RW | RW | CONFIG_RELAXED_SOURCE0_RESERVED1: reserved | |
| 32:39 | RW | RW | CONFIG_RELAXED_SOURCE0_RDSTART: P10: ttag(12:19) start-of-read-tags value (first tag) | |
| 40:47 | RW | RW | CONFIG_RELAXED_SOURCE0_RDEND: P10: ttag(12:19) end-of-read-tags value (last tag) | |
| 48:55 | RW | RW | CONFIG_RELAXED_SOURCE0_WRSTART: P10: ttag(12:19) start-of-write-tags value (first tag) | |
| 56:63 | RW | RW | CONFIG_RELAXED_SOURCE0_WREND: P10: ttag(12:19) end-of-write-tags value (last tag) | |
| Relexed-Ordering Source 1 Config | ||||
|---|---|---|---|---|
| Addr: |
000000001101089F (SCOM) 00000000134101F8 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.SNP.MISC.CONFIG_RELAXED_SRC1 | |||
| Constant(s): | ||||
| Comments: | Configure relaxed-ordering source Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM1.SNP.MISC.CONFIG_RELAXED_SRC1_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:13 | RW | RW | CONFIG_RELAXED_SOURCE1_TAG: P10: Match against ('00' & ttag(0:11)). | |
| 14:27 | RW | RW | CONFIG_RELAXED_SOURCE1_TAGMASK: Mask on tag(0:13). 0=must-match, 1=don't-care. | |
| 28 | RW | RW | CONFIG_RELAXED_SOURCE1_MASK_PAU: P10: match ttag(7:9)=000,001,111 | |
| 29 | RW | RW | CONFIG_RELAXED_SOURCE1_MASK_PCIE: P10: reserved | |
| 30 | RW | RW | CONFIG_RELAXED_SOURCE1_MASK_L2L3: P10: reserved | |
| 31 | RW | RW | CONFIG_RELAXED_SOURCE1_RESERVED1: reserved | |
| 32:39 | RW | RW | CONFIG_RELAXED_SOURCE1_RDSTART: P10: ttag(12:19) start-of-read-tags value (first tag) | |
| 40:47 | RW | RW | CONFIG_RELAXED_SOURCE1_RDEND: P10: ttag(12:19) end-of-read-tags value (last tag) | |
| 48:55 | RW | RW | CONFIG_RELAXED_SOURCE1_WRSTART: P10: ttag(12:19) start-of-write-tags value (first tag) | |
| 56:63 | RW | RW | CONFIG_RELAXED_SOURCE1_WREND: P10: ttag(12:19) end-of-write-tags value (last tag) | |
| Relexed-Ordering Source 2 Config | ||||
|---|---|---|---|---|
| Addr: |
00000000110108A0 (SCOM) 0000000013410200 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.SNP.MISC.CONFIG_RELAXED_SRC2 | |||
| Constant(s): | ||||
| Comments: | Configure relaxed-ordering source Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM1.SNP.MISC.CONFIG_RELAXED_SRC2_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:13 | RW | RW | CONFIG_RELAXED_SOURCE2_TAG: P10: Match against ('00' & ttag(0:11)). | |
| 14:27 | RW | RW | CONFIG_RELAXED_SOURCE2_TAGMASK: Mask on tag(0:13). 0=must-match, 1=don't-care. | |
| 28 | RW | RW | CONFIG_RELAXED_SOURCE2_MASK_PAU: P10: match ttag(7:9)=000,001,111 | |
| 29 | RW | RW | CONFIG_RELAXED_SOURCE2_MASK_PCIE: P10: reserved | |
| 30 | RW | RW | CONFIG_RELAXED_SOURCE2_MASK_L2L3: P10: reserved | |
| 31 | RW | RW | CONFIG_RELAXED_SOURCE2_RESERVED1: reserved | |
| 32:39 | RW | RW | CONFIG_RELAXED_SOURCE2_RDSTART: P10: ttag(12:19) start-of-read-tags value (first tag) | |
| 40:47 | RW | RW | CONFIG_RELAXED_SOURCE2_RDEND: P10: ttag(12:19) end-of-read-tags value (last tag) | |
| 48:55 | RW | RW | CONFIG_RELAXED_SOURCE2_WRSTART: P10: ttag(12:19) start-of-write-tags value (first tag) | |
| 56:63 | RW | RW | CONFIG_RELAXED_SOURCE2_WREND: P10: ttag(12:19) end-of-write-tags value (last tag) | |
| Relexed-Ordering Source 3 Config | ||||
|---|---|---|---|---|
| Addr: |
00000000110108A1 (SCOM) 0000000013410208 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.SNP.MISC.CONFIG_RELAXED_SRC3 | |||
| Constant(s): | ||||
| Comments: | Configure relaxed-ordering source Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM1.SNP.MISC.CONFIG_RELAXED_SRC3_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:13 | RW | RW | CONFIG_RELAXED_SOURCE3_TAG: P10: Match against ('00' & ttag(0:11)). | |
| 14:27 | RW | RW | CONFIG_RELAXED_SOURCE3_TAGMASK: Mask on tag(0:13). 0=must-match, 1=don't-care. | |
| 28 | RW | RW | CONFIG_RELAXED_SOURCE3_MASK_PAU: P10: match ttag(7:9)=000,001,111 | |
| 29 | RW | RW | CONFIG_RELAXED_SOURCE3_MASK_PCIE: P10: reserved | |
| 30 | RW | RW | CONFIG_RELAXED_SOURCE3_MASK_L2L3: P10: reserved | |
| 31 | RW | RW | CONFIG_RELAXED_SOURCE3_RESERVED1: reserved | |
| 32:39 | RW | RW | CONFIG_RELAXED_SOURCE3_RDSTART: P10: ttag(12:19) start-of-read-tags value (first tag) | |
| 40:47 | RW | RW | CONFIG_RELAXED_SOURCE3_RDEND: P10: ttag(12:19) end-of-read-tags value (last tag) | |
| 48:55 | RW | RW | CONFIG_RELAXED_SOURCE3_WRSTART: P10: ttag(12:19) start-of-write-tags value (first tag) | |
| 56:63 | RW | RW | CONFIG_RELAXED_SOURCE3_WREND: P10: ttag(12:19) end-of-write-tags value (last tag) | |
| Relexed-Ordering Source 4 Config | ||||
|---|---|---|---|---|
| Addr: |
00000000110108A2 (SCOM) 0000000013410210 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.SNP.MISC.CONFIG_RELAXED_SRC4 | |||
| Constant(s): | ||||
| Comments: | Configure relaxed-ordering source Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM1.SNP.MISC.CONFIG_RELAXED_SRC4_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:13 | RW | RW | CONFIG_RELAXED_SOURCE4_TAG: P10: Match against ('00' & ttag(0:11)). | |
| 14:27 | RW | RW | CONFIG_RELAXED_SOURCE4_TAGMASK: Mask on tag(0:13). 0=must-match, 1=don't-care. | |
| 28 | RW | RW | CONFIG_RELAXED_SOURCE4_MASK_PAU: P10: match ttag(7:9)=000,001,111 | |
| 29 | RW | RW | CONFIG_RELAXED_SOURCE4_MASK_PCIE: P10: reserved | |
| 30 | RW | RW | CONFIG_RELAXED_SOURCE4_MASK_L2L3: P10: reserved | |
| 31 | RW | RW | CONFIG_RELAXED_SOURCE4_RESERVED1: reserved | |
| 32:39 | RW | RW | CONFIG_RELAXED_SOURCE4_RDSTART: P10: ttag(12:19) start-of-read-tags value (first tag) | |
| 40:47 | RW | RW | CONFIG_RELAXED_SOURCE4_RDEND: P10: ttag(12:19) end-of-read-tags value (last tag) | |
| 48:55 | RW | RW | CONFIG_RELAXED_SOURCE4_WRSTART: P10: ttag(12:19) start-of-write-tags value (first tag) | |
| 56:63 | RW | RW | CONFIG_RELAXED_SOURCE4_WREND: P10: ttag(12:19) end-of-write-tags value (last tag) | |
| Relexed-Ordering Source 5 Config | ||||
|---|---|---|---|---|
| Addr: |
00000000110108A3 (SCOM) 0000000013410218 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.SNP.MISC.CONFIG_RELAXED_SRC5 | |||
| Constant(s): | ||||
| Comments: | Configure relaxed-ordering source Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM1.SNP.MISC.CONFIG_RELAXED_SRC5_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:13 | RW | RW | CONFIG_RELAXED_SOURCE5_TAG: P10: Match against ('00' & ttag(0:11)). | |
| 14:27 | RW | RW | CONFIG_RELAXED_SOURCE5_TAGMASK: Mask on tag(0:13). 0=must-match, 1=don't-care. | |
| 28 | RW | RW | CONFIG_RELAXED_SOURCE5_MASK_PAU: P10: match ttag(7:9)=000,001,111 | |
| 29 | RW | RW | CONFIG_RELAXED_SOURCE5_MASK_PCIE: P10: reserved | |
| 30 | RW | RW | CONFIG_RELAXED_SOURCE5_MASK_L2L3: P10: reserved | |
| 31 | RW | RW | CONFIG_RELAXED_SOURCE5_RESERVED1: reserved | |
| 32:39 | RW | RW | CONFIG_RELAXED_SOURCE5_RDSTART: P10: ttag(12:19) start-of-read-tags value (first tag) | |
| 40:47 | RW | RW | CONFIG_RELAXED_SOURCE5_RDEND: P10: ttag(12:19) end-of-read-tags value (last tag) | |
| 48:55 | RW | RW | CONFIG_RELAXED_SOURCE5_WRSTART: P10: ttag(12:19) start-of-write-tags value (first tag) | |
| 56:63 | RW | RW | CONFIG_RELAXED_SOURCE5_WREND: P10: ttag(12:19) end-of-write-tags value (last tag) | |
| Relexed-Ordering Source 6 Config | ||||
|---|---|---|---|---|
| Addr: |
00000000110108A4 (SCOM) 0000000013410220 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.SNP.MISC.CONFIG_RELAXED_SRC6 | |||
| Constant(s): | ||||
| Comments: | Configure relaxed-ordering source Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM1.SNP.MISC.CONFIG_RELAXED_SRC6_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:13 | RW | RW | CONFIG_RELAXED_SOURCE6_TAG: P10: Match against ('00' & ttag(0:11)). | |
| 14:27 | RW | RW | CONFIG_RELAXED_SOURCE6_TAGMASK: Mask on tag(0:13). 0=must-match, 1=don't-care. | |
| 28 | RW | RW | CONFIG_RELAXED_SOURCE6_MASK_PAU: P10: match ttag(7:9)=000,001,111 | |
| 29 | RW | RW | CONFIG_RELAXED_SOURCE6_MASK_PCIE: P10: reserved | |
| 30 | RW | RW | CONFIG_RELAXED_SOURCE6_MASK_L2L3: P10: reserved | |
| 31 | RW | RW | CONFIG_RELAXED_SOURCE6_RESERVED1: reserved | |
| 32:39 | RW | RW | CONFIG_RELAXED_SOURCE6_RDSTART: P10: ttag(12:19) start-of-read-tags value (first tag) | |
| 40:47 | RW | RW | CONFIG_RELAXED_SOURCE6_RDEND: P10: ttag(12:19) end-of-read-tags value (last tag) | |
| 48:55 | RW | RW | CONFIG_RELAXED_SOURCE6_WRSTART: P10: ttag(12:19) start-of-write-tags value (first tag) | |
| 56:63 | RW | RW | CONFIG_RELAXED_SOURCE6_WREND: P10: ttag(12:19) end-of-write-tags value (last tag) | |
| Relexed-Ordering Source 7 Config | ||||
|---|---|---|---|---|
| Addr: |
00000000110108A5 (SCOM) 0000000013410228 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.SNP.MISC.CONFIG_RELAXED_SRC7 | |||
| Constant(s): | ||||
| Comments: | Configure relaxed-ordering source Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM1.SNP.MISC.CONFIG_RELAXED_SRC7_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:13 | RW | RW | CONFIG_RELAXED_SOURCE7_TAG: P10: Match against ('00' & ttag(0:11)). | |
| 14:27 | RW | RW | CONFIG_RELAXED_SOURCE7_TAGMASK: Mask on tag(0:13). 0=must-match, 1=don't-care. | |
| 28 | RW | RW | CONFIG_RELAXED_SOURCE7_MASK_PAU: P10: match ttag(7:9)=000,001,111 | |
| 29 | RW | RW | CONFIG_RELAXED_SOURCE7_MASK_PCIE: P10: reserved | |
| 30 | RW | RW | CONFIG_RELAXED_SOURCE7_MASK_L2L3: P10: reserved | |
| 31 | RW | RW | CONFIG_RELAXED_SOURCE7_RESERVED1: reserved | |
| 32:39 | RW | RW | CONFIG_RELAXED_SOURCE7_RDSTART: P10: ttag(12:19) start-of-read-tags value (first tag) | |
| 40:47 | RW | RW | CONFIG_RELAXED_SOURCE7_RDEND: P10: ttag(12:19) end-of-read-tags value (last tag) | |
| 48:55 | RW | RW | CONFIG_RELAXED_SOURCE7_WRSTART: P10: ttag(12:19) start-of-write-tags value (first tag) | |
| 56:63 | RW | RW | CONFIG_RELAXED_SOURCE7_WREND: P10: ttag(12:19) end-of-write-tags value (last tag) | |
| Relaxed-Ordering Config2 brick 0 | ||||
|---|---|---|---|---|
| Addr: |
00000000110108A6 (SCOM) 0000000013410230 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.SNP.MISC.CONFIG_RELAXED_BRK0 | |||
| Constant(s): | ||||
| Comments: | Configure relaxed-ordering Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM1.SNP.MISC.CONFIG_RELAXED_BRK0_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_RELAXED_BRK0_CMD_CL_DMA_W: enable relaxed ordering for (non-atomic write) cl_dma_w (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 1 | RW | RW | CONFIG_RELAXED_BRK0_CMD_CL_DMA_W_HP: Reserved. (was: enable relaxed ordering for (non-atomic write) cl_dma_w_hp (only valid for GPU and AFU-M2 memory)) | |
| 2 | RW | RW | CONFIG_RELAXED_BRK0_CMD_CL_DMA_INJ: enable relaxed ordering for (non-atomic write) cl_dma_inj (only valid for GPU and AFU-M2 memory) | |
| 3 | RW | RW | CONFIG_RELAXED_BRK0_CMD_PR_DMA_INJ: enable relaxed ordering for (non-atomic write) pr_dma_inj (only valid for GPU and AFU-M2 memory) | |
| 4 | RW | RW | CONFIG_RELAXED_BRK0_CMD_DMA_PR_W: enable relaxed ordering for (non-atomic write) dma_pr_w (only valid for GPU and AFU-M2 memory) | |
| 5 | RW | RW | CONFIG_RELAXED_BRK0_CMD_CL_RD_NC_F0: enable relaxed ordering for (non-atomic read) cl_rd_nc(F=0) (only valid for GPU and AFU-M2 memory) | |
| 6 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMW_CAS_IMAX_U: enable relaxed ordering for (atomic write) armw_cas_imax_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 7 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMW_CAS_IMAX_S: enable relaxed ordering for (atomic write) armw_cas_imax_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 8 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMW_CAS_IMIN_U: enable relaxed ordering for (atomic write) armw_cas_imin_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 9 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMW_CAS_IMIN_S: enable relaxed ordering for (atomic write) armw_cas_imin_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 10 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMW_ADD: enable relaxed ordering for (atomic write) armw_add (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 11 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMW_AND: enable relaxed ordering for (atomic write) armw_and (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 12 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMW_OR: enable relaxed ordering for (atomic write) armw_or (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 13 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMW_XOR: enable relaxed ordering for (atomic write) armw_xor (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 14 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMWF_CAS_IMAX_U: enable relaxed ordering for (atomic read) armwf_cas_imax_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 15 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMWF_CAS_IMAX_S: enable relaxed ordering for (atomic read) armwf_cas_imax_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 16 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMWF_CAS_IMIN_U: enable relaxed ordering for (atomic read) armwf_cas_imin_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 17 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMWF_CAS_IMIN_S: enable relaxed ordering for (atomic read) armwf_cas_imin_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 18 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMWF_ADD: enable relaxed ordering for (atomic read) armwf_add (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 19 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMWF_AND: enable relaxed ordering for (atomic read) armwf_and (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 20 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMWF_OR: enable relaxed ordering for (atomic read) armwf_or (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 21 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMWF_XOR: enable relaxed ordering for (atomic read) armwf_xor (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 22 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMWF_CAS_E: enable relaxed ordering for (atomic read) armwf_cas_e (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 23 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMWF_CAS_U: enable relaxed ordering for (atomic read) armwf_cas_u (only valid for OCAPI AFU-M1 or AFU-M2 memory) (errata HW367501 requires this bit to be 0 for GPU memory) | |
| 24 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMW_CAS_T: enable relaxed ordering for (atomic write) armw_cas_t (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 25 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMWF_CAS_NE: enable relaxed ordering for (atomic read) armwf_cas_ne (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 26 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMWF_INC_B: enable relaxed ordering for (atomic read) armwf_inc_b (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 27 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMWF_INC_E: enable relaxed ordering for (atomic read) armwf_inc_e (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 28 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMWF_DEC_B: enable relaxed ordering for (atomic read) armwf_dec_b (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 29:31 | RW | RW | CONFIG_RELAXED_BRK0_RESERVED1: reserved | |
| 32 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE0_WRENA: 0/1 = disable/enable relaxed source 0 for (non-atomic) write operations | |
| 33 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE0_RDENA: 0/1 = disable/enable relaxed source 0 for (non-atomic) read operations | |
| 34 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE0_AWENA: 0/1 = disable/enable relaxed source 0 for atomic (write) operations | |
| 35 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE0_ARENA: 0/1 = disable/enable relaxed source 0 for atomic (read) operations | |
| 36 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE1_WRENA: 0/1 = disable/enable relaxed source 1 for (non-atomic) write operations | |
| 37 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE1_RDENA: 0/1 = disable/enable relaxed source 1 for (non-atomic) read operations | |
| 38 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE1_AWENA: 0/1 = disable/enable relaxed source 1 for atomic (write) operations | |
| 39 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE1_ARENA: 0/1 = disable/enable relaxed source 1 for atomic (read) operations | |
| 40 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE2_WRENA: 0/1 = disable/enable relaxed source 2 for (non-atomic) write operations | |
| 41 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE2_RDENA: 0/1 = disable/enable relaxed source 2 for (non-atomic) read operations | |
| 42 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE2_AWENA: 0/1 = disable/enable relaxed source 2 for atomic (write) operations | |
| 43 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE2_ARENA: 0/1 = disable/enable relaxed source 2 for atomic (read) operations | |
| 44 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE3_WRENA: 0/1 = disable/enable relaxed source 3 for (non-atomic) write operations | |
| 45 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE3_RDENA: 0/1 = disable/enable relaxed source 3 for (non-atomic) read operations | |
| 46 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE3_AWENA: 0/1 = disable/enable relaxed source 3 for atomic (write) operations | |
| 47 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE3_ARENA: 0/1 = disable/enable relaxed source 3 for atomic (read) operations | |
| 48 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE4_WRENA: 0/1 = disable/enable relaxed source 4 for (non-atomic) write operations | |
| 49 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE4_RDENA: 0/1 = disable/enable relaxed source 4 for (non-atomic) read operations | |
| 50 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE4_AWENA: 0/1 = disable/enable relaxed source 4 for atomic (write) operations | |
| 51 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE4_ARENA: 0/1 = disable/enable relaxed source 4 for atomic (read) operations | |
| 52 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE5_WRENA: 0/1 = disable/enable relaxed source 5 for (non-atomic) write operations | |
| 53 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE5_RDENA: 0/1 = disable/enable relaxed source 5 for (non-atomic) read operations | |
| 54 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE5_AWENA: 0/1 = disable/enable relaxed source 5 for atomic (write) operations | |
| 55 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE5_ARENA: 0/1 = disable/enable relaxed source 5 for atomic (read) operations | |
| 56 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE6_WRENA: 0/1 = disable/enable relaxed source 6 for (non-atomic) write operations | |
| 57 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE6_RDENA: 0/1 = disable/enable relaxed source 6 for (non-atomic) read operations | |
| 58 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE6_AWENA: 0/1 = disable/enable relaxed source 6 for atomic (write) operations | |
| 59 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE6_ARENA: 0/1 = disable/enable relaxed source 6 for atomic (read) operations | |
| 60 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE7_WRENA: 0/1 = disable/enable relaxed source 7 for (non-atomic) write operations | |
| 61 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE7_RDENA: 0/1 = disable/enable relaxed source 7 for (non-atomic) read operations | |
| 62 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE7_AWENA: 0/1 = disable/enable relaxed source 7 for atomic (write) operations | |
| 63 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE7_ARENA: 0/1 = disable/enable relaxed source 7 for atomic (read) operations | |
| Relaxed-Ordering Config2 brick 1 | ||||
|---|---|---|---|---|
| Addr: |
00000000110108A7 (SCOM) 0000000013410238 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.SNP.MISC.CONFIG_RELAXED_BRK1 | |||
| Constant(s): | ||||
| Comments: | Configure relaxed-ordering Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM1.SNP.MISC.CONFIG_RELAXED_BRK1_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_RELAXED_BRK1_CMD_CL_DMA_W: enable relaxed ordering for (non-atomic write) cl_dma_w (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 1 | RW | RW | CONFIG_RELAXED_BRK1_CMD_CL_DMA_W_HP: Reserved. (was: enable relaxed ordering for (non-atomic write) cl_dma_w_hp (only valid for GPU and AFU-M2 memory)) | |
| 2 | RW | RW | CONFIG_RELAXED_BRK1_CMD_CL_DMA_INJ: enable relaxed ordering for (non-atomic write) cl_dma_inj (only valid for GPU and AFU-M2 memory) | |
| 3 | RW | RW | CONFIG_RELAXED_BRK1_CMD_PR_DMA_INJ: enable relaxed ordering for (non-atomic write) pr_dma_inj (only valid for GPU and AFU-M2 memory) | |
| 4 | RW | RW | CONFIG_RELAXED_BRK1_CMD_DMA_PR_W: enable relaxed ordering for (non-atomic write) dma_pr_w (only valid for GPU and AFU-M2 memory) | |
| 5 | RW | RW | CONFIG_RELAXED_BRK1_CMD_CL_RD_NC_F0: enable relaxed ordering for (non-atomic read) cl_rd_nc(F=0) (only valid for GPU and AFU-M2 memory) | |
| 6 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMW_CAS_IMAX_U: enable relaxed ordering for (atomic write) armw_cas_imax_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 7 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMW_CAS_IMAX_S: enable relaxed ordering for (atomic write) armw_cas_imax_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 8 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMW_CAS_IMIN_U: enable relaxed ordering for (atomic write) armw_cas_imin_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 9 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMW_CAS_IMIN_S: enable relaxed ordering for (atomic write) armw_cas_imin_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 10 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMW_ADD: enable relaxed ordering for (atomic write) armw_add (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 11 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMW_AND: enable relaxed ordering for (atomic write) armw_and (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 12 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMW_OR: enable relaxed ordering for (atomic write) armw_or (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 13 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMW_XOR: enable relaxed ordering for (atomic write) armw_xor (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 14 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMWF_CAS_IMAX_U: enable relaxed ordering for (atomic read) armwf_cas_imax_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 15 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMWF_CAS_IMAX_S: enable relaxed ordering for (atomic read) armwf_cas_imax_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 16 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMWF_CAS_IMIN_U: enable relaxed ordering for (atomic read) armwf_cas_imin_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 17 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMWF_CAS_IMIN_S: enable relaxed ordering for (atomic read) armwf_cas_imin_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 18 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMWF_ADD: enable relaxed ordering for (atomic read) armwf_add (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 19 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMWF_AND: enable relaxed ordering for (atomic read) armwf_and (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 20 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMWF_OR: enable relaxed ordering for (atomic read) armwf_or (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 21 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMWF_XOR: enable relaxed ordering for (atomic read) armwf_xor (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 22 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMWF_CAS_E: enable relaxed ordering for (atomic read) armwf_cas_e (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 23 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMWF_CAS_U: enable relaxed ordering for (atomic read) armwf_cas_u (only valid for OCAPI AFU-M1 or AFU-M2 memory) (errata HW367501 requires this bit to be 0 for GPU memory) | |
| 24 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMW_CAS_T: enable relaxed ordering for (atomic write) armw_cas_t (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 25 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMWF_CAS_NE: enable relaxed ordering for (atomic read) armwf_cas_ne (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 26 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMWF_INC_B: enable relaxed ordering for (atomic read) armwf_inc_b (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 27 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMWF_INC_E: enable relaxed ordering for (atomic read) armwf_inc_e (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 28 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMWF_DEC_B: enable relaxed ordering for (atomic read) armwf_dec_b (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 29:31 | RW | RW | CONFIG_RELAXED_BRK1_RESERVED1: reserved | |
| 32 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE0_WRENA: 0/1 = disable/enable relaxed source 0 for (non-atomic) write operations | |
| 33 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE0_RDENA: 0/1 = disable/enable relaxed source 0 for (non-atomic) read operations | |
| 34 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE0_AWENA: 0/1 = disable/enable relaxed source 0 for atomic (write) operations | |
| 35 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE0_ARENA: 0/1 = disable/enable relaxed source 0 for atomic (read) operations | |
| 36 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE1_WRENA: 0/1 = disable/enable relaxed source 1 for (non-atomic) write operations | |
| 37 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE1_RDENA: 0/1 = disable/enable relaxed source 1 for (non-atomic) read operations | |
| 38 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE1_AWENA: 0/1 = disable/enable relaxed source 1 for atomic (write) operations | |
| 39 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE1_ARENA: 0/1 = disable/enable relaxed source 1 for atomic (read) operations | |
| 40 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE2_WRENA: 0/1 = disable/enable relaxed source 2 for (non-atomic) write operations | |
| 41 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE2_RDENA: 0/1 = disable/enable relaxed source 2 for (non-atomic) read operations | |
| 42 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE2_AWENA: 0/1 = disable/enable relaxed source 2 for atomic (write) operations | |
| 43 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE2_ARENA: 0/1 = disable/enable relaxed source 2 for atomic (read) operations | |
| 44 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE3_WRENA: 0/1 = disable/enable relaxed source 3 for (non-atomic) write operations | |
| 45 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE3_RDENA: 0/1 = disable/enable relaxed source 3 for (non-atomic) read operations | |
| 46 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE3_AWENA: 0/1 = disable/enable relaxed source 3 for atomic (write) operations | |
| 47 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE3_ARENA: 0/1 = disable/enable relaxed source 3 for atomic (read) operations | |
| 48 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE4_WRENA: 0/1 = disable/enable relaxed source 4 for (non-atomic) write operations | |
| 49 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE4_RDENA: 0/1 = disable/enable relaxed source 4 for (non-atomic) read operations | |
| 50 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE4_AWENA: 0/1 = disable/enable relaxed source 4 for atomic (write) operations | |
| 51 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE4_ARENA: 0/1 = disable/enable relaxed source 4 for atomic (read) operations | |
| 52 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE5_WRENA: 0/1 = disable/enable relaxed source 5 for (non-atomic) write operations | |
| 53 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE5_RDENA: 0/1 = disable/enable relaxed source 5 for (non-atomic) read operations | |
| 54 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE5_AWENA: 0/1 = disable/enable relaxed source 5 for atomic (write) operations | |
| 55 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE5_ARENA: 0/1 = disable/enable relaxed source 5 for atomic (read) operations | |
| 56 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE6_WRENA: 0/1 = disable/enable relaxed source 6 for (non-atomic) write operations | |
| 57 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE6_RDENA: 0/1 = disable/enable relaxed source 6 for (non-atomic) read operations | |
| 58 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE6_AWENA: 0/1 = disable/enable relaxed source 6 for atomic (write) operations | |
| 59 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE6_ARENA: 0/1 = disable/enable relaxed source 6 for atomic (read) operations | |
| 60 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE7_WRENA: 0/1 = disable/enable relaxed source 7 for (non-atomic) write operations | |
| 61 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE7_RDENA: 0/1 = disable/enable relaxed source 7 for (non-atomic) read operations | |
| 62 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE7_AWENA: 0/1 = disable/enable relaxed source 7 for atomic (write) operations | |
| 63 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE7_ARENA: 0/1 = disable/enable relaxed source 7 for atomic (read) operations | |
| Relaxed-Ordering Config2 brick 2 | ||||
|---|---|---|---|---|
| Addr: |
00000000110108A8 (SCOM) 0000000013410240 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.SNP.MISC.CONFIG_RELAXED_BRK2 | |||
| Constant(s): | ||||
| Comments: | Configure relaxed-ordering Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM1.SNP.MISC.CONFIG_RELAXED_BRK2_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_RELAXED_BRK2_CMD_CL_DMA_W: enable relaxed ordering for (non-atomic write) cl_dma_w (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 1 | RW | RW | CONFIG_RELAXED_BRK2_CMD_CL_DMA_W_HP: Reserved. (was: enable relaxed ordering for (non-atomic write) cl_dma_w_hp (only valid for GPU and AFU-M2 memory)) | |
| 2 | RW | RW | CONFIG_RELAXED_BRK2_CMD_CL_DMA_INJ: enable relaxed ordering for (non-atomic write) cl_dma_inj (only valid for GPU and AFU-M2 memory) | |
| 3 | RW | RW | CONFIG_RELAXED_BRK2_CMD_PR_DMA_INJ: enable relaxed ordering for (non-atomic write) pr_dma_inj (only valid for GPU and AFU-M2 memory) | |
| 4 | RW | RW | CONFIG_RELAXED_BRK2_CMD_DMA_PR_W: enable relaxed ordering for (non-atomic write) dma_pr_w (only valid for GPU and AFU-M2 memory) | |
| 5 | RW | RW | CONFIG_RELAXED_BRK2_CMD_CL_RD_NC_F0: enable relaxed ordering for (non-atomic read) cl_rd_nc(F=0) (only valid for GPU and AFU-M2 memory) | |
| 6 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMW_CAS_IMAX_U: enable relaxed ordering for (atomic write) armw_cas_imax_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 7 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMW_CAS_IMAX_S: enable relaxed ordering for (atomic write) armw_cas_imax_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 8 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMW_CAS_IMIN_U: enable relaxed ordering for (atomic write) armw_cas_imin_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 9 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMW_CAS_IMIN_S: enable relaxed ordering for (atomic write) armw_cas_imin_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 10 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMW_ADD: enable relaxed ordering for (atomic write) armw_add (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 11 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMW_AND: enable relaxed ordering for (atomic write) armw_and (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 12 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMW_OR: enable relaxed ordering for (atomic write) armw_or (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 13 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMW_XOR: enable relaxed ordering for (atomic write) armw_xor (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 14 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMWF_CAS_IMAX_U: enable relaxed ordering for (atomic read) armwf_cas_imax_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 15 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMWF_CAS_IMAX_S: enable relaxed ordering for (atomic read) armwf_cas_imax_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 16 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMWF_CAS_IMIN_U: enable relaxed ordering for (atomic read) armwf_cas_imin_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 17 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMWF_CAS_IMIN_S: enable relaxed ordering for (atomic read) armwf_cas_imin_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 18 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMWF_ADD: enable relaxed ordering for (atomic read) armwf_add (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 19 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMWF_AND: enable relaxed ordering for (atomic read) armwf_and (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 20 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMWF_OR: enable relaxed ordering for (atomic read) armwf_or (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 21 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMWF_XOR: enable relaxed ordering for (atomic read) armwf_xor (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 22 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMWF_CAS_E: enable relaxed ordering for (atomic read) armwf_cas_e (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 23 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMWF_CAS_U: enable relaxed ordering for (atomic read) armwf_cas_u (only valid for OCAPI AFU-M1 or AFU-M2 memory) (errata HW367501 requires this bit to be 0 for GPU memory) | |
| 24 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMW_CAS_T: enable relaxed ordering for (atomic write) armw_cas_t (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 25 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMWF_CAS_NE: enable relaxed ordering for (atomic read) armwf_cas_ne (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 26 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMWF_INC_B: enable relaxed ordering for (atomic read) armwf_inc_b (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 27 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMWF_INC_E: enable relaxed ordering for (atomic read) armwf_inc_e (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 28 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMWF_DEC_B: enable relaxed ordering for (atomic read) armwf_dec_b (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 29:31 | RW | RW | CONFIG_RELAXED_BRK2_RESERVED1: reserved | |
| 32 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE0_WRENA: 0/1 = disable/enable relaxed source 0 for (non-atomic) write operations | |
| 33 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE0_RDENA: 0/1 = disable/enable relaxed source 0 for (non-atomic) read operations | |
| 34 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE0_AWENA: 0/1 = disable/enable relaxed source 0 for atomic (write) operations | |
| 35 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE0_ARENA: 0/1 = disable/enable relaxed source 0 for atomic (read) operations | |
| 36 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE1_WRENA: 0/1 = disable/enable relaxed source 1 for (non-atomic) write operations | |
| 37 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE1_RDENA: 0/1 = disable/enable relaxed source 1 for (non-atomic) read operations | |
| 38 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE1_AWENA: 0/1 = disable/enable relaxed source 1 for atomic (write) operations | |
| 39 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE1_ARENA: 0/1 = disable/enable relaxed source 1 for atomic (read) operations | |
| 40 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE2_WRENA: 0/1 = disable/enable relaxed source 2 for (non-atomic) write operations | |
| 41 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE2_RDENA: 0/1 = disable/enable relaxed source 2 for (non-atomic) read operations | |
| 42 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE2_AWENA: 0/1 = disable/enable relaxed source 2 for atomic (write) operations | |
| 43 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE2_ARENA: 0/1 = disable/enable relaxed source 2 for atomic (read) operations | |
| 44 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE3_WRENA: 0/1 = disable/enable relaxed source 3 for (non-atomic) write operations | |
| 45 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE3_RDENA: 0/1 = disable/enable relaxed source 3 for (non-atomic) read operations | |
| 46 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE3_AWENA: 0/1 = disable/enable relaxed source 3 for atomic (write) operations | |
| 47 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE3_ARENA: 0/1 = disable/enable relaxed source 3 for atomic (read) operations | |
| 48 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE4_WRENA: 0/1 = disable/enable relaxed source 4 for (non-atomic) write operations | |
| 49 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE4_RDENA: 0/1 = disable/enable relaxed source 4 for (non-atomic) read operations | |
| 50 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE4_AWENA: 0/1 = disable/enable relaxed source 4 for atomic (write) operations | |
| 51 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE4_ARENA: 0/1 = disable/enable relaxed source 4 for atomic (read) operations | |
| 52 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE5_WRENA: 0/1 = disable/enable relaxed source 5 for (non-atomic) write operations | |
| 53 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE5_RDENA: 0/1 = disable/enable relaxed source 5 for (non-atomic) read operations | |
| 54 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE5_AWENA: 0/1 = disable/enable relaxed source 5 for atomic (write) operations | |
| 55 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE5_ARENA: 0/1 = disable/enable relaxed source 5 for atomic (read) operations | |
| 56 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE6_WRENA: 0/1 = disable/enable relaxed source 6 for (non-atomic) write operations | |
| 57 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE6_RDENA: 0/1 = disable/enable relaxed source 6 for (non-atomic) read operations | |
| 58 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE6_AWENA: 0/1 = disable/enable relaxed source 6 for atomic (write) operations | |
| 59 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE6_ARENA: 0/1 = disable/enable relaxed source 6 for atomic (read) operations | |
| 60 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE7_WRENA: 0/1 = disable/enable relaxed source 7 for (non-atomic) write operations | |
| 61 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE7_RDENA: 0/1 = disable/enable relaxed source 7 for (non-atomic) read operations | |
| 62 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE7_AWENA: 0/1 = disable/enable relaxed source 7 for atomic (write) operations | |
| 63 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE7_ARENA: 0/1 = disable/enable relaxed source 7 for atomic (read) operations | |
| Relaxed-Ordering Config2 brick 3 | ||||
|---|---|---|---|---|
| Addr: |
00000000110108A9 (SCOM) 0000000013410248 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.SNP.MISC.CONFIG_RELAXED_BRK3 | |||
| Constant(s): | ||||
| Comments: | Configure relaxed-ordering Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM1.SNP.MISC.CONFIG_RELAXED_BRK3_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_RELAXED_BRK3_CMD_CL_DMA_W: enable relaxed ordering for (non-atomic write) cl_dma_w (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 1 | RW | RW | CONFIG_RELAXED_BRK3_CMD_CL_DMA_W_HP: Reserved. (was: enable relaxed ordering for (non-atomic write) cl_dma_w_hp (only valid for GPU and AFU-M2 memory)) | |
| 2 | RW | RW | CONFIG_RELAXED_BRK3_CMD_CL_DMA_INJ: enable relaxed ordering for (non-atomic write) cl_dma_inj (only valid for GPU and AFU-M2 memory) | |
| 3 | RW | RW | CONFIG_RELAXED_BRK3_CMD_PR_DMA_INJ: enable relaxed ordering for (non-atomic write) pr_dma_inj (only valid for GPU and AFU-M2 memory) | |
| 4 | RW | RW | CONFIG_RELAXED_BRK3_CMD_DMA_PR_W: enable relaxed ordering for (non-atomic write) dma_pr_w (only valid for GPU and AFU-M2 memory) | |
| 5 | RW | RW | CONFIG_RELAXED_BRK3_CMD_CL_RD_NC_F0: enable relaxed ordering for (non-atomic read) cl_rd_nc(F=0) (only valid for GPU and AFU-M2 memory) | |
| 6 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMW_CAS_IMAX_U: enable relaxed ordering for (atomic write) armw_cas_imax_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 7 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMW_CAS_IMAX_S: enable relaxed ordering for (atomic write) armw_cas_imax_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 8 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMW_CAS_IMIN_U: enable relaxed ordering for (atomic write) armw_cas_imin_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 9 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMW_CAS_IMIN_S: enable relaxed ordering for (atomic write) armw_cas_imin_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 10 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMW_ADD: enable relaxed ordering for (atomic write) armw_add (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 11 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMW_AND: enable relaxed ordering for (atomic write) armw_and (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 12 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMW_OR: enable relaxed ordering for (atomic write) armw_or (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 13 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMW_XOR: enable relaxed ordering for (atomic write) armw_xor (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 14 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMWF_CAS_IMAX_U: enable relaxed ordering for (atomic read) armwf_cas_imax_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 15 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMWF_CAS_IMAX_S: enable relaxed ordering for (atomic read) armwf_cas_imax_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 16 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMWF_CAS_IMIN_U: enable relaxed ordering for (atomic read) armwf_cas_imin_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 17 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMWF_CAS_IMIN_S: enable relaxed ordering for (atomic read) armwf_cas_imin_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 18 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMWF_ADD: enable relaxed ordering for (atomic read) armwf_add (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 19 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMWF_AND: enable relaxed ordering for (atomic read) armwf_and (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 20 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMWF_OR: enable relaxed ordering for (atomic read) armwf_or (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 21 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMWF_XOR: enable relaxed ordering for (atomic read) armwf_xor (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 22 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMWF_CAS_E: enable relaxed ordering for (atomic read) armwf_cas_e (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 23 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMWF_CAS_U: enable relaxed ordering for (atomic read) armwf_cas_u (only valid for OCAPI AFU-M1 or AFU-M2 memory) (errata HW367501 requires this bit to be 0 for GPU memory) | |
| 24 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMW_CAS_T: enable relaxed ordering for (atomic write) armw_cas_t (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 25 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMWF_CAS_NE: enable relaxed ordering for (atomic read) armwf_cas_ne (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 26 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMWF_INC_B: enable relaxed ordering for (atomic read) armwf_inc_b (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 27 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMWF_INC_E: enable relaxed ordering for (atomic read) armwf_inc_e (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 28 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMWF_DEC_B: enable relaxed ordering for (atomic read) armwf_dec_b (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 29:31 | RW | RW | CONFIG_RELAXED_BRK3_RESERVED1: reserved | |
| 32 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE0_WRENA: 0/1 = disable/enable relaxed source 0 for (non-atomic) write operations | |
| 33 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE0_RDENA: 0/1 = disable/enable relaxed source 0 for (non-atomic) read operations | |
| 34 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE0_AWENA: 0/1 = disable/enable relaxed source 0 for atomic (write) operations | |
| 35 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE0_ARENA: 0/1 = disable/enable relaxed source 0 for atomic (read) operations | |
| 36 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE1_WRENA: 0/1 = disable/enable relaxed source 1 for (non-atomic) write operations | |
| 37 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE1_RDENA: 0/1 = disable/enable relaxed source 1 for (non-atomic) read operations | |
| 38 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE1_AWENA: 0/1 = disable/enable relaxed source 1 for atomic (write) operations | |
| 39 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE1_ARENA: 0/1 = disable/enable relaxed source 1 for atomic (read) operations | |
| 40 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE2_WRENA: 0/1 = disable/enable relaxed source 2 for (non-atomic) write operations | |
| 41 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE2_RDENA: 0/1 = disable/enable relaxed source 2 for (non-atomic) read operations | |
| 42 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE2_AWENA: 0/1 = disable/enable relaxed source 2 for atomic (write) operations | |
| 43 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE2_ARENA: 0/1 = disable/enable relaxed source 2 for atomic (read) operations | |
| 44 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE3_WRENA: 0/1 = disable/enable relaxed source 3 for (non-atomic) write operations | |
| 45 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE3_RDENA: 0/1 = disable/enable relaxed source 3 for (non-atomic) read operations | |
| 46 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE3_AWENA: 0/1 = disable/enable relaxed source 3 for atomic (write) operations | |
| 47 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE3_ARENA: 0/1 = disable/enable relaxed source 3 for atomic (read) operations | |
| 48 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE4_WRENA: 0/1 = disable/enable relaxed source 4 for (non-atomic) write operations | |
| 49 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE4_RDENA: 0/1 = disable/enable relaxed source 4 for (non-atomic) read operations | |
| 50 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE4_AWENA: 0/1 = disable/enable relaxed source 4 for atomic (write) operations | |
| 51 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE4_ARENA: 0/1 = disable/enable relaxed source 4 for atomic (read) operations | |
| 52 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE5_WRENA: 0/1 = disable/enable relaxed source 5 for (non-atomic) write operations | |
| 53 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE5_RDENA: 0/1 = disable/enable relaxed source 5 for (non-atomic) read operations | |
| 54 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE5_AWENA: 0/1 = disable/enable relaxed source 5 for atomic (write) operations | |
| 55 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE5_ARENA: 0/1 = disable/enable relaxed source 5 for atomic (read) operations | |
| 56 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE6_WRENA: 0/1 = disable/enable relaxed source 6 for (non-atomic) write operations | |
| 57 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE6_RDENA: 0/1 = disable/enable relaxed source 6 for (non-atomic) read operations | |
| 58 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE6_AWENA: 0/1 = disable/enable relaxed source 6 for atomic (write) operations | |
| 59 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE6_ARENA: 0/1 = disable/enable relaxed source 6 for atomic (read) operations | |
| 60 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE7_WRENA: 0/1 = disable/enable relaxed source 7 for (non-atomic) write operations | |
| 61 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE7_RDENA: 0/1 = disable/enable relaxed source 7 for (non-atomic) read operations | |
| 62 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE7_AWENA: 0/1 = disable/enable relaxed source 7 for atomic (write) operations | |
| 63 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE7_ARENA: 0/1 = disable/enable relaxed source 7 for atomic (read) operations | |
| Relaxed-Ordering Config2 brick 4 | ||||
|---|---|---|---|---|
| Addr: |
00000000110108AA (SCOM) 0000000013410250 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.SNP.MISC.CONFIG_RELAXED_BRK4 | |||
| Constant(s): | ||||
| Comments: | Configure relaxed-ordering Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM1.SNP.MISC.CONFIG_RELAXED_BRK4_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_RELAXED_BRK4_CMD_CL_DMA_W: enable relaxed ordering for (non-atomic write) cl_dma_w (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 1 | RW | RW | CONFIG_RELAXED_BRK4_CMD_CL_DMA_W_HP: Reserved. (was: enable relaxed ordering for (non-atomic write) cl_dma_w_hp (only valid for GPU and AFU-M2 memory)) | |
| 2 | RW | RW | CONFIG_RELAXED_BRK4_CMD_CL_DMA_INJ: enable relaxed ordering for (non-atomic write) cl_dma_inj (only valid for GPU and AFU-M2 memory) | |
| 3 | RW | RW | CONFIG_RELAXED_BRK4_CMD_PR_DMA_INJ: enable relaxed ordering for (non-atomic write) pr_dma_inj (only valid for GPU and AFU-M2 memory) | |
| 4 | RW | RW | CONFIG_RELAXED_BRK4_CMD_DMA_PR_W: enable relaxed ordering for (non-atomic write) dma_pr_w (only valid for GPU and AFU-M2 memory) | |
| 5 | RW | RW | CONFIG_RELAXED_BRK4_CMD_CL_RD_NC_F0: enable relaxed ordering for (non-atomic read) cl_rd_nc(F=0) (only valid for GPU and AFU-M2 memory) | |
| 6 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMW_CAS_IMAX_U: enable relaxed ordering for (atomic write) armw_cas_imax_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 7 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMW_CAS_IMAX_S: enable relaxed ordering for (atomic write) armw_cas_imax_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 8 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMW_CAS_IMIN_U: enable relaxed ordering for (atomic write) armw_cas_imin_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 9 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMW_CAS_IMIN_S: enable relaxed ordering for (atomic write) armw_cas_imin_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 10 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMW_ADD: enable relaxed ordering for (atomic write) armw_add (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 11 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMW_AND: enable relaxed ordering for (atomic write) armw_and (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 12 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMW_OR: enable relaxed ordering for (atomic write) armw_or (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 13 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMW_XOR: enable relaxed ordering for (atomic write) armw_xor (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 14 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMWF_CAS_IMAX_U: enable relaxed ordering for (atomic read) armwf_cas_imax_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 15 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMWF_CAS_IMAX_S: enable relaxed ordering for (atomic read) armwf_cas_imax_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 16 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMWF_CAS_IMIN_U: enable relaxed ordering for (atomic read) armwf_cas_imin_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 17 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMWF_CAS_IMIN_S: enable relaxed ordering for (atomic read) armwf_cas_imin_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 18 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMWF_ADD: enable relaxed ordering for (atomic read) armwf_add (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 19 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMWF_AND: enable relaxed ordering for (atomic read) armwf_and (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 20 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMWF_OR: enable relaxed ordering for (atomic read) armwf_or (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 21 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMWF_XOR: enable relaxed ordering for (atomic read) armwf_xor (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 22 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMWF_CAS_E: enable relaxed ordering for (atomic read) armwf_cas_e (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 23 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMWF_CAS_U: enable relaxed ordering for (atomic read) armwf_cas_u (only valid for OCAPI AFU-M1 or AFU-M2 memory) (errata HW367501 requires this bit to be 0 for GPU memory) | |
| 24 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMW_CAS_T: enable relaxed ordering for (atomic write) armw_cas_t (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 25 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMWF_CAS_NE: enable relaxed ordering for (atomic read) armwf_cas_ne (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 26 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMWF_INC_B: enable relaxed ordering for (atomic read) armwf_inc_b (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 27 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMWF_INC_E: enable relaxed ordering for (atomic read) armwf_inc_e (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 28 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMWF_DEC_B: enable relaxed ordering for (atomic read) armwf_dec_b (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 29:31 | RW | RW | CONFIG_RELAXED_BRK4_RESERVED1: reserved | |
| 32 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE0_WRENA: 0/1 = disable/enable relaxed source 0 for (non-atomic) write operations | |
| 33 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE0_RDENA: 0/1 = disable/enable relaxed source 0 for (non-atomic) read operations | |
| 34 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE0_AWENA: 0/1 = disable/enable relaxed source 0 for atomic (write) operations | |
| 35 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE0_ARENA: 0/1 = disable/enable relaxed source 0 for atomic (read) operations | |
| 36 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE1_WRENA: 0/1 = disable/enable relaxed source 1 for (non-atomic) write operations | |
| 37 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE1_RDENA: 0/1 = disable/enable relaxed source 1 for (non-atomic) read operations | |
| 38 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE1_AWENA: 0/1 = disable/enable relaxed source 1 for atomic (write) operations | |
| 39 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE1_ARENA: 0/1 = disable/enable relaxed source 1 for atomic (read) operations | |
| 40 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE2_WRENA: 0/1 = disable/enable relaxed source 2 for (non-atomic) write operations | |
| 41 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE2_RDENA: 0/1 = disable/enable relaxed source 2 for (non-atomic) read operations | |
| 42 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE2_AWENA: 0/1 = disable/enable relaxed source 2 for atomic (write) operations | |
| 43 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE2_ARENA: 0/1 = disable/enable relaxed source 2 for atomic (read) operations | |
| 44 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE3_WRENA: 0/1 = disable/enable relaxed source 3 for (non-atomic) write operations | |
| 45 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE3_RDENA: 0/1 = disable/enable relaxed source 3 for (non-atomic) read operations | |
| 46 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE3_AWENA: 0/1 = disable/enable relaxed source 3 for atomic (write) operations | |
| 47 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE3_ARENA: 0/1 = disable/enable relaxed source 3 for atomic (read) operations | |
| 48 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE4_WRENA: 0/1 = disable/enable relaxed source 4 for (non-atomic) write operations | |
| 49 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE4_RDENA: 0/1 = disable/enable relaxed source 4 for (non-atomic) read operations | |
| 50 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE4_AWENA: 0/1 = disable/enable relaxed source 4 for atomic (write) operations | |
| 51 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE4_ARENA: 0/1 = disable/enable relaxed source 4 for atomic (read) operations | |
| 52 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE5_WRENA: 0/1 = disable/enable relaxed source 5 for (non-atomic) write operations | |
| 53 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE5_RDENA: 0/1 = disable/enable relaxed source 5 for (non-atomic) read operations | |
| 54 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE5_AWENA: 0/1 = disable/enable relaxed source 5 for atomic (write) operations | |
| 55 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE5_ARENA: 0/1 = disable/enable relaxed source 5 for atomic (read) operations | |
| 56 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE6_WRENA: 0/1 = disable/enable relaxed source 6 for (non-atomic) write operations | |
| 57 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE6_RDENA: 0/1 = disable/enable relaxed source 6 for (non-atomic) read operations | |
| 58 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE6_AWENA: 0/1 = disable/enable relaxed source 6 for atomic (write) operations | |
| 59 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE6_ARENA: 0/1 = disable/enable relaxed source 6 for atomic (read) operations | |
| 60 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE7_WRENA: 0/1 = disable/enable relaxed source 7 for (non-atomic) write operations | |
| 61 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE7_RDENA: 0/1 = disable/enable relaxed source 7 for (non-atomic) read operations | |
| 62 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE7_AWENA: 0/1 = disable/enable relaxed source 7 for atomic (write) operations | |
| 63 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE7_ARENA: 0/1 = disable/enable relaxed source 7 for atomic (read) operations | |
| Low-Water Marks | ||||
|---|---|---|---|---|
| Addr: |
00000000110108AB (SCOM) 0000000013410258 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.SNP.MISC.LOW_WATER | |||
| Constant(s): | ||||
| Comments: | State-Machine allocation Low-Water Marks the sum of the Low-Water marks must be less than config_max_machines Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM1.SNP.MISC.LOW_WATER_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_LOW_WATER_PWR0: Low-Water mark for PowerBus rd/dclaim/atomic/etc. requests | |
| 1 | RW | RW | CONFIG_LOW_WATER_PWR1: Low-Water mark for PowerBus cp (castout-push) requests. | |
| 2 | RW | RW | CONFIG_LOW_WATER_PWR2: Low-Water mark for PowerBus snoops for force-evict requests. | |
| 3 | RW | RW | CONFIG_LOW_WATER_XATS: Low-Water mark for ATS/XSL PowerBus requests | |
| 4 | RW | RW | CONFIG_LOW_WATER_INTS: Low-Water mark for MISC Interrupt requests | |
| 5 | RW | RW | CONFIG_LOW_WATER_REQ0: Low-Water mark for brick-0 NVLink brick-0 Req channel or OCAPI TLX.vc.3 requests | |
| 6 | RW | RW | CONFIG_LOW_WATER_CST0: Low-Water mark for brick-0 OCAPI Castout requests | |
| 7 | RW | RW | CONFIG_LOW_WATER_PRB0: Low-Water mark for brick-0 NVLink Probe or OCAPI mem_pa_flush requests | |
| 8 | RW | RW | CONFIG_LOW_WATER_REQ1: Low-Water mark for brick-1 NVLink Req channel or OCAPI TLX.vc.3 requests | |
| 9 | RW | RW | CONFIG_LOW_WATER_CST1: Low-Water mark for brick-1 OCAPI Castout requests | |
| 10 | RW | RW | CONFIG_LOW_WATER_PRB1: Low-Water mark for brick-1 NVLink Probe or OCAPI mem_pa_flush requests | |
| 11 | RW | RW | CONFIG_LOW_WATER_REQ2: Low-Water mark for brick-2 NVLink brick-0 Req channel or OCAPI TLX.vc.3 requests | |
| 12 | RW | RW | CONFIG_LOW_WATER_CST2: Low-Water mark for brick-2 OCAPI Castout requests | |
| 13 | RW | RW | CONFIG_LOW_WATER_PRB2: Low-Water mark for brick-2 NVLink Probe or OCAPI mem_pa_flush requests | |
| 14 | RW | RW | CONFIG_LOW_WATER_REQ3: Low-Water mark for brick-3 NVLink Req channel or OCAPI TLX.vc.3 requests | |
| 15 | RW | RW | CONFIG_LOW_WATER_CST3: Low-Water mark for brick-3 OCAPI Castout requests | |
| 16 | RW | RW | CONFIG_LOW_WATER_PRB3: Low-Water mark for brick-3 NVLink Probe or OCAPI mem_pa_flush requests | |
| 17 | RW | RW | CONFIG_LOW_WATER_REQ4: Low-Water mark for brick-4 NVLink brick-0 Req channel or OCAPI TLX.vc.3 requests | |
| 18 | RW | RW | CONFIG_LOW_WATER_CST4: Low-Water mark for brick-4 OCAPI Castout requests | |
| 19 | RW | RW | CONFIG_LOW_WATER_PRB4: Low-Water mark for brick-4 NVLink Probe or OCAPI mem_pa_flush requests | |
| 20 | RW | RW | CONFIG_LOW_WATER_XI_SHARED: shared Low-Water mark for ATS/XSL/MISC-INT requests if set to 1, the only one of config_low_water_{xats,ints} should be set to 1 | |
| 21 | RW | RW | CONFIG_LOW_WATER_REQX_SHARED: shared Low-Water mark for req0...req4 if set to 1, the only one of config_low_water_{req0...req4} should be set to 1 | |
| 22 | RW | RW | CONFIG_LOW_WATER_CSTX_SHARED: shared Low-Water mark for cst0...cst4 if set to 1, the only one of config_low_water_{cst0...cst4} should be set to 1 | |
| 23 | RW | RW | CONFIG_LOW_WATER_PRBX_SHARED: shared Low-Water mark for prb0...prb4 if set to 1, the only one of config_low_water_{prb0...prb4} should be set to 1 | |
| 24:25 | RW | RW | CONFIG_WEIGHT_PWR0: 0...3 -> weight 1..4 when balancing PWR0 against other classes | |
| 26:27 | RW | RW | CONFIG_WEIGHT_PWR1: 0...3 -> weight 1..4 when balancing PWR1 against other classes | |
| 28:29 | RW | RW | CONFIG_WEIGHT_PWR2: 0...3 -> weight 1..4 when balancing PWR2 against other classes | |
| 30:31 | RW | RW | CONFIG_WEIGHT_XATS: 0...3 -> weight 1..4 when balancing XATS against other classes | |
| 32:33 | RW | RW | CONFIG_WEIGHT_INTS: 0...3 -> weight 1..4 when balancing INTS against other classes | |
| 34:35 | RW | RW | CONFIG_WEIGHT_REQ0: 0...3 -> weight 1..4 when balancing REQ0 against other classes | |
| 36:37 | RW | RW | CONFIG_WEIGHT_CST0: 0...3 -> weight 1..4 when balancing CST0 against other classes | |
| 38:39 | RW | RW | CONFIG_WEIGHT_PRB0: 0...3 -> weight 1..4 when balancing PRB0 against other classes | |
| 40:41 | RW | RW | CONFIG_WEIGHT_REQ1: 0...3 -> weight 1..4 when balancing REQ1 against other classes | |
| 42:43 | RW | RW | CONFIG_WEIGHT_CST1: 0...3 -> weight 1..4 when balancing CST1 against other classes | |
| 44:45 | RW | RW | CONFIG_WEIGHT_PRB1: 0...3 -> weight 1..4 when balancing PRB1 against other classes | |
| 46:47 | RW | RW | CONFIG_WEIGHT_REQ2: 0...3 -> weight 1..4 when balancing REQ2 against other classes | |
| 48:49 | RW | RW | CONFIG_WEIGHT_CST2: 0...3 -> weight 1..4 when balancing CST2 against other classes | |
| 50:51 | RW | RW | CONFIG_WEIGHT_PRB2: 0...3 -> weight 1..4 when balancing PRB2 against other classes | |
| 52:53 | RW | RW | CONFIG_WEIGHT_REQ3: 0...3 -> weight 1..4 when balancing REQ3 against other classes | |
| 54:55 | RW | RW | CONFIG_WEIGHT_CST3: 0...3 -> weight 1..4 when balancing CST3 against other classes | |
| 56:57 | RW | RW | CONFIG_WEIGHT_PRB3: 0...3 -> weight 1..4 when balancing PRB3 against other classes | |
| 58:59 | RW | RW | CONFIG_WEIGHT_REQ4: 0...3 -> weight 1..4 when balancing REQ4 against other classes | |
| 60:61 | RW | RW | CONFIG_WEIGHT_CST4: 0...3 -> weight 1..4 when balancing CST4 against other classes | |
| 62:63 | RW | RW | CONFIG_WEIGHT_PRB4: 0...3 -> weight 1..4 when balancing PRB4 against other classes | |
| Machine Allocation configuration | ||||
|---|---|---|---|---|
| Addr: |
00000000110108AD (SCOM) 0000000013410268 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.SNP.MISC.MACHINE_ALLOC | |||
| Constant(s): | ||||
| Comments: | State-Machine configuration and control Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM1.SNP.MISC.MACHINE_ALLOC_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_ENABLE_MACHINE_ALLOC: Enable state-machine allocation Can only be changed 0->1, must stay 1 once set | |
| 1 | RW | RW | CONFIG_ENABLE_EXCEED_HIGH: Enable exceeding high water marks | |
| 2:7 | RW | RW | CONFIG_MAX_MACHINES: Maximum number of state-machines to be used. Must be >= 20 and <= 62 | |
| 8:13 | RW | RW | CONFIG_HIGH_WATER_IDLE: High-water mark for 'Idle' allocation classes | |
| 14:19 | RW | RW | CONFIG_HIGH_BONUS1: Signed 6-bit bonus value to apply to the available machines count prior to division | |
| 20:29 | RW | RW | CONFIG_HIGH_MIN_SHARE: Minimum share after division (machines * 8) | |
| 30:39 | RW | RW | CONFIG_HIGH_BONUS2: Signed 10-bit bonus value to apply to machines count after division (signed machines * 8) | |
| 40:43 | RW | RW | CONFIG_MAX_HIGH_RESERVED: Maximum of state-machines reserved for classes below their high-water marks | |
| 44:48 | RW | RW | CONFIG_SMAL_DEBUG_SEL0: Debug select mux for state-machine-allocation debug output 0 | |
| 49:53 | RW | RW | CONFIG_SMAL_DEBUG_SEL1: Debug select mux for state-machine-allocation debug output 1 | |
| 54:58 | RW | RW | CONFIG_SMAL_DEBUG_SEL2: Debug select mux for state-machine-allocation debug output 2 | |
| 59:63 | RW | RW | CONFIG_SMAL_DEBUG_SEL3: Debug select mux for state-machine-allocation debug output 3 | |
| Perf Config Reg | ||||
|---|---|---|---|---|
| Addr: |
00000000110108AE (SCOM) 0000000013410270 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.SNP.MISC.PERF_CONFIG | |||
| Constant(s): | ||||
| Comments: | Performance Event selection | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:35 | PAU3.CS.SM1.SNP.MISC.PERF_CONFIG_Q_0_INST.LATC.L2(0:35) [000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:7 | RW | RW | PERF_CONFIG_EVENT0: Event 0 select 0: count nothing 1: count cycles 2: count # of cycles REQ0 count matches perf_mask/match_alloc 3: count # of cycles CST0 count matches perf_mask/match_alloc 4: count # of cycles PRB0 count matches perf_mask/match_alloc 5: count # of cycles REQ1 count matches perf_mask/match_alloc 6: count # of cycles CST1 count matches perf_mask/match_alloc 7: count # of cycles PRB1 count matches perf_mask/match_alloc 8: count # of cycles REQ2 count matches perf_mask/match_alloc 9: count # of cycles CST2 count matches perf_mask/match_alloc 10: count # of cycles PRB2 count matches perf_mask/match_alloc 11: count # of cycles REQ3 count matches perf_mask/match_alloc 12: count # of cycles CST3 count matches perf_mask/match_alloc 13: count # of cycles PRB3 count matches perf_mask/match_alloc 14: count # of cycles REQ4 count matches perf_mask/match_alloc 15: count # of cycles CST4 count matches perf_mask/match_alloc 16: count # of cycles PRB4 count matches perf_mask/match_alloc 17: count # of cycles PWR0 count matches perf_mask/match_alloc 18: count # of cycles PWR1 count matches perf_mask/match_alloc 19: count # of cycles PWR2 count matches perf_mask/match_alloc 20: count # of cycles XATS count matches perf_mask/match_alloc 21: count # of cycles reserved count matches perf_mask/match_alloc 22: count # of cycles free count matches perf_mask/match_alloc 23: count # of cycles INTS count matches perf_mask/match_alloc 24: count # of RCmds received matching perf_mask/match 25: count # of times PResp=rty_dinc was driven 26: count # of RCmds received from PAU/PAU 27: count # of perf-select RCmds that had cam_hit_pckt_vld_d asserted as an input to the fsnoop_coll table 28: count # of perf-select RCmds that had cam_hit_pckt_vld_nd asserted as an input to the fsnoop_coll table 29: count # of perf-select RCmds that had cam_hit_pckt_vld_ond asserted as an input to the fsnoop_coll table 30: count # of perf-select RCmds that had cam_hit_pckt_win asserted as an input to the fsnoop_coll table 31: count # of perf-select RCmds that had cam_hit_rty_dif asserted as an input to the fsnoop_coll table 32: count # of perf-select RCmds that had cam_hit_rty_dif_mpf asserted as an input to the fsnoop_coll table 33: count # of perf-select RCmds that had cam_hit_pckt_poison asserted as an input to the fsnoop_coll table 34: count # of perf-select RCmds that had cam_hit_rty_lco asserted as an input to the fsnoop_coll table 35: count # of perf-select RCmds that had cam_hit_rty_abbk asserted as an input to the fsnoop_coll table 36: count # of perf-select RCmds that had cam_hit_rty_abbks asserted as an input to the fsnoop_coll table 37: count # of perf-select RCmds that had cam_hit_rty_all asserted as an input to the fsnoop_coll table 38: count # of perf-select RCmds that had cam_hit_snarf_cpm asserted as an input to the fsnoop_coll table 39: count # of perf-select RCmds that had cam_hit_pb_req asserted as an input to the fsnoop_coll table 40: count # of perf-select RCmds that had presp_rty_spec asserted as an output from the fsnoop_coll table 41: count # of perf-select RCmds that had presp_rty_hpc asserted as an output from the fsnoop_coll table 42: count # of perf-select RCmds that had presp_rty_prot asserted as an output from the fsnoop_coll table 43: count # of perf-select RCmds that had presp_rty_r_coll asserted as an output from the fsnoop_coll table 44: count # of perf-select RCmds that had presp_pckt_hit asserted as an output from the fsnoop_coll table 45: count # of perf-select RCmds that had presp_accept asserted as an output from the fsnoop_coll table 46: count # of perf-select RCmds that had cam_hit_mod_addr asserted as an input to the fsnoop_dir table 47: count # of perf-select RCmds that had cam_hit_mod_lock asserted as an input to the fsnoop_dir table 48: count # of perf-select RCmds that had cam_hit_syn_pend asserted as an input to the fsnoop_dir table 49: count # of perf-select RCmds that had cam_hit_sfe_addr asserted as an input to the fsnoop_dir table 50: count # of perf-select RCmds that had cam_hit_sfe_pend asserted as an input to the fsnoop_dir table 51: count # of perf-select RCmds that had cam_hit_co_pend asserted as an input to the fsnoop_dir table 52: count # of perf-select RCmds that had cam_hit_rs_pend asserted as an input to the fsnoop_dir table 53: count # of perf-select RCmds that had cam_hit_row_not_head asserted as an input to the fsnoop_dir table 54: count # of perf-select RCmds that had l2_dir_valid_or_alloc asserted as an input to the fsnoop_dir table 55: count # of perf-select RCmds that had l2_dir_any_pro_note asserted as an input to the fsnoop_dir table 56: count # of perf-select RCmds that had l2_dir_max_e asserted as an input to the fsnoop_dir table 57: count # of perf-select RCmds that had l2_dir_has_s asserted as an input to the fsnoop_dir table 58: count # of perf-select RCmds that had l2_dir_any_cmd_i asserted as an input to the fsnoop_dir table 59: count # of perf-select RCmds that had l2_dir_other_brick_s asserted as an input to the fsnoop_dir table 60: count # of perf-select RCmds that had l2_dir_other_brick_e asserted as an input to the fsnoop_dir table 61: count # of perf-select RCmds that had presp_shd asserted as an output from the fsnoop_dir table 62: count # of perf-select RCmds that had presp_rty asserted as an output from the fsnoop_dir table 63: count # of perf-select RCmds that had presp_m_mu_ix asserted as an output from the fsnoop_dir table 64: count # of perf-select RCmds that had presp_rty_lost_claim asserted as an output from the fsnoop_dir table 65: count # of perf-select RCmds that had lock_snp_sfe asserted as an output from the fsnoop_dir table 66: count # of perf-select RCmds that had lock_snp_mod asserted as an output from the fsnoop_dir table 67: count # of perf-select RCmds that had lock_mod asserted as an output from the fsnoop_dir table 68: count # of perf-select RCmds that had send_mugging asserted as an output from the fsnoop_dir table 69: count # of perf-select RCmds that had block_dir asserted as an input to the psnoop table others: reserved (count nothing) | |
| 8:15 | RW | RW | PERF_CONFIG_EVENT1: Event 1 select See Event 0 select for encodes | |
| 16:23 | RW | RW | PERF_CONFIG_EVENT2: Event 2 select See Event 0 select for encodes | |
| 24:31 | RW | RW | PERF_CONFIG_EVENT3: Event 3 select See Event 0 select for encodes | |
| 32:34 | RW | RW | PERF_CONFIG_RESERVED2: reserved | |
| 35 | RW | RW | PERF_CONFIG_ACT: Enable clock-gates for performance monitor latches | |
| 36:63 | RO | RO | constant=0b0000000000000000000000000000 | |
| Inhibit configuration Register | ||||
|---|---|---|---|---|
| Addr: |
00000000110108AF (SCOM) 0000000013410278 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.SNP.MISC.INHIBIT_CONFIG | |||
| Constant(s): | ||||
| Comments: | Configures Inhibits for CQ_SM | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:31 | PAU3.CS.SM1.SNP.MISC.INHIBIT_CONFIG_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:7 | RW | RW | CONFIG_INHIBIT_DEST0: Selects the destination of the inhibit | |
| 8:15 | RW | RW | CONFIG_INHIBIT_DEST1: Selects the destination of the inhibit | |
| 16:23 | RW | RW | CONFIG_INHIBIT_DEST2: Selects the destination of the inhibit | |
| 24:31 | RW | RW | CONFIG_INHIBIT_DEST3: Selects the destination of the inhibit | |
| 32:63 | RO | RO | constant=0b00000000000000000000000000000000 | |
| c_err_rpt Message-0 latches | ||||
|---|---|---|---|---|
| Addr: |
00000000110108B0 (SCOM) 0000000013410280 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.SNP.MISC.CERR_MESSAGE0 | |||
| Constant(s): | ||||
| Comments: | Error message/capture register 0 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM1.SNP.MISC.CERR_MESSAGE0_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:63 | RWX_WCLRREG | RWX_WCLRREG | CERR_MESSAGE_BITS0: reserved | |
| c_err_rpt Message-1 latches | ||||
|---|---|---|---|---|
| Addr: |
00000000110108B1 (SCOM) 0000000013410288 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.SNP.MISC.CERR_MESSAGE1 | |||
| Constant(s): | ||||
| Comments: | Error message/capture register 1 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM1.SNP.MISC.CERR_MESSAGE1_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:63 | RWX_WCLRREG | RWX_WCLRREG | CERR_MESSAGE_BITS1: reserved | |
| CQ_SM status register | ||||
|---|---|---|---|---|
| Addr: |
00000000110108B2 (SCOM) 0000000013410290 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.SNP.MISC.SM_STATUS | |||
| Constant(s): | ||||
| Comments: | Status reporting register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:23 | PAU3.CS.SM1.SNP.MISC.SM_STATUS_Q_0_INST.LATC.L2(0:23) [000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | ROX | ROX | SM_STATUS_PWR0: 1 when PowerBus (non-cp*) allocation is at its idle level | |
| 1 | ROX | ROX | SM_STATUS_PWR1: 1 when PowerBus (cp*) allocation is at its idle level | |
| 2 | ROX | ROX | SM_STATUS_PWR2: 1 when PowerBus (cp*) allocation is at its idle level | |
| 3 | ROX | ROX | SM_STATUS_XATS: 1 when ATS/MISC allocation is at its idle level | |
| 4 | ROX | ROX | SM_STATUS_INTS: 1 when INTS allocation is at its idle level | |
| 5 | ROX | ROX | SM_STATUS_CREQ0: 1 when brick 0 CReq allocation is at its idle level | |
| 6 | ROX | ROX | SM_STATUS_CST0: 1 when brick 0 Castout allocation is at its idle level | |
| 7 | ROX | ROX | SM_STATUS_PRB0: 1 when brick 0 Probe allocation is at its idle level | |
| 8 | ROX | ROX | SM_STATUS_CREQ1: 1 when brick 1 CReq allocation is at its idle level | |
| 9 | ROX | ROX | SM_STATUS_CST1: 1 when brick 1 Castout allocation is at its idle level | |
| 10 | ROX | ROX | SM_STATUS_PRB1: 1 when brick 1 Probe allocation is at its idle level | |
| 11 | ROX | ROX | SM_STATUS_CREQ2: 1 when brick 1 CReq allocation is at its idle level | |
| 12 | ROX | ROX | SM_STATUS_CST2: 1 when brick 1 Castout allocation is at its idle level | |
| 13 | ROX | ROX | SM_STATUS_PRB2: 1 when brick 1 Probe allocation is at its idle level | |
| 14 | ROX | ROX | SM_STATUS_CREQ3: 1 when brick 1 CReq allocation is at its idle level | |
| 15 | ROX | ROX | SM_STATUS_CST3: 1 when brick 1 Castout allocation is at its idle level | |
| 16 | ROX | ROX | SM_STATUS_PRB3: 1 when brick 1 Probe allocation is at its idle level | |
| 17 | ROX | ROX | SM_STATUS_CREQ4: 1 when brick 1 CReq allocation is at its idle level | |
| 18 | ROX | ROX | SM_STATUS_CST4: 1 when brick 1 Castout allocation is at its idle level | |
| 19 | ROX | ROX | SM_STATUS_PRB4: 1 when brick 1 Probe allocation is at its idle level | |
| 20 | ROX | ROX | SM_STATUS_CHGRATE: 1 when chgrate.hang slowdown is being applied to machine allocation | |
| 21:23 | ROX | ROX | SM_STATUS_RESERVED1: reserved | |
| 24:63 | RO | RO | constant=0b0000000000000000000000000000000000000000 | |
| c_err_rpt first-0 latches | ||||
|---|---|---|---|---|
| Addr: |
00000000110108B3 (SCOM) 0000000013410298 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.SNP.MISC.CERR_FIRST0 | |||
| Constant(s): | ||||
| Comments: | c_err_rpt first latches read-write-1-clear reg | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:7 | PAU3.CS.SM1.SNP.MISC.CERR_FIRST0_Q_0_INST.LATC.L2(0:7) [00000000] | |||
| 8:15 | PAU3.CS.SM1.SNP.MISC.CERR_FIRST0_Q_8_INST.LATC.L2(8:15) [00000000] | |||
| 16:23 | PAU3.CS.SM1.SNP.MISC.CERR_FIRST0_Q_16_INST.LATC.L2(16:23) [00000000] | |||
| 24:35 | PAU3.CS.SM1.SNP.MISC.CERR_FIRST0_Q_24_INST.LATC.L2(24:35) [000000000000] | |||
| 36:59 | PAU3.CS.SM1.SNP.MISC.CERR_FIRST0_Q_36_INST.LATC.L2(36:59) [000000000000000000000000] | |||
| 60:63 | PAU3.CS.SM1.SNP.MISC.CERR_FIRST0_Q_60_INST.LATC.L2(60:63) [0000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NCF_0: NCF0 An NVLink probe did not match its GPUBar | |
| 1 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NCF_1: NCF1 Epoch timeout while ProNoted L2-dir entry was waiting for castout | |
| 2 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NCF_2: NCF2 (reserved) | |
| 3 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NCF_3: NCF3 NVLink NCF error for brick 0 occurred | |
| 4 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NCF_4: NCF4 NVLink NCF error for brick 1 occurred | |
| 5 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NCF_5: NCF5 NVLink NCF error for brick 2 occurred | |
| 6 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NCF_6: NCF6 NVLink NCF error for brick 3 occurred | |
| 7 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NCF_7: NCF7 NVLink NCF error for brick 4 occurred | |
| 8 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBR_0: PBR0 Addr_Error received for self-lpc command (SSF) | |
| 9 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBR_1: PBR1 (reserved) | |
| 10 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBR_2: PBR2 (reserved) | |
| 11 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBR_3: PBR3 (reserved) | |
| 12 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBR_4: PBR4 Illegal Cmd to GPU Memory received | |
| 13 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBR_5: PBR5 (reserved) | |
| 14 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBR_6: PBR6 (reserved) | |
| 15 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBR_7: PBR7 (reserved) | |
| 16 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBP_0: PBP0 Parity error detected on rcmd ttag field | |
| 17 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBP_1: PBP1 Parity error detected on rcmd addr field | |
| 18 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBP_2: PBP2 Parity error detected on CResp ttag | |
| 19 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBP_3: PBP3 Parity error detected on CResp atag | |
| 20 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBP_4: PBP4 (reserved) | |
| 21 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBP_5: PBP5 (reserved) | |
| 22 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBP_6: PBP6 (reserved) | |
| 23 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBP_7: PBP7 (reserved) | |
| 24 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBC_0: PBC0 (reserved) | |
| 25 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBC_1: PBC1 (reserved) | |
| 26 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBC_2: PBC2 (reserved) | |
| 27 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBC_3: PBC3 (reserved) | |
| 28 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBC_4: PBC4 Reserved (was: RCmd TTag received with illegal group ID) | |
| 29 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBC_5: PBC5 Reserved (was: RCmd TTag received with illegal chip ID) | |
| 30 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBC_6: PBC6 Reserved (was: CResp TTag received with illegal group ID) | |
| 31 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBC_7: PBC7 Reserved (was: CResp TTag received with illegal chip ID) | |
| 32 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBC_8: PBC8 RCmd received with disabled topo-idx in address | |
| 33 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBC_9: PBC9 (reserved) | |
| 34 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBC_10: PBC10 (reserved) | |
| 35 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBC_11: PBC11 (reserved) | |
| 36 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_0: NLG0 RCmd Pre-Snoop table lookup missed the table | |
| 37 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_1: NLG1 (reserved) | |
| 38 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_2: NLG2 Req-in logic dropped an ATS-response | |
| 39 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_3: NLG3 (reserved) | |
| 40 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_4: NLG4 RCmd Final-Snoop Coll-Shd table lookup missed the table | |
| 41 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_5: NLG5 CAM lookup hit multiple snarf-cpm entries (multiple probes received from GPU) | |
| 42 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_6: NLG6 Arb request-in queue overflowed | |
| 43 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_7: NLG7 RCmd Final-Snoop coll collision/lpc table lookup missed the table | |
| 44 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_8: NLG8 RCmd Final-Snoop dir C2/L2-directory table lookup missed the table | |
| 45 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_9: NLG9 RCmd Final-Snoop Coll-Retry-Spec table lookup missed the table | |
| 46 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_10: NLG10 RCmd Final-Snoop Coll-Retry-HPC table lookup missed the table | |
| 47 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_11: NLG11 RCmd Final-Snoop Coll-Retry-Prot table lookup missed the table | |
| 48 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_12: NLG12 RCmd Final-Snoop Coll-Retry-RColl table lookup missed the table | |
| 49 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_13: NLG13 RCmd Final-Snoop Coll-Pocket-Hit table lookup missed the table | |
| 50 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_14: NLG14 RCmd Final-Snoop Coll-Accept table lookup missed the table | |
| 51 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_15: NLG15 RCmd Final-Snoop Dir-Shd table lookup missed the table | |
| 52 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_16: NLG16 RCmd Final-Snoop Dir-Rty table lookup missed the table | |
| 53 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_17: NLG17 RCmd Final-Snoop Dir-MMU(Ix) table lookup missed the table | |
| 54 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_18: NLG18 RCmd Final-Snoop Dir C2/L2 directory impossible command/state combination | |
| 55 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_19: NLG19 RCmd Final-Snoop Dir-Snoop-SFE table lookup missed the table | |
| 56 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_20: NLG20 RCmd Final-Snoop Dir-Snoop-Mod table lookup missed the table | |
| 57 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_21: NLG21 RCmd Final-Snoop Dir-Mod table lookup missed the table | |
| 58 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_22: NLG22 RCmd Final-Snoop CAM-Shared table lookup missed the table | |
| 59 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_23: NLG23 An internal sequencer had an invalid state | |
| 60 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBF_0: PBF0 Addr_Error received for self-lpc command (SSF) | |
| 61 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBF_1: PBF1 (reserved) | |
| 62 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBF_2: PBF2 (reserved) | |
| 63 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBF_3: PBF3 (reserved) | |
| c_err_rpt mask-0 latches | ||||
|---|---|---|---|---|
| Addr: |
00000000110108B4 (SCOM) 00000000134102A0 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.SNP.MISC.CERR_MASK0 | |||
| Constant(s): | ||||
| Comments: | c_err_rpt mask reg Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM1.SNP.MISC.CERR_MASK0_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | IDIAL_SNP_MASK_NCF_0: NCF0 An NVLink probe did not match its GPUBar | |
| 1 | RW | RW | IDIAL_SNP_MASK_NCF_1: NCF1 Epoch timeout while ProNoted L2-dir entry was waiting for castout | |
| 2 | RW | RW | IDIAL_SNP_MASK_NCF_2: NCF2 (reserved) | |
| 3 | RW | RW | IDIAL_SNP_MASK_NCF_3: NCF3 NVLink NCF error for brick 0 occurred | |
| 4 | RW | RW | IDIAL_SNP_MASK_NCF_4: NCF4 NVLink NCF error for brick 1 occurred | |
| 5 | RW | RW | IDIAL_SNP_MASK_NCF_5: NCF5 NVLink NCF error for brick 2 occurred | |
| 6 | RW | RW | IDIAL_SNP_MASK_NCF_6: NCF6 NVLink NCF error for brick 3 occurred | |
| 7 | RW | RW | IDIAL_SNP_MASK_NCF_7: NCF7 NVLink NCF error for brick 4 occurred | |
| 8 | RW | RW | IDIAL_SNP_MASK_PBR_0: PBR0 Addr_Error received for self-lpc command (SSF) | |
| 9 | RW | RW | IDIAL_SNP_MASK_PBR_1: PBR1 (reserved) | |
| 10 | RW | RW | IDIAL_SNP_MASK_PBR_2: PBR2 (reserved) | |
| 11 | RW | RW | IDIAL_SNP_MASK_PBR_3: PBR3 (reserved) | |
| 12 | RW | RW | IDIAL_SNP_MASK_PBR_4: PBR4 Illegal Cmd to GPU Memory received | |
| 13 | RW | RW | IDIAL_SNP_MASK_PBR_5: PBR5 (reserved) | |
| 14 | RW | RW | IDIAL_SNP_MASK_PBR_6: PBR6 (reserved) | |
| 15 | RW | RW | IDIAL_SNP_MASK_PBR_7: PBR7 (reserved) | |
| 16 | RW | RW | IDIAL_SNP_MASK_PBP_0: PBP0 Parity error detected on rcmd ttag field | |
| 17 | RW | RW | IDIAL_SNP_MASK_PBP_1: PBP1 Parity error detected on rcmd addr field | |
| 18 | RW | RW | IDIAL_SNP_MASK_PBP_2: PBP2 Parity error detected on CResp ttag | |
| 19 | RW | RW | IDIAL_SNP_MASK_PBP_3: PBP3 Parity error detected on CResp atag | |
| 20 | RW | RW | IDIAL_SNP_MASK_PBP_4: PBP4 (reserved) | |
| 21 | RW | RW | IDIAL_SNP_MASK_PBP_5: PBP5 (reserved) | |
| 22 | RW | RW | IDIAL_SNP_MASK_PBP_6: PBP6 (reserved) | |
| 23 | RW | RW | IDIAL_SNP_MASK_PBP_7: PBP7 (reserved) | |
| 24 | RW | RW | IDIAL_SNP_MASK_PBC_0: PBC0 (reserved) | |
| 25 | RW | RW | IDIAL_SNP_MASK_PBC_1: PBC1 (reserved) | |
| 26 | RW | RW | IDIAL_SNP_MASK_PBC_2: PBC2 (reserved) | |
| 27 | RW | RW | IDIAL_SNP_MASK_PBC_3: PBC3 (reserved) | |
| 28 | RW | RW | IDIAL_SNP_MASK_PBC_4: PBC4 Reserved (was: RCmd TTag received with illegal group ID) | |
| 29 | RW | RW | IDIAL_SNP_MASK_PBC_5: PBC5 Reserved (was: RCmd TTag received with illegal chip ID) | |
| 30 | RW | RW | IDIAL_SNP_MASK_PBC_6: PBC6 Reserved (was: CResp TTag received with illegal group ID) | |
| 31 | RW | RW | IDIAL_SNP_MASK_PBC_7: PBC7 Reserved (was: CResp TTag received with illegal chip ID) | |
| 32 | RW | RW | IDIAL_SNP_MASK_PBC_8: PBC8 RCmd received with disabled topo-idx in address | |
| 33 | RW | RW | IDIAL_SNP_MASK_PBC_9: PBC9 (reserved) | |
| 34 | RW | RW | IDIAL_SNP_MASK_PBC_10: PBC10 (reserved) | |
| 35 | RW | RW | IDIAL_SNP_MASK_PBC_11: PBC11 (reserved) | |
| 36 | RW | RW | IDIAL_SNP_MASK_NLG_0: NLG0 RCmd Pre-Snoop table lookup missed the table | |
| 37 | RW | RW | IDIAL_SNP_MASK_NLG_1: NLG1 (reserved) | |
| 38 | RW | RW | IDIAL_SNP_MASK_NLG_2: NLG2 Req-in logic dropped an ATS-response | |
| 39 | RW | RW | IDIAL_SNP_MASK_NLG_3: NLG3 (reserved) | |
| 40 | RW | RW | IDIAL_SNP_MASK_NLG_4: NLG4 RCmd Final-Snoop Coll-Shd table lookup missed the table | |
| 41 | RW | RW | IDIAL_SNP_MASK_NLG_5: NLG5 CAM lookup hit multiple snarf-cpm entries (multiple probes received from GPU) | |
| 42 | RW | RW | IDIAL_SNP_MASK_NLG_6: NLG6 Arb request-in queue overflowed | |
| 43 | RW | RW | IDIAL_SNP_MASK_NLG_7: NLG7 RCmd Final-Snoop coll collision/lpc table lookup missed the table | |
| 44 | RW | RW | IDIAL_SNP_MASK_NLG_8: NLG8 RCmd Final-Snoop dir C2/L2-directory table lookup missed the table | |
| 45 | RW | RW | IDIAL_SNP_MASK_NLG_9: NLG9 RCmd Final-Snoop Coll-Retry-Spec table lookup missed the table | |
| 46 | RW | RW | IDIAL_SNP_MASK_NLG_10: NLG10 RCmd Final-Snoop Coll-Retry-HPC table lookup missed the table | |
| 47 | RW | RW | IDIAL_SNP_MASK_NLG_11: NLG11 RCmd Final-Snoop Coll-Retry-Prot table lookup missed the table | |
| 48 | RW | RW | IDIAL_SNP_MASK_NLG_12: NLG12 RCmd Final-Snoop Coll-Retry-RColl table lookup missed the table | |
| 49 | RW | RW | IDIAL_SNP_MASK_NLG_13: NLG13 RCmd Final-Snoop Coll-Pocket-Hit table lookup missed the table | |
| 50 | RW | RW | IDIAL_SNP_MASK_NLG_14: NLG14 RCmd Final-Snoop Coll-Accept table lookup missed the table | |
| 51 | RW | RW | IDIAL_SNP_MASK_NLG_15: NLG15 RCmd Final-Snoop Dir-Shd table lookup missed the table | |
| 52 | RW | RW | IDIAL_SNP_MASK_NLG_16: NLG16 RCmd Final-Snoop Dir-Rty table lookup missed the table | |
| 53 | RW | RW | IDIAL_SNP_MASK_NLG_17: NLG17 RCmd Final-Snoop Dir-MMU(Ix) table lookup missed the table | |
| 54 | RW | RW | IDIAL_SNP_MASK_NLG_18: NLG18 RCmd Final-Snoop Dir C2/L2 directory impossible command/state combination | |
| 55 | RW | RW | IDIAL_SNP_MASK_NLG_19: NLG19 RCmd Final-Snoop Dir-Snoop-SFE table lookup missed the table | |
| 56 | RW | RW | IDIAL_SNP_MASK_NLG_20: NLG20 RCmd Final-Snoop Dir-Snoop-Mod table lookup missed the table | |
| 57 | RW | RW | IDIAL_SNP_MASK_NLG_21: NLG21 RCmd Final-Snoop Dir-Mod table lookup missed the table | |
| 58 | RW | RW | IDIAL_SNP_MASK_NLG_22: NLG22 RCmd Final-Snoop CAM-Shared table lookup missed the table | |
| 59 | RW | RW | IDIAL_SNP_MASK_NLG_23: NLG23 An internal sequencer had an invalid state | |
| 60 | RW | RW | IDIAL_SNP_MASK_PBF_0: PBF0 Addr_Error received for self-lpc command (SSF) | |
| 61 | RW | RW | IDIAL_SNP_MASK_PBF_1: PBF1 (reserved) | |
| 62 | RW | RW | IDIAL_SNP_MASK_PBF_2: PBF2 (reserved) | |
| 63 | RW | RW | IDIAL_SNP_MASK_PBF_3: PBF3 (reserved) | |
| c_err_rpt hold-0 latches | ||||
|---|---|---|---|---|
| Addr: |
00000000110108B5 (SCOM) 00000000134102A8 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.SNP.MISC.CERR_HOLD0 | |||
| Constant(s): | ||||
| Comments: | c_err_rpt hold latches read-write-clear reg | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:7 | PAU3.CS.SM1.SNP.MISC.CERPT_NCF.HOLD_LATCH_INST.HOLD.LATC.L2(0:7) [00000000] | |||
| 8:15 | PAU3.CS.SM1.SNP.MISC.CERPT_PBR.HOLD_LATCH_INST.HOLD.LATC.L2(0:7) [00000000] | |||
| 16:23 | PAU3.CS.SM1.SNP.MISC.CERPT_PBP.HOLD_LATCH_INST.HOLD.LATC.L2(0:7) [00000000] | |||
| 24:35 | PAU3.CS.SM1.SNP.MISC.CERPT_PBC.HOLD_LATCH_INST.HOLD.LATC.L2(0:11) [000000000000] | |||
| 36:59 | PAU3.CS.SM1.SNP.MISC.CERPT_NLG.HOLD_LATCH_INST.HOLD.LATC.L2(0:23) [000000000000000000000000] | |||
| 60:63 | PAU3.CS.SM1.SNP.MISC.CERPT_PBF.HOLD_LATCH_INST.HOLD.LATC.L2(0:3) [0000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NCF_0: NCF0 An NVLink probe did not match its GPUBar | |
| 1 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NCF_1: NCF1 Epoch timeout while ProNoted L2-dir entry was waiting for castout | |
| 2 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NCF_2: NCF2 (reserved) | |
| 3 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NCF_3: NCF3 NVLink NCF error for brick 0 occurred | |
| 4 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NCF_4: NCF4 NVLink NCF error for brick 1 occurred | |
| 5 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NCF_5: NCF5 NVLink NCF error for brick 2 occurred | |
| 6 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NCF_6: NCF6 NVLink NCF error for brick 3 occurred | |
| 7 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NCF_7: NCF7 NVLink NCF error for brick 4 occurred | |
| 8 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBR_0: PBR0 Addr_Error received for self-lpc command (SSF) | |
| 9 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBR_1: PBR1 (reserved) | |
| 10 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBR_2: PBR2 (reserved) | |
| 11 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBR_3: PBR3 (reserved) | |
| 12 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBR_4: PBR4 Illegal Cmd to GPU Memory received | |
| 13 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBR_5: PBR5 (reserved) | |
| 14 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBR_6: PBR6 (reserved) | |
| 15 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBR_7: PBR7 (reserved) | |
| 16 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBP_0: PBP0 Parity error detected on rcmd ttag field | |
| 17 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBP_1: PBP1 Parity error detected on rcmd addr field | |
| 18 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBP_2: PBP2 Parity error detected on CResp ttag | |
| 19 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBP_3: PBP3 Parity error detected on CResp atag | |
| 20 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBP_4: PBP4 (reserved) | |
| 21 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBP_5: PBP5 (reserved) | |
| 22 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBP_6: PBP6 (reserved) | |
| 23 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBP_7: PBP7 (reserved) | |
| 24 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBC_0: PBC0 (reserved) | |
| 25 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBC_1: PBC1 (reserved) | |
| 26 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBC_2: PBC2 (reserved) | |
| 27 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBC_3: PBC3 (reserved) | |
| 28 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBC_4: PBC4 Reserved (was: RCmd TTag received with illegal group ID) | |
| 29 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBC_5: PBC5 Reserved (was: RCmd TTag received with illegal chip ID) | |
| 30 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBC_6: PBC6 Reserved (was: CResp TTag received with illegal group ID) | |
| 31 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBC_7: PBC7 Reserved (was: CResp TTag received with illegal chip ID) | |
| 32 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBC_8: PBC8 RCmd received with disabled topo-idx in address | |
| 33 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBC_9: PBC9 (reserved) | |
| 34 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBC_10: PBC10 (reserved) | |
| 35 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBC_11: PBC11 (reserved) | |
| 36 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_0: NLG0 RCmd Pre-Snoop table lookup missed the table | |
| 37 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_1: NLG1 (reserved) | |
| 38 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_2: NLG2 Req-in logic dropped an ATS-response | |
| 39 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_3: NLG3 (reserved) | |
| 40 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_4: NLG4 RCmd Final-Snoop Coll-Shd table lookup missed the table | |
| 41 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_5: NLG5 CAM lookup hit multiple snarf-cpm entries (multiple probes received from GPU) | |
| 42 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_6: NLG6 Arb request-in queue overflowed | |
| 43 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_7: NLG7 RCmd Final-Snoop coll collision/lpc table lookup missed the table | |
| 44 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_8: NLG8 RCmd Final-Snoop dir C2/L2-directory table lookup missed the table | |
| 45 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_9: NLG9 RCmd Final-Snoop Coll-Retry-Spec table lookup missed the table | |
| 46 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_10: NLG10 RCmd Final-Snoop Coll-Retry-HPC table lookup missed the table | |
| 47 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_11: NLG11 RCmd Final-Snoop Coll-Retry-Prot table lookup missed the table | |
| 48 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_12: NLG12 RCmd Final-Snoop Coll-Retry-RColl table lookup missed the table | |
| 49 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_13: NLG13 RCmd Final-Snoop Coll-Pocket-Hit table lookup missed the table | |
| 50 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_14: NLG14 RCmd Final-Snoop Coll-Accept table lookup missed the table | |
| 51 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_15: NLG15 RCmd Final-Snoop Dir-Shd table lookup missed the table | |
| 52 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_16: NLG16 RCmd Final-Snoop Dir-Rty table lookup missed the table | |
| 53 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_17: NLG17 RCmd Final-Snoop Dir-MMU(Ix) table lookup missed the table | |
| 54 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_18: NLG18 RCmd Final-Snoop Dir C2/L2 directory impossible command/state combination | |
| 55 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_19: NLG19 RCmd Final-Snoop Dir-Snoop-SFE table lookup missed the table | |
| 56 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_20: NLG20 RCmd Final-Snoop Dir-Snoop-Mod table lookup missed the table | |
| 57 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_21: NLG21 RCmd Final-Snoop Dir-Mod table lookup missed the table | |
| 58 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_22: NLG22 RCmd Final-Snoop CAM-Shared table lookup missed the table | |
| 59 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_23: NLG23 An internal sequencer had an invalid state | |
| 60 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBF_0: PBF0 Addr_Error received for self-lpc command (SSF) | |
| 61 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBF_1: PBF1 (reserved) | |
| 62 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBF_2: PBF2 (reserved) | |
| 63 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBF_3: PBF3 (reserved) | |
| Perf Address Match | ||||
|---|---|---|---|---|
| Addr: |
00000000110108B6 (SCOM) 00000000134102B0 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.SNP.MISC.PERF_ADDR_CONFIG | |||
| Constant(s): | ||||
| Comments: | Performance Address Match | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:43 | PAU3.CS.SM1.SNP.MISC.PERF_ADDR_CONFIG_Q_0_INST.LATC.L2(0:43) [00000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:5 | RW | RW | PERF_SIZE_ADDR: Size of address range to match 35 = 64K 34 = 128K ... 25 = 64M 15 = 64G 10 = 2T 0 = 2P | |
| 6:41 | RW | RW | PERF_MATCH_ADDR: Address to match | |
| 42:43 | RW | RW | PERF_ADDR_RESERVED1: reserved | |
| 44:63 | RO | RO | constant=0b00000000000000000000 | |
| Perf Match Reg | ||||
|---|---|---|---|---|
| Addr: |
00000000110108B7 (SCOM) 00000000134102B8 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.SNP.MISC.PERF_MATCH_CONFIG | |||
| Constant(s): | ||||
| Comments: | Performance Event Field Match | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:39 | PAU3.CS.SM1.SNP.MISC.PERF_MATCH_CONFIG_Q_0_INST.LATC.L2(0:39) [0000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:4 | RW | RW | PERF_MATCH_ALLOC_CLASS: Allocation Class / Source bus | |
| 5:16 | RW | RW | PERF_MATCH_TTYPE: TType | |
| 17:24 | RW | RW | PERF_MATCH_TSIZE: TSize | |
| 25 | RW | RW | PERF_MATCH_NVBE: NVLink byte enables | |
| 26 | RW | RW | PERF_MATCH_UT: NVLink UT | |
| 27:33 | RW | RW | PERF_MATCH_ATYPE: Address Type | |
| 34:39 | RW | RW | PERF_MATCH_ALLOC: Alloc | |
| 40:63 | RO | RO | constant=0b000000000000000000000000 | |
| Perf Mask Reg | ||||
|---|---|---|---|---|
| Addr: |
00000000110108B8 (SCOM) 00000000134102C0 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.SNP.MISC.PERF_MASK_CONFIG | |||
| Constant(s): | ||||
| Comments: | Performance Event Field Mask | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:39 | PAU3.CS.SM1.SNP.MISC.PERF_MASK_CONFIG_Q_0_INST.LATC.L2(0:39) [0000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:4 | RW | RW | PERF_MASK_ALLOC_CLASS: Allocation Class / Source bus | |
| 5:16 | RW | RW | PERF_MASK_TTYPE: TType | |
| 17:24 | RW | RW | PERF_MASK_TSIZE: TSize | |
| 25 | RW | RW | PERF_MASK_NVBE: NVLink byte enables | |
| 26 | RW | RW | PERF_MASK_UT: NVLink UT | |
| 27:33 | RW | RW | PERF_MASK_ATYPE: Address Type | |
| 34:39 | RW | RW | PERF_MASK_ALLOC: Alloc | |
| 40:63 | RO | RO | constant=0b000000000000000000000000 | |
| Debug0 Config Reg | ||||
|---|---|---|---|---|
| Addr: |
00000000110108B9 (SCOM) 00000000134102C8 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.SNP.MISC.DEBUG0_CONFIG | |||
| Constant(s): | ||||
| Comments: | Config register for trace-0 chain | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM1.SNP.MISC.DEBUG0_CONFIG_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:4 | RW | RW | DEBUG0_CONFIG_POD0: Mux control for byte 0 of trace-0 | |
| 5:9 | RW | RW | DEBUG0_CONFIG_POD1: Mux control for byte 1 of trace-0 | |
| 10:14 | RW | RW | DEBUG0_CONFIG_POD2: Mux control for byte 2 of trace-0 | |
| 15:19 | RW | RW | DEBUG0_CONFIG_POD3: Mux control for byte 3 of trace-0 | |
| 20:24 | RW | RW | DEBUG0_CONFIG_POD4: Mux control for byte 4 of trace-0 | |
| 25:29 | RW | RW | DEBUG0_CONFIG_POD5: Mux control for byte 5 of trace-0 | |
| 30:34 | RW | RW | DEBUG0_CONFIG_POD6: Mux control for byte 6 of trace-0 | |
| 35:39 | RW | RW | DEBUG0_CONFIG_POD7: Mux control for byte 7 of trace-0 | |
| 40:44 | RW | RW | DEBUG0_CONFIG_POD8: Mux control for byte 8 of trace-0 | |
| 45:49 | RW | RW | DEBUG0_CONFIG_POD9: Mux control for byte 9 of trace-0 | |
| 50:54 | RW | RW | DEBUG0_CONFIG_POD10: Mux control for byte 10 of trace-0 | |
| 55:62 | RW | RW | DEBUG0_CONFIG_RESERVED1: reserved | |
| 63 | RW | RW | DEBUG0_CONFIG_ACT: Enable clock-gates for debug trace latches | |
| Debug1 Config Reg | ||||
|---|---|---|---|---|
| Addr: |
00000000110108BA (SCOM) 00000000134102D0 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.SNP.MISC.DEBUG1_CONFIG | |||
| Constant(s): | ||||
| Comments: | Config register for trace-1 chain | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM1.SNP.MISC.DEBUG1_CONFIG_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:4 | RW | RW | DEBUG1_CONFIG_POD0: Mux control for byte 0 of trace-1 | |
| 5:9 | RW | RW | DEBUG1_CONFIG_POD1: Mux control for byte 1 of trace-1 | |
| 10:14 | RW | RW | DEBUG1_CONFIG_POD2: Mux control for byte 2 of trace-1 | |
| 15:19 | RW | RW | DEBUG1_CONFIG_POD3: Mux control for byte 3 of trace-1 | |
| 20:24 | RW | RW | DEBUG1_CONFIG_POD4: Mux control for byte 4 of trace-1 | |
| 25:29 | RW | RW | DEBUG1_CONFIG_POD5: Mux control for byte 5 of trace-1 | |
| 30:34 | RW | RW | DEBUG1_CONFIG_POD6: Mux control for byte 6 of trace-1 | |
| 35:39 | RW | RW | DEBUG1_CONFIG_POD7: Mux control for byte 7 of trace-1 | |
| 40:44 | RW | RW | DEBUG1_CONFIG_POD8: Mux control for byte 8 of trace-1 | |
| 45:49 | RW | RW | DEBUG1_CONFIG_POD9: Mux control for byte 9 of trace-1 | |
| 50:54 | RW | RW | DEBUG1_CONFIG_POD10: Mux control for byte 10 of trace-1 | |
| 55:62 | RW | RW | DEBUG1_CONFIG_RESERVED1: reserved | |
| 63 | RW | RW | DEBUG1_CONFIG_ACT: Enable clock-gates for debug trace latches | |
| L2 Directory SCOM address register | ||||
|---|---|---|---|---|
| Addr: |
00000000110108BB (SCOM) 00000000134102D8 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.SNP.MISC.SCOM_L2_ADDR | |||
| Constant(s): | ||||
| Comments: | register to initiate SCOM reads of the L2 direcotry | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:15 | PAU3.CS.SM1.SNP.MISC.SCOM_L2_ADDR_Q_0_INST.LATC.L2(0:15) [0000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX | RWX | SCOM_L2_VALID: Valid read Write 1 initiates a SCOM access Returns to 0 when access is finished and data is available in the DIR scom_l2_data register | |
| 1:3 | RW | RW | SCOM_L2_ADDR_RESERVED1: reserved | |
| 4:13 | RW | RW | SCOM_L2_CCI: Directory Congruence Class Index (aka SRAM address) to read | |
| 14:15 | RW | RW | SCOM_L2_WAY: Directory 'way' to read | |
| 16:63 | RO | RO | constant=0b000000000000000000000000000000000000000000000000 | |
| Topology Table register 0 | ||||
|---|---|---|---|---|
| Addr: |
00000000110108BC (SCOM) 00000000134102E0 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.SNP.MISC.TOPOLOGY_TABLE0 | |||
| Constant(s): | ||||
| Comments: | Defines topology mapping for toplogy indexes 0 through 7 Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:39 | PAU3.CS.SM1.SNP.MISC.TOPOLOGY_TABLE0_Q_0_INST.LATC.L2(0:39) [0000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:7 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENABLE_0_7: Enable bit for entries 0 through 7 | |
| 8:11 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY0: Topology ID(0:3) for Topology Index 0 | |
| 12:15 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY1: Topology ID(0:3) for Topology Index 1 | |
| 16:19 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY2: Topology ID(0:3) for Topology Index 2 | |
| 20:23 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY3: Topology ID(0:3) for Topology Index 3 | |
| 24:27 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY4: Topology ID(0:3) for Topology Index 4 | |
| 28:31 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY5: Topology ID(0:3) for Topology Index 5 | |
| 32:35 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY6: Topology ID(0:3) for Topology Index 6 | |
| 36:39 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY7: Topology ID(0:3) for Topology Index 7 | |
| 40:63 | RO | RO | constant=0b000000000000000000000000 | |
| Topology Table register 1 | ||||
|---|---|---|---|---|
| Addr: |
00000000110108BD (SCOM) 00000000134102E8 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.SNP.MISC.TOPOLOGY_TABLE1 | |||
| Constant(s): | ||||
| Comments: | Defines topology mapping for toplogy indexes 8 through 15 Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:39 | PAU3.CS.SM1.SNP.MISC.TOPOLOGY_TABLE1_Q_0_INST.LATC.L2(0:39) [0000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:7 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENABLE_8_15: Enable bit for entries 8 through 15 | |
| 8:11 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY8: Topology ID(0:3) for Topology Index 8 | |
| 12:15 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY9: Topology ID(0:3) for Topology Index 9 | |
| 16:19 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY10: Topology ID(0:3) for Topology Index 10 | |
| 20:23 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY11: Topology ID(0:3) for Topology Index 11 | |
| 24:27 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY12: Topology ID(0:3) for Topology Index 12 | |
| 28:31 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY13: Topology ID(0:3) for Topology Index 13 | |
| 32:35 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY14: Topology ID(0:3) for Topology Index 14 | |
| 36:39 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY15: Topology ID(0:3) for Topology Index 15 | |
| 40:63 | RO | RO | constant=0b000000000000000000000000 | |
| Topology Table register 2 | ||||
|---|---|---|---|---|
| Addr: |
00000000110108BE (SCOM) 00000000134102F0 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.SNP.MISC.TOPOLOGY_TABLE2 | |||
| Constant(s): | ||||
| Comments: | Defines topology mapping for toplogy indexes 16 through 23 Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:39 | PAU3.CS.SM1.SNP.MISC.TOPOLOGY_TABLE2_Q_0_INST.LATC.L2(0:39) [0000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:7 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENABLE_16_23: Enable bit for entries 16 through 23 | |
| 8:11 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY16: Topology ID(0:3) for Topology Index 16 | |
| 12:15 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY17: Topology ID(0:3) for Topology Index 17 | |
| 16:19 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY18: Topology ID(0:3) for Topology Index 18 | |
| 20:23 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY19: Topology ID(0:3) for Topology Index 19 | |
| 24:27 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY20: Topology ID(0:3) for Topology Index 20 | |
| 28:31 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY21: Topology ID(0:3) for Topology Index 21 | |
| 32:35 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY22: Topology ID(0:3) for Topology Index 22 | |
| 36:39 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY23: Topology ID(0:3) for Topology Index 23 | |
| 40:63 | RO | RO | constant=0b000000000000000000000000 | |
| Topology Table register 3 | ||||
|---|---|---|---|---|
| Addr: |
00000000110108BF (SCOM) 00000000134102F8 (PAU_RING) | |||
| Name: | PAU3.CS.SM1.SNP.MISC.TOPOLOGY_TABLE3 | |||
| Constant(s): | ||||
| Comments: | Defines topology mapping for toplogy indexes 24 through 31 Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:39 | PAU3.CS.SM1.SNP.MISC.TOPOLOGY_TABLE3_Q_0_INST.LATC.L2(0:39) [0000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:7 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENABLE_24_31: Enable bit for entries 24 through 31 | |
| 8:11 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY24: Topology ID(0:3) for Topology Index 24 | |
| 12:15 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY25: Topology ID(0:3) for Topology Index 25 | |
| 16:19 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY26: Topology ID(0:3) for Topology Index 26 | |
| 20:23 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY27: Topology ID(0:3) for Topology Index 27 | |
| 24:27 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY28: Topology ID(0:3) for Topology Index 28 | |
| 28:31 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY29: Topology ID(0:3) for Topology Index 29 | |
| 32:35 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY30: Topology ID(0:3) for Topology Index 30 | |
| 36:39 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY31: Topology ID(0:3) for Topology Index 31 | |
| 40:63 | RO | RO | constant=0b000000000000000000000000 | |
| CQ_SM Misc Config register #0 | ||||
|---|---|---|---|---|
| Addr: |
00000000110108C0 (SCOM) 0000000013420000 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.MCP.MISC.CONFIG0 | |||
| Constant(s): | ||||
| Comments: | Misc config register Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM2.MCP.MISC.CONFIG0_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_MA_DSA_OPT_CLAIM_UR: 0/1 = use Read.RWC/Upgrade.DN for dclaim/dcbz to GPU Mem | |
| 1 | RW | RW | CONFIG_MA_DSA_OPT_FLUSH_UR: 0/1 = use Read.RWC/Upgrade.DN for dcbf/dcbfc to GPU Mem | |
| 2 | RW | RW | CONFIG_MA_DSA_OPT_RP_MODE: 0/1 = use DMA/Read-Push for Write.NC to Proc Mem | |
| 3 | RW | RW | CONFIG_ADR_BAR_MODE: Reserved (was: PowerBus adr_bar: 0/1 = large-system-mode/small-system-mode) | |
| 4 | RW | RW | CONFIG_DISABLE_NN_RN: PowerBus scope: 0/1 = Enable Nn & Rn scopes / Disable Nn & Rn scopes | |
| 5 | RW | RW | CONFIG_DISABLE_VG_NOT_SYS: PowerBus scope: 0/1 = Enable Vg less than sys / Force all Vg to sys | |
| 6 | RW | RW | CONFIG_DISABLE_G: PowerBus scope: 0/1 = Enable G scope / Disable G scope | |
| 7 | RW | RW | CONFIG_DISABLE_LN: PowerBus scope: 0/1 = Enable Ln scope / Disable Ln scope | |
| 8 | RW | RW | CONFIG_SKIP_G: PowerBus scope: 0/1 = Allow G on rty_inc / Skip G on rty_inc | |
| 9 | RW | RW | CONFIG_MA_MCRESP_OPT_WRP: 0/1 = increase scope on rty_inc to dma_w / use write-read-push on rty_inc to dma_w | |
| 10 | RW | RW | CONFIG_USE_CL_DMA_W: 0/1 = Start cache-line DMA writes using cl_dma_inj / using cl_dma_w | |
| 11 | RW | RW | CONFIG_USE_DMA_PR_W: 0/1 = Start partial-line DMA writes using pr_dma_inj / using dma_pr_w | |
| 12:14 | RW | RW | CONFIG_INC_PRI_MASK: Mask select for priority increase due to rty_drp 0: 100% chance to increase priority 1: 50% chance to increase priority 2: 25% chance to increase priority 3: 12.5% chance to increase priority 4: 6% chance to increase priority 5: 3% chance to increase priority 6,7: 1.5% chance to increase priority | |
| 15 | RW | RW | CONFIG_MACH_CORRENAB: 0/1 = disable/enable state machine array ECC correction | |
| 16 | RW | RW | CONFIG_MACH_INJECT_ENABLE1: 0/1 = disable/enable state machine array ECC error inject bit 1 | |
| 17 | RW | RW | CONFIG_MACH_INJECT_ENABLE2: 0/1 = disable/enable state machine array ECC error inject bit 2 | |
| 18 | RW | RW | CONFIG_RXO_CORRENAB: 0/1 = disable/enable ReqRspOut array ECC correction | |
| 19 | RW | RW | CONFIG_RXO_INJECT_ENABLE1: 0/1 = disable/enable ReqRspOut array ECC error inject bit 1 | |
| 20 | RW | RW | CONFIG_RXO_INJECT_ENABLE2: 0/1 = disable/enable ReqRspOut array ECC error inject bit 2 | |
| 21 | RW | RW | CONFIG_RSI_CORRENAB: 0/1 = disable/enable PB-Rsp-In array ECC correction | |
| 22 | RW | RW | CONFIG_RSI_INJECT_ENABLE1: 0/1 = disable/enable PB-Rsp-In array ECC error inject bit 1 | |
| 23 | RW | RW | CONFIG_RSI_INJECT_ENABLE2: 0/1 = disable/enable PB-Rsp-In array ECC error inject bit 2 | |
| 24 | RW | RW | CONFIG_MA_DSA_OPT_DMA_UPG: 0/1 = non-relaxed dma_w use Read.RWC/Upgrade.DN to acquire pocket-cache state/data | |
| 25 | RW | RW | CONFIG_EVAPORATE_BY_LCO: 0/1 = just free the state-machine without lco/evaporate pocket-cache entries by lco | |
| 26 | RW | RW | CONFIG_ENABLE_PBUS: 0/1 = disable PAU PowerBus RCmd, PResp, and CResp interfaces / enable these interfaces Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 27 | RW | RW | CONFIG_ENABLE_SNARF_CPM: 0/1 = disable/enable Probe.I.MO snarfing a cp_m | |
| 28 | RW | RW | CONFIG_DISABLE_INJECT: 0/1 = enable sending cl,pr_dma_inj / disable sending cl,pr_dma_inj Note: to truly disable sending _inj commands, the following bits must also be set to '0': config_ma_dsa_opt_rp_mode | |
| 29 | RW | RW | CONFIG_DCACHE_MODE: 0/1 = drive data-bus dcache field in basic mode / CAPP mode. | |
| 30 | RW | RW | CONFIG_DCACHE_REPORTS_PHYSICAL: 0/1 = in basic mode, report local masters as near / local. | |
| 31 | RW | RW | CONFIG_RSI_DISABLE_DATIN_FASTPATH: 0/1 = enable rsi PB data-in fastpath/disable fastpath | |
| 32 | RW | RW | CONFIG_FORBID_MMIO_READ_GT_32: 0/1 = Allow GPU->PB MMIOs > 32-bytes / flag-error & brick-fence on MMIOs > 32-bytes | |
| 33 | RW | RW | CONFIG_FORBID_MMIO_ATOMIC: 0/1 = Allow GPU->PB atomics to MMIO space / flag-error & brick-fence on atomics to MMIO space | |
| 34 | RW | RW | CONFIG_DISABLE_HW555363_FASTPATH_AND_FENCE: 0/1 = enable HW555363 fix for fence happening between fastpath RCmd and CResp / disable fix. | |
| 35 | RW | RW | CONFIG0_RESERVED1: reserved | |
| 36 | RW | RW | CONFIG_ENABLE_CONTEXT_LCO: 0/1 = disable LCOing context entries into L3/enable LCOing context entries into L3 | |
| 37 | RW | RW | CONFIG_MA_DSA_OPT_FAIL_WAKE: 0/1 = send wake_host_thread to PB as asb_notify / fail all wake_host_thread w/ thread-not-found status (no PB asb_notify) | |
| 38 | RW | RW | CONFIG_ENABLE_FAST_DIR_UPDATE: 0/1 = disable directory fast update from mach pipe / enable directory fast update from mach pipe | |
| 39 | RW | RW | CONFIG_OPT_MES_USE_GO_M: 0/1 = read_mes w/ RW authority uses rd_go_s/rd_go_m to acquire the line | |
| 40 | RW | RW | CONFIG_OPT_LCO_M_USE_MU: 0/1 = use lco_m to inject a modified line into an L3 / use lco_mu | |
| 41 | RW | RW | CONFIG_OPT_SNOOP_EX_LCO: 0/1 = use cp_* when a castout.push(128B)->I is due to a snoop against an exclusive directory entry / use an lco_m,mu | |
| 42 | RW | RW | CONFIG_ENABLE_CP_ME: 0/1 = disable sending cp_me / enable cp_me when a cleaning E->I and homed off-node. | |
| 43 | RW | RW | CONFIG_FENCE_ON_DERR_MMIO: 0/1 = write SUE data to MMIO on data error from OCAPI / fence brick (note: dual NVF10/OCR7 error flagged) | |
| 44 | RW | RW | CONFIG_BRK0_OCAPI_MODE: 0/1 = Disable OpenCAPI mode / enable OpenCAPI mode for brick 0 (mutually exclusive with config_brk0_nvlink_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 45 | RW | RW | CONFIG_BRK1_OCAPI_MODE: 0/1 = Disable OpenCAPI mode / enable OpenCAPI mode for brick 1 (mutually exclusive with config_brk1_nvlink_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 46 | RW | RW | CONFIG_BRK2_OCAPI_MODE: 0/1 = Disable OpenCAPI mode / enable OpenCAPI mode for brick 2 (mutually exclusive with config_brk2_nvlink_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 47 | RW | RW | CONFIG_BRK3_OCAPI_MODE: 0/1 = Disable OpenCAPI mode / enable OpenCAPI mode for brick 3 (mutually exclusive with config_brk3_nvlink_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 48 | RW | RW | CONFIG_BRK4_OCAPI_MODE: 0/1 = Disable OpenCAPI mode / enable OpenCAPI mode for brick 4 (mutually exclusive with config_brk4_nvlink_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 49 | RW | RW | CONFIG_BRK0_NVLINK_MODE: 0/1 = Disable NVLink mode / enable NVLink mode for brick 0 (mutually exclusive with config_brk0_ocapi_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 50 | RW | RW | CONFIG_BRK1_NVLINK_MODE: 0/1 = Disable NVLink mode / enable NVLink mode for brick 1 (mutually exclusive with config_brk1_ocapi_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 51 | RW | RW | CONFIG_BRK2_NVLINK_MODE: 0/1 = Disable NVLink mode / enable NVLink mode for brick 2 (mutually exclusive with config_brk2_ocapi_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 52 | RW | RW | CONFIG_BRK3_NVLINK_MODE: 0/1 = Disable NVLink mode / enable NVLink mode for brick 3 (mutually exclusive with config_brk3_ocapi_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 53 | RW | RW | CONFIG_BRK4_NVLINK_MODE: 0/1 = Disable NVLink mode / enable NVLink mode for brick 4 (mutually exclusive with config_brk4_ocapi_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 54 | RW | RW | CONFIG_BRK0_POISON_FENCE_L2: 0/1 = write all-ones-good-ECC/all-ones-SUE to E/Ei/M L2 directory entries when brick 0 is fenced Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 55 | RW | RW | CONFIG_BRK1_POISON_FENCE_L2: 0/1 = write all-ones-good-ECC/all-ones-SUE to E/Ei/M L2 directory entries when brick 0 is fenced Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 56:58 | RW | RW | CONFIG0_RESERVED0: reserved | |
| 59 | RW | RW | CONFIG_BRK0_IMP_TAGS_MODE_ENABLE: 0/1 = disable IMP (HAPPI) iseries tags mode / enable tags mode for brick 0 Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 60 | RW | RW | CONFIG_BRK1_IMP_TAGS_MODE_ENABLE: 0/1 = disable IMP (HAPPI) iseries tags mode / enable tags mode for brick 1 Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 61 | RW | RW | CONFIG_BRK2_IMP_TAGS_MODE_ENABLE: 0/1 = disable IMP (HAPPI) iseries tags mode / enable tags mode for brick 2 Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 62 | RW | RW | CONFIG_BRK3_IMP_TAGS_MODE_ENABLE: 0/1 = disable IMP (HAPPI) iseries tags mode / enable tags mode for brick 3 Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 63 | RW | RW | CONFIG_BRK4_IMP_TAGS_MODE_ENABLE: 0/1 = disable IMP (HAPPI) iseries tags mode / enable tags mode for brick 4 Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| CQ_SM Misc Config register #1 | ||||
|---|---|---|---|---|
| Addr: |
00000000110108C1 (SCOM) 0000000013420008 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.MCP.MISC.CONFIG1 | |||
| Constant(s): | ||||
| Comments: | Misc config register Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM2.MCP.MISC.CONFIG1_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:3 | RW | RW | CONFIG_RANDOM_BACKOFF_DUR_MASK: Mask for the base random duration of a random retry backoff 0000 -> 0-15 base random duration 0001 -> 0-31 base random duration 0011 -> 0-63 base random duration 0111 -> 0-127 base random duration 1111 -> 0-255 base random duration | |
| 4:7 | RW | RW | CONFIG_CHGRATE_HANG_SLOWDOWN_REQ: Mask for for the slowdown of NTL CReq or OCAPI TLX.vc.3 credits during chgrate.hang 'n' -> 1/(2^(n+1)) cycles average rate Note that for a single PowerBus ramp, the rate is actually 8 times faster since there are 4 RCmd slice x 2 NTL Bricks that get CReq credits. This field is the rate for 1 brick receiving credit from 1 RCmd slice. | |
| 8:11 | RW | RW | CONFIG_CHGRATE_HANG_SLOWDOWN_CST: Mask for for the slowdown of OCAPI TLX.vc.2 credits during chgrate.hang 'n' -> 1/(2^(n+1)) cycles average rate Note that for a single PowerBus ramp, the rate is actually 8 times faster since there are 4 RCmd slice x 2 NTL Bricks that get CReq credits. This field is the rate for 1 brick receiving credit from 1 RCmd slice. | |
| 12:15 | RW | RW | CONFIG_CHGRATE_HANG_SLOWDOWN_PRB: Mask for for the slowdown of NTL Probe or OCAPI TLX.vc.1 credits during chgrate.hang 'n' -> 1/(2^(n+1)) cycles average rate Note that for a single PowerBus ramp, the rate is actually 8 times faster since there are 4 RCmd slice x 2 NTL Bricks that get CReq credits. This field is the rate for 1 brick receiving credit from 1 RCmd slice. | |
| 16:27 | RW | RW | CONFIG_EPSILON_WLN_COUNT: epsilon count for Ln scope CP-Write | |
| 28 | RW | RW | CONFIG_MIMIRROR_MASTER_ENABLE: 0/1 = disable MI mirroring support / enable MI mirroring | |
| 29:31 | RW | RW | CONFIG_MIMIRROR_BRICK_MODE: Primary & Secondary bricks are: 000 = Primary is brick 0, brick 1 not used 001 = Primary is brick 1, brick 0 not used 010 = Primary is brick 0, stores mirror to brick 1 011 = Primary is brick 1, stores mirror to brick 0 100 = Primary is brick 0, stores mirror to brick 1, loads can failover to brick 1 101 = Primary is brick 1, stores mirror to brick 0, loads can failover to brick 0 110 = Primary brick is addr(54), stores mirror to both bricks, loads can failover to the other brick 111 = Primary brick is random, stores mirror to both bricks, loads can failover to the other brick | |
| 32 | RW | RW | CONFIG_MIMIRROR_FENCE_ON_BAD_DATA: 0/1 = don't force fence for bad_data responses / force fence when bad_data arrives in a response. | |
| 33:34 | RW | RW | CONFIG1_RESERVED2: reserved | |
| 35 | RW | RW | CONFIG_PCKT_LONG_CL_DMA_INJ: 0/1 = allow cl_dma_inj to use short pocket-cache timer/ force cl_dma_inj to use long pocket-cache timer | |
| 36 | RW | RW | CONFIG_PCKT_LONG_PR_DMA_INJ: 0/1 = allow pr_dma_inj to use short pocket-cache timer/ force pr_dma_inj to use long pocket-cache timer | |
| 37:42 | RW | RW | CONFIG_PCKT_LONG_MIN_COUNT: Minimum number of state-machine w/ long pocket-cache timers before short timers can be used | |
| 43 | RW | RW | CONFIG_PCKT_LONG_USES_HANG: 0/1 = use config_pocket_long_rate2 / use rpt_hang.poll ticks to drive long pocket-cache timer | |
| 44 | RW | RW | CONFIG_DONT_RETRY_LCO_LONG: reserved (was config_dont_retry_lco_long) | |
| 45 | RW | RW | CONFIG_DONT_RETRY_LCO_LONG_STRESSED: reserved (was config_dont_retry_lco_long_stressed). | |
| 46 | RW | RW | CONFIG_DONT_RETRY_LCO_SHORT: reserved (was config_dont_retry_lco_short) | |
| 47 | RW | RW | CONFIG_DONT_RETRY_LCO_SHORT_STRESSED: reserved (was config_dont_retry_lco_short_stressed). | |
| 48 | RW | RW | CONFIG_STOP_ASB_AT_LN_SCOPE: 0/1 = increase to asb_notify to G scope / stop and return thread-not-found when asb_notify @ Ln scope doesn't find the thread | |
| 49 | RW | RW | CONFIG_STOP_ASB_AT_G_SCOPE: 0/1 = increase to asb_notify to Vg(sys) scope / stop and return thread-not-found when asb_notify @ G scope doesn't find the thread | |
| 50 | RW | RW | CONFIG_INITIAL_HPC_PROBE_PRIORITY: Initial drop_priority value when mastering an hpc_probe | |
| 51 | RW | RW | CONFIG_NVLINK_P10P10_MODE: 0/1 = normal NVLink mode / special lab-debug-only P10-to-P10 NVLink mode | |
| 52 | RW | RW | CONFIG_HANG_ON_ADDRESS_ERRORS: 0/1 = abort and continue on CResp=addr_error / hang state-machine on CResp=addr_error | |
| 53 | RW | RW | CONFIG_DISABLE_HW525464_CLEAN_XUE_FENCE_PB: 0/1 = enable HW525464 fix for cleaning XUE data on fence of pb cmd / disable fix. | |
| 54 | RW | RW | CONFIG_DISABLE_HW517903_BAD_SYNC: 0/1 = handle bad sync in non-4.0 mode / disable fix. | |
| 55 | RW | RW | CONFIG_DISABLE_HW526620_BAD_SYN_DONE: 0/1 = handle mis-aligned synonym_done / disable fix. | |
| 56 | RW | RW | CONFIG_ENABLE_OPENCAPI_NETWORKING: 0/1 = disable networking / enable OpenCAPI MI networking mode. | |
| 57 | RW | RW | CONFIG_NET0_TORUS_MODE: 0/1 = Dragonfly network mode / Torus network mode for brick 0 | |
| 58 | RW | RW | CONFIG_NET1_TORUS_MODE: 0/1 = Dragonfly network mode / Torus network mode for brick 1 | |
| 59 | RW | RW | CONFIG_DISABLE_HW532477_ARMWF_IMP_TAGS_RESET: 0/1 = Enable resetting itags after transmitting armwf data / disable fix | |
| 60 | RW | RW | CONFIG_DISABLE_HW536051_FENCE_HOSPICE_PRONOTE: 0/1 = Enable an extra dirscan before waiting for REQ to drain / disable fix | |
| 61 | RW | RW | CONFIG_DISABLE_HW537584_HOSPICE_QUALIFIER: 0/1 = Enable correctly qualifying hp_vec_empty with dir_allocated to indicate hospice / disable fix | |
| 62 | RW | RW | CONFIG_DISABLE_HW546460_INC_DEC_ALL_ONES: 0/1 = Enable IM-network brick4-fence causing inc/dec atomics to return all ones / disable fix | |
| 63 | RW | RW | CONFIG_ENABLE_HW555343_ALL_PTL_ARE_BE: 0/1 = disable HW555343 fix / enable fix to convert all partial writes to byte-enable writes. | |
| PowerBus Epsilon | ||||
|---|---|---|---|---|
| Addr: |
00000000110108C2 (SCOM) 0000000013420010 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.MCP.MISC.EPSILON_CONFIG | |||
| Constant(s): | ||||
| Comments: | PowerBus Epsilon config register Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM2.MCP.MISC.EPSILON_CONFIG_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:3 | RW | RW | CONFIG_EPSILON_RATE: 0 = decrement epsilon count at 1:1 pau_clock_1to1 ... 15 = epsilon count at 1/16 pau_clock_1to1 | |
| 4:15 | RW | RW | CONFIG_EPSILON_W0_COUNT: epsilon count for Nn/G scope CP-Write | |
| 16:27 | RW | RW | CONFIG_EPSILON_W1_COUNT: epsilon count for Rn/Vg scope CP-Write | |
| 28:39 | RW | RW | CONFIG_EPSILON_R0_COUNT: epsilon count for Ln scope Reads | |
| 40:51 | RW | RW | CONFIG_EPSILON_R1_COUNT: epsilon count for Nn/G scope Reads | |
| 52:63 | RW | RW | CONFIG_EPSILON_R2_COUNT: epsilon count for Rn/Vg scope Reads | |
| Timer Config Reg | ||||
|---|---|---|---|---|
| Addr: |
00000000110108C3 (SCOM) 0000000013420018 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.MCP.MISC.XTIMER_CONFIG | |||
| Constant(s): | ||||
| Comments: | Timer Configuration Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:59 | PAU3.CS.SM2.MCP.MISC.XTIMER_CONFIG_Q_0_INST.LATC.L2(0:59) [000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:1 | RW | RW | CONFIG_POCKET_LONG_RATE1: Rate_1 for the Long Pocket-Cache timer. The Pocket-Cache timer is used to evaporate pocket-cache entries which are not claimed. The Long timer duration is f(Rate_1)*2^(Rate_2)*5e-10 seconds Unless config_pckt_long_uses_hang=1, then it is f(Rate1)*rpt_hang.poll interval. f(0b00) = 2 f(0b01) = 3 f(0b10) = 4 f(0b11) = 5 | |
| 2:7 | RW | RW | CONFIG_POCKET_LONG_RATE2: Rate_2 for the long timer for Pocket-Cache entries (2^n cycles). | |
| 8:13 | RW | RW | CONFIG_POCKET_SHORT_RATE2: Rate_2 for the short timer for Pocket-Cache entries (2^n cycles). | |
| 14:19 | RW | RW | CONFIG_FWD_PROG_RATE2: Rate_2 for the forward-progress timer (2^n cycles). | |
| 20:25 | RW | RW | CONFIG_XTIMER_RESERVED1: Reserved (was: Rate for CTL timer tick (default 63 = off)) | |
| 26:31 | RW | RW | CONFIG_INH0_TICK: Rate for SM-Inhibit timer tick0 (default 63 = off) Note: This field can/should have different values in each instance. No MDials have been created for this field's IDials | |
| 32:37 | RW | RW | CONFIG_INH1_TICK: Rate for SM-Inhibit timer tick1 (default 63 = off) Note: This field can/should have different values in each instance. No MDials have been created for this field's IDials | |
| 38:39 | RW | RW | CONFIG_NV_RESP_RATE1: Reserved (was: Rate_1 for NV-Response timer) | |
| 40:45 | RW | RW | CONFIG_NV_RESP_RATE2: Rate_2 for the NV-Response timer (2^n cycles). Overall timeout is (3 to 4)*(2^Rate_2)*5e-10 seconds. | |
| 46:47 | RW | RW | CONFIG_POCKET_SHORT_RATE1: Rate_1 for the Short Pocket-Cache timer. The Pocket-Cache timer is used to evaporate pocket-cache entries which are not claimed. the Short timer duration is f(Rate_1)*2^(Rate_2)*5e-10 seconds where f(Rate_1) is: f(0b00) = 7 f(0b01) = 63 f(0b10) = 511 f(0b11) = 4095 | |
| 48:53 | RW | RW | CONFIG_SCAN_WAIT_RATE: Rate for directory-scanning wait-walker 2^Rate cycles per tick | |
| 54:59 | RW | RW | CONFIG_EPOCH_RATE: Rate for epoch-checks Overall timeout is (2 to 3)*(2^Rate)*5e-10 seconds. | |
| 60:63 | RO | RO | constant=0b0000 | |
| Perf Config Reg | ||||
|---|---|---|---|---|
| Addr: |
00000000110108C4 (SCOM) 0000000013420020 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.MCP.MISC.PERF_CONFIG | |||
| Constant(s): | ||||
| Comments: | Performance Event selection | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM2.MCP.MISC.PERF_CONFIG_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:8 | RW | RW | PERF_CONFIG_LATSTART: Latency count start event | |
| 9:17 | RW | RW | PERF_CONFIG_LATCANCEL: Latency count abort event | |
| 18:26 | RW | RW | PERF_CONFIG_LATFINISH: Latency count finish event | |
| 27 | RW | RW | PERF_CONFIG_RESERVED1: reserved | |
| 28:35 | RW | RW | PERF_CONFIG_EVENT0: Event 0 select 0: count nothing 1: count cycles 2: count latency events (see latstart/cancel/finish fields) 3: count latency cycles (avg latency = cycles divided by events) 4: count latency aborts (start condition was detected, but finish condition was not) 5: count # Same-address checks detected a collision 6: count # Same-address checks detected no collision 7: count # CResps matching cresp + original command 8: count # of PB Cmds sent w/ matching scope 9: count # CResps matching cresp + scope + master command + original command 10: count # of PB Cmds sent w/ matching scope+command 11: count # of NV/OC Cmds sent w/ matching command 12: count # of NV/OC Resps sent w/ matching response(command) 13: count # of force_evicts sent due to dir-scan / XSL-castouts 14: count # of force_evicts sent due to sfe / PowerBus RCmd snoops 15: count # of force_evicts sent due to the other brick having state (needed by the requesting brick) 16: count # of force_evicts / EF responses sent due to capacity evicts in the L2 directory 17: count # of allocating C2 commands that update state in an existing directory entry (ie cacheline was alreayd present) 18: count # of allocating C2 commands that update state in a new directory entry (ie cacheline was not present in the directory) others: reserved (count nothing) | |
| 36:43 | RW | RW | PERF_CONFIG_EVENT1: Event 1 select See Event 0 select for encodes | |
| 44:51 | RW | RW | PERF_CONFIG_EVENT2: Event 2 select See Event 0 select for encodes | |
| 52:59 | RW | RW | PERF_CONFIG_EVENT3: Event 3 select See Event 0 select for encodes | |
| 60:61 | RW | RW | PERF_CONFIG_RESERVED2: reserved | |
| 62 | RW | RW | PERF_CONFIG_LATFILTER: 0/1 = count max latency events / filter latency events by 1/1024 for bias reduction | |
| 63 | RW | RW | PERF_CONFIG_ACT: Enable clock-gates for performance monitor latches | |
| Inhibit configuration Register | ||||
|---|---|---|---|---|
| Addr: |
00000000110108C5 (SCOM) 0000000013420028 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.MCP.MISC.INHIBIT_CONFIG | |||
| Constant(s): | ||||
| Comments: | Configures Inhibits for CQ_SM | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM2.MCP.MISC.INHIBIT_CONFIG_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:3 | RW | RW | CONFIG_INHIBIT_LFREQ0: Base LFSR frequency 0: 0..11 = 1/2^(n+1) 12 = 1/2^14 13 = 1/2^16 14 = 1/2^18 15 = 1/2^20 | |
| 4:5 | RW | RW | CONFIG_INHIBIT_PFREQ0: Selects pre frequency 0: 0 = Inhibit timer tick0 1 = inverted Inhibit timer tick0 2 = LFSR 3 = inverted LFSR (-> 1/2, 3/4, 7/8, ...) | |
| 6 | RW | RW | CONFIG_INHIBIT_BLOCKY0: 0/1 = disable blocky mode / enable blocky mode | |
| 7 | RW | RW | CONFIG_INHIBIT_ONESHOT0: 0/1 = continus mode / one-shot mode | |
| 8:15 | RW | RW | CONFIG_INHIBIT_DEST0: Selects the destination of the inhibit | |
| 16:19 | RW | RW | CONFIG_INHIBIT_LFREQ1: Base LFSR frequency 0: 0..12 = 1/2^(n+1) 13 = 1/2^16 14 = 1/2^18 15 = 1/2^20 | |
| 20:21 | RW | RW | CONFIG_INHIBIT_PFREQ1: Selects pre frequency 0: 0 = Inhibit timer tick1 1 = inverted Inhibit timer tick1 2 = LFSR 3 = inverted LFSR (-> 1/2, 3/4, 7/8, ...) | |
| 22 | RW | RW | CONFIG_INHIBIT_BLOCKY1: 0/1 = disable blocky mode / enable blocky mode | |
| 23 | RW | RW | CONFIG_INHIBIT_ONESHOT1: 0/1 = continus mode / one-shot mode | |
| 24:31 | RW | RW | CONFIG_INHIBIT_DEST1: Selects the destination of the inhibit | |
| 32:35 | RW | RW | CONFIG_INHIBIT_LFREQ2: Base LFSR frequency 2: 0..11 = 1/2^(n+1) 12 = 1/2^14 13 = 1/2^16 14 = 1/2^18 15 = 1/2^20 | |
| 36:37 | RW | RW | CONFIG_INHIBIT_PFREQ2: Selects pre frequency 2: 0 = Inhibit timer tick0 1 = inverted Inhibit timer tick0 2 = LFSR 3 = inverted LFSR (-> 1/2, 3/4, 7/8, ...) | |
| 38 | RW | RW | CONFIG_INHIBIT_BLOCKY2: 0/1 = disable blocky mode / enable blocky mode | |
| 39 | RW | RW | CONFIG_INHIBIT_ONESHOT2: 0/1 = continus mode / one-shot mode | |
| 40:47 | RW | RW | CONFIG_INHIBIT_DEST2: Selects the destination of the inhibit | |
| 48:51 | RW | RW | CONFIG_INHIBIT_LFREQ3: Base LFSR frequency 3: 0..12 = 1/2^(n+1) 13 = 1/2^16 14 = 1/2^18 15 = 1/2^20 | |
| 52:53 | RW | RW | CONFIG_INHIBIT_PFREQ3: Selects pre frequency 3: 0 = Inhibit timer tick1 1 = inverted Inhibit timer tick1 2 = LFSR 3 = inverted LFSR (-> 1/2, 3/4, 7/8, ...) | |
| 54 | RW | RW | CONFIG_INHIBIT_BLOCKY3: 0/1 = disable blocky mode / enable blocky mode | |
| 55 | RW | RW | CONFIG_INHIBIT_ONESHOT3: 0/1 = continus mode / one-shot mode | |
| 56:63 | RW | RW | CONFIG_INHIBIT_DEST3: Selects the destination of the inhibit | |
| c_err_rpt Message-0 latches | ||||
|---|---|---|---|---|
| Addr: |
00000000110108C6 (SCOM) 0000000013420030 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.MCP.MISC.CERR_MESSAGE0 | |||
| Constant(s): | ||||
| Comments: | Error message/capture register 0 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM2.MCP.MISC.CERR_MESSAGE0_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:63 | RWX_WCLRREG | RWX_WCLRREG | CERR_MESSAGE_BITS0: reserved | |
| c_err_rpt Message-1 latches | ||||
|---|---|---|---|---|
| Addr: |
00000000110108C7 (SCOM) 0000000013420038 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.MCP.MISC.CERR_MESSAGE1 | |||
| Constant(s): | ||||
| Comments: | Error message/capture register 1 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM2.MCP.MISC.CERR_MESSAGE1_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:63 | RWX_WCLRREG | RWX_WCLRREG | CERR_MESSAGE_BITS1: reserved | |
| c_err_rpt Message-2 latches | ||||
|---|---|---|---|---|
| Addr: |
00000000110108C8 (SCOM) 0000000013420040 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.MCP.MISC.CERR_MESSAGE2 | |||
| Constant(s): | ||||
| Comments: | Error message/capture register 2 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM2.MCP.MISC.CERR_MESSAGE2_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:63 | RWX_WCLRREG | RWX_WCLRREG | CERR_MESSAGE_BITS2: reserved | |
| c_err_rpt Message-3 latches | ||||
|---|---|---|---|---|
| Addr: |
00000000110108C9 (SCOM) 0000000013420048 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.MCP.MISC.CERR_MESSAGE3 | |||
| Constant(s): | ||||
| Comments: | Error message/capture register 3 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM2.MCP.MISC.CERR_MESSAGE3_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:63 | RWX_WCLRREG | RWX_WCLRREG | CERR_MESSAGE_BITS3: reserved | |
| c_err_rpt Message-4 latches | ||||
|---|---|---|---|---|
| Addr: |
00000000110108CA (SCOM) 0000000013420050 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.MCP.MISC.CERR_MESSAGE4 | |||
| Constant(s): | ||||
| Comments: | Error message/capture register 4 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM2.MCP.MISC.CERR_MESSAGE4_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:63 | RWX_WCLRREG | RWX_WCLRREG | CERR_MESSAGE_BITS4: reserved | |
| c_err_rpt Message-5 latches | ||||
|---|---|---|---|---|
| Addr: |
00000000110108CB (SCOM) 0000000013420058 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.MCP.MISC.CERR_MESSAGE5 | |||
| Constant(s): | ||||
| Comments: | Error message/capture register 5 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM2.MCP.MISC.CERR_MESSAGE5_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:63 | RWX_WCLRREG | RWX_WCLRREG | CERR_MESSAGE_BITS5: reserved | |
| c_err_rpt Message-6 latches | ||||
|---|---|---|---|---|
| Addr: |
00000000110108CC (SCOM) 0000000013420060 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.MCP.MISC.CERR_MESSAGE6 | |||
| Constant(s): | ||||
| Comments: | Error message/capture register 6 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM2.MCP.MISC.CERR_MESSAGE6_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:63 | RWX_WCLRREG | RWX_WCLRREG | CERR_MESSAGE_BITS6: reserved | |
| c_err_rpt Message-7 latches | ||||
|---|---|---|---|---|
| Addr: |
00000000110108CD (SCOM) 0000000013420068 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.MCP.MISC.CERR_MESSAGE7 | |||
| Constant(s): | ||||
| Comments: | Error message/capture register 7 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:39 | PAU3.CS.SM2.MCP.MISC.CERR_MESSAGE7_Q_0_INST.LATC.L2(0:39) [0000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:39 | RWX_WCLRREG | RWX_WCLRREG | CERR_MESSAGE_BITS7: reserved | |
| 40:63 | RO | RO | constant=0b000000000000000000000000 | |
| CQ_SM status register | ||||
|---|---|---|---|---|
| Addr: |
00000000110108CE (SCOM) 0000000013420070 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.MCP.MISC.SM_STATUS | |||
| Constant(s): | ||||
| Comments: | Status reporting register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM2.MCP.MISC.SM_STATUS_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:3 | ROX | ROX | SM_STATUS_MRBGP: Master-Retry backoff level for Group-Pump commands | |
| 4:7 | ROX | ROX | SM_STATUS_MRBSP: Master-Retry backoff level for System-Pump commands | |
| 8:11 | ROX | ROX | SM_STATUS_FENCE0: Brick-0 Fence sequencing state 0b0000 = Idle state, completely unfenced 0b0--- = in transition between fenced and not-fenced 0b10-- = in transition between fenced and not-fenced 0b1100 = Fenced state, fence sequencing complete 0b1101 = Flushing pocket-cache entries prior to exiting fence 0b1110 = Flushing pocket-cache entries prior to exiting fence 0b1111 = reserved | |
| 12:15 | ROX | ROX | SM_STATUS_FENCE1: Brick-1 Fence sequencing state 0b0000 = Idle state, completely unfenced 0b0--- = in transition between fenced and not-fenced 0b10-- = in transition between fenced and not-fenced 0b1100 = Fenced state, fence sequencing complete 0b1101 = Flushing pocket-cache entries prior to exiting fence 0b1110 = Flushing pocket-cache entries prior to exiting fence 0b1111 = reserved | |
| 16:19 | ROX | ROX | SM_STATUS_FENCE2: Brick-2 Fence sequencing state 0b0000 = Idle state, completely unfenced 0b0--- = in transition between fenced and not-fenced 0b10-- = in transition between fenced and not-fenced 0b1100 = Fenced state, fence sequencing complete 0b1101 = Flushing pocket-cache entries prior to exiting fence 0b1110 = Flushing pocket-cache entries prior to exiting fence 0b1111 = reserved | |
| 20:23 | ROX | ROX | SM_STATUS_FENCE3: Brick-3 Fence sequencing state 0b0000 = Idle state, completely unfenced 0b0--- = in transition between fenced and not-fenced 0b10-- = in transition between fenced and not-fenced 0b1100 = Fenced state, fence sequencing complete 0b1101 = Flushing pocket-cache entries prior to exiting fence 0b1110 = Flushing pocket-cache entries prior to exiting fence 0b1111 = reserved | |
| 24:27 | ROX | ROX | SM_STATUS_FENCE4: Brick-4 Fence sequencing state 0b0000 = Idle state, completely unfenced 0b0--- = in transition between fenced and not-fenced 0b10-- = in transition between fenced and not-fenced 0b1100 = Fenced state, fence sequencing complete 0b1101 = Flushing pocket-cache entries prior to exiting fence 0b1110 = Flushing pocket-cache entries prior to exiting fence 0b1111 = reserved | |
| 28 | ROX | ROX | SM_STATUS_PBLN: 1 when outbound Ln-scope PowerBus request queue is empty | |
| 29 | ROX | ROX | SM_STATUS_PBNNG: 1 when outbound Nn/G-scope PowerBus request queue is empty | |
| 30 | ROX | ROX | SM_STATUS_PBRNVG: 1 when outbound Rn/Vg-scope PowerBus request queue is empty | |
| 31 | ROX | ROX | SM_STATUS_B0REQ: 1 when outbound brick 0 CReq request queue is empty | |
| 32 | ROX | ROX | SM_STATUS_B0DGD: 1 when outbound brick 0 Downgrade request queue is empty | |
| 33 | ROX | ROX | SM_STATUS_B1REQ: 1 when outbound brick 1 CReq request queue is empty | |
| 34 | ROX | ROX | SM_STATUS_B1DGD: 1 when outbound brick 1 Downgrade request queue is empty | |
| 35 | ROX | ROX | SM_STATUS_B2REQ: 1 when outbound brick 2 CReq request queue is empty | |
| 36 | ROX | ROX | SM_STATUS_B2DGD: 1 when outbound brick 2 Downgrade request queue is empty | |
| 37 | ROX | ROX | SM_STATUS_B3REQ: 1 when outbound brick 3 CReq request queue is empty | |
| 38 | ROX | ROX | SM_STATUS_B3DGD: 1 when outbound brick 3 Downgrade request queue is empty | |
| 39 | ROX | ROX | SM_STATUS_B4REQ: 1 when outbound brick 4 CReq request queue is empty | |
| 40 | ROX | ROX | SM_STATUS_B4DGD: 1 when outbound brick 4 Downgrade request queue is empty | |
| 41 | ROX | ROX | SM_STATUS_MMIO: 1 when outbound MMIO/GenId request queue is empty | |
| 42 | ROX | ROX | SM_STATUS_MMIOSUE: 1 when outbound MMIO-SUE request queue is empty | |
| 43 | ROX | ROX | SM_STATUS_ATSXLATE: 1 when outbound ATS-TCE-Translation request queue is empty | |
| 44 | ROX | ROX | SM_STATUS_REPLAY: 1 when outbound replay-to-directory queue is empty | |
| 45 | ROX | ROX | SM_STATUS_PBRSP: 1 when outbound PowerBus data-response/merge-operation queue is empty | |
| 46 | ROX | ROX | SM_STATUS_B0RSP: 1 when outbound brick 0 response queue is empty | |
| 47 | ROX | ROX | SM_STATUS_B1RSP: 1 when outbound brick 1 response queue is empty | |
| 48 | ROX | ROX | SM_STATUS_B2RSP: 1 when outbound brick 2 response queue is empty | |
| 49 | ROX | ROX | SM_STATUS_B3RSP: 1 when outbound brick 3 response queue is empty | |
| 50 | ROX | ROX | SM_STATUS_B4RSP: 1 when outbound brick 4 response queue is empty | |
| 51 | ROX | ROX | SM_STATUS_XARSP: 1 when outbound ATS/MISC response queue is empty | |
| 52 | ROX | ROX | SM_STATUS_FREE: 1 when Free state machine queue is empty | |
| 53 | ROX | ROX | SM_STATUS_DIRUPD: 1 when Directory-Update queue is empty | |
| 54 | ROX | ROX | SM_STATUS_SACOLL: 1 when Same-Address Collision-Check queue is empty | |
| 55:58 | ROX | ROX | SM_STATUS_MRBCP: Master-Retry backoff level for Chip-Pump commands | |
| 59:60 | ROX | ROX | SM_STATUS_PERF_LSTATE: Performance-counter Latency state | |
| 61:63 | ROX | ROX | SM_STATUS_RESERVED2: reserved | |
| c_err_rpt first-0 latches | ||||
|---|---|---|---|---|
| Addr: |
00000000110108CF (SCOM) 0000000013420078 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.MCP.MISC.CERR_FIRST0 | |||
| Constant(s): | ||||
| Comments: | c_err_rpt first latches read-write-1-clear reg | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:55 | PAU3.CS.SM2.MCP.MISC.CERR_FIRST0_Q_0_INST.LATC.L2(0:55) [00000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_0: NVF0 s4: NVLink UT=0 to MMIO space bad cmd/length/alignment | |
| 1 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_1: NVF1 s4: UT=1 to MMIO space bad cmd/length/alignment | |
| 2 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_2: NVF2 s4: Target-Error/Unsupported-Request/Reserved Rsp_Status received in NVLink Response | |
| 3 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_3: NVF3 s4: Unexpected NVLink/OCAPI Response | |
| 4 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_4: NVF4 s4: Bad NV or OC response received (fence brick) | |
| 5 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_5: NVF5 s7: MCP_M_EVAL_DSA: illegal castout/.push arrives vs L2 directory state | |
| 6 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_6: NVF6 s4: Target-Error/Unsupported-Request/Reserved Rsp_Status received in NVLink Trans-Done Response | |
| 7 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_7: NVF7 s4: NVLink or OCAPI response timeout | |
| 8 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_8: NVF8 s4: Bad synonym_done received | |
| 9 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_9: NVF9 s4: OCAPI request to MMIO space bad cmd/length/alignment | |
| 10 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_10: NVF10 s4: DMA write/atomic to MMIO space w/ Data error | |
| 11 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_11: NVF11 s7: MCP_M_EVAL_DSA: Topology-index of the Request address is not valid in the topology-index table | |
| 12 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_12: NVF12 s7: MCP_M_EVAL_DSA: addr_error CResp to posted request | |
| 13 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_13: NVF13 (reserved) | |
| 14 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_14: NVF14 (reserved) | |
| 15 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_15: NVF15 NVLink NVF error for brick 0 occurred | |
| 16 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_16: NVF16 NVLink NVF error for brick 1 occurred | |
| 17 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_17: NVF17 NVLink NVF error for brick 2 occurred | |
| 18 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_18: NVF18 NVLink NVF error for brick 3 occurred | |
| 19 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_19: NVF19 NVLink NVF error for brick 4 occurred | |
| 20 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_ASBE_0: ASBE0 SBE ECC error detected from State-machine array | |
| 21 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_ASBE_1: ASBE1 SBE ECC error detected from Rq/Rs output queue array | |
| 22 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_ASBE_2: ASBE2 SBE ECC error detected from PowerBus data flit combiner array | |
| 23 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_ASBE_3: ASBE3 (reserved) | |
| 24 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_ASBE_4: ASBE4 SBE ECC error detected from L2-Directory SRAM 0 | |
| 25 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_ASBE_5: ASBE5 SBE ECC error detected from L2-Directory SRAM 1 | |
| 26 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_ASBE_6: ASBE6 SBE ECC error detected from L2-Directory SRAM 2 | |
| 27 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_ASBE_7: ASBE7 SBE ECC error detected from L2-Directory SRAM 3 | |
| 28 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBR_0: PBR0 s4: MCP_PC_WT_CRESP: abort_trm(_ed) cresp received to PAU request | |
| 29 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBR_1: PBR1 s4: MCP_PC_BK_WT_CRESP: abort_trm cresp received to PAU BKill request | |
| 30 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBR_2: PBR2 s4: Mis-aligned dma_pr_w/pr_dma_inj to AFU-MMIO space | |
| 31 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBR_3: PBR3 s4: rpt_hang.poll signalled hang condition | |
| 32 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBR_4: PBR4 s4: MCP_PC_WT_CRESP: Addr_Error received for self-lpc command (SSF) | |
| 33 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBR_5: PBR5 (reserved) | |
| 34 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBR_6: PBR6 (reserved) | |
| 35 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBR_7: PBR7 (reserved) | |
| 36 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_REG_0: REG0 s4: Address/Length/Alignment error on MMIO/GenId/Config access | |
| 37 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_REG_1: REG1 (reserved) | |
| 38 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_REG_2: REG2 (reserved) | |
| 39 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_REG_3: REG3 (reserved) | |
| 40 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_OCR_0: OCR0 s4: UT=0 to MMIO space bad cmd/length/alignment | |
| 41 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_OCR_1: OCR1 s4: Bad OC response received | |
| 42 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_OCR_2: OCR2 s4: AFU request w/ bad data received | |
| 43 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_OCR_3: OCR3 s4: Intrp_Req ObjHandle did not map to MMIO space | |
| 44 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_OCR_4: OCR4 s4: NVLink UT=0 to MMIO space bad cmd/length/alignment | |
| 45 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_OCR_5: OCR5 s4: UT=1 to MMIO space bad cmd/length/alignment | |
| 46 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_OCR_6: OCR6 s4: OCAPI request to MMIO space bad cmd/length/alignment | |
| 47 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_OCR_7: OCR7 s4: DMA write/atomic to MMIO space w/ Data error | |
| 48 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_OCR_8: OCR8 Epoch scanning did not complete before the next tick | |
| 49 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_OCR_9: OCR9 (reserved) | |
| 50 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_OCR_10: OCR10 (reserved) | |
| 51 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_OCR_11: OCR11 NVLink OCR error for brick 0 occurred | |
| 52 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_OCR_12: OCR12 NVLink OCR error for brick 1 occurred | |
| 53 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_OCR_13: OCR13 NVLink OCR error for brick 2 occurred | |
| 54 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_OCR_14: OCR14 NVLink OCR error for brick 3 occurred | |
| 55 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_OCR_15: OCR15 NVLink OCR error for brick 4 occurred | |
| 56:63 | RO | RO | constant=0b00000000 | |
| c_err_rpt first-1 latches | ||||
|---|---|---|---|---|
| Addr: |
00000000110108D0 (SCOM) 0000000013420080 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.MCP.MISC.CERR_FIRST1 | |||
| Constant(s): | ||||
| Comments: | c_err_rpt first latches read-write-1-clear reg | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:35 | PAU3.CS.SM2.MCP.MISC.CERR_FIRST1_Q_0_INST.LATC.L2(0:35) [000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLGX_0: NLGX0 Unknown xtype in stage s0r of RXO pipe | |
| 1 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLGX_1: NLGX1 Unknown xtype in stage s2r of RXO pipe | |
| 2 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLGX_2: NLGX2 (reserved) | |
| 3 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLGX_3: NLGX3 (reserved) | |
| 4 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_FWD_0: FWD0 s4: Forward progress timer expired | |
| 5 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_FWD_1: FWD1 s4: rpt_hang.data waiting-for-data timeout | |
| 6 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_FWD_2: FWD2 (reserved) | |
| 7 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_FWD_3: FWD3 (reserved) | |
| 8 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_AUE_0: AUE0 UE ECC error detected from State-machine array | |
| 9 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_AUE_1: AUE1 UE ECC error detected from Rq/Rs output queue array | |
| 10 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_AUE_2: AUE2 UE ECC error detected from PowerBus data flit combiner array | |
| 11 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_AUE_3: AUE3 (reserved) | |
| 12 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_AUE_4: AUE4 UE ECC error detected from L2-Directory SRAM 0 | |
| 13 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_AUE_5: AUE5 UE ECC error detected from L2-Directory SRAM 1 | |
| 14 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_AUE_6: AUE6 UE ECC error detected from L2-Directory SRAM 2 | |
| 15 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_AUE_7: AUE7 UE ECC error detected from L2-Directory SRAM 3 | |
| 16 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBF_0: PBF0 s5: MCP_M_WT_CRESP: error cresp received for a command | |
| 17 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBF_1: PBF1 s5: MCP_PC_WT_CRESP: error cresp received for a command | |
| 18 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBF_2: PBF2 s4: MCP_PC_WT_CRESP: Addr_Error received for self-lpc command (SSF) | |
| 19 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBF_3: PBF3 s4: MCP_PC_BK_WT_CRESP: ack_dead cresp received for a bkill | |
| 20 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBF_4: PBF4 s5: MCP_M_RCV_DATA_PTL: not all segments/OWs were received | |
| 21 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBF_5: PBF5 s4: dma_pr_w/pr_dma_inj snooped that crosses 128B boundary | |
| 22 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBF_6: PBF6 s4: SMEV_DATIN: Received data with illegal data_stat value. | |
| 23 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBF_7: PBF7 Unexpected data beat received | |
| 24 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBF_8: PBF8 s7: addr_error CResp to internal PAU request | |
| 25 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBF_9: PBF9 (reserved) | |
| 26 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBF_10: PBF10 s5: Received 64B of data but snooped command wasn't cp_*(m=1) | |
| 27 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBF_11: PBF11 s5: Received 64B of data to PAU-mastered command | |
| 28 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_LDA_0: LDA0 s4: MCP_PC_WT_CRESP: Addr_Error received for load command (LD) | |
| 29 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_LDA_1: LDA1 (reserved) | |
| 30 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_LDA_2: LDA2 (reserved) | |
| 31 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_LDA_3: LDA3 (reserved) | |
| 32 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_STA_0: STA0 s4: MCP_PC_WT_CRESP: Addr_Error received for store command (ST) | |
| 33 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_STA_1: STA1 s4: MCP_PC_BK_WT_CRESP: Addr_Error received for bkill command (ST) | |
| 34 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_STA_2: STA2 (reserved) | |
| 35 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_STA_3: STA3 (reserved) | |
| 36:63 | RO | RO | constant=0b0000000000000000000000000000 | |
| c_err_rpt first-2 latches | ||||
|---|---|---|---|---|
| Addr: |
00000000110108D1 (SCOM) 0000000013420088 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.MCP.MISC.CERR_FIRST2 | |||
| Constant(s): | ||||
| Comments: | c_err_rpt first latches read-write-1-clear reg | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM2.MCP.MISC.CERR_FIRST2_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_0: NLG0 s4: Rcmd Event received but state machine is not IDLE | |
| 1 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_1: NLG1 s4: Pocket-Hit event but not in MCP_M_PCKT_WAIT_HIT/PC_* state | |
| 2 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_2: NLG2 s4: MCP_M_WT_CRESP: ma_scresp table lookup missed | |
| 3 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_3: NLG3 s4: MCP_M_WT_CRESP: start epsilon, but epsilon already in progress | |
| 4 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_4: NLG4 s5: MCP_M_WT_CRESP: ma_scresp indicated 'evaporate' but have xTL modified data | |
| 5 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_5: NLG5 s5: MCP_M_WT_CRESP: ma_scresp indicated 'evaporate' but have PB modified data | |
| 6 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_6: NLG6 s5: MCP_M_WT_CRESP: bad scenario code from ma_scresp table | |
| 7 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_7: NLG7 s4: snoop Cresp received but not in MCP_M_WT_CRESP state | |
| 8 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_8: NLG8 s4: Dir-Lock Event received but state machine is not MCP_PC_WT_CRESP/MCP_M_WAIT_SYN_PEND/MCP_M_WAIT_DIR_LOCK or bad ttype | |
| 9 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_9: NLG9 s4: MCP_PC_WT_CRESP: ma_mcresp table lookup missed | |
| 10 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_10: NLG10 s4/5: MCP_PC/_BK/_WT_CRESP: Write coll state didn't match early protection state | |
| 11 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_11: NLG11 s4: MCP_PC_WT_CRESP: start epsilon, but epsilon already in progress | |
| 12 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_12: NLG12 s5: MCP_PC_WT_CRESP: bad scenario code from ma_mcresp table | |
| 13 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_13: NLG13 s4: MCP_PC_BK_WT_CRESP: bad next-step for bkill (ack-done) | |
| 14 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_14: NLG14 s4: MCP_PC_BK_WT_CRESP: bad next-step for bkill (retry) | |
| 15 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_15: NLG15 s4: MCP_PC_BK_WT_CRESP: bad cresp for a bkill | |
| 16 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_16: NLG16 s4: master Cresp received but not in MCP_PC_WT_CRESP/MCP_PC_BK_WT_CRESP states | |
| 17 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_17: NLG17 s4: M_IDLE: Invalid DATALEN[3:0] for NVLink data command | |
| 18 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_18: NLG18 s4: M_IDLE: Invalid command type received | |
| 19 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_19: NLG19 s4: AT-translate-Response event but not in wait-translate state | |
| 20 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_20: NLG20 s4: AT-translate-Response event had bad translate status, but cmd not recognized | |
| 21 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_21: NLG21 s4: SA-Done event but not in wait-SA state | |
| 22 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_22: NLG22 s4: MCP_PC_WAIT_DATADONE: bad next-step for PB data transmit | |
| 23 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_23: NLG23 s4: MCP_TD_WAIT_DATADONE: Unknown NVLink Master Command | |
| 24 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_24: NLG24 s4: BuffDone event but not in PB/PC/MG/NR/XATS/MCP_TD_WAIT_DATADONE state | |
| 25 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_25: NLG25 s4: MCP_NC_WT_RESP: Unknown nv-master command for NVLink response | |
| 26 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_26: NLG26 s4: RG-RspIn event but not in MCP_RG_WT_RESP or MCP_NC_WT_RESP* state | |
| 27 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_27: NLG27 s4: Epsilon-In-Progress, but epsilon counter clock is not the epsilon clock | |
| 28 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_28: NLG28 s4: Epsilon counter clock is 'epsilon' but epsilon_ip is not set | |
| 29 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_29: NLG29 s4: MCP_PC_WT_BK_RBACK: bad next-step for bkill | |
| 30 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_30: NLG30 s4: M/RR_BACK timer expired but not in PC_WT(_BK)_RBACK state | |
| 31 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_31: NLG31 s4: Bad epclock value | |
| 32 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_32: NLG32 s4: coll_state is POCKET_RCOLL_ND but master state is not PCKT_WAIT_HIT | |
| 33 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_33: NLG33 s7: Did not find anything to do for a MCMD_COH response | |
| 34 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_34: NLG34 s4: Unknown Event type received | |
| 35 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_35: NLG35 s4: SMEV_DIRDONE received but sm_dir_upd_pending=0 | |
| 36 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_36: NLG36 s7: MCP_M_EVAL_DSA: Unknown merge opcode from dsa table | |
| 37 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_37: NLG37 s7: Unknown State | |
| 38 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_38: NLG38 s4: coll_state is POCKET_RCOLL_OND but master state is not PCKT_WAIT_HIT | |
| 39 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_39: NLG39 s4: Unknown sm_master_state in ESCAN_FENCE event | |
| 40 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_40: NLG40 s4: MCP_FENCE_WT_RESP_FILL: Unknown nv-master command for Fence-Fill-SUE response | |
| 41 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_41: NLG41 s4: MCP_M_WT_CRESP: impossible command/cresp | |
| 42 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_42: NLG42 s4: MCP_PC_WT_CRESP: impossible command/cresp | |
| 43 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_43: NLG43 s7: MCP_M_EVAL_DSA: impossible command/state | |
| 44 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_44: NLG44 s7: Unexpected Error State (bad sub-sequence return) | |
| 45 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_45: NLG45 s5: sfstat-retry but not in retry-abbks collision state | |
| 46 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_46: NLG46 s5: *cond*-retry but not in retry-abbks collision state | |
| 47 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_47: NLG47 s4: Request from CTL/xTL caused bad MMIO alignment, but cmd not recognized | |
| 48 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_48: NLG48 s5: MCP_NC_EXE_RESP: Unknown nv-master command for NVLink response | |
| 49 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_49: NLG49 s7: MCP_M_EVAL_DSA: Topology-index of the Request address is not valid in the topology-index table | |
| 50 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_50: NLG50 s4: Request from CTL/xTL caused bad MMIO alignment, but cmd not recognized | |
| 51 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_51: NLG51 s4: Request from CTL/xTL loaded into non-idle state-machine | |
| 52 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_52: NLG52 s4: POCKET-HIT event but coll_state is not POCKET_WINNER* | |
| 53 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_53: NLG53 s4: Unknown rspin event w/ unknown master-command in MCP_RG_WT_RESP state | |
| 54 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_54: NLG54 s7: Attempt to send PBus request but config_enable_pbus=0 | |
| 55 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_55: NLG55 s4: Invalid SrcBus on response from CTL | |
| 56 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_56: NLG56 s4: Shoulder-tap event but not in MCP_M_WT_SHOULDER_TAP state | |
| 57 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_57: NLG57 s7: MCP_M_EVAL_DSA: ma_dsasfe table lookup missed | |
| 58 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_58: NLG58 s7: MCP_M_EVAL_DSA: ma_dsac2alc table lookup missed | |
| 59 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_59: NLG59 s7: MCP_M_EVAL_DSA: ma_dsac2co table lookup missed | |
| 60 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_60: NLG60 s7: MCP_M_EVAL_DSA: ma_dsaoth table lookup missed | |
| 61 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_61: NLG61 s7: MCP_M_EVAL_DSA: ma_dsascan table lookup missed | |
| 62 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_62: NLG62 s7: Nothing to do after looking in DSA table | |
| 63 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_63: NLG63 s7: coherence update/response but directory lock is not DLOCK_MOD | |
| c_err_rpt mask-0 latches | ||||
|---|---|---|---|---|
| Addr: |
00000000110108D2 (SCOM) 0000000013420090 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.MCP.MISC.CERR_MASK0 | |||
| Constant(s): | ||||
| Comments: | c_err_rpt mask reg Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:55 | PAU3.CS.SM2.MCP.MISC.CERR_MASK0_Q_0_INST.LATC.L2(0:55) [00000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | IDIAL_MCP_MASK_NVF_0: NVF0 s4: NVLink UT=0 to MMIO space bad cmd/length/alignment | |
| 1 | RW | RW | IDIAL_MCP_MASK_NVF_1: NVF1 s4: UT=1 to MMIO space bad cmd/length/alignment | |
| 2 | RW | RW | IDIAL_MCP_MASK_NVF_2: NVF2 s4: Target-Error/Unsupported-Request/Reserved Rsp_Status received in NVLink Response | |
| 3 | RW | RW | IDIAL_MCP_MASK_NVF_3: NVF3 s4: Unexpected NVLink/OCAPI Response | |
| 4 | RW | RW | IDIAL_MCP_MASK_NVF_4: NVF4 s4: Bad NV or OC response received (fence brick) | |
| 5 | RW | RW | IDIAL_MCP_MASK_NVF_5: NVF5 s7: MCP_M_EVAL_DSA: illegal castout/.push arrives vs L2 directory state | |
| 6 | RW | RW | IDIAL_MCP_MASK_NVF_6: NVF6 s4: Target-Error/Unsupported-Request/Reserved Rsp_Status received in NVLink Trans-Done Response | |
| 7 | RW | RW | IDIAL_MCP_MASK_NVF_7: NVF7 s4: NVLink or OCAPI response timeout | |
| 8 | RW | RW | IDIAL_MCP_MASK_NVF_8: NVF8 s4: Bad synonym_done received | |
| 9 | RW | RW | IDIAL_MCP_MASK_NVF_9: NVF9 s4: OCAPI request to MMIO space bad cmd/length/alignment | |
| 10 | RW | RW | IDIAL_MCP_MASK_NVF_10: NVF10 s4: DMA write/atomic to MMIO space w/ Data error | |
| 11 | RW | RW | IDIAL_MCP_MASK_NVF_11: NVF11 s7: MCP_M_EVAL_DSA: Topology-index of the Request address is not valid in the topology-index table | |
| 12 | RW | RW | IDIAL_MCP_MASK_NVF_12: NVF12 s7: MCP_M_EVAL_DSA: addr_error CResp to posted request | |
| 13 | RW | RW | IDIAL_MCP_MASK_NVF_13: NVF13 (reserved) | |
| 14 | RW | RW | IDIAL_MCP_MASK_NVF_14: NVF14 (reserved) | |
| 15 | RW | RW | IDIAL_MCP_MASK_NVF_15: NVF15 NVLink NVF error for brick 0 occurred | |
| 16 | RW | RW | IDIAL_MCP_MASK_NVF_16: NVF16 NVLink NVF error for brick 1 occurred | |
| 17 | RW | RW | IDIAL_MCP_MASK_NVF_17: NVF17 NVLink NVF error for brick 2 occurred | |
| 18 | RW | RW | IDIAL_MCP_MASK_NVF_18: NVF18 NVLink NVF error for brick 3 occurred | |
| 19 | RW | RW | IDIAL_MCP_MASK_NVF_19: NVF19 NVLink NVF error for brick 4 occurred | |
| 20 | RW | RW | IDIAL_MCP_MASK_ASBE_0: ASBE0 SBE ECC error detected from State-machine array | |
| 21 | RW | RW | IDIAL_MCP_MASK_ASBE_1: ASBE1 SBE ECC error detected from Rq/Rs output queue array | |
| 22 | RW | RW | IDIAL_MCP_MASK_ASBE_2: ASBE2 SBE ECC error detected from PowerBus data flit combiner array | |
| 23 | RW | RW | IDIAL_MCP_MASK_ASBE_3: ASBE3 (reserved) | |
| 24 | RW | RW | IDIAL_MCP_MASK_ASBE_4: ASBE4 SBE ECC error detected from L2-Directory SRAM 0 | |
| 25 | RW | RW | IDIAL_MCP_MASK_ASBE_5: ASBE5 SBE ECC error detected from L2-Directory SRAM 1 | |
| 26 | RW | RW | IDIAL_MCP_MASK_ASBE_6: ASBE6 SBE ECC error detected from L2-Directory SRAM 2 | |
| 27 | RW | RW | IDIAL_MCP_MASK_ASBE_7: ASBE7 SBE ECC error detected from L2-Directory SRAM 3 | |
| 28 | RW | RW | IDIAL_MCP_MASK_PBR_0: PBR0 s4: MCP_PC_WT_CRESP: abort_trm(_ed) cresp received to PAU request | |
| 29 | RW | RW | IDIAL_MCP_MASK_PBR_1: PBR1 s4: MCP_PC_BK_WT_CRESP: abort_trm cresp received to PAU BKill request | |
| 30 | RW | RW | IDIAL_MCP_MASK_PBR_2: PBR2 s4: Mis-aligned dma_pr_w/pr_dma_inj to AFU-MMIO space | |
| 31 | RW | RW | IDIAL_MCP_MASK_PBR_3: PBR3 s4: rpt_hang.poll signalled hang condition | |
| 32 | RW | RW | IDIAL_MCP_MASK_PBR_4: PBR4 s4: MCP_PC_WT_CRESP: Addr_Error received for self-lpc command (SSF) | |
| 33 | RW | RW | IDIAL_MCP_MASK_PBR_5: PBR5 (reserved) | |
| 34 | RW | RW | IDIAL_MCP_MASK_PBR_6: PBR6 (reserved) | |
| 35 | RW | RW | IDIAL_MCP_MASK_PBR_7: PBR7 (reserved) | |
| 36 | RW | RW | IDIAL_MCP_MASK_REG_0: REG0 s4: Address/Length/Alignment error on MMIO/GenId/Config access | |
| 37 | RW | RW | IDIAL_MCP_MASK_REG_1: REG1 (reserved) | |
| 38 | RW | RW | IDIAL_MCP_MASK_REG_2: REG2 (reserved) | |
| 39 | RW | RW | IDIAL_MCP_MASK_REG_3: REG3 (reserved) | |
| 40 | RW | RW | IDIAL_MCP_MASK_OCR_0: OCR0 s4: UT=0 to MMIO space bad cmd/length/alignment | |
| 41 | RW | RW | IDIAL_MCP_MASK_OCR_1: OCR1 s4: Bad OC response received | |
| 42 | RW | RW | IDIAL_MCP_MASK_OCR_2: OCR2 s4: AFU request w/ bad data received | |
| 43 | RW | RW | IDIAL_MCP_MASK_OCR_3: OCR3 s4: Intrp_Req ObjHandle did not map to MMIO space | |
| 44 | RW | RW | IDIAL_MCP_MASK_OCR_4: OCR4 s4: NVLink UT=0 to MMIO space bad cmd/length/alignment | |
| 45 | RW | RW | IDIAL_MCP_MASK_OCR_5: OCR5 s4: UT=1 to MMIO space bad cmd/length/alignment | |
| 46 | RW | RW | IDIAL_MCP_MASK_OCR_6: OCR6 s4: OCAPI request to MMIO space bad cmd/length/alignment | |
| 47 | RW | RW | IDIAL_MCP_MASK_OCR_7: OCR7 s4: DMA write/atomic to MMIO space w/ Data error | |
| 48 | RW | RW | IDIAL_MCP_MASK_OCR_8: OCR8 Epoch scanning did not complete before the next tick | |
| 49 | RW | RW | IDIAL_MCP_MASK_OCR_9: OCR9 (reserved) | |
| 50 | RW | RW | IDIAL_MCP_MASK_OCR_10: OCR10 (reserved) | |
| 51 | RW | RW | IDIAL_MCP_MASK_OCR_11: OCR11 NVLink OCR error for brick 0 occurred | |
| 52 | RW | RW | IDIAL_MCP_MASK_OCR_12: OCR12 NVLink OCR error for brick 1 occurred | |
| 53 | RW | RW | IDIAL_MCP_MASK_OCR_13: OCR13 NVLink OCR error for brick 2 occurred | |
| 54 | RW | RW | IDIAL_MCP_MASK_OCR_14: OCR14 NVLink OCR error for brick 3 occurred | |
| 55 | RW | RW | IDIAL_MCP_MASK_OCR_15: OCR15 NVLink OCR error for brick 4 occurred | |
| 56:63 | RO | RO | constant=0b00000000 | |
| c_err_rpt mask-1 latches | ||||
|---|---|---|---|---|
| Addr: |
00000000110108D3 (SCOM) 0000000013420098 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.MCP.MISC.CERR_MASK1 | |||
| Constant(s): | ||||
| Comments: | c_err_rpt mask reg Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:35 | PAU3.CS.SM2.MCP.MISC.CERR_MASK1_Q_0_INST.LATC.L2(0:35) [000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | IDIAL_MCP_MASK_NLGX_0: NLGX0 Unknown xtype in stage s0r of RXO pipe | |
| 1 | RW | RW | IDIAL_MCP_MASK_NLGX_1: NLGX1 Unknown xtype in stage s2r of RXO pipe | |
| 2 | RW | RW | IDIAL_MCP_MASK_NLGX_2: NLGX2 (reserved) | |
| 3 | RW | RW | IDIAL_MCP_MASK_NLGX_3: NLGX3 (reserved) | |
| 4 | RW | RW | IDIAL_MCP_MASK_FWD_0: FWD0 s4: Forward progress timer expired | |
| 5 | RW | RW | IDIAL_MCP_MASK_FWD_1: FWD1 s4: rpt_hang.data waiting-for-data timeout | |
| 6 | RW | RW | IDIAL_MCP_MASK_FWD_2: FWD2 (reserved) | |
| 7 | RW | RW | IDIAL_MCP_MASK_FWD_3: FWD3 (reserved) | |
| 8 | RW | RW | IDIAL_MCP_MASK_AUE_0: AUE0 UE ECC error detected from State-machine array | |
| 9 | RW | RW | IDIAL_MCP_MASK_AUE_1: AUE1 UE ECC error detected from Rq/Rs output queue array | |
| 10 | RW | RW | IDIAL_MCP_MASK_AUE_2: AUE2 UE ECC error detected from PowerBus data flit combiner array | |
| 11 | RW | RW | IDIAL_MCP_MASK_AUE_3: AUE3 (reserved) | |
| 12 | RW | RW | IDIAL_MCP_MASK_AUE_4: AUE4 UE ECC error detected from L2-Directory SRAM 0 | |
| 13 | RW | RW | IDIAL_MCP_MASK_AUE_5: AUE5 UE ECC error detected from L2-Directory SRAM 1 | |
| 14 | RW | RW | IDIAL_MCP_MASK_AUE_6: AUE6 UE ECC error detected from L2-Directory SRAM 2 | |
| 15 | RW | RW | IDIAL_MCP_MASK_AUE_7: AUE7 UE ECC error detected from L2-Directory SRAM 3 | |
| 16 | RW | RW | IDIAL_MCP_MASK_PBF_0: PBF0 s5: MCP_M_WT_CRESP: error cresp received for a command | |
| 17 | RW | RW | IDIAL_MCP_MASK_PBF_1: PBF1 s5: MCP_PC_WT_CRESP: error cresp received for a command | |
| 18 | RW | RW | IDIAL_MCP_MASK_PBF_2: PBF2 s4: MCP_PC_WT_CRESP: Addr_Error received for self-lpc command (SSF) | |
| 19 | RW | RW | IDIAL_MCP_MASK_PBF_3: PBF3 s4: MCP_PC_BK_WT_CRESP: ack_dead cresp received for a bkill | |
| 20 | RW | RW | IDIAL_MCP_MASK_PBF_4: PBF4 s5: MCP_M_RCV_DATA_PTL: not all segments/OWs were received | |
| 21 | RW | RW | IDIAL_MCP_MASK_PBF_5: PBF5 s4: dma_pr_w/pr_dma_inj snooped that crosses 128B boundary | |
| 22 | RW | RW | IDIAL_MCP_MASK_PBF_6: PBF6 s4: SMEV_DATIN: Received data with illegal data_stat value. | |
| 23 | RW | RW | IDIAL_MCP_MASK_PBF_7: PBF7 Unexpected data beat received | |
| 24 | RW | RW | IDIAL_MCP_MASK_PBF_8: PBF8 s7: addr_error CResp to internal PAU request | |
| 25 | RW | RW | IDIAL_MCP_MASK_PBF_9: PBF9 (reserved) | |
| 26 | RW | RW | IDIAL_MCP_MASK_PBF_10: PBF10 s5: Received 64B of data but snooped command wasn't cp_*(m=1) | |
| 27 | RW | RW | IDIAL_MCP_MASK_PBF_11: PBF11 s5: Received 64B of data to PAU-mastered command | |
| 28 | RW | RW | IDIAL_MCP_MASK_LDA_0: LDA0 s4: MCP_PC_WT_CRESP: Addr_Error received for load command (LD) | |
| 29 | RW | RW | IDIAL_MCP_MASK_LDA_1: LDA1 (reserved) | |
| 30 | RW | RW | IDIAL_MCP_MASK_LDA_2: LDA2 (reserved) | |
| 31 | RW | RW | IDIAL_MCP_MASK_LDA_3: LDA3 (reserved) | |
| 32 | RW | RW | IDIAL_MCP_MASK_STA_0: STA0 s4: MCP_PC_WT_CRESP: Addr_Error received for store command (ST) | |
| 33 | RW | RW | IDIAL_MCP_MASK_STA_1: STA1 s4: MCP_PC_BK_WT_CRESP: Addr_Error received for bkill command (ST) | |
| 34 | RW | RW | IDIAL_MCP_MASK_STA_2: STA2 (reserved) | |
| 35 | RW | RW | IDIAL_MCP_MASK_STA_3: STA3 (reserved) | |
| 36:63 | RO | RO | constant=0b0000000000000000000000000000 | |
| c_err_rpt mask-2 latches | ||||
|---|---|---|---|---|
| Addr: |
00000000110108D4 (SCOM) 00000000134200A0 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.MCP.MISC.CERR_MASK2 | |||
| Constant(s): | ||||
| Comments: | c_err_rpt mask reg Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM2.MCP.MISC.CERR_MASK2_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | IDIAL_MCP_MASK_NLG_0: NLG0 s4: Rcmd Event received but state machine is not IDLE | |
| 1 | RW | RW | IDIAL_MCP_MASK_NLG_1: NLG1 s4: Pocket-Hit event but not in MCP_M_PCKT_WAIT_HIT/PC_* state | |
| 2 | RW | RW | IDIAL_MCP_MASK_NLG_2: NLG2 s4: MCP_M_WT_CRESP: ma_scresp table lookup missed | |
| 3 | RW | RW | IDIAL_MCP_MASK_NLG_3: NLG3 s4: MCP_M_WT_CRESP: start epsilon, but epsilon already in progress | |
| 4 | RW | RW | IDIAL_MCP_MASK_NLG_4: NLG4 s5: MCP_M_WT_CRESP: ma_scresp indicated 'evaporate' but have xTL modified data | |
| 5 | RW | RW | IDIAL_MCP_MASK_NLG_5: NLG5 s5: MCP_M_WT_CRESP: ma_scresp indicated 'evaporate' but have PB modified data | |
| 6 | RW | RW | IDIAL_MCP_MASK_NLG_6: NLG6 s5: MCP_M_WT_CRESP: bad scenario code from ma_scresp table | |
| 7 | RW | RW | IDIAL_MCP_MASK_NLG_7: NLG7 s4: snoop Cresp received but not in MCP_M_WT_CRESP state | |
| 8 | RW | RW | IDIAL_MCP_MASK_NLG_8: NLG8 s4: Dir-Lock Event received but state machine is not MCP_PC_WT_CRESP/MCP_M_WAIT_SYN_PEND/MCP_M_WAIT_DIR_LOCK or bad ttype | |
| 9 | RW | RW | IDIAL_MCP_MASK_NLG_9: NLG9 s4: MCP_PC_WT_CRESP: ma_mcresp table lookup missed | |
| 10 | RW | RW | IDIAL_MCP_MASK_NLG_10: NLG10 s4/5: MCP_PC/_BK/_WT_CRESP: Write coll state didn't match early protection state | |
| 11 | RW | RW | IDIAL_MCP_MASK_NLG_11: NLG11 s4: MCP_PC_WT_CRESP: start epsilon, but epsilon already in progress | |
| 12 | RW | RW | IDIAL_MCP_MASK_NLG_12: NLG12 s5: MCP_PC_WT_CRESP: bad scenario code from ma_mcresp table | |
| 13 | RW | RW | IDIAL_MCP_MASK_NLG_13: NLG13 s4: MCP_PC_BK_WT_CRESP: bad next-step for bkill (ack-done) | |
| 14 | RW | RW | IDIAL_MCP_MASK_NLG_14: NLG14 s4: MCP_PC_BK_WT_CRESP: bad next-step for bkill (retry) | |
| 15 | RW | RW | IDIAL_MCP_MASK_NLG_15: NLG15 s4: MCP_PC_BK_WT_CRESP: bad cresp for a bkill | |
| 16 | RW | RW | IDIAL_MCP_MASK_NLG_16: NLG16 s4: master Cresp received but not in MCP_PC_WT_CRESP/MCP_PC_BK_WT_CRESP states | |
| 17 | RW | RW | IDIAL_MCP_MASK_NLG_17: NLG17 s4: M_IDLE: Invalid DATALEN[3:0] for NVLink data command | |
| 18 | RW | RW | IDIAL_MCP_MASK_NLG_18: NLG18 s4: M_IDLE: Invalid command type received | |
| 19 | RW | RW | IDIAL_MCP_MASK_NLG_19: NLG19 s4: AT-translate-Response event but not in wait-translate state | |
| 20 | RW | RW | IDIAL_MCP_MASK_NLG_20: NLG20 s4: AT-translate-Response event had bad translate status, but cmd not recognized | |
| 21 | RW | RW | IDIAL_MCP_MASK_NLG_21: NLG21 s4: SA-Done event but not in wait-SA state | |
| 22 | RW | RW | IDIAL_MCP_MASK_NLG_22: NLG22 s4: MCP_PC_WAIT_DATADONE: bad next-step for PB data transmit | |
| 23 | RW | RW | IDIAL_MCP_MASK_NLG_23: NLG23 s4: MCP_TD_WAIT_DATADONE: Unknown NVLink Master Command | |
| 24 | RW | RW | IDIAL_MCP_MASK_NLG_24: NLG24 s4: BuffDone event but not in PB/PC/MG/NR/XATS/MCP_TD_WAIT_DATADONE state | |
| 25 | RW | RW | IDIAL_MCP_MASK_NLG_25: NLG25 s4: MCP_NC_WT_RESP: Unknown nv-master command for NVLink response | |
| 26 | RW | RW | IDIAL_MCP_MASK_NLG_26: NLG26 s4: RG-RspIn event but not in MCP_RG_WT_RESP or MCP_NC_WT_RESP* state | |
| 27 | RW | RW | IDIAL_MCP_MASK_NLG_27: NLG27 s4: Epsilon-In-Progress, but epsilon counter clock is not the epsilon clock | |
| 28 | RW | RW | IDIAL_MCP_MASK_NLG_28: NLG28 s4: Epsilon counter clock is 'epsilon' but epsilon_ip is not set | |
| 29 | RW | RW | IDIAL_MCP_MASK_NLG_29: NLG29 s4: MCP_PC_WT_BK_RBACK: bad next-step for bkill | |
| 30 | RW | RW | IDIAL_MCP_MASK_NLG_30: NLG30 s4: M/RR_BACK timer expired but not in PC_WT(_BK)_RBACK state | |
| 31 | RW | RW | IDIAL_MCP_MASK_NLG_31: NLG31 s4: Bad epclock value | |
| 32 | RW | RW | IDIAL_MCP_MASK_NLG_32: NLG32 s4: coll_state is POCKET_RCOLL_ND but master state is not PCKT_WAIT_HIT | |
| 33 | RW | RW | IDIAL_MCP_MASK_NLG_33: NLG33 s7: Did not find anything to do for a MCMD_COH response | |
| 34 | RW | RW | IDIAL_MCP_MASK_NLG_34: NLG34 s4: Unknown Event type received | |
| 35 | RW | RW | IDIAL_MCP_MASK_NLG_35: NLG35 s4: SMEV_DIRDONE received but sm_dir_upd_pending=0 | |
| 36 | RW | RW | IDIAL_MCP_MASK_NLG_36: NLG36 s7: MCP_M_EVAL_DSA: Unknown merge opcode from dsa table | |
| 37 | RW | RW | IDIAL_MCP_MASK_NLG_37: NLG37 s7: Unknown State | |
| 38 | RW | RW | IDIAL_MCP_MASK_NLG_38: NLG38 s4: coll_state is POCKET_RCOLL_OND but master state is not PCKT_WAIT_HIT | |
| 39 | RW | RW | IDIAL_MCP_MASK_NLG_39: NLG39 s4: Unknown sm_master_state in ESCAN_FENCE event | |
| 40 | RW | RW | IDIAL_MCP_MASK_NLG_40: NLG40 s4: MCP_FENCE_WT_RESP_FILL: Unknown nv-master command for Fence-Fill-SUE response | |
| 41 | RW | RW | IDIAL_MCP_MASK_NLG_41: NLG41 s4: MCP_M_WT_CRESP: impossible command/cresp | |
| 42 | RW | RW | IDIAL_MCP_MASK_NLG_42: NLG42 s4: MCP_PC_WT_CRESP: impossible command/cresp | |
| 43 | RW | RW | IDIAL_MCP_MASK_NLG_43: NLG43 s7: MCP_M_EVAL_DSA: impossible command/state | |
| 44 | RW | RW | IDIAL_MCP_MASK_NLG_44: NLG44 s7: Unexpected Error State (bad sub-sequence return) | |
| 45 | RW | RW | IDIAL_MCP_MASK_NLG_45: NLG45 s5: sfstat-retry but not in retry-abbks collision state | |
| 46 | RW | RW | IDIAL_MCP_MASK_NLG_46: NLG46 s5: *cond*-retry but not in retry-abbks collision state | |
| 47 | RW | RW | IDIAL_MCP_MASK_NLG_47: NLG47 s4: Request from CTL/xTL caused bad MMIO alignment, but cmd not recognized | |
| 48 | RW | RW | IDIAL_MCP_MASK_NLG_48: NLG48 s5: MCP_NC_EXE_RESP: Unknown nv-master command for NVLink response | |
| 49 | RW | RW | IDIAL_MCP_MASK_NLG_49: NLG49 s7: MCP_M_EVAL_DSA: Topology-index of the Request address is not valid in the topology-index table | |
| 50 | RW | RW | IDIAL_MCP_MASK_NLG_50: NLG50 s4: Request from CTL/xTL caused bad MMIO alignment, but cmd not recognized | |
| 51 | RW | RW | IDIAL_MCP_MASK_NLG_51: NLG51 s4: Request from CTL/xTL loaded into non-idle state-machine | |
| 52 | RW | RW | IDIAL_MCP_MASK_NLG_52: NLG52 s4: POCKET-HIT event but coll_state is not POCKET_WINNER* | |
| 53 | RW | RW | IDIAL_MCP_MASK_NLG_53: NLG53 s4: Unknown rspin event w/ unknown master-command in MCP_RG_WT_RESP state | |
| 54 | RW | RW | IDIAL_MCP_MASK_NLG_54: NLG54 s7: Attempt to send PBus request but config_enable_pbus=0 | |
| 55 | RW | RW | IDIAL_MCP_MASK_NLG_55: NLG55 s4: Invalid SrcBus on response from CTL | |
| 56 | RW | RW | IDIAL_MCP_MASK_NLG_56: NLG56 s4: Shoulder-tap event but not in MCP_M_WT_SHOULDER_TAP state | |
| 57 | RW | RW | IDIAL_MCP_MASK_NLG_57: NLG57 s7: MCP_M_EVAL_DSA: ma_dsasfe table lookup missed | |
| 58 | RW | RW | IDIAL_MCP_MASK_NLG_58: NLG58 s7: MCP_M_EVAL_DSA: ma_dsac2alc table lookup missed | |
| 59 | RW | RW | IDIAL_MCP_MASK_NLG_59: NLG59 s7: MCP_M_EVAL_DSA: ma_dsac2co table lookup missed | |
| 60 | RW | RW | IDIAL_MCP_MASK_NLG_60: NLG60 s7: MCP_M_EVAL_DSA: ma_dsaoth table lookup missed | |
| 61 | RW | RW | IDIAL_MCP_MASK_NLG_61: NLG61 s7: MCP_M_EVAL_DSA: ma_dsascan table lookup missed | |
| 62 | RW | RW | IDIAL_MCP_MASK_NLG_62: NLG62 s7: Nothing to do after looking in DSA table | |
| 63 | RW | RW | IDIAL_MCP_MASK_NLG_63: NLG63 s7: coherence update/response but directory lock is not DLOCK_MOD | |
| c_err_rpt hold-0 latches | ||||
|---|---|---|---|---|
| Addr: |
00000000110108D5 (SCOM) 00000000134200A8 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.MCP.MISC.CERR_HOLD0 | |||
| Constant(s): | ||||
| Comments: | c_err_rpt hold latches read-write-clear reg | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:19 | PAU3.CS.SM2.MCP.MISC.CERPT_NVF.HOLD_LATCH_INST.HOLD.LATC.L2(0:19) [00000000000000000000] | |||
| 20:27 | PAU3.CS.SM2.MCP.MISC.CERPT_ASBE.HOLD_LATCH_INST.HOLD.LATC.L2(0:7) [00000000] | |||
| 28:35 | PAU3.CS.SM2.MCP.MISC.CERPT_PBR.HOLD_LATCH_INST.HOLD.LATC.L2(0:7) [00000000] | |||
| 36:39 | PAU3.CS.SM2.MCP.MISC.CERPT_REG.HOLD_LATCH_INST.HOLD.LATC.L2(0:3) [0000] | |||
| 40:55 | PAU3.CS.SM2.MCP.MISC.CERPT_OCR.HOLD_LATCH_INST.HOLD.LATC.L2(0:15) [0000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_0: NVF0 s4: NVLink UT=0 to MMIO space bad cmd/length/alignment | |
| 1 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_1: NVF1 s4: UT=1 to MMIO space bad cmd/length/alignment | |
| 2 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_2: NVF2 s4: Target-Error/Unsupported-Request/Reserved Rsp_Status received in NVLink Response | |
| 3 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_3: NVF3 s4: Unexpected NVLink/OCAPI Response | |
| 4 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_4: NVF4 s4: Bad NV or OC response received (fence brick) | |
| 5 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_5: NVF5 s7: MCP_M_EVAL_DSA: illegal castout/.push arrives vs L2 directory state | |
| 6 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_6: NVF6 s4: Target-Error/Unsupported-Request/Reserved Rsp_Status received in NVLink Trans-Done Response | |
| 7 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_7: NVF7 s4: NVLink or OCAPI response timeout | |
| 8 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_8: NVF8 s4: Bad synonym_done received | |
| 9 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_9: NVF9 s4: OCAPI request to MMIO space bad cmd/length/alignment | |
| 10 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_10: NVF10 s4: DMA write/atomic to MMIO space w/ Data error | |
| 11 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_11: NVF11 s7: MCP_M_EVAL_DSA: Topology-index of the Request address is not valid in the topology-index table | |
| 12 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_12: NVF12 s7: MCP_M_EVAL_DSA: addr_error CResp to posted request | |
| 13 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_13: NVF13 (reserved) | |
| 14 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_14: NVF14 (reserved) | |
| 15 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_15: NVF15 NVLink NVF error for brick 0 occurred | |
| 16 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_16: NVF16 NVLink NVF error for brick 1 occurred | |
| 17 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_17: NVF17 NVLink NVF error for brick 2 occurred | |
| 18 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_18: NVF18 NVLink NVF error for brick 3 occurred | |
| 19 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_19: NVF19 NVLink NVF error for brick 4 occurred | |
| 20 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_ASBE_0: ASBE0 SBE ECC error detected from State-machine array | |
| 21 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_ASBE_1: ASBE1 SBE ECC error detected from Rq/Rs output queue array | |
| 22 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_ASBE_2: ASBE2 SBE ECC error detected from PowerBus data flit combiner array | |
| 23 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_ASBE_3: ASBE3 (reserved) | |
| 24 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_ASBE_4: ASBE4 SBE ECC error detected from L2-Directory SRAM 0 | |
| 25 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_ASBE_5: ASBE5 SBE ECC error detected from L2-Directory SRAM 1 | |
| 26 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_ASBE_6: ASBE6 SBE ECC error detected from L2-Directory SRAM 2 | |
| 27 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_ASBE_7: ASBE7 SBE ECC error detected from L2-Directory SRAM 3 | |
| 28 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBR_0: PBR0 s4: MCP_PC_WT_CRESP: abort_trm(_ed) cresp received to PAU request | |
| 29 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBR_1: PBR1 s4: MCP_PC_BK_WT_CRESP: abort_trm cresp received to PAU BKill request | |
| 30 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBR_2: PBR2 s4: Mis-aligned dma_pr_w/pr_dma_inj to AFU-MMIO space | |
| 31 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBR_3: PBR3 s4: rpt_hang.poll signalled hang condition | |
| 32 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBR_4: PBR4 s4: MCP_PC_WT_CRESP: Addr_Error received for self-lpc command (SSF) | |
| 33 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBR_5: PBR5 (reserved) | |
| 34 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBR_6: PBR6 (reserved) | |
| 35 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBR_7: PBR7 (reserved) | |
| 36 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_REG_0: REG0 s4: Address/Length/Alignment error on MMIO/GenId/Config access | |
| 37 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_REG_1: REG1 (reserved) | |
| 38 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_REG_2: REG2 (reserved) | |
| 39 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_REG_3: REG3 (reserved) | |
| 40 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_OCR_0: OCR0 s4: UT=0 to MMIO space bad cmd/length/alignment | |
| 41 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_OCR_1: OCR1 s4: Bad OC response received | |
| 42 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_OCR_2: OCR2 s4: AFU request w/ bad data received | |
| 43 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_OCR_3: OCR3 s4: Intrp_Req ObjHandle did not map to MMIO space | |
| 44 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_OCR_4: OCR4 s4: NVLink UT=0 to MMIO space bad cmd/length/alignment | |
| 45 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_OCR_5: OCR5 s4: UT=1 to MMIO space bad cmd/length/alignment | |
| 46 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_OCR_6: OCR6 s4: OCAPI request to MMIO space bad cmd/length/alignment | |
| 47 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_OCR_7: OCR7 s4: DMA write/atomic to MMIO space w/ Data error | |
| 48 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_OCR_8: OCR8 Epoch scanning did not complete before the next tick | |
| 49 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_OCR_9: OCR9 (reserved) | |
| 50 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_OCR_10: OCR10 (reserved) | |
| 51 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_OCR_11: OCR11 NVLink OCR error for brick 0 occurred | |
| 52 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_OCR_12: OCR12 NVLink OCR error for brick 1 occurred | |
| 53 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_OCR_13: OCR13 NVLink OCR error for brick 2 occurred | |
| 54 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_OCR_14: OCR14 NVLink OCR error for brick 3 occurred | |
| 55 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_OCR_15: OCR15 NVLink OCR error for brick 4 occurred | |
| 56:63 | RO | RO | constant=0b00000000 | |
| c_err_rpt hold-1 latches | ||||
|---|---|---|---|---|
| Addr: |
00000000110108D6 (SCOM) 00000000134200B0 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.MCP.MISC.CERR_HOLD1 | |||
| Constant(s): | ||||
| Comments: | c_err_rpt hold latches read-write-clear reg | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:3 | PAU3.CS.SM2.MCP.MISC.CERPT_NLGX.HOLD_LATCH_INST.HOLD.LATC.L2(0:3) [0000] | |||
| 4:7 | PAU3.CS.SM2.MCP.MISC.CERPT_FWD.HOLD_LATCH_INST.HOLD.LATC.L2(0:3) [0000] | |||
| 8:15 | PAU3.CS.SM2.MCP.MISC.CERPT_AUE.HOLD_LATCH_INST.HOLD.LATC.L2(0:7) [00000000] | |||
| 16:27 | PAU3.CS.SM2.MCP.MISC.CERPT_PBF.HOLD_LATCH_INST.HOLD.LATC.L2(0:11) [000000000000] | |||
| 28:31 | PAU3.CS.SM2.MCP.MISC.CERPT_LDA.HOLD_LATCH_INST.HOLD.LATC.L2(0:3) [0000] | |||
| 32:35 | PAU3.CS.SM2.MCP.MISC.CERPT_STA.HOLD_LATCH_INST.HOLD.LATC.L2(0:3) [0000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLGX_0: NLGX0 Unknown xtype in stage s0r of RXO pipe | |
| 1 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLGX_1: NLGX1 Unknown xtype in stage s2r of RXO pipe | |
| 2 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLGX_2: NLGX2 (reserved) | |
| 3 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLGX_3: NLGX3 (reserved) | |
| 4 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_FWD_0: FWD0 s4: Forward progress timer expired | |
| 5 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_FWD_1: FWD1 s4: rpt_hang.data waiting-for-data timeout | |
| 6 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_FWD_2: FWD2 (reserved) | |
| 7 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_FWD_3: FWD3 (reserved) | |
| 8 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_AUE_0: AUE0 UE ECC error detected from State-machine array | |
| 9 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_AUE_1: AUE1 UE ECC error detected from Rq/Rs output queue array | |
| 10 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_AUE_2: AUE2 UE ECC error detected from PowerBus data flit combiner array | |
| 11 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_AUE_3: AUE3 (reserved) | |
| 12 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_AUE_4: AUE4 UE ECC error detected from L2-Directory SRAM 0 | |
| 13 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_AUE_5: AUE5 UE ECC error detected from L2-Directory SRAM 1 | |
| 14 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_AUE_6: AUE6 UE ECC error detected from L2-Directory SRAM 2 | |
| 15 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_AUE_7: AUE7 UE ECC error detected from L2-Directory SRAM 3 | |
| 16 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBF_0: PBF0 s5: MCP_M_WT_CRESP: error cresp received for a command | |
| 17 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBF_1: PBF1 s5: MCP_PC_WT_CRESP: error cresp received for a command | |
| 18 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBF_2: PBF2 s4: MCP_PC_WT_CRESP: Addr_Error received for self-lpc command (SSF) | |
| 19 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBF_3: PBF3 s4: MCP_PC_BK_WT_CRESP: ack_dead cresp received for a bkill | |
| 20 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBF_4: PBF4 s5: MCP_M_RCV_DATA_PTL: not all segments/OWs were received | |
| 21 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBF_5: PBF5 s4: dma_pr_w/pr_dma_inj snooped that crosses 128B boundary | |
| 22 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBF_6: PBF6 s4: SMEV_DATIN: Received data with illegal data_stat value. | |
| 23 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBF_7: PBF7 Unexpected data beat received | |
| 24 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBF_8: PBF8 s7: addr_error CResp to internal PAU request | |
| 25 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBF_9: PBF9 (reserved) | |
| 26 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBF_10: PBF10 s5: Received 64B of data but snooped command wasn't cp_*(m=1) | |
| 27 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBF_11: PBF11 s5: Received 64B of data to PAU-mastered command | |
| 28 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_LDA_0: LDA0 s4: MCP_PC_WT_CRESP: Addr_Error received for load command (LD) | |
| 29 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_LDA_1: LDA1 (reserved) | |
| 30 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_LDA_2: LDA2 (reserved) | |
| 31 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_LDA_3: LDA3 (reserved) | |
| 32 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_STA_0: STA0 s4: MCP_PC_WT_CRESP: Addr_Error received for store command (ST) | |
| 33 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_STA_1: STA1 s4: MCP_PC_BK_WT_CRESP: Addr_Error received for bkill command (ST) | |
| 34 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_STA_2: STA2 (reserved) | |
| 35 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_STA_3: STA3 (reserved) | |
| 36:63 | RO | RO | constant=0b0000000000000000000000000000 | |
| c_err_rpt hold-2 latches | ||||
|---|---|---|---|---|
| Addr: |
00000000110108D7 (SCOM) 00000000134200B8 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.MCP.MISC.CERR_HOLD2 | |||
| Constant(s): | ||||
| Comments: | c_err_rpt hold latches read-write-clear reg | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM2.MCP.MISC.CERPT_NLG.HOLD_LATCH_INST.HOLD.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_0: NLG0 s4: Rcmd Event received but state machine is not IDLE | |
| 1 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_1: NLG1 s4: Pocket-Hit event but not in MCP_M_PCKT_WAIT_HIT/PC_* state | |
| 2 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_2: NLG2 s4: MCP_M_WT_CRESP: ma_scresp table lookup missed | |
| 3 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_3: NLG3 s4: MCP_M_WT_CRESP: start epsilon, but epsilon already in progress | |
| 4 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_4: NLG4 s5: MCP_M_WT_CRESP: ma_scresp indicated 'evaporate' but have xTL modified data | |
| 5 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_5: NLG5 s5: MCP_M_WT_CRESP: ma_scresp indicated 'evaporate' but have PB modified data | |
| 6 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_6: NLG6 s5: MCP_M_WT_CRESP: bad scenario code from ma_scresp table | |
| 7 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_7: NLG7 s4: snoop Cresp received but not in MCP_M_WT_CRESP state | |
| 8 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_8: NLG8 s4: Dir-Lock Event received but state machine is not MCP_PC_WT_CRESP/MCP_M_WAIT_SYN_PEND/MCP_M_WAIT_DIR_LOCK or bad ttype | |
| 9 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_9: NLG9 s4: MCP_PC_WT_CRESP: ma_mcresp table lookup missed | |
| 10 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_10: NLG10 s4/5: MCP_PC/_BK/_WT_CRESP: Write coll state didn't match early protection state | |
| 11 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_11: NLG11 s4: MCP_PC_WT_CRESP: start epsilon, but epsilon already in progress | |
| 12 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_12: NLG12 s5: MCP_PC_WT_CRESP: bad scenario code from ma_mcresp table | |
| 13 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_13: NLG13 s4: MCP_PC_BK_WT_CRESP: bad next-step for bkill (ack-done) | |
| 14 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_14: NLG14 s4: MCP_PC_BK_WT_CRESP: bad next-step for bkill (retry) | |
| 15 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_15: NLG15 s4: MCP_PC_BK_WT_CRESP: bad cresp for a bkill | |
| 16 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_16: NLG16 s4: master Cresp received but not in MCP_PC_WT_CRESP/MCP_PC_BK_WT_CRESP states | |
| 17 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_17: NLG17 s4: M_IDLE: Invalid DATALEN[3:0] for NVLink data command | |
| 18 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_18: NLG18 s4: M_IDLE: Invalid command type received | |
| 19 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_19: NLG19 s4: AT-translate-Response event but not in wait-translate state | |
| 20 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_20: NLG20 s4: AT-translate-Response event had bad translate status, but cmd not recognized | |
| 21 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_21: NLG21 s4: SA-Done event but not in wait-SA state | |
| 22 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_22: NLG22 s4: MCP_PC_WAIT_DATADONE: bad next-step for PB data transmit | |
| 23 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_23: NLG23 s4: MCP_TD_WAIT_DATADONE: Unknown NVLink Master Command | |
| 24 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_24: NLG24 s4: BuffDone event but not in PB/PC/MG/NR/XATS/MCP_TD_WAIT_DATADONE state | |
| 25 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_25: NLG25 s4: MCP_NC_WT_RESP: Unknown nv-master command for NVLink response | |
| 26 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_26: NLG26 s4: RG-RspIn event but not in MCP_RG_WT_RESP or MCP_NC_WT_RESP* state | |
| 27 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_27: NLG27 s4: Epsilon-In-Progress, but epsilon counter clock is not the epsilon clock | |
| 28 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_28: NLG28 s4: Epsilon counter clock is 'epsilon' but epsilon_ip is not set | |
| 29 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_29: NLG29 s4: MCP_PC_WT_BK_RBACK: bad next-step for bkill | |
| 30 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_30: NLG30 s4: M/RR_BACK timer expired but not in PC_WT(_BK)_RBACK state | |
| 31 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_31: NLG31 s4: Bad epclock value | |
| 32 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_32: NLG32 s4: coll_state is POCKET_RCOLL_ND but master state is not PCKT_WAIT_HIT | |
| 33 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_33: NLG33 s7: Did not find anything to do for a MCMD_COH response | |
| 34 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_34: NLG34 s4: Unknown Event type received | |
| 35 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_35: NLG35 s4: SMEV_DIRDONE received but sm_dir_upd_pending=0 | |
| 36 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_36: NLG36 s7: MCP_M_EVAL_DSA: Unknown merge opcode from dsa table | |
| 37 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_37: NLG37 s7: Unknown State | |
| 38 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_38: NLG38 s4: coll_state is POCKET_RCOLL_OND but master state is not PCKT_WAIT_HIT | |
| 39 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_39: NLG39 s4: Unknown sm_master_state in ESCAN_FENCE event | |
| 40 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_40: NLG40 s4: MCP_FENCE_WT_RESP_FILL: Unknown nv-master command for Fence-Fill-SUE response | |
| 41 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_41: NLG41 s4: MCP_M_WT_CRESP: impossible command/cresp | |
| 42 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_42: NLG42 s4: MCP_PC_WT_CRESP: impossible command/cresp | |
| 43 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_43: NLG43 s7: MCP_M_EVAL_DSA: impossible command/state | |
| 44 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_44: NLG44 s7: Unexpected Error State (bad sub-sequence return) | |
| 45 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_45: NLG45 s5: sfstat-retry but not in retry-abbks collision state | |
| 46 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_46: NLG46 s5: *cond*-retry but not in retry-abbks collision state | |
| 47 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_47: NLG47 s4: Request from CTL/xTL caused bad MMIO alignment, but cmd not recognized | |
| 48 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_48: NLG48 s5: MCP_NC_EXE_RESP: Unknown nv-master command for NVLink response | |
| 49 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_49: NLG49 s7: MCP_M_EVAL_DSA: Topology-index of the Request address is not valid in the topology-index table | |
| 50 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_50: NLG50 s4: Request from CTL/xTL caused bad MMIO alignment, but cmd not recognized | |
| 51 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_51: NLG51 s4: Request from CTL/xTL loaded into non-idle state-machine | |
| 52 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_52: NLG52 s4: POCKET-HIT event but coll_state is not POCKET_WINNER* | |
| 53 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_53: NLG53 s4: Unknown rspin event w/ unknown master-command in MCP_RG_WT_RESP state | |
| 54 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_54: NLG54 s7: Attempt to send PBus request but config_enable_pbus=0 | |
| 55 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_55: NLG55 s4: Invalid SrcBus on response from CTL | |
| 56 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_56: NLG56 s4: Shoulder-tap event but not in MCP_M_WT_SHOULDER_TAP state | |
| 57 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_57: NLG57 s7: MCP_M_EVAL_DSA: ma_dsasfe table lookup missed | |
| 58 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_58: NLG58 s7: MCP_M_EVAL_DSA: ma_dsac2alc table lookup missed | |
| 59 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_59: NLG59 s7: MCP_M_EVAL_DSA: ma_dsac2co table lookup missed | |
| 60 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_60: NLG60 s7: MCP_M_EVAL_DSA: ma_dsaoth table lookup missed | |
| 61 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_61: NLG61 s7: MCP_M_EVAL_DSA: ma_dsascan table lookup missed | |
| 62 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_62: NLG62 s7: Nothing to do after looking in DSA table | |
| 63 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_63: NLG63 s7: coherence update/response but directory lock is not DLOCK_MOD | |
| Perf Match Reg | ||||
|---|---|---|---|---|
| Addr: |
00000000110108D8 (SCOM) 00000000134200C0 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.MCP.MISC.PERF_MATCH_CONFIG | |||
| Constant(s): | ||||
| Comments: | Performance Event Field Match | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:43 | PAU3.CS.SM2.MCP.MISC.PERF_MATCH_CONFIG_Q_0_INST.LATC.L2(0:43) [00000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:23 | RW | RW | PERF_MATCH_RESERVED2: reserved | |
| 24:28 | RW | RW | PERF_MATCH_CRESP: CResp | |
| 29:31 | RW | RW | PERF_MATCH_SCOPE: Scope | |
| 32:41 | RW | RW | PERF_MATCH_MCMD: MCmd | |
| 42:43 | RW | RW | PERF_MATCH_RESERVED1: reserved | |
| 44:63 | RO | RO | constant=0b00000000000000000000 | |
| Perf Mask Reg | ||||
|---|---|---|---|---|
| Addr: |
00000000110108D9 (SCOM) 00000000134200C8 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.MCP.MISC.PERF_MASK_CONFIG | |||
| Constant(s): | ||||
| Comments: | Performance Event Field Mask | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:43 | PAU3.CS.SM2.MCP.MISC.PERF_MASK_CONFIG_Q_0_INST.LATC.L2(0:43) [00000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:23 | RW | RW | PERF_MASK_RESERVED2: reserved | |
| 24:28 | RW | RW | PERF_MASK_CRESP: CResp | |
| 29:31 | RW | RW | PERF_MASK_SCOPE: Scope | |
| 32:41 | RW | RW | PERF_MASK_MCMD: MCmd | |
| 42:43 | RW | RW | PERF_MASK_RESERVED1: reserved | |
| 44:63 | RO | RO | constant=0b00000000000000000000 | |
| Debug0 Config Reg | ||||
|---|---|---|---|---|
| Addr: |
00000000110108DA (SCOM) 00000000134200D0 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.MCP.MISC.DEBUG0_CONFIG | |||
| Constant(s): | ||||
| Comments: | Config register for trace-0 chain | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM2.MCP.MISC.DEBUG0_CONFIG_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:4 | RW | RW | DEBUG0_CONFIG_POD0: Mux control for byte 0 of trace-0 | |
| 5:9 | RW | RW | DEBUG0_CONFIG_POD1: Mux control for byte 1 of trace-0 | |
| 10:14 | RW | RW | DEBUG0_CONFIG_POD2: Mux control for byte 2 of trace-0 | |
| 15:19 | RW | RW | DEBUG0_CONFIG_POD3: Mux control for byte 3 of trace-0 | |
| 20:24 | RW | RW | DEBUG0_CONFIG_POD4: Mux control for byte 4 of trace-0 | |
| 25:29 | RW | RW | DEBUG0_CONFIG_POD5: Mux control for byte 5 of trace-0 | |
| 30:34 | RW | RW | DEBUG0_CONFIG_POD6: Mux control for byte 6 of trace-0 | |
| 35:39 | RW | RW | DEBUG0_CONFIG_POD7: Mux control for byte 7 of trace-0 | |
| 40:44 | RW | RW | DEBUG0_CONFIG_POD8: Mux control for byte 8 of trace-0 | |
| 45:49 | RW | RW | DEBUG0_CONFIG_POD9: Mux control for byte 9 of trace-0 | |
| 50:54 | RW | RW | DEBUG0_CONFIG_POD10: Mux control for byte 10 of trace-0 | |
| 55:62 | RW | RW | DEBUG0_CONFIG_RESERVED1: reserved | |
| 63 | RW | RW | DEBUG0_CONFIG_ACT: Enable clock-gates for debug trace latches | |
| Debug1 Config Reg | ||||
|---|---|---|---|---|
| Addr: |
00000000110108DB (SCOM) 00000000134200D8 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.MCP.MISC.DEBUG1_CONFIG | |||
| Constant(s): | ||||
| Comments: | Config register for trace-1 chain | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM2.MCP.MISC.DEBUG1_CONFIG_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:4 | RW | RW | DEBUG1_CONFIG_POD0: Mux control for byte 0 of trace-1 | |
| 5:9 | RW | RW | DEBUG1_CONFIG_POD1: Mux control for byte 1 of trace-1 | |
| 10:14 | RW | RW | DEBUG1_CONFIG_POD2: Mux control for byte 2 of trace-1 | |
| 15:19 | RW | RW | DEBUG1_CONFIG_POD3: Mux control for byte 3 of trace-1 | |
| 20:24 | RW | RW | DEBUG1_CONFIG_POD4: Mux control for byte 4 of trace-1 | |
| 25:29 | RW | RW | DEBUG1_CONFIG_POD5: Mux control for byte 5 of trace-1 | |
| 30:34 | RW | RW | DEBUG1_CONFIG_POD6: Mux control for byte 6 of trace-1 | |
| 35:39 | RW | RW | DEBUG1_CONFIG_POD7: Mux control for byte 7 of trace-1 | |
| 40:44 | RW | RW | DEBUG1_CONFIG_POD8: Mux control for byte 8 of trace-1 | |
| 45:49 | RW | RW | DEBUG1_CONFIG_POD9: Mux control for byte 9 of trace-1 | |
| 50:54 | RW | RW | DEBUG1_CONFIG_POD10: Mux control for byte 10 of trace-1 | |
| 55:62 | RW | RW | DEBUG1_CONFIG_RESERVED1: reserved | |
| 63 | RW | RW | DEBUG1_CONFIG_ACT: Enable clock-gates for debug trace latches | |
| Debug Machine-Pipe config 3 | ||||
|---|---|---|---|---|
| Addr: |
00000000110108DC (SCOM) 00000000134200E0 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.MCP.MISC.DEBUG3_CONFIG | |||
| Constant(s): | ||||
| Comments: | Config register for machine-pipe fields into internal-group 4 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM2.MCP.MISC.DEBUG3_CONFIG_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:6 | RW | RW | DEBUG_CONFIG_MACH_BYTE0: Mux control for mach byte 0 | |
| 7:13 | RW | RW | DEBUG_CONFIG_MACH_BYTE1: Mux control for mach byte 1 | |
| 14:20 | RW | RW | DEBUG_CONFIG_MACH_BYTE2: Mux control for mach byte 2 | |
| 21:27 | RW | RW | DEBUG_CONFIG_MACH_BYTE3: Mux control for mach byte 3 | |
| 28:34 | RW | RW | DEBUG_CONFIG_MACH_BYTE4: Mux control for mach byte 4 | |
| 35:41 | RW | RW | DEBUG_CONFIG_MACH_BYTE5: Mux control for mach byte 5 | |
| 42:48 | RW | RW | DEBUG_CONFIG_MACH_BYTE6: Mux control for mach byte 6 | |
| 49:55 | RW | RW | DEBUG_CONFIG_MACH_BYTE7: Mux control for mach byte 7 | |
| 56:62 | RW | RW | DEBUG_CONFIG_MACH_BYTE8: Mux control for mach byte 8 | |
| 63 | RW | RW | DEBUG_CONFIG_MACH_ACT: Clock-gate enable for mach byte latches | |
| Debug Machine-Pipe config 4 | ||||
|---|---|---|---|---|
| Addr: |
00000000110108DD (SCOM) 00000000134200E8 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.MCP.MISC.DEBUG4_CONFIG | |||
| Constant(s): | ||||
| Comments: | Config register for machine-pipe fields into internal-group 4 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:51 | PAU3.CS.SM2.MCP.MISC.DEBUG4_CONFIG_Q_0_INST.LATC.L2(0:51) [0000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:6 | RW | RW | DEBUG_CONFIG_MACH_BYTE9: Mux control for mach byte 9 | |
| 7:13 | RW | RW | DEBUG_CONFIG_MACH_BYTE10: Mux control for mach byte 10 | |
| 14:20 | RW | RW | DEBUG_CONFIG_MACH_BYTE11: Mux control for mach byte 11 | |
| 21:27 | RW | RW | DEBUG_CONFIG_MACH_BYTE12: Mux control for mach byte 12 | |
| 28:34 | RW | RW | DEBUG_CONFIG_MACH_BYTE13: Mux control for mach byte 13 | |
| 35:41 | RW | RW | DEBUG_CONFIG_MACH_BYTE14: Mux control for mach byte 14 | |
| 42:48 | RW | RW | DEBUG_CONFIG_MACH_BYTE15: Mux control for mach byte 15 | |
| 49:51 | RW | RW | DEBUG_CONFIG_MACH_RESERVED1: reserved | |
| 52:63 | RO | RO | constant=0b000000000000 | |
| CQ_SM Misc Config register #2 | ||||
|---|---|---|---|---|
| Addr: |
00000000110108DE (SCOM) 00000000134200F0 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.MCP.MISC.CONFIG2 | |||
| Constant(s): | ||||
| Comments: | Misc config register Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM2.MCP.MISC.CONFIG2_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:11 | RW | RW | CONFIG_MCP_FIR_TO_INHIBIT_MASK: Mask of FIR bits that should force inhibit-all Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 12 | RW | RW | CONFIG_BRK0_FENCE_TO_INHIBIT_MASK: 0/1 = brick-0 fence operates normally / brick-0 fence inhibits everything Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 13 | RW | RW | CONFIG_BRK1_FENCE_TO_INHIBIT_MASK: 0/1 = brick-1 fence operates normally / brick-1 fence inhibits everything Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 14 | RW | RW | CONFIG_BRK2_FENCE_TO_INHIBIT_MASK: 0/1 = brick-2 fence operates normally / brick-2 fence inhibits everything Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 15 | RW | RW | CONFIG_BRK3_FENCE_TO_INHIBIT_MASK: 0/1 = brick-3 fence operates normally / brick-3 fence inhibits everything Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 16 | RW | RW | CONFIG_BRK4_FENCE_TO_INHIBIT_MASK: 0/1 = brick-4 fence operates normally / brick-4 fence inhibits everything Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 17 | RW | RW | CONFIG_ENABLE_PHASE1_DCBF: 0/1 = disable DCARM (PB V5 arch sec 9.6) protocol for dcbf,dcbfc,dcbfps (group 1) / enable dcarm protocol | |
| 18 | RW | RW | CONFIG_ENABLE_PHASE1_CLEAN: 0/1 = disable DCARM (PB V5 arch sec 9.6) protocol for dcbfstp (group 2) / enable dcarm protocol | |
| 19 | RW | RW | CONFIG_ENABLE_PHASE1_AMO: 0/1 = disable DCARM (PB V5 arch sec 9.6) protocol for armw*,armwf* (group 3) / enable dcarm protocol | |
| 20:31 | RW | RW | CONFIG_DCARM_TIMER: timeout value for DCARM phase-2 measured in PowerBus epsilon steps | |
| 32:33 | RW | RW | CONFIG_BRK0_EXT_MEM_TAGS: Even and Odd iSeries tag bits for brick-0 OCAPI 128B dma_w (Extended memory) | |
| 34:35 | RW | RW | CONFIG_BRK1_EXT_MEM_TAGS: Even and Odd iSeries tag bits for brick-1 OCAPI 128B dma_w (Extended memory) | |
| 36:37 | RW | RW | CONFIG_BRK2_EXT_MEM_TAGS: Even and Odd iSeries tag bits for brick-2 OCAPI 128B dma_w (Extended memory) | |
| 38:39 | RW | RW | CONFIG_BRK3_EXT_MEM_TAGS: Even and Odd iSeries tag bits for brick-3 OCAPI 128B dma_w (Extended memory) | |
| 40:41 | RW | RW | CONFIG_BRK4_EXT_MEM_TAGS: Even and Odd iSeries tag bits for brick-4 OCAPI 128B dma_w (Extended memory) | |
| 42 | RW | RW | CONFIG_PB_TO_OC_FASTPATH_MASTER_ENABLE: 0/1 = disable sending OC read request at RCmd / enable sending early OC read request before CResp | |
| 43 | RW | RW | CONFIG_PB_TO_OC_FASTPATH_ENABLE_READ: 0/1 = disable sending fastpath oc read for rd_go_s, rd_go_m, rd_larx / enable fastpath. | |
| 44 | RW | RW | CONFIG_PB_TO_OC_FASTPATH_ENABLE_PREF: 0/1 = disable sending fastpath oc read for pref_go_s, pref_go_m / enable fastpath. | |
| 45 | RW | RW | CONFIG_PB_TO_OC_FASTPATH_ENABLE_DMA: 0/1 = disable sending fastpath oc read for cl_dma_rd, cl_rd_nc / enable fastpath. | |
| 46 | RW | RW | CONFIG_PB_TO_OC_FASTPATH_ENABLE_RWITM: 0/1 = disable sending fastpath oc read for rwitm, rwitm_stwx / enable fastpath. | |
| 47 | RW | RW | CONFIG_PB_TO_OC_FASTPATH_ENABLE_CI: 0/1 = disable sending fastpath oc read for ci_pr_rd / enable fastpath. | |
| 48 | RW | RW | CONFIG_PB_TO_OC_FASTPATH_REQUIRE_QOS_1: 0/1 = for fastpath oc reads, don't-care the q (QoS) bit in reads / require the q bit to be '1' if it exists. | |
| 49 | RW | RW | CONFIG_PB_TO_OC_FASTPATH_REQUIRE_HINT_0: 0/1 = for fastpath oc reads, don't-care the h (hint) bit in reads / require the h bit to be '0' if it exists. | |
| 50:51 | RW | RW | CONFIG_PB_TO_OC_FASTPATH_REQUIRE_CL: for fastpath oc reads, require the cl0/cl1 field (if it exists) to be >= this value. | |
| 52 | RW | RW | CONFIG_PB_TO_OC_FASTPATH_REQUIRE_LD_PR_1: 0/1 = for fastpath oc reads, don't-care the ld_pr (load promote) bit in reads / require the ld_pr bit to be '1' if it exists. | |
| 53 | RW | RW | CONFIG_PB_TO_OC_FASTPATH_REQUIRE_RXO_EMPTY: 0/1 = for fastpath oc reads, don't require the RXO queue to be empty / require the RXO request-out queue to be empty | |
| 54 | RW | RW | CONFIG_DISABLE_HW551717_PTLA_TO_UCI: 0/1 = enable swapping pr_wr_mem_ptla_uco to pr_wr_mem_ptla_uci / disable fix | |
| 55 | RW | RW | CONFIG_DISABLE_HW552185_BKRETRY_TO_RMA: 0/1 = enable using COLL_RMA in place of bkretry / disable fix | |
| 56 | RW | RW | CONFIG_ENABLE_HW549830_MI_RETRY_NON_CP: 0/1 = disable hw549830 fix / enable retrying non-cp commands back to requesting PAU when retried on the PowerBus. | |
| 57:60 | RW | RW | CONFIG_HW549830_MI_RETRY_THRESH: Number of retries on the PowerBus before retrying the non-cp command back to the source PAU. | |
| 61:63 | RW | RW | CONFIG2_RESERVED: Reserved | |
| Timer Config Reg 2 | ||||
|---|---|---|---|---|
| Addr: |
00000000110108DF (SCOM) 00000000134200F8 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.MCP.MISC.XTIMER2_CONFIG | |||
| Constant(s): | ||||
| Comments: | Timer Configuration Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:11 | PAU3.CS.SM2.MCP.MISC.XTIMER2_CONFIG_Q_0_INST.LATC.L2(0:11) [000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:5 | RW | RW | CONFIG_INH2_TICK: Rate for SM-Inhibit timer tick 2 (default 63=off) | |
| 6:11 | RW | RW | CONFIG_INH3_TICK: Rate for SM-Inhibit timer tick 3 (default 63=off) | |
| 12:63 | RO | RO | constant=0b0000000000000000000000000000000000000000000000000000 | |
| CQ_DIR Misc Config register #0 | ||||
|---|---|---|---|---|
| Addr: |
00000000110108E8 (SCOM) 0000000013420140 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.DIR.MISC.CONFIG0 | |||
| Constant(s): | ||||
| Comments: | Misc config register Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM2.DIR.MISC.CONFIG0Q.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:3 | RW | RW | CONFIG_HOST_TAG_SIZE: Configured host tag size (in bits) Must be less than or equal to the maximum host tag size supported by the AFUs connected to this PAU. 15 = maximum host tag size supported 6 = minimum host tag size supported 5..0 = reserved values, do not use | |
| 4:62 | RW | RW | CONFIG0_RESERVED: Reserved | |
| 63 | RW | RW | CONFIG_DEBUG0_ACT: Clock-gate enable for debug0 latches | |
| Perf Config Reg | ||||
|---|---|---|---|---|
| Addr: |
00000000110108E9 (SCOM) 0000000013420148 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.DIR.MISC.PERF_CONFIG | |||
| Constant(s): | ||||
| Comments: | Performance Event selection | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM2.DIR.MISC.PERF_CONFIGQ.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:27 | RW | RW | PERF_CONFIG_RESERVED1: reserved | |
| 28:35 | RW | RW | PERF_CONFIG_EVENT0: Event 0 select 0: count nothing 1: count cycles others: reserved (count nothing) | |
| 36:43 | RW | RW | PERF_CONFIG_EVENT1: Event 1 select See Event 0 select for encodes | |
| 44:51 | RW | RW | PERF_CONFIG_EVENT2: Event 2 select See Event 0 select for encodes | |
| 52:59 | RW | RW | PERF_CONFIG_EVENT3: Event 3 select See Event 0 select for encodes | |
| 60:62 | RW | RW | PERF_CONFIG_RESERVED2: reserved | |
| 63 | RW | RW | PERF_CONFIG_ACT: Enable clock-gates for performance monitor latches | |
| Debug0 Config Reg | ||||
|---|---|---|---|---|
| Addr: |
00000000110108EA (SCOM) 0000000013420150 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.DIR.MISC.DEBUG0_CONFIG | |||
| Constant(s): | ||||
| Comments: | Config register for trace-0 chain | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM2.DIR.MISC.DEBUG0_CONFIGQ.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:4 | RW | RW | DEBUG0_CONFIG_POD0: Mux control for byte 0 of trace-0 | |
| 5:9 | RW | RW | DEBUG0_CONFIG_POD1: Mux control for byte 1 of trace-0 | |
| 10:14 | RW | RW | DEBUG0_CONFIG_POD2: Mux control for byte 2 of trace-0 | |
| 15:19 | RW | RW | DEBUG0_CONFIG_POD3: Mux control for byte 3 of trace-0 | |
| 20:24 | RW | RW | DEBUG0_CONFIG_POD4: Mux control for byte 4 of trace-0 | |
| 25:29 | RW | RW | DEBUG0_CONFIG_POD5: Mux control for byte 5 of trace-0 | |
| 30:34 | RW | RW | DEBUG0_CONFIG_POD6: Mux control for byte 6 of trace-0 | |
| 35:39 | RW | RW | DEBUG0_CONFIG_POD7: Mux control for byte 7 of trace-0 | |
| 40:44 | RW | RW | DEBUG0_CONFIG_POD8: Mux control for byte 8 of trace-0 | |
| 45:49 | RW | RW | DEBUG0_CONFIG_POD9: Mux control for byte 9 of trace-0 | |
| 50:54 | RW | RW | DEBUG0_CONFIG_POD10: Mux control for byte 10 of trace-0 | |
| 55:62 | RW | RW | DEBUG0_CONFIG_RESERVED1: reserved | |
| 63 | RW | RW | DEBUG0_CONFIG_ACT: Enable clock-gates for debug trace latches | |
| Debug1 Config Reg | ||||
|---|---|---|---|---|
| Addr: |
00000000110108EB (SCOM) 0000000013420158 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.DIR.MISC.DEBUG1_CONFIG | |||
| Constant(s): | ||||
| Comments: | Config register for trace-1 chain | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM2.DIR.MISC.DEBUG1_CONFIGQ.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:4 | RW | RW | DEBUG1_CONFIG_POD0: Mux control for byte 0 of trace-1 | |
| 5:9 | RW | RW | DEBUG1_CONFIG_POD1: Mux control for byte 1 of trace-1 | |
| 10:14 | RW | RW | DEBUG1_CONFIG_POD2: Mux control for byte 2 of trace-1 | |
| 15:19 | RW | RW | DEBUG1_CONFIG_POD3: Mux control for byte 3 of trace-1 | |
| 20:24 | RW | RW | DEBUG1_CONFIG_POD4: Mux control for byte 4 of trace-1 | |
| 25:29 | RW | RW | DEBUG1_CONFIG_POD5: Mux control for byte 5 of trace-1 | |
| 30:34 | RW | RW | DEBUG1_CONFIG_POD6: Mux control for byte 6 of trace-1 | |
| 35:39 | RW | RW | DEBUG1_CONFIG_POD7: Mux control for byte 7 of trace-1 | |
| 40:44 | RW | RW | DEBUG1_CONFIG_POD8: Mux control for byte 8 of trace-1 | |
| 45:49 | RW | RW | DEBUG1_CONFIG_POD9: Mux control for byte 9 of trace-1 | |
| 50:54 | RW | RW | DEBUG1_CONFIG_POD10: Mux control for byte 10 of trace-1 | |
| 55:62 | RW | RW | DEBUG1_CONFIG_RESERVED1: reserved | |
| 63 | RW | RW | DEBUG1_CONFIG_ACT: Enable clock-gates for debug trace latches | |
| SCOM L2 Data Reg | ||||
|---|---|---|---|---|
| Addr: |
00000000110108EC (SCOM) 0000000013420160 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.DIR.MISC.SCOM_L2_DATA | |||
| Constant(s): | ||||
| Comments: | Read-only register for SCOM reads of the L2 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM2.DIR.MISC.SCOM_L2_DATAQ.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:63 | ROX | ROX | L2_SCOM_READ_DATA: Data read out of the L2 directory by the SCOM interface | |
| CQ_SM Misc Config register #0 | ||||
|---|---|---|---|---|
| Addr: |
00000000110108F0 (SCOM) 0000000013420180 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.SNP.MISC.CONFIG0 | |||
| Constant(s): | ||||
| Comments: | Misc config register Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM2.SNP.MISC.CONFIG0_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:1 | RW | RW | CONFIG_MA_RSNOOP_OPT_DCLAIM: 0 = partial-respond to dclaim to GPU Mem with lpc_ack 1 = (deprecated - do not use) partial-respond to dclaim to GPU Mem with lpc_ack+rty_lost_claim Nv: 2 = partial-respond to dclaim to GPU Mem with lpc_ack+rty_lpc+start pocket cache Oc: 2 = reserved (must not be set when config_ocapi_mode=1 for this stack) 3 = reserved | |
| 2 | RW | RW | CONFIG_ENABLE_PBUS: 0/1 = disable PAU PowerBus RCmd, PResp, and CResp interfaces / enable these interfaces Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 3 | RW | RW | CONFIG_BRAZOS_MODE: Reserved (was: brazos_mode 0/1 = non-brazos 4-group;2-chip mode / brazos 2-group;4-chip mode) | |
| 4 | RW | RW | CONFIG_PCKT_BLK_PRB: 0/1 = valid pocket-cache entries do not block probes / probes are blocked | |
| 5 | RW | RW | CONFIG_ADR_BAR_MODE: Reserved (was: PowerBus adr_bar: 0/1 = large-system-mode/small-system-mode) | |
| 6 | RW | RW | CONFIG_RESTRICT_CHIP_GROUP: Reserved (was: 0/1 = support all 16 groups and all 8 chips / restrict chip/group to 4/2 or 2/4) | |
| 7 | RW | RW | CONFIG_DISABLE_HW552185_BKRETRY_TO_RMA: 0/1 = 'or' hit_rma into hit_bk_rty_abbk and hit_pckt_win signals / disable fix | |
| 8 | RW | RW | CONFIG0_RESERVED3: reserved | |
| 9:15 | RW | RW | CONFIG_SNP_FIR_TO_INHIBIT_MASK: Mask of FIR bits that should force inhibit-all Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 16 | RW | RW | CONFIG_BRK0_FENCE_TO_INHIBIT_MASK: 0/1 = brick-0 fence operates normally / brick-0 fence inhibits everything Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 17 | RW | RW | CONFIG_BRK1_FENCE_TO_INHIBIT_MASK: 0/1 = brick-1 fence operates normally / brick-1 fence inhibits everything Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 18 | RW | RW | CONFIG_BRK2_FENCE_TO_INHIBIT_MASK: 0/1 = brick-2 fence operates normally / brick-2 fence inhibits everything Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 19 | RW | RW | CONFIG_BRK3_FENCE_TO_INHIBIT_MASK: 0/1 = brick-3 fence operates normally / brick-3 fence inhibits everything Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 20 | RW | RW | CONFIG_BRK4_FENCE_TO_INHIBIT_MASK: 0/1 = brick-4 fence operates normally / brick-4 fence inhibits everything Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 21 | RW | RW | CONFIG_MRBGP_TRACK_ALL: 0/1 = master-retry-backoff group-pump track only this stack's/all-this-chips retry responses | |
| 22 | RW | RW | CONFIG_MRBSP_TRACK_ALL: 0/1 = master-retry-backoff system-pump track only this stack's/all-this-chips retry responses | |
| 23 | RW | RW | CONFIG_MRBCP_TRACK_ALL: 0/1 = master-retry-backoff chip-pump track only this stack's/all-this-chips retry responses | |
| 24:30 | RW | RW | CONFIG_ADDR_EX_MASK_ENA: Reserved (was: Mask for address bits to ignore when checking for different-group/different-chip when calculating initial scope.) aka config_chip_address_extension_mask_enable(15:21) | |
| 31 | RW | RW | CONFIG_SINGLE_AFU_DUAL_BRICK: 0/1 = AFU(s) use only one brick / 1 AFU is using both bricks on this ramp (the only effect of this bit is to 'wildcard' brick numbers when processing XSL-castouts) | |
| 32 | RW | RW | CONFIG_BRK0_OCAPI_MODE: 0/1 = Disable OpenCAPI mode / enable OpenCAPI mode for brick 0 (mutually exclusive with config_brk0_nvlink_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 33 | RW | RW | CONFIG_BRK1_OCAPI_MODE: 0/1 = Disable OpenCAPI mode / enable OpenCAPI mode for brick 1 (mutually exclusive with config_brk1_nvlink_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 34 | RW | RW | CONFIG_BRK2_OCAPI_MODE: 0/1 = Disable OpenCAPI mode / enable OpenCAPI mode for brick 2 (mutually exclusive with config_brk2_nvlink_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 35 | RW | RW | CONFIG_BRK3_OCAPI_MODE: 0/1 = Disable OpenCAPI mode / enable OpenCAPI mode for brick 3 (mutually exclusive with config_brk3_nvlink_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 36 | RW | RW | CONFIG_BRK4_OCAPI_MODE: 0/1 = Disable OpenCAPI mode / enable OpenCAPI mode for brick 4 (mutually exclusive with config_brk4_nvlink_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 37 | RW | RW | CONFIG_BRK0_NVLINK_MODE: 0/1 = Disable NVLink mode / enable NVLink mode for brick 0 (mutually exclusive with config_brk0_ocapi_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 38 | RW | RW | CONFIG_BRK1_NVLINK_MODE: 0/1 = Disable NVLink mode / enable NVLink mode for brick 1 (mutually exclusive with config_brk1_ocapi_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 39 | RW | RW | CONFIG_BRK2_NVLINK_MODE: 0/1 = Disable NVLink mode / enable NVLink mode for brick 2 (mutually exclusive with config_brk2_ocapi_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 40 | RW | RW | CONFIG_BRK3_NVLINK_MODE: 0/1 = Disable NVLink mode / enable NVLink mode for brick 3 (mutually exclusive with config_brk3_ocapi_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 41 | RW | RW | CONFIG_BRK4_NVLINK_MODE: 0/1 = Disable NVLink mode / enable NVLink mode for brick 4 (mutually exclusive with config_brk4_ocapi_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 42 | RW | RW | CONFIG_ENABLE_BLOCKING_RCMD_DIR: 0/1 = disable blocking RCmd dir lookups to give bandwidth to internal accesses / enable blocking | |
| 43 | RW | RW | CONFIG_DISABLE_DIR_POWERSAVE: 0/1 = allow clock-gating empty directory lookups to save power / disable clock-gating | |
| 44 | RW | RW | CONFIG_DISABLE_PRESP_POWERSAVE: 0/1 = allow clock-gating empty CAM+DIR PResps to save power / disable clock-gating | |
| 45 | RW | RW | CONFIG_ENABLE_BRK0_OCAPI_C2: 0/1 = disable receiving OCAPI C2 opcodes / enable receiving on brick 0 | |
| 46 | RW | RW | CONFIG_ENABLE_BRK1_OCAPI_C2: 0/1 = disable receiving OCAPI C2 opcodes / enable receiving on brick 1 | |
| 47 | RW | RW | CONFIG_ENABLE_BRK2_OCAPI_C2: 0/1 = disable receiving OCAPI C2 opcodes / enable receiving on brick 2 | |
| 48 | RW | RW | CONFIG_ENABLE_BRK3_OCAPI_C2: 0/1 = disable receiving OCAPI C2 opcodes / enable receiving on brick 3 | |
| 49 | RW | RW | CONFIG_ENABLE_BRK4_OCAPI_C2: 0/1 = disable receiving OCAPI C2 opcodes / enable receiving on brick 4 | |
| 50 | RW | RW | CONFIG_DISABLE_CAN_BY_CP: 0/1 = enable cancel-by-cp logic / disable cancel-by-cp logic | |
| 51 | RW | RW | CONFIG0_RESERVED1: reserved (was: chicken switch hw483005) | |
| 52 | RW | RW | CONFIG0_RESERVED2: reserved (was: chicken switch hw484205) | |
| 53 | RW | RW | CONFIG0_RESERVED4: reserved (was: chicken switch hw484205) | |
| 54 | RW | RW | CONFIG0_RESERVED5: reserved (was: chicken switch hw484205) | |
| 55 | RW | RW | CONFIG0_RESERVED6: reserved (was: chicken switch hw484099) | |
| 56 | RW | RW | CONFIG0_RESERVED7: reserved (was: chicken switch hw484668) | |
| 57 | RW | RW | CONFIG0_RESERVED8: reserved (was: chicken switch hw484695) | |
| 58 | RW | RW | CONFIG0_RESERVED9: reserved (was: chicken switch hw484972) | |
| 59 | RW | RW | CONFIG0_RESERVED10: reserved (was: chicken switch hw485798) | |
| 60 | RW | RW | CONFIG_DISABLE_CAN_BY_PROBE: 0/1 = enable cancel-by-probe logic / disable cancel-by-probe logic | |
| 61 | RW | RW | CONFIG_HANG_ON_ADDRESS_ERRORS: 0/1 = abort and continue on CResp=addr_error / hang state-machine on CResp=addr_error | |
| 62 | RW | RW | CONFIG_DISABLE_HW521165_SFE_BLOCKS_CASTOUT: 0/1 = enable hw521165 fix / disable and allow SFE to block castouts | |
| 63 | RW | RW | CONFIG_DISABLE_HW517982_PSNOOP_MISS_PRESP_NULL: 0/1 = enable hw517982 fix to force PResp=null for psnoop table miss / disable fix. | |
| CQ_SM Misc Config register #1 | ||||
|---|---|---|---|---|
| Addr: |
00000000110108F1 (SCOM) 0000000013420188 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.SNP.MISC.CONFIG1 | |||
| Constant(s): | ||||
| Comments: | Misc config register Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM2.SNP.MISC.CONFIG1_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:3 | RW | RW | CONFIG_SCALE_RPT_HANG_POLL: Scaling factor for rpt_hang.poll 0 = 1:1 PowerBus rpt_hang.polls received 1 = 1:2 PowerBus rpt_hang.polls received ... 15 = 1:16 PowerBus rpt_hang.polls received | |
| 4:7 | RW | RW | CONFIG_SCALE_RPT_HANG_DATA: Scaling factor for rpt_hang.data 0 = 1:1 PowerBus rpt_hang.datas received 1 = 1:2 PowerBus rpt_hang.datas received ... 15 = 1:16 PowerBus rpt_hang.datas received | |
| 8:11 | RW | RW | CONFIG_HOST_TAG_SIZE: Configured host tag size (in bits) Must be less than or equal to the maximum host tag size supported by the AFUs connected to this PAU. 15 = maximum host tag size supported 6 = minimum host tag size supported 5..0 = reserved values, do not use | |
| 12:15 | RW | RW | CONFIG_ARB_NONCRR_SAFETY: Safety valve for non-cresp/non-reqin events going down the arb pipe. after N+1 reqin events go through the arbiter while a non-crr event is waiting, reqin events are blocked to give non-crr events a chance. | |
| 16:18 | RW | RW | CONFIG_REPLAY_IP_LIMIT: Limit on number of replays in-progress in the snoop/directory pipe. Must not be set to zero | |
| 19 | RW | RW | CONFIG1_RESERVED1: Reserved | |
| 20:23 | RW | RW | CONFIG_BLOCK_FOR_REPLAY_TIME: Controls the # of cycles to count before forcing an opportunity for a 'replay' to access the directory 0 = 16 cycles 1 = 15 cycles ... 15 = 1 cycle | |
| 24:27 | RW | RW | CONFIG_BLOCK_FOR_DIRSCAN_TIME: Controls the # of cycles to count before forcing an opportunity for a directory-scan to access the directory 0 = 16 cycles 1 = 15 cycles ... 15 = 1 cycle | |
| 28:29 | RW | RW | CONFIG_THROT_ADDR_HASH: select the addr hash crc function used for PWR0/1/2 throttling | |
| 30 | RW | RW | CONFIG_DISABLE_HW510185_DIR_WALKER_REF_COUNT: 0/1 = enable hw510185 dir walker ref counts / disable and return to single-threaded evicts. | |
| 31 | RW | RW | CONFIG_ENABLE_OPENCAPI_NETWORKING: 0/1 = disable networking / enable OpenCAPI MI networking mode. | |
| 32 | RW | RW | CONFIG_NETWORKING_GVC_LOCATION: 0/1 = GVC in PowerBus RA(8:11) / GVC in PowerBus RA(20:23) | |
| 33 | RW | RW | CONFIG_TORUS_ENABLE_E_TO_A: 0/1 = Disable Torus from transferring VC-E into VC-A / Enable Torus to tranfer VC-E into VC-A. | |
| 34 | RW | RW | CONFIG_NETWORKING_SUPPRESS_CAM: 0/1 = Allow CAM results to retry networking RCmds / Disable CAM results for networking RCmds. | |
| 35 | RW | RW | CONFIG_DISABLE_HW532135_FENCE_SHARED_C2_ALC: 0/1 = enable shared state for c2-allocating requests when fenced / disable fix | |
| 36 | RW | RW | CONFIG_TORUS_ENABLE_VC_A: 0/1 = disable torus mode using VC-A (only use VC-E & VC-HP) / enable torus using VC-A | |
| 37 | RW | RW | CONFIG_TORUS_ENABLE_FAIRNESS: 0/1 = disable torus continuation vs new-insertion fairness / enable fairness mechanism | |
| 38:39 | RW | RW | CONFIG1_RESERVED2: Reserved | |
| 40:43 | RW | RW | CONFIG_BRK0_TORUS_NEW_INS_ACC_DEC: (brick 0) Amount to subtract (x4+3) from the fairness counter when a new-insertion is accepted. | |
| 44:47 | RW | RW | CONFIG_BRK0_TORUS_NEW_INS_REJ_INC: (brick 0) Amount to add to the fairness counter when a new-insertion is rejected and the counter is primed. | |
| 48:51 | RW | RW | CONFIG_BRK0_TORUS_CONT_ACC_INC: (brick 0) Amount to add to the fairness counter when a continuation is accepted in the forward-progress state. | |
| 52:55 | RW | RW | CONFIG_BRK1_TORUS_NEW_INS_ACC_DEC: (brick 1) Amount to subtract (x4+3) from the fairness counter when a new-insertion is accepted. | |
| 56:59 | RW | RW | CONFIG_BRK1_TORUS_NEW_INS_REJ_INC: (brick 1) Amount to add to the fairness counter when a new-insertion is rejected and the counter is primed. | |
| 60:63 | RW | RW | CONFIG_BRK1_TORUS_CONT_ACC_INC: (brick 1) Amount to add to the fairness counter when a continuation is accepted in the forward-progress state. | |
| GPU0-Memory BAR | ||||
|---|---|---|---|---|
| Addr: |
00000000110108F2 (SCOM) 0000000013420190 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.SNP.MISC.GPU0_BAR | |||
| Constant(s): | ||||
| Comments: | BAR register defining GPU Mem addresses serviced by brick 0 connected to this stack. Note: This register should be set to the same value for each brick/stack. MDials have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:51 | PAU3.CS.SM2.SNP.MISC.GPU0_BAR_Q_0_INST.LATC.L2(0:51) [0000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_GPU0_BAR_ENABLE: Enable for this BAR (0=disabled, 1=enabled) for brick 0 | |
| 1:35 | RW | RW | CONFIG_GPU0_BAR_ADDR_MASK: BAR Address/Mask bits 1:35 for brick 0 In Small-BAR mode (see bit 36): 1:7 = Base_Addr(13:19) = 16T slice 8:21 = Base_Addr(20:33) = 1G address in slice 22:35 = Base_Mask(20:33) = 1G...16T BAR size. (Note: Mask limited to 1G...4T in Axone and P10 w/ GPU systems) In Large-BAR mode (see bit 36): 1 = '1' to match MemSel = addr(13:14) = 0b00 2 = '1' to match MemSel = addr(13:14) = 0b01 3 = '1' to match MemSel = addr(13:14) = 0b10 4:35 = Topology_Id_Mask(0:31) when chip_eq_group=0, TIM(0:31) bit 'i' corresponds to addr(15:19) = 'i' when chip_eq_group=1, TIM(0:31) bit 'i' corresponds to (addr(15:16) & addr(19:21)) = 'i' | |
| 36 | RW | RW | CONFIG_GPU0_BAR_SL_MODE: 0/1 = Small-BAR/Large-BAR Mode selector | |
| 37 | RW | RW | CONFIG_GPU0_BAR_4T_LIMIT: 0 = no limit, 16T slices can be used. 1 = limit slices to 4T. -> when chip_eq_group=0, addr(20:21) must match bar_4t_select -> when chip_eq_group=1, addr(17:18) must match bar_4t_select limit=1 is used in P10 systems w/ a GPU or in Axone systems | |
| 38:39 | RW | RW | CONFIG_GPU0_BAR_4T_SELECT: when bar_4t_limit=1 this field selects the value in addr(20:21) to match | |
| 40:43 | RW | RW | CONFIG_GPU0_BAR_MODE: Hash mode of the BAR for brick 0: if bar_extended_mode == 0: 0 = (single) match on all address in addr/size 1 = (dual.0) match if hashbits(7)=0 2 = (dual.1) match if hashbits(7)=1 3 = (triple.0) match if hashbits%3=0 4 = (triple.1) match if hashbits%3=1 5 = (triple.2) match if hashbits%3=2 6 = (quad.0) match if hashbits(6:7)=0 7 = (quad.1) match if hashbits(6:7)=1 8 = (quad.2) match if hashbits(6:7)=2 9 = (quad.3) match if hashbits(6:7)=3 10 = (six.0) match if hashbits%3=0 and hashbits(7)=0 11 = (six.1) match if hashbits%3=0 and hashbits(7)=1 12 = (six.2) match if hashbits%3=1 and hashbits(7)=0 13 = (six.3) match if hashbits%3=1 and hashbits(7)=1 14 = (six.4) match if hashbits%3=2 and hashbits(7)=0 15 = (six.5) match if hashbits%3=2 and hashbits(7)=1 if bar_extended_mode == 1: 0 = (oct.0) match if hashbits(5:7)=0 1 = (oct.1) match if hashbits(5:7)=1 2 = (oct.2) match if hashbits(5:7)=2 3 = (oct.3) match if hashbits(5:7)=3 4 = (oct.4) match if hashbits(5:7)=4 5 = (oct.5) match if hashbits(5:7)=5 6 = (oct.6) match if hashbits(5:7)=6 7 = (oct.7) match if hashbits(5:7)=7 others = reserved | |
| 44 | RW | RW | CONFIG_GPU0_BAR_GRANULE: Hash boundary for brick 0: 0 = hash on 512B boundary (hashbits(0:7)=addr(47:54)) 1 = hash on 1024B boundary (hashbits(0:7)=addr(46:53)) | |
| 45 | RW | RW | CONFIG_GPU0_BAR_POISON: on failed access return all ones 0/1 = with good ECC / with SUE ECC. | |
| 46 | RW | RW | CONFIG_GPU0_BAR_M2MODE: 0 = OpenCAPI AFU M1 mode / 1 = OpenCAPI AFU M2 mode Has no effect when in NVLink mode | |
| 47 | RW | RW | CONFIG_GPU0_BAR_PA_IGNORE_MODE: Set to '1' for RA-to-PA conversion to ignore the mode field | |
| 48 | RW | RW | CONFIG_GPU0_BAR_SECURE_A12: P10 Only: this specifies the addr(12) value to match for this BAR. Can only be set to one in P10 and only when SMF_CONFIG=0b11. | |
| 49 | RW | RW | CONFIG_GPU0_BAR_CHIP_EQ_GROUP: Axone Only: this specifies that the system is in chip=group mode. This bit should only be set when sl_mode=1 and 4t_limit=1. 0/1 = TIM(0:31) applies to addr(15:19) / TIM(0:31) applies to (addr(15:16) & addr(19:21)). | |
| 50 | RW | RW | CONFIG_GPU0_BAR_EXTENDED_MODE: 0/1 = bar_mode selects 1,2,3,4,6 way hashing / bar_mode selects 8-way hashing | |
| 51 | RW | RW | CONFIG_GPU0_BAR_RESERVED: reserved | |
| 52:63 | RO | RO | constant=0b000000000000 | |
| GPU1-Memory BAR | ||||
|---|---|---|---|---|
| Addr: |
00000000110108F3 (SCOM) 0000000013420198 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.SNP.MISC.GPU1_BAR | |||
| Constant(s): | ||||
| Comments: | BAR register defining GPU Mem addresses serviced by brick 1 connected to this stack. Note: This register should be set to the same value for each brick/stack. MDials have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:51 | PAU3.CS.SM2.SNP.MISC.GPU1_BAR_Q_0_INST.LATC.L2(0:51) [0000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_GPU1_BAR_ENABLE: Enable for this BAR (0=disabled, 1=enabled) for brick 1 | |
| 1:35 | RW | RW | CONFIG_GPU1_BAR_ADDR_MASK: BAR Address/Mask bits 1:35 for brick 1 In Small-BAR mode (see bit 36): 1:7 = Base_Addr(13:19) = 16T slice 8:21 = Base_Addr(20:33) = 1G address in slice 22:35 = Base_Mask(20:33) = 1G...16T BAR size. (Note: Mask limited to 1G...4T in Axone and P10 w/ GPU systems) In Large-BAR mode (see bit 36): 1 = '1' to match MemSel = addr(13:14) = 0b00 2 = '1' to match MemSel = addr(13:14) = 0b01 3 = '1' to match MemSel = addr(13:14) = 0b10 4:35 = Topology_Id_Mask(0:31) when chip_eq_group=0, TIM(0:31) bit 'i' corresponds to addr(15:19) = 'i' when chip_eq_group=1, TIM(0:31) bit 'i' corresponds to (addr(15:16) & addr(19:21)) = 'i' | |
| 36 | RW | RW | CONFIG_GPU1_BAR_SL_MODE: 0/1 = Small-BAR/Large-BAR Mode selector | |
| 37 | RW | RW | CONFIG_GPU1_BAR_4T_LIMIT: 0 = no limit, 16T slices can be used. 1 = limit slices to 4T. -> when chip_eq_group=0, addr(20:21) must match bar_4t_select -> when chip_eq_group=1, addr(17:18) must match bar_4t_select limit=1 is used in P10 systems w/ a GPU or in Axone systems | |
| 38:39 | RW | RW | CONFIG_GPU1_BAR_4T_SELECT: when bar_4t_limit=1 this field selects the value in addr(20:21) to match | |
| 40:43 | RW | RW | CONFIG_GPU1_BAR_MODE: Hash mode of the BAR for brick 1: if bar_extended_mode == 0: 0 = (single) match on all address in addr/size 1 = (dual.0) match if hashbits(7)=0 2 = (dual.1) match if hashbits(7)=1 3 = (triple.0) match if hashbits%3=0 4 = (triple.1) match if hashbits%3=1 5 = (triple.2) match if hashbits%3=2 6 = (quad.0) match if hashbits(6:7)=0 7 = (quad.1) match if hashbits(6:7)=1 8 = (quad.2) match if hashbits(6:7)=2 9 = (quad.3) match if hashbits(6:7)=3 10 = (six.0) match if hashbits%3=0 and hashbits(7)=0 11 = (six.1) match if hashbits%3=0 and hashbits(7)=1 12 = (six.2) match if hashbits%3=1 and hashbits(7)=0 13 = (six.3) match if hashbits%3=1 and hashbits(7)=1 14 = (six.4) match if hashbits%3=2 and hashbits(7)=0 15 = (six.5) match if hashbits%3=2 and hashbits(7)=1 if bar_extended_mode == 1: 0 = (oct.0) match if hashbits(5:7)=0 1 = (oct.1) match if hashbits(5:7)=1 2 = (oct.2) match if hashbits(5:7)=2 3 = (oct.3) match if hashbits(5:7)=3 4 = (oct.4) match if hashbits(5:7)=4 5 = (oct.5) match if hashbits(5:7)=5 6 = (oct.6) match if hashbits(5:7)=6 7 = (oct.7) match if hashbits(5:7)=7 others = reserved | |
| 44 | RW | RW | CONFIG_GPU1_BAR_GRANULE: Hash boundary for brick 1: 0 = hash on 512B boundary (hashbits(0:7)=addr(47:54)) 1 = hash on 1024B boundary (hashbits(0:7)=addr(46:53)) | |
| 45 | RW | RW | CONFIG_GPU1_BAR_POISON: on failed access return all ones 0/1 = with good ECC / with SUE ECC. | |
| 46 | RW | RW | CONFIG_GPU1_BAR_M2MODE: 0 = OpenCAPI AFU M1 mode / 1 = OpenCAPI AFU M2 mode Has no effect when in NVLink mode | |
| 47 | RW | RW | CONFIG_GPU1_BAR_PA_IGNORE_MODE: Set to '1' for RA-to-PA conversion to ignore the mode field | |
| 48 | RW | RW | CONFIG_GPU1_BAR_SECURE_A12: P10 Only: this specifies the addr(12) value to match for this BAR. Can only be set to one in P10 and only when SMF_CONFIG=0b11. | |
| 49 | RW | RW | CONFIG_GPU1_BAR_CHIP_EQ_GROUP: Axone Only: this specifies that the system is in chip=group mode. This bit should only be set when sl_mode=1 and 4t_limit=1. 0/1 = TIM(0:31) applies to addr(15:19) / TIM(0:31) applies to (addr(15:16) & addr(19:21)). | |
| 50 | RW | RW | CONFIG_GPU1_BAR_EXTENDED_MODE: 0/1 = bar_mode selects 1,2,3,4,6 way hashing / bar_mode selects 8-way hashing | |
| 51 | RW | RW | CONFIG_GPU1_BAR_RESERVED: reserved | |
| 52:63 | RO | RO | constant=0b000000000000 | |
| GPU2-Memory BAR | ||||
|---|---|---|---|---|
| Addr: |
00000000110108F4 (SCOM) 00000000134201A0 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.SNP.MISC.GPU2_BAR | |||
| Constant(s): | ||||
| Comments: | BAR register defining GPU Mem addresses serviced by brick 2 connected to this stack. Note: This register should be set to the same value for each brick/stack. MDials have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:51 | PAU3.CS.SM2.SNP.MISC.GPU2_BAR_Q_0_INST.LATC.L2(0:51) [0000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_GPU2_BAR_ENABLE: Enable for this BAR (0=disabled, 1=enabled) for brick 2 | |
| 1:35 | RW | RW | CONFIG_GPU2_BAR_ADDR_MASK: BAR Address/Mask bits 1:35 for brick 2 In Small-BAR mode (see bit 36): 1:7 = Base_Addr(13:19) = 16T slice 8:21 = Base_Addr(20:33) = 1G address in slice 22:35 = Base_Mask(20:33) = 1G...16T BAR size. (Note: Mask limited to 1G...4T in Axone and P10 w/ GPU systems) In Large-BAR mode (see bit 36): 1 = '1' to match MemSel = addr(13:14) = 0b00 2 = '1' to match MemSel = addr(13:14) = 0b01 3 = '1' to match MemSel = addr(13:14) = 0b10 4:35 = Topology_Id_Mask(0:31) when chip_eq_group=0, TIM(0:31) bit 'i' corresponds to addr(15:19) = 'i' when chip_eq_group=1, TIM(0:31) bit 'i' corresponds to (addr(15:16) & addr(19:21)) = 'i' | |
| 36 | RW | RW | CONFIG_GPU2_BAR_SL_MODE: 0/1 = Small-BAR/Large-BAR Mode selector | |
| 37 | RW | RW | CONFIG_GPU2_BAR_4T_LIMIT: 0 = no limit, 16T slices can be used. 1 = limit slices to 4T. -> when chip_eq_group=0, addr(20:21) must match bar_4t_select -> when chip_eq_group=1, addr(17:18) must match bar_4t_select limit=1 is used in P10 systems w/ a GPU or in Axone systems | |
| 38:39 | RW | RW | CONFIG_GPU2_BAR_4T_SELECT: when bar_4t_limit=1 this field selects the value in addr(20:21) to match | |
| 40:43 | RW | RW | CONFIG_GPU2_BAR_MODE: Hash mode of the BAR for brick 2: if bar_extended_mode == 0: 0 = (single) match on all address in addr/size 1 = (dual.0) match if hashbits(7)=0 2 = (dual.1) match if hashbits(7)=1 3 = (triple.0) match if hashbits%3=0 4 = (triple.1) match if hashbits%3=1 5 = (triple.2) match if hashbits%3=2 6 = (quad.0) match if hashbits(6:7)=0 7 = (quad.1) match if hashbits(6:7)=1 8 = (quad.2) match if hashbits(6:7)=2 9 = (quad.3) match if hashbits(6:7)=3 10 = (six.0) match if hashbits%3=0 and hashbits(7)=0 11 = (six.1) match if hashbits%3=0 and hashbits(7)=1 12 = (six.2) match if hashbits%3=1 and hashbits(7)=0 13 = (six.3) match if hashbits%3=1 and hashbits(7)=1 14 = (six.4) match if hashbits%3=2 and hashbits(7)=0 15 = (six.5) match if hashbits%3=2 and hashbits(7)=1 if bar_extended_mode == 1: 0 = (oct.0) match if hashbits(5:7)=0 1 = (oct.1) match if hashbits(5:7)=1 2 = (oct.2) match if hashbits(5:7)=2 3 = (oct.3) match if hashbits(5:7)=3 4 = (oct.4) match if hashbits(5:7)=4 5 = (oct.5) match if hashbits(5:7)=5 6 = (oct.6) match if hashbits(5:7)=6 7 = (oct.7) match if hashbits(5:7)=7 others = reserved | |
| 44 | RW | RW | CONFIG_GPU2_BAR_GRANULE: Hash boundary for brick 2: 0 = hash on 512B boundary (hashbits(0:7)=addr(47:54)) 1 = hash on 1024B boundary (hashbits(0:7)=addr(46:53)) | |
| 45 | RW | RW | CONFIG_GPU2_BAR_POISON: on failed access return all ones 0/1 = with good ECC / with SUE ECC. | |
| 46 | RW | RW | CONFIG_GPU2_BAR_M2MODE: 0 = OpenCAPI AFU M1 mode / 1 = OpenCAPI AFU M2 mode Has no effect when in NVLink mode | |
| 47 | RW | RW | CONFIG_GPU2_BAR_PA_IGNORE_MODE: Set to '1' for RA-to-PA conversion to ignore the mode field | |
| 48 | RW | RW | CONFIG_GPU2_BAR_SECURE_A12: P10 Only: this specifies the addr(12) value to match for this BAR. Can only be set to one in P10 and only when SMF_CONFIG=0b11. | |
| 49 | RW | RW | CONFIG_GPU2_BAR_CHIP_EQ_GROUP: Axone Only: this specifies that the system is in chip=group mode. This bit should only be set when sl_mode=1 and 4t_limit=1. 0/1 = TIM(0:31) applies to addr(15:19) / TIM(0:31) applies to (addr(15:16) & addr(19:21)). | |
| 50 | RW | RW | CONFIG_GPU2_BAR_EXTENDED_MODE: 0/1 = bar_mode selects 1,2,3,4,6 way hashing / bar_mode selects 8-way hashing | |
| 51 | RW | RW | CONFIG_GPU2_BAR_RESERVED: reserved | |
| 52:63 | RO | RO | constant=0b000000000000 | |
| GPU3-Memory BAR | ||||
|---|---|---|---|---|
| Addr: |
00000000110108F5 (SCOM) 00000000134201A8 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.SNP.MISC.GPU3_BAR | |||
| Constant(s): | ||||
| Comments: | BAR register defining GPU Mem addresses serviced by brick 3 connected to this stack. Note: This register should be set to the same value for each brick/stack. MDials have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:51 | PAU3.CS.SM2.SNP.MISC.GPU3_BAR_Q_0_INST.LATC.L2(0:51) [0000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_GPU3_BAR_ENABLE: Enable for this BAR (0=disabled, 1=enabled) for brick 3 | |
| 1:35 | RW | RW | CONFIG_GPU3_BAR_ADDR_MASK: BAR Address/Mask bits 1:35 for brick 3 In Small-BAR mode (see bit 36): 1:7 = Base_Addr(13:19) = 16T slice 8:21 = Base_Addr(20:33) = 1G address in slice 22:35 = Base_Mask(20:33) = 1G...16T BAR size. (Note: Mask limited to 1G...4T in Axone and P10 w/ GPU systems) In Large-BAR mode (see bit 36): 1 = '1' to match MemSel = addr(13:14) = 0b00 2 = '1' to match MemSel = addr(13:14) = 0b01 3 = '1' to match MemSel = addr(13:14) = 0b10 4:35 = Topology_Id_Mask(0:31) when chip_eq_group=0, TIM(0:31) bit 'i' corresponds to addr(15:19) = 'i' when chip_eq_group=1, TIM(0:31) bit 'i' corresponds to (addr(15:16) & addr(19:21)) = 'i' | |
| 36 | RW | RW | CONFIG_GPU3_BAR_SL_MODE: 0/1 = Small-BAR/Large-BAR Mode selector | |
| 37 | RW | RW | CONFIG_GPU3_BAR_4T_LIMIT: 0 = no limit, 16T slices can be used. 1 = limit slices to 4T. -> when chip_eq_group=0, addr(20:21) must match bar_4t_select -> when chip_eq_group=1, addr(17:18) must match bar_4t_select limit=1 is used in P10 systems w/ a GPU or in Axone systems | |
| 38:39 | RW | RW | CONFIG_GPU3_BAR_4T_SELECT: when bar_4t_limit=1 this field selects the value in addr(20:21) to match | |
| 40:43 | RW | RW | CONFIG_GPU3_BAR_MODE: Hash mode of the BAR for brick 3: if bar_extended_mode == 0: 0 = (single) match on all address in addr/size 1 = (dual.0) match if hashbits(7)=0 2 = (dual.1) match if hashbits(7)=1 3 = (triple.0) match if hashbits%3=0 4 = (triple.1) match if hashbits%3=1 5 = (triple.2) match if hashbits%3=2 6 = (quad.0) match if hashbits(6:7)=0 7 = (quad.1) match if hashbits(6:7)=1 8 = (quad.2) match if hashbits(6:7)=2 9 = (quad.3) match if hashbits(6:7)=3 10 = (six.0) match if hashbits%3=0 and hashbits(7)=0 11 = (six.1) match if hashbits%3=0 and hashbits(7)=1 12 = (six.2) match if hashbits%3=1 and hashbits(7)=0 13 = (six.3) match if hashbits%3=1 and hashbits(7)=1 14 = (six.4) match if hashbits%3=2 and hashbits(7)=0 15 = (six.5) match if hashbits%3=2 and hashbits(7)=1 if bar_extended_mode == 1: 0 = (oct.0) match if hashbits(5:7)=0 1 = (oct.1) match if hashbits(5:7)=1 2 = (oct.2) match if hashbits(5:7)=2 3 = (oct.3) match if hashbits(5:7)=3 4 = (oct.4) match if hashbits(5:7)=4 5 = (oct.5) match if hashbits(5:7)=5 6 = (oct.6) match if hashbits(5:7)=6 7 = (oct.7) match if hashbits(5:7)=7 others = reserved | |
| 44 | RW | RW | CONFIG_GPU3_BAR_GRANULE: Hash boundary for brick 3: 0 = hash on 512B boundary (hashbits(0:7)=addr(47:54)) 1 = hash on 1024B boundary (hashbits(0:7)=addr(46:53)) | |
| 45 | RW | RW | CONFIG_GPU3_BAR_POISON: on failed access return all ones 0/1 = with good ECC / with SUE ECC. | |
| 46 | RW | RW | CONFIG_GPU3_BAR_M2MODE: 0 = OpenCAPI AFU M1 mode / 1 = OpenCAPI AFU M2 mode Has no effect when in NVLink mode | |
| 47 | RW | RW | CONFIG_GPU3_BAR_PA_IGNORE_MODE: Set to '1' for RA-to-PA conversion to ignore the mode field | |
| 48 | RW | RW | CONFIG_GPU3_BAR_SECURE_A12: P10 Only: this specifies the addr(12) value to match for this BAR. Can only be set to one in P10 and only when SMF_CONFIG=0b11. | |
| 49 | RW | RW | CONFIG_GPU3_BAR_CHIP_EQ_GROUP: Axone Only: this specifies that the system is in chip=group mode. This bit should only be set when sl_mode=1 and 4t_limit=1. 0/1 = TIM(0:31) applies to addr(15:19) / TIM(0:31) applies to (addr(15:16) & addr(19:21)). | |
| 50 | RW | RW | CONFIG_GPU3_BAR_EXTENDED_MODE: 0/1 = bar_mode selects 1,2,3,4,6 way hashing / bar_mode selects 8-way hashing | |
| 51 | RW | RW | CONFIG_GPU3_BAR_RESERVED: reserved | |
| 52:63 | RO | RO | constant=0b000000000000 | |
| GPU4-Memory BAR | ||||
|---|---|---|---|---|
| Addr: |
00000000110108F6 (SCOM) 00000000134201B0 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.SNP.MISC.GPU4_BAR | |||
| Constant(s): | ||||
| Comments: | BAR register defining GPU Mem addresses serviced by brick 4 connected to this stack. Note: This register should be set to the same value for each brick/stack. MDials have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:51 | PAU3.CS.SM2.SNP.MISC.GPU4_BAR_Q_0_INST.LATC.L2(0:51) [0000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_GPU4_BAR_ENABLE: Enable for this BAR (0=disabled, 1=enabled) for brick 4 | |
| 1:35 | RW | RW | CONFIG_GPU4_BAR_ADDR_MASK: BAR Address/Mask bits 1:35 for brick 4 In Small-BAR mode (see bit 36): 1:7 = Base_Addr(13:19) = 16T slice 8:21 = Base_Addr(20:33) = 1G address in slice 22:35 = Base_Mask(20:33) = 1G...16T BAR size. (Note: Mask limited to 1G...4T in Axone and P10 w/ GPU systems) In Large-BAR mode (see bit 36): 1 = '1' to match MemSel = addr(13:14) = 0b00 2 = '1' to match MemSel = addr(13:14) = 0b01 3 = '1' to match MemSel = addr(13:14) = 0b10 4:35 = Topology_Id_Mask(0:31) when chip_eq_group=0, TIM(0:31) bit 'i' corresponds to addr(15:19) = 'i' when chip_eq_group=1, TIM(0:31) bit 'i' corresponds to (addr(15:16) & addr(19:21)) = 'i' | |
| 36 | RW | RW | CONFIG_GPU4_BAR_SL_MODE: 0/1 = Small-BAR/Large-BAR Mode selector | |
| 37 | RW | RW | CONFIG_GPU4_BAR_4T_LIMIT: 0 = no limit, 16T slices can be used. 1 = limit slices to 4T. -> when chip_eq_group=0, addr(20:21) must match bar_4t_select -> when chip_eq_group=1, addr(17:18) must match bar_4t_select limit=1 is used in P10 systems w/ a GPU or in Axone systems | |
| 38:39 | RW | RW | CONFIG_GPU4_BAR_4T_SELECT: when bar_4t_limit=1 this field selects the value in addr(20:21) to match | |
| 40:43 | RW | RW | CONFIG_GPU4_BAR_MODE: Hash mode of the BAR for brick 4: if bar_extended_mode == 0: 0 = (single) match on all address in addr/size 1 = (dual.0) match if hashbits(7)=0 2 = (dual.1) match if hashbits(7)=1 3 = (triple.0) match if hashbits%3=0 4 = (triple.1) match if hashbits%3=1 5 = (triple.2) match if hashbits%3=2 6 = (quad.0) match if hashbits(6:7)=0 7 = (quad.1) match if hashbits(6:7)=1 8 = (quad.2) match if hashbits(6:7)=2 9 = (quad.3) match if hashbits(6:7)=3 10 = (six.0) match if hashbits%3=0 and hashbits(7)=0 11 = (six.1) match if hashbits%3=0 and hashbits(7)=1 12 = (six.2) match if hashbits%3=1 and hashbits(7)=0 13 = (six.3) match if hashbits%3=1 and hashbits(7)=1 14 = (six.4) match if hashbits%3=2 and hashbits(7)=0 15 = (six.5) match if hashbits%3=2 and hashbits(7)=1 if bar_extended_mode == 1: 0 = (oct.0) match if hashbits(5:7)=0 1 = (oct.1) match if hashbits(5:7)=1 2 = (oct.2) match if hashbits(5:7)=2 3 = (oct.3) match if hashbits(5:7)=3 4 = (oct.4) match if hashbits(5:7)=4 5 = (oct.5) match if hashbits(5:7)=5 6 = (oct.6) match if hashbits(5:7)=6 7 = (oct.7) match if hashbits(5:7)=7 others = reserved | |
| 44 | RW | RW | CONFIG_GPU4_BAR_GRANULE: Hash boundary for brick 4: 0 = hash on 512B boundary (hashbits(0:7)=addr(47:54)) 1 = hash on 1024B boundary (hashbits(0:7)=addr(46:53)) | |
| 45 | RW | RW | CONFIG_GPU4_BAR_POISON: on failed access return all ones 0/1 = with good ECC / with SUE ECC. | |
| 46 | RW | RW | CONFIG_GPU4_BAR_M2MODE: 0 = OpenCAPI AFU M1 mode / 1 = OpenCAPI AFU M2 mode Has no effect when in NVLink mode | |
| 47 | RW | RW | CONFIG_GPU4_BAR_PA_IGNORE_MODE: Set to '1' for RA-to-PA conversion to ignore the mode field | |
| 48 | RW | RW | CONFIG_GPU4_BAR_SECURE_A12: P10 Only: this specifies the addr(12) value to match for this BAR. Can only be set to one in P10 and only when SMF_CONFIG=0b11. | |
| 49 | RW | RW | CONFIG_GPU4_BAR_CHIP_EQ_GROUP: Axone Only: this specifies that the system is in chip=group mode. This bit should only be set when sl_mode=1 and 4t_limit=1. 0/1 = TIM(0:31) applies to addr(15:19) / TIM(0:31) applies to (addr(15:16) & addr(19:21)). | |
| 50 | RW | RW | CONFIG_GPU4_BAR_EXTENDED_MODE: 0/1 = bar_mode selects 1,2,3,4,6 way hashing / bar_mode selects 8-way hashing | |
| 51 | RW | RW | CONFIG_GPU4_BAR_RESERVED: reserved | |
| 52:63 | RO | RO | constant=0b000000000000 | |
| NTL0/NDL0 MMIO BAR | ||||
|---|---|---|---|---|
| Addr: |
00000000110108F7 (SCOM) 00000000134201B8 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.SNP.MISC.NDT0_BAR | |||
| Constant(s): | ||||
| Comments: | BAR register defining NDL/NTL MMIO (NVLink) or AFU MMIO (OpenCAPI) range for brick 0 connected to this stack Note: This register should be set to the same value for each brick/stack. MDials have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:43 | PAU3.CS.SM2.SNP.MISC.NDT0_BAR_Q_0_INST.LATC.L2(0:43) [00000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_NDT0_BAR_ENABLE: 0/1 = disable/enable BAR for brick 0 | |
| 1 | RW | RW | CONFIG_NDT0_BAR_SECURE_A12: P10 Only: this specifies the addr(12) value to match for this BAR. Can only be set to one in P10 and only when SMF_CONFIG=0b11. | |
| 2 | RW | RW | NDT0_RESERVED1: reserved | |
| 3:35 | RW | RW | CONFIG_NDT0_BAR_ADDR: 64K aligned address of BAR for brick 0's 64K range | |
| 36 | RW | RW | CONFIG_NDT0_BAR_POISON: on failed access return all ones 0/1 = with good ECC / with SUE ECC. | |
| 37:38 | RW | RW | NDT0_RESERVED2: reserved | |
| 39:43 | RW | RW | CONFIG_NDT0_BAR_SIZE: Size of BAR region. 0 = 64K 1 = 128K (NVLink must select this size) 2 = 256K ... 26 = 4T others = reserved | |
| 44:63 | RO | RO | constant=0b00000000000000000000 | |
| NTL1/NDL1 MMIO BAR | ||||
|---|---|---|---|---|
| Addr: |
00000000110108F8 (SCOM) 00000000134201C0 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.SNP.MISC.NDT1_BAR | |||
| Constant(s): | ||||
| Comments: | BAR register defining NDL/NTL MMIO (NVLink) or AFU MMIO (OpenCAPI) range for brick 1 connected to this stack Note: This register should be set to the same value for each brick/stack. MDials have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:43 | PAU3.CS.SM2.SNP.MISC.NDT1_BAR_Q_0_INST.LATC.L2(0:43) [00000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_NDT1_BAR_ENABLE: 0/1 = disable/enable BAR for brick 1 | |
| 1 | RW | RW | CONFIG_NDT1_BAR_SECURE_A12: P10 Only: this specifies the addr(12) value to match for this BAR. Can only be set to one in P10 and only when SMF_CONFIG=0b11. | |
| 2 | RW | RW | NDT1_RESERVED1: reserved | |
| 3:35 | RW | RW | CONFIG_NDT1_BAR_ADDR: 64K aligned address of BAR for brick 1's 64K range | |
| 36 | RW | RW | CONFIG_NDT1_BAR_POISON: on failed access return all ones 0/1 = with good ECC / with SUE ECC. | |
| 37:38 | RW | RW | NDT1_RESERVED2: reserved | |
| 39:43 | RW | RW | CONFIG_NDT1_BAR_SIZE: Size of BAR region. 0 = 64K 1 = 128K (NVLink must select this size) 2 = 256K ... 26 = 4T others = reserved | |
| 44:63 | RO | RO | constant=0b00000000000000000000 | |
| NTL2/NDL2 MMIO BAR | ||||
|---|---|---|---|---|
| Addr: |
00000000110108F9 (SCOM) 00000000134201C8 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.SNP.MISC.NDT2_BAR | |||
| Constant(s): | ||||
| Comments: | BAR register defining NDL/NTL MMIO (NVLink) or AFU MMIO (OpenCAPI) range for brick 2 connected to this stack Note: This register should be set to the same value for each brick/stack. MDials have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:43 | PAU3.CS.SM2.SNP.MISC.NDT2_BAR_Q_0_INST.LATC.L2(0:43) [00000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_NDT2_BAR_ENABLE: 0/1 = disable/enable BAR for brick 2 | |
| 1 | RW | RW | CONFIG_NDT2_BAR_SECURE_A12: P10 Only: this specifies the addr(12) value to match for this BAR. Can only be set to one in P10 and only when SMF_CONFIG=0b11. | |
| 2 | RW | RW | NDT2_RESERVED1: reserved | |
| 3:35 | RW | RW | CONFIG_NDT2_BAR_ADDR: 64K aligned address of BAR for brick 2's 64K range | |
| 36 | RW | RW | CONFIG_NDT2_BAR_POISON: on failed access return all ones 0/1 = with good ECC / with SUE ECC. | |
| 37:38 | RW | RW | NDT2_RESERVED2: reserved | |
| 39:43 | RW | RW | CONFIG_NDT2_BAR_SIZE: Size of BAR region. 0 = 64K 1 = 128K (NVLink must select this size) 2 = 256K ... 26 = 4T others = reserved | |
| 44:63 | RO | RO | constant=0b00000000000000000000 | |
| NTL3/NDL3 MMIO BAR | ||||
|---|---|---|---|---|
| Addr: |
00000000110108FA (SCOM) 00000000134201D0 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.SNP.MISC.NDT3_BAR | |||
| Constant(s): | ||||
| Comments: | BAR register defining NDL/NTL MMIO (NVLink) or AFU MMIO (OpenCAPI) range for brick 3 connected to this stack Note: This register should be set to the same value for each brick/stack. MDials have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:43 | PAU3.CS.SM2.SNP.MISC.NDT3_BAR_Q_0_INST.LATC.L2(0:43) [00000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_NDT3_BAR_ENABLE: 0/1 = disable/enable BAR for brick 3 | |
| 1 | RW | RW | CONFIG_NDT3_BAR_SECURE_A12: P10 Only: this specifies the addr(12) value to match for this BAR. Can only be set to one in P10 and only when SMF_CONFIG=0b11. | |
| 2 | RW | RW | NDT3_RESERVED1: reserved | |
| 3:35 | RW | RW | CONFIG_NDT3_BAR_ADDR: 64K aligned address of BAR for brick 3's 64K range | |
| 36 | RW | RW | CONFIG_NDT3_BAR_POISON: on failed access return all ones 0/1 = with good ECC / with SUE ECC. | |
| 37:38 | RW | RW | NDT3_RESERVED2: reserved | |
| 39:43 | RW | RW | CONFIG_NDT3_BAR_SIZE: Size of BAR region. 0 = 64K 1 = 128K (NVLink must select this size) 2 = 256K ... 26 = 4T others = reserved | |
| 44:63 | RO | RO | constant=0b00000000000000000000 | |
| NTL4/NDL4 MMIO BAR | ||||
|---|---|---|---|---|
| Addr: |
00000000110108FB (SCOM) 00000000134201D8 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.SNP.MISC.NDT4_BAR | |||
| Constant(s): | ||||
| Comments: | BAR register defining NDL/NTL MMIO (NVLink) or AFU MMIO (OpenCAPI) range for brick 4 connected to this stack Note: This register should be set to the same value for each brick/stack. MDials have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:43 | PAU3.CS.SM2.SNP.MISC.NDT4_BAR_Q_0_INST.LATC.L2(0:43) [00000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_NDT4_BAR_ENABLE: 0/1 = disable/enable BAR for brick 4 | |
| 1 | RW | RW | CONFIG_NDT4_BAR_SECURE_A12: P10 Only: this specifies the addr(12) value to match for this BAR. Can only be set to one in P10 and only when SMF_CONFIG=0b11. | |
| 2 | RW | RW | NDT4_RESERVED1: reserved | |
| 3:35 | RW | RW | CONFIG_NDT4_BAR_ADDR: 64K aligned address of BAR for brick 4's 64K range | |
| 36 | RW | RW | CONFIG_NDT4_BAR_POISON: on failed access return all ones 0/1 = with good ECC / with SUE ECC. | |
| 37:38 | RW | RW | NDT4_RESERVED2: reserved | |
| 39:43 | RW | RW | CONFIG_NDT4_BAR_SIZE: Size of BAR region. 0 = 64K 1 = 128K (NVLink must select this size) 2 = 256K ... 26 = 4T others = reserved | |
| 44:63 | RO | RO | constant=0b00000000000000000000 | |
| PAU MMIO BAR | ||||
|---|---|---|---|---|
| Addr: |
00000000110108FC (SCOM) 00000000134201E0 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.SNP.MISC.PAUMMIO_BAR | |||
| Constant(s): | ||||
| Comments: | BAR register definingPAU MMIO range Note: This register should be set to the same value for each brick/stack. MDials have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:31 | PAU3.CS.SM2.SNP.MISC.PAUMMIO_BAR_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_PAUMMIO_BAR_ENABLE: 0/1 = disable/enable PAUMMIO_BAR | |
| 1 | RW | RW | CONFIG_PAUMMIO_BAR_SECURE_A12: P10 Only: this specifies the addr(12) value to match for this BAR. Can only be set to one in P10 and only when SMF_CONFIG=0b11. | |
| 2 | RW | RW | PAUMMIO_RESERVED1: reserved | |
| 3:27 | RW | RW | CONFIG_PAUMMIO_BAR_ADDR: 16M aligned address of this PAUMMIO_BAR's 16M range. Bits 15:39 of the RA | |
| 28:30 | RW | RW | PAUMMIO_RESERVED2: reserved | |
| 31 | RW | RW | CONFIG_PAUMMIO_BAR_POISON: On failed access return all ones 0/1 = with good ECC / with SUE ECC. | |
| 32:63 | RO | RO | constant=0b00000000000000000000000000000000 | |
| Generation-ID Registers MMIO BAR | ||||
|---|---|---|---|---|
| Addr: |
00000000110108FD (SCOM) 00000000134201E8 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.SNP.MISC.GENID_BAR | |||
| Constant(s): | ||||
| Comments: | NVLink mode: BAR register defining Generation-ID registers for this stack/ramp OCAPI mode: BAR register defining Config space + Generation-ID registers registers for this stack/ramp Note: This register should be set to the same value for each brick/stack. MDials have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:35 | PAU3.CS.SM2.SNP.MISC.GENID_BAR_Q_0_INST.LATC.L2(0:35) [000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_GENID_BAR_ENABLE: 0/1 = disable/enable this BAR | |
| 1 | RW | RW | CONFIG_GENID_BAR_SECURE_A12: P10 Only: this specifies the addr(12) value to match for this BAR. Can only be set to one in P10 and only when SMF_CONFIG=0b11. | |
| 2 | RW | RW | GENID_RESERVED1: reserved | |
| 3:32 | RW | RW | CONFIG_GENID_BAR_ADDR: 512K aligned address +0K = Brick 0 Gen-Id Registers +64K = Brick 1 Gen-Id Registers +128K = Brick 2 Gen-Id Registers +192K = Brick 3 Gen-Id Registers +256K = Brick 4 Gen-Id Registers +320K = Bricks 0-4 Config Addr/Data registers for OCAPI links +384K = reserved +448K = reserved | |
| 33:34 | RW | RW | GENID_RESERVED2: reserved | |
| 35 | RW | RW | CONFIG_GENID_BAR_POISON: on failed access return all ones 0/1 = with good ECC / with SUE ECC. | |
| 36:63 | RO | RO | constant=0b0000000000000000000000000000 | |
| Relexed-Ordering Source 0 Config | ||||
|---|---|---|---|---|
| Addr: |
00000000110108FE (SCOM) 00000000134201F0 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.SNP.MISC.CONFIG_RELAXED_SRC0 | |||
| Constant(s): | ||||
| Comments: | Configure relaxed-ordering source Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM2.SNP.MISC.CONFIG_RELAXED_SRC0_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:13 | RW | RW | CONFIG_RELAXED_SOURCE0_TAG: P10: Match against ('00' & ttag(0:11)). | |
| 14:27 | RW | RW | CONFIG_RELAXED_SOURCE0_TAGMASK: Mask on tag(0:13). 0=must-match, 1=don't-care. | |
| 28 | RW | RW | CONFIG_RELAXED_SOURCE0_MASK_PAU: P10: match ttag(7:9)=000,001,111 | |
| 29 | RW | RW | CONFIG_RELAXED_SOURCE0_MASK_PCIE: P10: reserved | |
| 30 | RW | RW | CONFIG_RELAXED_SOURCE0_MASK_L2L3: P10: reserved | |
| 31 | RW | RW | CONFIG_RELAXED_SOURCE0_RESERVED1: reserved | |
| 32:39 | RW | RW | CONFIG_RELAXED_SOURCE0_RDSTART: P10: ttag(12:19) start-of-read-tags value (first tag) | |
| 40:47 | RW | RW | CONFIG_RELAXED_SOURCE0_RDEND: P10: ttag(12:19) end-of-read-tags value (last tag) | |
| 48:55 | RW | RW | CONFIG_RELAXED_SOURCE0_WRSTART: P10: ttag(12:19) start-of-write-tags value (first tag) | |
| 56:63 | RW | RW | CONFIG_RELAXED_SOURCE0_WREND: P10: ttag(12:19) end-of-write-tags value (last tag) | |
| Relexed-Ordering Source 1 Config | ||||
|---|---|---|---|---|
| Addr: |
00000000110108FF (SCOM) 00000000134201F8 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.SNP.MISC.CONFIG_RELAXED_SRC1 | |||
| Constant(s): | ||||
| Comments: | Configure relaxed-ordering source Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM2.SNP.MISC.CONFIG_RELAXED_SRC1_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:13 | RW | RW | CONFIG_RELAXED_SOURCE1_TAG: P10: Match against ('00' & ttag(0:11)). | |
| 14:27 | RW | RW | CONFIG_RELAXED_SOURCE1_TAGMASK: Mask on tag(0:13). 0=must-match, 1=don't-care. | |
| 28 | RW | RW | CONFIG_RELAXED_SOURCE1_MASK_PAU: P10: match ttag(7:9)=000,001,111 | |
| 29 | RW | RW | CONFIG_RELAXED_SOURCE1_MASK_PCIE: P10: reserved | |
| 30 | RW | RW | CONFIG_RELAXED_SOURCE1_MASK_L2L3: P10: reserved | |
| 31 | RW | RW | CONFIG_RELAXED_SOURCE1_RESERVED1: reserved | |
| 32:39 | RW | RW | CONFIG_RELAXED_SOURCE1_RDSTART: P10: ttag(12:19) start-of-read-tags value (first tag) | |
| 40:47 | RW | RW | CONFIG_RELAXED_SOURCE1_RDEND: P10: ttag(12:19) end-of-read-tags value (last tag) | |
| 48:55 | RW | RW | CONFIG_RELAXED_SOURCE1_WRSTART: P10: ttag(12:19) start-of-write-tags value (first tag) | |
| 56:63 | RW | RW | CONFIG_RELAXED_SOURCE1_WREND: P10: ttag(12:19) end-of-write-tags value (last tag) | |
| Relexed-Ordering Source 2 Config | ||||
|---|---|---|---|---|
| Addr: |
0000000011010900 (SCOM) 0000000013420200 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.SNP.MISC.CONFIG_RELAXED_SRC2 | |||
| Constant(s): | ||||
| Comments: | Configure relaxed-ordering source Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM2.SNP.MISC.CONFIG_RELAXED_SRC2_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:13 | RW | RW | CONFIG_RELAXED_SOURCE2_TAG: P10: Match against ('00' & ttag(0:11)). | |
| 14:27 | RW | RW | CONFIG_RELAXED_SOURCE2_TAGMASK: Mask on tag(0:13). 0=must-match, 1=don't-care. | |
| 28 | RW | RW | CONFIG_RELAXED_SOURCE2_MASK_PAU: P10: match ttag(7:9)=000,001,111 | |
| 29 | RW | RW | CONFIG_RELAXED_SOURCE2_MASK_PCIE: P10: reserved | |
| 30 | RW | RW | CONFIG_RELAXED_SOURCE2_MASK_L2L3: P10: reserved | |
| 31 | RW | RW | CONFIG_RELAXED_SOURCE2_RESERVED1: reserved | |
| 32:39 | RW | RW | CONFIG_RELAXED_SOURCE2_RDSTART: P10: ttag(12:19) start-of-read-tags value (first tag) | |
| 40:47 | RW | RW | CONFIG_RELAXED_SOURCE2_RDEND: P10: ttag(12:19) end-of-read-tags value (last tag) | |
| 48:55 | RW | RW | CONFIG_RELAXED_SOURCE2_WRSTART: P10: ttag(12:19) start-of-write-tags value (first tag) | |
| 56:63 | RW | RW | CONFIG_RELAXED_SOURCE2_WREND: P10: ttag(12:19) end-of-write-tags value (last tag) | |
| Relexed-Ordering Source 3 Config | ||||
|---|---|---|---|---|
| Addr: |
0000000011010901 (SCOM) 0000000013420208 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.SNP.MISC.CONFIG_RELAXED_SRC3 | |||
| Constant(s): | ||||
| Comments: | Configure relaxed-ordering source Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM2.SNP.MISC.CONFIG_RELAXED_SRC3_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:13 | RW | RW | CONFIG_RELAXED_SOURCE3_TAG: P10: Match against ('00' & ttag(0:11)). | |
| 14:27 | RW | RW | CONFIG_RELAXED_SOURCE3_TAGMASK: Mask on tag(0:13). 0=must-match, 1=don't-care. | |
| 28 | RW | RW | CONFIG_RELAXED_SOURCE3_MASK_PAU: P10: match ttag(7:9)=000,001,111 | |
| 29 | RW | RW | CONFIG_RELAXED_SOURCE3_MASK_PCIE: P10: reserved | |
| 30 | RW | RW | CONFIG_RELAXED_SOURCE3_MASK_L2L3: P10: reserved | |
| 31 | RW | RW | CONFIG_RELAXED_SOURCE3_RESERVED1: reserved | |
| 32:39 | RW | RW | CONFIG_RELAXED_SOURCE3_RDSTART: P10: ttag(12:19) start-of-read-tags value (first tag) | |
| 40:47 | RW | RW | CONFIG_RELAXED_SOURCE3_RDEND: P10: ttag(12:19) end-of-read-tags value (last tag) | |
| 48:55 | RW | RW | CONFIG_RELAXED_SOURCE3_WRSTART: P10: ttag(12:19) start-of-write-tags value (first tag) | |
| 56:63 | RW | RW | CONFIG_RELAXED_SOURCE3_WREND: P10: ttag(12:19) end-of-write-tags value (last tag) | |
| Relexed-Ordering Source 4 Config | ||||
|---|---|---|---|---|
| Addr: |
0000000011010902 (SCOM) 0000000013420210 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.SNP.MISC.CONFIG_RELAXED_SRC4 | |||
| Constant(s): | ||||
| Comments: | Configure relaxed-ordering source Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM2.SNP.MISC.CONFIG_RELAXED_SRC4_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:13 | RW | RW | CONFIG_RELAXED_SOURCE4_TAG: P10: Match against ('00' & ttag(0:11)). | |
| 14:27 | RW | RW | CONFIG_RELAXED_SOURCE4_TAGMASK: Mask on tag(0:13). 0=must-match, 1=don't-care. | |
| 28 | RW | RW | CONFIG_RELAXED_SOURCE4_MASK_PAU: P10: match ttag(7:9)=000,001,111 | |
| 29 | RW | RW | CONFIG_RELAXED_SOURCE4_MASK_PCIE: P10: reserved | |
| 30 | RW | RW | CONFIG_RELAXED_SOURCE4_MASK_L2L3: P10: reserved | |
| 31 | RW | RW | CONFIG_RELAXED_SOURCE4_RESERVED1: reserved | |
| 32:39 | RW | RW | CONFIG_RELAXED_SOURCE4_RDSTART: P10: ttag(12:19) start-of-read-tags value (first tag) | |
| 40:47 | RW | RW | CONFIG_RELAXED_SOURCE4_RDEND: P10: ttag(12:19) end-of-read-tags value (last tag) | |
| 48:55 | RW | RW | CONFIG_RELAXED_SOURCE4_WRSTART: P10: ttag(12:19) start-of-write-tags value (first tag) | |
| 56:63 | RW | RW | CONFIG_RELAXED_SOURCE4_WREND: P10: ttag(12:19) end-of-write-tags value (last tag) | |
| Relexed-Ordering Source 5 Config | ||||
|---|---|---|---|---|
| Addr: |
0000000011010903 (SCOM) 0000000013420218 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.SNP.MISC.CONFIG_RELAXED_SRC5 | |||
| Constant(s): | ||||
| Comments: | Configure relaxed-ordering source Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM2.SNP.MISC.CONFIG_RELAXED_SRC5_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:13 | RW | RW | CONFIG_RELAXED_SOURCE5_TAG: P10: Match against ('00' & ttag(0:11)). | |
| 14:27 | RW | RW | CONFIG_RELAXED_SOURCE5_TAGMASK: Mask on tag(0:13). 0=must-match, 1=don't-care. | |
| 28 | RW | RW | CONFIG_RELAXED_SOURCE5_MASK_PAU: P10: match ttag(7:9)=000,001,111 | |
| 29 | RW | RW | CONFIG_RELAXED_SOURCE5_MASK_PCIE: P10: reserved | |
| 30 | RW | RW | CONFIG_RELAXED_SOURCE5_MASK_L2L3: P10: reserved | |
| 31 | RW | RW | CONFIG_RELAXED_SOURCE5_RESERVED1: reserved | |
| 32:39 | RW | RW | CONFIG_RELAXED_SOURCE5_RDSTART: P10: ttag(12:19) start-of-read-tags value (first tag) | |
| 40:47 | RW | RW | CONFIG_RELAXED_SOURCE5_RDEND: P10: ttag(12:19) end-of-read-tags value (last tag) | |
| 48:55 | RW | RW | CONFIG_RELAXED_SOURCE5_WRSTART: P10: ttag(12:19) start-of-write-tags value (first tag) | |
| 56:63 | RW | RW | CONFIG_RELAXED_SOURCE5_WREND: P10: ttag(12:19) end-of-write-tags value (last tag) | |
| Relexed-Ordering Source 6 Config | ||||
|---|---|---|---|---|
| Addr: |
0000000011010904 (SCOM) 0000000013420220 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.SNP.MISC.CONFIG_RELAXED_SRC6 | |||
| Constant(s): | ||||
| Comments: | Configure relaxed-ordering source Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM2.SNP.MISC.CONFIG_RELAXED_SRC6_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:13 | RW | RW | CONFIG_RELAXED_SOURCE6_TAG: P10: Match against ('00' & ttag(0:11)). | |
| 14:27 | RW | RW | CONFIG_RELAXED_SOURCE6_TAGMASK: Mask on tag(0:13). 0=must-match, 1=don't-care. | |
| 28 | RW | RW | CONFIG_RELAXED_SOURCE6_MASK_PAU: P10: match ttag(7:9)=000,001,111 | |
| 29 | RW | RW | CONFIG_RELAXED_SOURCE6_MASK_PCIE: P10: reserved | |
| 30 | RW | RW | CONFIG_RELAXED_SOURCE6_MASK_L2L3: P10: reserved | |
| 31 | RW | RW | CONFIG_RELAXED_SOURCE6_RESERVED1: reserved | |
| 32:39 | RW | RW | CONFIG_RELAXED_SOURCE6_RDSTART: P10: ttag(12:19) start-of-read-tags value (first tag) | |
| 40:47 | RW | RW | CONFIG_RELAXED_SOURCE6_RDEND: P10: ttag(12:19) end-of-read-tags value (last tag) | |
| 48:55 | RW | RW | CONFIG_RELAXED_SOURCE6_WRSTART: P10: ttag(12:19) start-of-write-tags value (first tag) | |
| 56:63 | RW | RW | CONFIG_RELAXED_SOURCE6_WREND: P10: ttag(12:19) end-of-write-tags value (last tag) | |
| Relexed-Ordering Source 7 Config | ||||
|---|---|---|---|---|
| Addr: |
0000000011010905 (SCOM) 0000000013420228 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.SNP.MISC.CONFIG_RELAXED_SRC7 | |||
| Constant(s): | ||||
| Comments: | Configure relaxed-ordering source Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM2.SNP.MISC.CONFIG_RELAXED_SRC7_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:13 | RW | RW | CONFIG_RELAXED_SOURCE7_TAG: P10: Match against ('00' & ttag(0:11)). | |
| 14:27 | RW | RW | CONFIG_RELAXED_SOURCE7_TAGMASK: Mask on tag(0:13). 0=must-match, 1=don't-care. | |
| 28 | RW | RW | CONFIG_RELAXED_SOURCE7_MASK_PAU: P10: match ttag(7:9)=000,001,111 | |
| 29 | RW | RW | CONFIG_RELAXED_SOURCE7_MASK_PCIE: P10: reserved | |
| 30 | RW | RW | CONFIG_RELAXED_SOURCE7_MASK_L2L3: P10: reserved | |
| 31 | RW | RW | CONFIG_RELAXED_SOURCE7_RESERVED1: reserved | |
| 32:39 | RW | RW | CONFIG_RELAXED_SOURCE7_RDSTART: P10: ttag(12:19) start-of-read-tags value (first tag) | |
| 40:47 | RW | RW | CONFIG_RELAXED_SOURCE7_RDEND: P10: ttag(12:19) end-of-read-tags value (last tag) | |
| 48:55 | RW | RW | CONFIG_RELAXED_SOURCE7_WRSTART: P10: ttag(12:19) start-of-write-tags value (first tag) | |
| 56:63 | RW | RW | CONFIG_RELAXED_SOURCE7_WREND: P10: ttag(12:19) end-of-write-tags value (last tag) | |
| Relaxed-Ordering Config2 brick 0 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010906 (SCOM) 0000000013420230 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.SNP.MISC.CONFIG_RELAXED_BRK0 | |||
| Constant(s): | ||||
| Comments: | Configure relaxed-ordering Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM2.SNP.MISC.CONFIG_RELAXED_BRK0_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_RELAXED_BRK0_CMD_CL_DMA_W: enable relaxed ordering for (non-atomic write) cl_dma_w (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 1 | RW | RW | CONFIG_RELAXED_BRK0_CMD_CL_DMA_W_HP: Reserved. (was: enable relaxed ordering for (non-atomic write) cl_dma_w_hp (only valid for GPU and AFU-M2 memory)) | |
| 2 | RW | RW | CONFIG_RELAXED_BRK0_CMD_CL_DMA_INJ: enable relaxed ordering for (non-atomic write) cl_dma_inj (only valid for GPU and AFU-M2 memory) | |
| 3 | RW | RW | CONFIG_RELAXED_BRK0_CMD_PR_DMA_INJ: enable relaxed ordering for (non-atomic write) pr_dma_inj (only valid for GPU and AFU-M2 memory) | |
| 4 | RW | RW | CONFIG_RELAXED_BRK0_CMD_DMA_PR_W: enable relaxed ordering for (non-atomic write) dma_pr_w (only valid for GPU and AFU-M2 memory) | |
| 5 | RW | RW | CONFIG_RELAXED_BRK0_CMD_CL_RD_NC_F0: enable relaxed ordering for (non-atomic read) cl_rd_nc(F=0) (only valid for GPU and AFU-M2 memory) | |
| 6 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMW_CAS_IMAX_U: enable relaxed ordering for (atomic write) armw_cas_imax_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 7 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMW_CAS_IMAX_S: enable relaxed ordering for (atomic write) armw_cas_imax_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 8 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMW_CAS_IMIN_U: enable relaxed ordering for (atomic write) armw_cas_imin_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 9 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMW_CAS_IMIN_S: enable relaxed ordering for (atomic write) armw_cas_imin_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 10 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMW_ADD: enable relaxed ordering for (atomic write) armw_add (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 11 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMW_AND: enable relaxed ordering for (atomic write) armw_and (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 12 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMW_OR: enable relaxed ordering for (atomic write) armw_or (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 13 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMW_XOR: enable relaxed ordering for (atomic write) armw_xor (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 14 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMWF_CAS_IMAX_U: enable relaxed ordering for (atomic read) armwf_cas_imax_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 15 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMWF_CAS_IMAX_S: enable relaxed ordering for (atomic read) armwf_cas_imax_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 16 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMWF_CAS_IMIN_U: enable relaxed ordering for (atomic read) armwf_cas_imin_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 17 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMWF_CAS_IMIN_S: enable relaxed ordering for (atomic read) armwf_cas_imin_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 18 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMWF_ADD: enable relaxed ordering for (atomic read) armwf_add (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 19 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMWF_AND: enable relaxed ordering for (atomic read) armwf_and (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 20 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMWF_OR: enable relaxed ordering for (atomic read) armwf_or (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 21 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMWF_XOR: enable relaxed ordering for (atomic read) armwf_xor (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 22 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMWF_CAS_E: enable relaxed ordering for (atomic read) armwf_cas_e (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 23 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMWF_CAS_U: enable relaxed ordering for (atomic read) armwf_cas_u (only valid for OCAPI AFU-M1 or AFU-M2 memory) (errata HW367501 requires this bit to be 0 for GPU memory) | |
| 24 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMW_CAS_T: enable relaxed ordering for (atomic write) armw_cas_t (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 25 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMWF_CAS_NE: enable relaxed ordering for (atomic read) armwf_cas_ne (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 26 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMWF_INC_B: enable relaxed ordering for (atomic read) armwf_inc_b (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 27 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMWF_INC_E: enable relaxed ordering for (atomic read) armwf_inc_e (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 28 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMWF_DEC_B: enable relaxed ordering for (atomic read) armwf_dec_b (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 29:31 | RW | RW | CONFIG_RELAXED_BRK0_RESERVED1: reserved | |
| 32 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE0_WRENA: 0/1 = disable/enable relaxed source 0 for (non-atomic) write operations | |
| 33 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE0_RDENA: 0/1 = disable/enable relaxed source 0 for (non-atomic) read operations | |
| 34 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE0_AWENA: 0/1 = disable/enable relaxed source 0 for atomic (write) operations | |
| 35 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE0_ARENA: 0/1 = disable/enable relaxed source 0 for atomic (read) operations | |
| 36 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE1_WRENA: 0/1 = disable/enable relaxed source 1 for (non-atomic) write operations | |
| 37 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE1_RDENA: 0/1 = disable/enable relaxed source 1 for (non-atomic) read operations | |
| 38 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE1_AWENA: 0/1 = disable/enable relaxed source 1 for atomic (write) operations | |
| 39 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE1_ARENA: 0/1 = disable/enable relaxed source 1 for atomic (read) operations | |
| 40 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE2_WRENA: 0/1 = disable/enable relaxed source 2 for (non-atomic) write operations | |
| 41 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE2_RDENA: 0/1 = disable/enable relaxed source 2 for (non-atomic) read operations | |
| 42 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE2_AWENA: 0/1 = disable/enable relaxed source 2 for atomic (write) operations | |
| 43 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE2_ARENA: 0/1 = disable/enable relaxed source 2 for atomic (read) operations | |
| 44 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE3_WRENA: 0/1 = disable/enable relaxed source 3 for (non-atomic) write operations | |
| 45 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE3_RDENA: 0/1 = disable/enable relaxed source 3 for (non-atomic) read operations | |
| 46 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE3_AWENA: 0/1 = disable/enable relaxed source 3 for atomic (write) operations | |
| 47 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE3_ARENA: 0/1 = disable/enable relaxed source 3 for atomic (read) operations | |
| 48 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE4_WRENA: 0/1 = disable/enable relaxed source 4 for (non-atomic) write operations | |
| 49 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE4_RDENA: 0/1 = disable/enable relaxed source 4 for (non-atomic) read operations | |
| 50 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE4_AWENA: 0/1 = disable/enable relaxed source 4 for atomic (write) operations | |
| 51 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE4_ARENA: 0/1 = disable/enable relaxed source 4 for atomic (read) operations | |
| 52 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE5_WRENA: 0/1 = disable/enable relaxed source 5 for (non-atomic) write operations | |
| 53 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE5_RDENA: 0/1 = disable/enable relaxed source 5 for (non-atomic) read operations | |
| 54 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE5_AWENA: 0/1 = disable/enable relaxed source 5 for atomic (write) operations | |
| 55 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE5_ARENA: 0/1 = disable/enable relaxed source 5 for atomic (read) operations | |
| 56 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE6_WRENA: 0/1 = disable/enable relaxed source 6 for (non-atomic) write operations | |
| 57 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE6_RDENA: 0/1 = disable/enable relaxed source 6 for (non-atomic) read operations | |
| 58 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE6_AWENA: 0/1 = disable/enable relaxed source 6 for atomic (write) operations | |
| 59 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE6_ARENA: 0/1 = disable/enable relaxed source 6 for atomic (read) operations | |
| 60 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE7_WRENA: 0/1 = disable/enable relaxed source 7 for (non-atomic) write operations | |
| 61 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE7_RDENA: 0/1 = disable/enable relaxed source 7 for (non-atomic) read operations | |
| 62 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE7_AWENA: 0/1 = disable/enable relaxed source 7 for atomic (write) operations | |
| 63 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE7_ARENA: 0/1 = disable/enable relaxed source 7 for atomic (read) operations | |
| Relaxed-Ordering Config2 brick 1 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010907 (SCOM) 0000000013420238 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.SNP.MISC.CONFIG_RELAXED_BRK1 | |||
| Constant(s): | ||||
| Comments: | Configure relaxed-ordering Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM2.SNP.MISC.CONFIG_RELAXED_BRK1_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_RELAXED_BRK1_CMD_CL_DMA_W: enable relaxed ordering for (non-atomic write) cl_dma_w (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 1 | RW | RW | CONFIG_RELAXED_BRK1_CMD_CL_DMA_W_HP: Reserved. (was: enable relaxed ordering for (non-atomic write) cl_dma_w_hp (only valid for GPU and AFU-M2 memory)) | |
| 2 | RW | RW | CONFIG_RELAXED_BRK1_CMD_CL_DMA_INJ: enable relaxed ordering for (non-atomic write) cl_dma_inj (only valid for GPU and AFU-M2 memory) | |
| 3 | RW | RW | CONFIG_RELAXED_BRK1_CMD_PR_DMA_INJ: enable relaxed ordering for (non-atomic write) pr_dma_inj (only valid for GPU and AFU-M2 memory) | |
| 4 | RW | RW | CONFIG_RELAXED_BRK1_CMD_DMA_PR_W: enable relaxed ordering for (non-atomic write) dma_pr_w (only valid for GPU and AFU-M2 memory) | |
| 5 | RW | RW | CONFIG_RELAXED_BRK1_CMD_CL_RD_NC_F0: enable relaxed ordering for (non-atomic read) cl_rd_nc(F=0) (only valid for GPU and AFU-M2 memory) | |
| 6 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMW_CAS_IMAX_U: enable relaxed ordering for (atomic write) armw_cas_imax_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 7 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMW_CAS_IMAX_S: enable relaxed ordering for (atomic write) armw_cas_imax_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 8 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMW_CAS_IMIN_U: enable relaxed ordering for (atomic write) armw_cas_imin_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 9 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMW_CAS_IMIN_S: enable relaxed ordering for (atomic write) armw_cas_imin_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 10 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMW_ADD: enable relaxed ordering for (atomic write) armw_add (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 11 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMW_AND: enable relaxed ordering for (atomic write) armw_and (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 12 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMW_OR: enable relaxed ordering for (atomic write) armw_or (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 13 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMW_XOR: enable relaxed ordering for (atomic write) armw_xor (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 14 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMWF_CAS_IMAX_U: enable relaxed ordering for (atomic read) armwf_cas_imax_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 15 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMWF_CAS_IMAX_S: enable relaxed ordering for (atomic read) armwf_cas_imax_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 16 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMWF_CAS_IMIN_U: enable relaxed ordering for (atomic read) armwf_cas_imin_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 17 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMWF_CAS_IMIN_S: enable relaxed ordering for (atomic read) armwf_cas_imin_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 18 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMWF_ADD: enable relaxed ordering for (atomic read) armwf_add (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 19 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMWF_AND: enable relaxed ordering for (atomic read) armwf_and (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 20 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMWF_OR: enable relaxed ordering for (atomic read) armwf_or (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 21 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMWF_XOR: enable relaxed ordering for (atomic read) armwf_xor (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 22 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMWF_CAS_E: enable relaxed ordering for (atomic read) armwf_cas_e (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 23 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMWF_CAS_U: enable relaxed ordering for (atomic read) armwf_cas_u (only valid for OCAPI AFU-M1 or AFU-M2 memory) (errata HW367501 requires this bit to be 0 for GPU memory) | |
| 24 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMW_CAS_T: enable relaxed ordering for (atomic write) armw_cas_t (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 25 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMWF_CAS_NE: enable relaxed ordering for (atomic read) armwf_cas_ne (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 26 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMWF_INC_B: enable relaxed ordering for (atomic read) armwf_inc_b (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 27 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMWF_INC_E: enable relaxed ordering for (atomic read) armwf_inc_e (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 28 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMWF_DEC_B: enable relaxed ordering for (atomic read) armwf_dec_b (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 29:31 | RW | RW | CONFIG_RELAXED_BRK1_RESERVED1: reserved | |
| 32 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE0_WRENA: 0/1 = disable/enable relaxed source 0 for (non-atomic) write operations | |
| 33 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE0_RDENA: 0/1 = disable/enable relaxed source 0 for (non-atomic) read operations | |
| 34 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE0_AWENA: 0/1 = disable/enable relaxed source 0 for atomic (write) operations | |
| 35 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE0_ARENA: 0/1 = disable/enable relaxed source 0 for atomic (read) operations | |
| 36 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE1_WRENA: 0/1 = disable/enable relaxed source 1 for (non-atomic) write operations | |
| 37 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE1_RDENA: 0/1 = disable/enable relaxed source 1 for (non-atomic) read operations | |
| 38 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE1_AWENA: 0/1 = disable/enable relaxed source 1 for atomic (write) operations | |
| 39 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE1_ARENA: 0/1 = disable/enable relaxed source 1 for atomic (read) operations | |
| 40 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE2_WRENA: 0/1 = disable/enable relaxed source 2 for (non-atomic) write operations | |
| 41 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE2_RDENA: 0/1 = disable/enable relaxed source 2 for (non-atomic) read operations | |
| 42 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE2_AWENA: 0/1 = disable/enable relaxed source 2 for atomic (write) operations | |
| 43 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE2_ARENA: 0/1 = disable/enable relaxed source 2 for atomic (read) operations | |
| 44 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE3_WRENA: 0/1 = disable/enable relaxed source 3 for (non-atomic) write operations | |
| 45 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE3_RDENA: 0/1 = disable/enable relaxed source 3 for (non-atomic) read operations | |
| 46 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE3_AWENA: 0/1 = disable/enable relaxed source 3 for atomic (write) operations | |
| 47 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE3_ARENA: 0/1 = disable/enable relaxed source 3 for atomic (read) operations | |
| 48 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE4_WRENA: 0/1 = disable/enable relaxed source 4 for (non-atomic) write operations | |
| 49 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE4_RDENA: 0/1 = disable/enable relaxed source 4 for (non-atomic) read operations | |
| 50 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE4_AWENA: 0/1 = disable/enable relaxed source 4 for atomic (write) operations | |
| 51 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE4_ARENA: 0/1 = disable/enable relaxed source 4 for atomic (read) operations | |
| 52 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE5_WRENA: 0/1 = disable/enable relaxed source 5 for (non-atomic) write operations | |
| 53 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE5_RDENA: 0/1 = disable/enable relaxed source 5 for (non-atomic) read operations | |
| 54 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE5_AWENA: 0/1 = disable/enable relaxed source 5 for atomic (write) operations | |
| 55 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE5_ARENA: 0/1 = disable/enable relaxed source 5 for atomic (read) operations | |
| 56 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE6_WRENA: 0/1 = disable/enable relaxed source 6 for (non-atomic) write operations | |
| 57 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE6_RDENA: 0/1 = disable/enable relaxed source 6 for (non-atomic) read operations | |
| 58 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE6_AWENA: 0/1 = disable/enable relaxed source 6 for atomic (write) operations | |
| 59 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE6_ARENA: 0/1 = disable/enable relaxed source 6 for atomic (read) operations | |
| 60 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE7_WRENA: 0/1 = disable/enable relaxed source 7 for (non-atomic) write operations | |
| 61 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE7_RDENA: 0/1 = disable/enable relaxed source 7 for (non-atomic) read operations | |
| 62 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE7_AWENA: 0/1 = disable/enable relaxed source 7 for atomic (write) operations | |
| 63 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE7_ARENA: 0/1 = disable/enable relaxed source 7 for atomic (read) operations | |
| Relaxed-Ordering Config2 brick 2 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010908 (SCOM) 0000000013420240 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.SNP.MISC.CONFIG_RELAXED_BRK2 | |||
| Constant(s): | ||||
| Comments: | Configure relaxed-ordering Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM2.SNP.MISC.CONFIG_RELAXED_BRK2_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_RELAXED_BRK2_CMD_CL_DMA_W: enable relaxed ordering for (non-atomic write) cl_dma_w (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 1 | RW | RW | CONFIG_RELAXED_BRK2_CMD_CL_DMA_W_HP: Reserved. (was: enable relaxed ordering for (non-atomic write) cl_dma_w_hp (only valid for GPU and AFU-M2 memory)) | |
| 2 | RW | RW | CONFIG_RELAXED_BRK2_CMD_CL_DMA_INJ: enable relaxed ordering for (non-atomic write) cl_dma_inj (only valid for GPU and AFU-M2 memory) | |
| 3 | RW | RW | CONFIG_RELAXED_BRK2_CMD_PR_DMA_INJ: enable relaxed ordering for (non-atomic write) pr_dma_inj (only valid for GPU and AFU-M2 memory) | |
| 4 | RW | RW | CONFIG_RELAXED_BRK2_CMD_DMA_PR_W: enable relaxed ordering for (non-atomic write) dma_pr_w (only valid for GPU and AFU-M2 memory) | |
| 5 | RW | RW | CONFIG_RELAXED_BRK2_CMD_CL_RD_NC_F0: enable relaxed ordering for (non-atomic read) cl_rd_nc(F=0) (only valid for GPU and AFU-M2 memory) | |
| 6 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMW_CAS_IMAX_U: enable relaxed ordering for (atomic write) armw_cas_imax_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 7 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMW_CAS_IMAX_S: enable relaxed ordering for (atomic write) armw_cas_imax_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 8 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMW_CAS_IMIN_U: enable relaxed ordering for (atomic write) armw_cas_imin_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 9 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMW_CAS_IMIN_S: enable relaxed ordering for (atomic write) armw_cas_imin_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 10 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMW_ADD: enable relaxed ordering for (atomic write) armw_add (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 11 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMW_AND: enable relaxed ordering for (atomic write) armw_and (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 12 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMW_OR: enable relaxed ordering for (atomic write) armw_or (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 13 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMW_XOR: enable relaxed ordering for (atomic write) armw_xor (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 14 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMWF_CAS_IMAX_U: enable relaxed ordering for (atomic read) armwf_cas_imax_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 15 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMWF_CAS_IMAX_S: enable relaxed ordering for (atomic read) armwf_cas_imax_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 16 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMWF_CAS_IMIN_U: enable relaxed ordering for (atomic read) armwf_cas_imin_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 17 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMWF_CAS_IMIN_S: enable relaxed ordering for (atomic read) armwf_cas_imin_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 18 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMWF_ADD: enable relaxed ordering for (atomic read) armwf_add (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 19 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMWF_AND: enable relaxed ordering for (atomic read) armwf_and (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 20 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMWF_OR: enable relaxed ordering for (atomic read) armwf_or (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 21 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMWF_XOR: enable relaxed ordering for (atomic read) armwf_xor (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 22 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMWF_CAS_E: enable relaxed ordering for (atomic read) armwf_cas_e (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 23 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMWF_CAS_U: enable relaxed ordering for (atomic read) armwf_cas_u (only valid for OCAPI AFU-M1 or AFU-M2 memory) (errata HW367501 requires this bit to be 0 for GPU memory) | |
| 24 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMW_CAS_T: enable relaxed ordering for (atomic write) armw_cas_t (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 25 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMWF_CAS_NE: enable relaxed ordering for (atomic read) armwf_cas_ne (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 26 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMWF_INC_B: enable relaxed ordering for (atomic read) armwf_inc_b (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 27 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMWF_INC_E: enable relaxed ordering for (atomic read) armwf_inc_e (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 28 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMWF_DEC_B: enable relaxed ordering for (atomic read) armwf_dec_b (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 29:31 | RW | RW | CONFIG_RELAXED_BRK2_RESERVED1: reserved | |
| 32 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE0_WRENA: 0/1 = disable/enable relaxed source 0 for (non-atomic) write operations | |
| 33 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE0_RDENA: 0/1 = disable/enable relaxed source 0 for (non-atomic) read operations | |
| 34 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE0_AWENA: 0/1 = disable/enable relaxed source 0 for atomic (write) operations | |
| 35 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE0_ARENA: 0/1 = disable/enable relaxed source 0 for atomic (read) operations | |
| 36 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE1_WRENA: 0/1 = disable/enable relaxed source 1 for (non-atomic) write operations | |
| 37 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE1_RDENA: 0/1 = disable/enable relaxed source 1 for (non-atomic) read operations | |
| 38 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE1_AWENA: 0/1 = disable/enable relaxed source 1 for atomic (write) operations | |
| 39 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE1_ARENA: 0/1 = disable/enable relaxed source 1 for atomic (read) operations | |
| 40 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE2_WRENA: 0/1 = disable/enable relaxed source 2 for (non-atomic) write operations | |
| 41 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE2_RDENA: 0/1 = disable/enable relaxed source 2 for (non-atomic) read operations | |
| 42 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE2_AWENA: 0/1 = disable/enable relaxed source 2 for atomic (write) operations | |
| 43 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE2_ARENA: 0/1 = disable/enable relaxed source 2 for atomic (read) operations | |
| 44 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE3_WRENA: 0/1 = disable/enable relaxed source 3 for (non-atomic) write operations | |
| 45 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE3_RDENA: 0/1 = disable/enable relaxed source 3 for (non-atomic) read operations | |
| 46 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE3_AWENA: 0/1 = disable/enable relaxed source 3 for atomic (write) operations | |
| 47 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE3_ARENA: 0/1 = disable/enable relaxed source 3 for atomic (read) operations | |
| 48 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE4_WRENA: 0/1 = disable/enable relaxed source 4 for (non-atomic) write operations | |
| 49 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE4_RDENA: 0/1 = disable/enable relaxed source 4 for (non-atomic) read operations | |
| 50 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE4_AWENA: 0/1 = disable/enable relaxed source 4 for atomic (write) operations | |
| 51 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE4_ARENA: 0/1 = disable/enable relaxed source 4 for atomic (read) operations | |
| 52 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE5_WRENA: 0/1 = disable/enable relaxed source 5 for (non-atomic) write operations | |
| 53 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE5_RDENA: 0/1 = disable/enable relaxed source 5 for (non-atomic) read operations | |
| 54 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE5_AWENA: 0/1 = disable/enable relaxed source 5 for atomic (write) operations | |
| 55 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE5_ARENA: 0/1 = disable/enable relaxed source 5 for atomic (read) operations | |
| 56 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE6_WRENA: 0/1 = disable/enable relaxed source 6 for (non-atomic) write operations | |
| 57 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE6_RDENA: 0/1 = disable/enable relaxed source 6 for (non-atomic) read operations | |
| 58 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE6_AWENA: 0/1 = disable/enable relaxed source 6 for atomic (write) operations | |
| 59 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE6_ARENA: 0/1 = disable/enable relaxed source 6 for atomic (read) operations | |
| 60 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE7_WRENA: 0/1 = disable/enable relaxed source 7 for (non-atomic) write operations | |
| 61 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE7_RDENA: 0/1 = disable/enable relaxed source 7 for (non-atomic) read operations | |
| 62 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE7_AWENA: 0/1 = disable/enable relaxed source 7 for atomic (write) operations | |
| 63 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE7_ARENA: 0/1 = disable/enable relaxed source 7 for atomic (read) operations | |
| Relaxed-Ordering Config2 brick 3 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010909 (SCOM) 0000000013420248 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.SNP.MISC.CONFIG_RELAXED_BRK3 | |||
| Constant(s): | ||||
| Comments: | Configure relaxed-ordering Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM2.SNP.MISC.CONFIG_RELAXED_BRK3_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_RELAXED_BRK3_CMD_CL_DMA_W: enable relaxed ordering for (non-atomic write) cl_dma_w (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 1 | RW | RW | CONFIG_RELAXED_BRK3_CMD_CL_DMA_W_HP: Reserved. (was: enable relaxed ordering for (non-atomic write) cl_dma_w_hp (only valid for GPU and AFU-M2 memory)) | |
| 2 | RW | RW | CONFIG_RELAXED_BRK3_CMD_CL_DMA_INJ: enable relaxed ordering for (non-atomic write) cl_dma_inj (only valid for GPU and AFU-M2 memory) | |
| 3 | RW | RW | CONFIG_RELAXED_BRK3_CMD_PR_DMA_INJ: enable relaxed ordering for (non-atomic write) pr_dma_inj (only valid for GPU and AFU-M2 memory) | |
| 4 | RW | RW | CONFIG_RELAXED_BRK3_CMD_DMA_PR_W: enable relaxed ordering for (non-atomic write) dma_pr_w (only valid for GPU and AFU-M2 memory) | |
| 5 | RW | RW | CONFIG_RELAXED_BRK3_CMD_CL_RD_NC_F0: enable relaxed ordering for (non-atomic read) cl_rd_nc(F=0) (only valid for GPU and AFU-M2 memory) | |
| 6 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMW_CAS_IMAX_U: enable relaxed ordering for (atomic write) armw_cas_imax_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 7 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMW_CAS_IMAX_S: enable relaxed ordering for (atomic write) armw_cas_imax_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 8 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMW_CAS_IMIN_U: enable relaxed ordering for (atomic write) armw_cas_imin_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 9 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMW_CAS_IMIN_S: enable relaxed ordering for (atomic write) armw_cas_imin_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 10 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMW_ADD: enable relaxed ordering for (atomic write) armw_add (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 11 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMW_AND: enable relaxed ordering for (atomic write) armw_and (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 12 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMW_OR: enable relaxed ordering for (atomic write) armw_or (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 13 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMW_XOR: enable relaxed ordering for (atomic write) armw_xor (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 14 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMWF_CAS_IMAX_U: enable relaxed ordering for (atomic read) armwf_cas_imax_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 15 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMWF_CAS_IMAX_S: enable relaxed ordering for (atomic read) armwf_cas_imax_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 16 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMWF_CAS_IMIN_U: enable relaxed ordering for (atomic read) armwf_cas_imin_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 17 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMWF_CAS_IMIN_S: enable relaxed ordering for (atomic read) armwf_cas_imin_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 18 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMWF_ADD: enable relaxed ordering for (atomic read) armwf_add (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 19 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMWF_AND: enable relaxed ordering for (atomic read) armwf_and (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 20 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMWF_OR: enable relaxed ordering for (atomic read) armwf_or (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 21 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMWF_XOR: enable relaxed ordering for (atomic read) armwf_xor (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 22 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMWF_CAS_E: enable relaxed ordering for (atomic read) armwf_cas_e (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 23 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMWF_CAS_U: enable relaxed ordering for (atomic read) armwf_cas_u (only valid for OCAPI AFU-M1 or AFU-M2 memory) (errata HW367501 requires this bit to be 0 for GPU memory) | |
| 24 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMW_CAS_T: enable relaxed ordering for (atomic write) armw_cas_t (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 25 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMWF_CAS_NE: enable relaxed ordering for (atomic read) armwf_cas_ne (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 26 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMWF_INC_B: enable relaxed ordering for (atomic read) armwf_inc_b (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 27 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMWF_INC_E: enable relaxed ordering for (atomic read) armwf_inc_e (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 28 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMWF_DEC_B: enable relaxed ordering for (atomic read) armwf_dec_b (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 29:31 | RW | RW | CONFIG_RELAXED_BRK3_RESERVED1: reserved | |
| 32 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE0_WRENA: 0/1 = disable/enable relaxed source 0 for (non-atomic) write operations | |
| 33 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE0_RDENA: 0/1 = disable/enable relaxed source 0 for (non-atomic) read operations | |
| 34 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE0_AWENA: 0/1 = disable/enable relaxed source 0 for atomic (write) operations | |
| 35 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE0_ARENA: 0/1 = disable/enable relaxed source 0 for atomic (read) operations | |
| 36 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE1_WRENA: 0/1 = disable/enable relaxed source 1 for (non-atomic) write operations | |
| 37 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE1_RDENA: 0/1 = disable/enable relaxed source 1 for (non-atomic) read operations | |
| 38 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE1_AWENA: 0/1 = disable/enable relaxed source 1 for atomic (write) operations | |
| 39 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE1_ARENA: 0/1 = disable/enable relaxed source 1 for atomic (read) operations | |
| 40 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE2_WRENA: 0/1 = disable/enable relaxed source 2 for (non-atomic) write operations | |
| 41 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE2_RDENA: 0/1 = disable/enable relaxed source 2 for (non-atomic) read operations | |
| 42 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE2_AWENA: 0/1 = disable/enable relaxed source 2 for atomic (write) operations | |
| 43 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE2_ARENA: 0/1 = disable/enable relaxed source 2 for atomic (read) operations | |
| 44 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE3_WRENA: 0/1 = disable/enable relaxed source 3 for (non-atomic) write operations | |
| 45 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE3_RDENA: 0/1 = disable/enable relaxed source 3 for (non-atomic) read operations | |
| 46 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE3_AWENA: 0/1 = disable/enable relaxed source 3 for atomic (write) operations | |
| 47 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE3_ARENA: 0/1 = disable/enable relaxed source 3 for atomic (read) operations | |
| 48 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE4_WRENA: 0/1 = disable/enable relaxed source 4 for (non-atomic) write operations | |
| 49 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE4_RDENA: 0/1 = disable/enable relaxed source 4 for (non-atomic) read operations | |
| 50 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE4_AWENA: 0/1 = disable/enable relaxed source 4 for atomic (write) operations | |
| 51 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE4_ARENA: 0/1 = disable/enable relaxed source 4 for atomic (read) operations | |
| 52 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE5_WRENA: 0/1 = disable/enable relaxed source 5 for (non-atomic) write operations | |
| 53 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE5_RDENA: 0/1 = disable/enable relaxed source 5 for (non-atomic) read operations | |
| 54 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE5_AWENA: 0/1 = disable/enable relaxed source 5 for atomic (write) operations | |
| 55 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE5_ARENA: 0/1 = disable/enable relaxed source 5 for atomic (read) operations | |
| 56 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE6_WRENA: 0/1 = disable/enable relaxed source 6 for (non-atomic) write operations | |
| 57 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE6_RDENA: 0/1 = disable/enable relaxed source 6 for (non-atomic) read operations | |
| 58 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE6_AWENA: 0/1 = disable/enable relaxed source 6 for atomic (write) operations | |
| 59 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE6_ARENA: 0/1 = disable/enable relaxed source 6 for atomic (read) operations | |
| 60 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE7_WRENA: 0/1 = disable/enable relaxed source 7 for (non-atomic) write operations | |
| 61 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE7_RDENA: 0/1 = disable/enable relaxed source 7 for (non-atomic) read operations | |
| 62 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE7_AWENA: 0/1 = disable/enable relaxed source 7 for atomic (write) operations | |
| 63 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE7_ARENA: 0/1 = disable/enable relaxed source 7 for atomic (read) operations | |
| Relaxed-Ordering Config2 brick 4 | ||||
|---|---|---|---|---|
| Addr: |
000000001101090A (SCOM) 0000000013420250 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.SNP.MISC.CONFIG_RELAXED_BRK4 | |||
| Constant(s): | ||||
| Comments: | Configure relaxed-ordering Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM2.SNP.MISC.CONFIG_RELAXED_BRK4_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_RELAXED_BRK4_CMD_CL_DMA_W: enable relaxed ordering for (non-atomic write) cl_dma_w (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 1 | RW | RW | CONFIG_RELAXED_BRK4_CMD_CL_DMA_W_HP: Reserved. (was: enable relaxed ordering for (non-atomic write) cl_dma_w_hp (only valid for GPU and AFU-M2 memory)) | |
| 2 | RW | RW | CONFIG_RELAXED_BRK4_CMD_CL_DMA_INJ: enable relaxed ordering for (non-atomic write) cl_dma_inj (only valid for GPU and AFU-M2 memory) | |
| 3 | RW | RW | CONFIG_RELAXED_BRK4_CMD_PR_DMA_INJ: enable relaxed ordering for (non-atomic write) pr_dma_inj (only valid for GPU and AFU-M2 memory) | |
| 4 | RW | RW | CONFIG_RELAXED_BRK4_CMD_DMA_PR_W: enable relaxed ordering for (non-atomic write) dma_pr_w (only valid for GPU and AFU-M2 memory) | |
| 5 | RW | RW | CONFIG_RELAXED_BRK4_CMD_CL_RD_NC_F0: enable relaxed ordering for (non-atomic read) cl_rd_nc(F=0) (only valid for GPU and AFU-M2 memory) | |
| 6 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMW_CAS_IMAX_U: enable relaxed ordering for (atomic write) armw_cas_imax_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 7 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMW_CAS_IMAX_S: enable relaxed ordering for (atomic write) armw_cas_imax_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 8 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMW_CAS_IMIN_U: enable relaxed ordering for (atomic write) armw_cas_imin_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 9 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMW_CAS_IMIN_S: enable relaxed ordering for (atomic write) armw_cas_imin_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 10 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMW_ADD: enable relaxed ordering for (atomic write) armw_add (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 11 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMW_AND: enable relaxed ordering for (atomic write) armw_and (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 12 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMW_OR: enable relaxed ordering for (atomic write) armw_or (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 13 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMW_XOR: enable relaxed ordering for (atomic write) armw_xor (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 14 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMWF_CAS_IMAX_U: enable relaxed ordering for (atomic read) armwf_cas_imax_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 15 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMWF_CAS_IMAX_S: enable relaxed ordering for (atomic read) armwf_cas_imax_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 16 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMWF_CAS_IMIN_U: enable relaxed ordering for (atomic read) armwf_cas_imin_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 17 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMWF_CAS_IMIN_S: enable relaxed ordering for (atomic read) armwf_cas_imin_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 18 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMWF_ADD: enable relaxed ordering for (atomic read) armwf_add (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 19 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMWF_AND: enable relaxed ordering for (atomic read) armwf_and (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 20 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMWF_OR: enable relaxed ordering for (atomic read) armwf_or (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 21 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMWF_XOR: enable relaxed ordering for (atomic read) armwf_xor (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 22 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMWF_CAS_E: enable relaxed ordering for (atomic read) armwf_cas_e (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 23 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMWF_CAS_U: enable relaxed ordering for (atomic read) armwf_cas_u (only valid for OCAPI AFU-M1 or AFU-M2 memory) (errata HW367501 requires this bit to be 0 for GPU memory) | |
| 24 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMW_CAS_T: enable relaxed ordering for (atomic write) armw_cas_t (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 25 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMWF_CAS_NE: enable relaxed ordering for (atomic read) armwf_cas_ne (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 26 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMWF_INC_B: enable relaxed ordering for (atomic read) armwf_inc_b (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 27 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMWF_INC_E: enable relaxed ordering for (atomic read) armwf_inc_e (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 28 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMWF_DEC_B: enable relaxed ordering for (atomic read) armwf_dec_b (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 29:31 | RW | RW | CONFIG_RELAXED_BRK4_RESERVED1: reserved | |
| 32 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE0_WRENA: 0/1 = disable/enable relaxed source 0 for (non-atomic) write operations | |
| 33 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE0_RDENA: 0/1 = disable/enable relaxed source 0 for (non-atomic) read operations | |
| 34 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE0_AWENA: 0/1 = disable/enable relaxed source 0 for atomic (write) operations | |
| 35 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE0_ARENA: 0/1 = disable/enable relaxed source 0 for atomic (read) operations | |
| 36 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE1_WRENA: 0/1 = disable/enable relaxed source 1 for (non-atomic) write operations | |
| 37 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE1_RDENA: 0/1 = disable/enable relaxed source 1 for (non-atomic) read operations | |
| 38 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE1_AWENA: 0/1 = disable/enable relaxed source 1 for atomic (write) operations | |
| 39 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE1_ARENA: 0/1 = disable/enable relaxed source 1 for atomic (read) operations | |
| 40 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE2_WRENA: 0/1 = disable/enable relaxed source 2 for (non-atomic) write operations | |
| 41 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE2_RDENA: 0/1 = disable/enable relaxed source 2 for (non-atomic) read operations | |
| 42 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE2_AWENA: 0/1 = disable/enable relaxed source 2 for atomic (write) operations | |
| 43 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE2_ARENA: 0/1 = disable/enable relaxed source 2 for atomic (read) operations | |
| 44 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE3_WRENA: 0/1 = disable/enable relaxed source 3 for (non-atomic) write operations | |
| 45 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE3_RDENA: 0/1 = disable/enable relaxed source 3 for (non-atomic) read operations | |
| 46 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE3_AWENA: 0/1 = disable/enable relaxed source 3 for atomic (write) operations | |
| 47 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE3_ARENA: 0/1 = disable/enable relaxed source 3 for atomic (read) operations | |
| 48 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE4_WRENA: 0/1 = disable/enable relaxed source 4 for (non-atomic) write operations | |
| 49 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE4_RDENA: 0/1 = disable/enable relaxed source 4 for (non-atomic) read operations | |
| 50 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE4_AWENA: 0/1 = disable/enable relaxed source 4 for atomic (write) operations | |
| 51 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE4_ARENA: 0/1 = disable/enable relaxed source 4 for atomic (read) operations | |
| 52 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE5_WRENA: 0/1 = disable/enable relaxed source 5 for (non-atomic) write operations | |
| 53 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE5_RDENA: 0/1 = disable/enable relaxed source 5 for (non-atomic) read operations | |
| 54 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE5_AWENA: 0/1 = disable/enable relaxed source 5 for atomic (write) operations | |
| 55 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE5_ARENA: 0/1 = disable/enable relaxed source 5 for atomic (read) operations | |
| 56 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE6_WRENA: 0/1 = disable/enable relaxed source 6 for (non-atomic) write operations | |
| 57 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE6_RDENA: 0/1 = disable/enable relaxed source 6 for (non-atomic) read operations | |
| 58 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE6_AWENA: 0/1 = disable/enable relaxed source 6 for atomic (write) operations | |
| 59 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE6_ARENA: 0/1 = disable/enable relaxed source 6 for atomic (read) operations | |
| 60 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE7_WRENA: 0/1 = disable/enable relaxed source 7 for (non-atomic) write operations | |
| 61 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE7_RDENA: 0/1 = disable/enable relaxed source 7 for (non-atomic) read operations | |
| 62 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE7_AWENA: 0/1 = disable/enable relaxed source 7 for atomic (write) operations | |
| 63 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE7_ARENA: 0/1 = disable/enable relaxed source 7 for atomic (read) operations | |
| Low-Water Marks | ||||
|---|---|---|---|---|
| Addr: |
000000001101090B (SCOM) 0000000013420258 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.SNP.MISC.LOW_WATER | |||
| Constant(s): | ||||
| Comments: | State-Machine allocation Low-Water Marks the sum of the Low-Water marks must be less than config_max_machines Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM2.SNP.MISC.LOW_WATER_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_LOW_WATER_PWR0: Low-Water mark for PowerBus rd/dclaim/atomic/etc. requests | |
| 1 | RW | RW | CONFIG_LOW_WATER_PWR1: Low-Water mark for PowerBus cp (castout-push) requests. | |
| 2 | RW | RW | CONFIG_LOW_WATER_PWR2: Low-Water mark for PowerBus snoops for force-evict requests. | |
| 3 | RW | RW | CONFIG_LOW_WATER_XATS: Low-Water mark for ATS/XSL PowerBus requests | |
| 4 | RW | RW | CONFIG_LOW_WATER_INTS: Low-Water mark for MISC Interrupt requests | |
| 5 | RW | RW | CONFIG_LOW_WATER_REQ0: Low-Water mark for brick-0 NVLink brick-0 Req channel or OCAPI TLX.vc.3 requests | |
| 6 | RW | RW | CONFIG_LOW_WATER_CST0: Low-Water mark for brick-0 OCAPI Castout requests | |
| 7 | RW | RW | CONFIG_LOW_WATER_PRB0: Low-Water mark for brick-0 NVLink Probe or OCAPI mem_pa_flush requests | |
| 8 | RW | RW | CONFIG_LOW_WATER_REQ1: Low-Water mark for brick-1 NVLink Req channel or OCAPI TLX.vc.3 requests | |
| 9 | RW | RW | CONFIG_LOW_WATER_CST1: Low-Water mark for brick-1 OCAPI Castout requests | |
| 10 | RW | RW | CONFIG_LOW_WATER_PRB1: Low-Water mark for brick-1 NVLink Probe or OCAPI mem_pa_flush requests | |
| 11 | RW | RW | CONFIG_LOW_WATER_REQ2: Low-Water mark for brick-2 NVLink brick-0 Req channel or OCAPI TLX.vc.3 requests | |
| 12 | RW | RW | CONFIG_LOW_WATER_CST2: Low-Water mark for brick-2 OCAPI Castout requests | |
| 13 | RW | RW | CONFIG_LOW_WATER_PRB2: Low-Water mark for brick-2 NVLink Probe or OCAPI mem_pa_flush requests | |
| 14 | RW | RW | CONFIG_LOW_WATER_REQ3: Low-Water mark for brick-3 NVLink Req channel or OCAPI TLX.vc.3 requests | |
| 15 | RW | RW | CONFIG_LOW_WATER_CST3: Low-Water mark for brick-3 OCAPI Castout requests | |
| 16 | RW | RW | CONFIG_LOW_WATER_PRB3: Low-Water mark for brick-3 NVLink Probe or OCAPI mem_pa_flush requests | |
| 17 | RW | RW | CONFIG_LOW_WATER_REQ4: Low-Water mark for brick-4 NVLink brick-0 Req channel or OCAPI TLX.vc.3 requests | |
| 18 | RW | RW | CONFIG_LOW_WATER_CST4: Low-Water mark for brick-4 OCAPI Castout requests | |
| 19 | RW | RW | CONFIG_LOW_WATER_PRB4: Low-Water mark for brick-4 NVLink Probe or OCAPI mem_pa_flush requests | |
| 20 | RW | RW | CONFIG_LOW_WATER_XI_SHARED: shared Low-Water mark for ATS/XSL/MISC-INT requests if set to 1, the only one of config_low_water_{xats,ints} should be set to 1 | |
| 21 | RW | RW | CONFIG_LOW_WATER_REQX_SHARED: shared Low-Water mark for req0...req4 if set to 1, the only one of config_low_water_{req0...req4} should be set to 1 | |
| 22 | RW | RW | CONFIG_LOW_WATER_CSTX_SHARED: shared Low-Water mark for cst0...cst4 if set to 1, the only one of config_low_water_{cst0...cst4} should be set to 1 | |
| 23 | RW | RW | CONFIG_LOW_WATER_PRBX_SHARED: shared Low-Water mark for prb0...prb4 if set to 1, the only one of config_low_water_{prb0...prb4} should be set to 1 | |
| 24:25 | RW | RW | CONFIG_WEIGHT_PWR0: 0...3 -> weight 1..4 when balancing PWR0 against other classes | |
| 26:27 | RW | RW | CONFIG_WEIGHT_PWR1: 0...3 -> weight 1..4 when balancing PWR1 against other classes | |
| 28:29 | RW | RW | CONFIG_WEIGHT_PWR2: 0...3 -> weight 1..4 when balancing PWR2 against other classes | |
| 30:31 | RW | RW | CONFIG_WEIGHT_XATS: 0...3 -> weight 1..4 when balancing XATS against other classes | |
| 32:33 | RW | RW | CONFIG_WEIGHT_INTS: 0...3 -> weight 1..4 when balancing INTS against other classes | |
| 34:35 | RW | RW | CONFIG_WEIGHT_REQ0: 0...3 -> weight 1..4 when balancing REQ0 against other classes | |
| 36:37 | RW | RW | CONFIG_WEIGHT_CST0: 0...3 -> weight 1..4 when balancing CST0 against other classes | |
| 38:39 | RW | RW | CONFIG_WEIGHT_PRB0: 0...3 -> weight 1..4 when balancing PRB0 against other classes | |
| 40:41 | RW | RW | CONFIG_WEIGHT_REQ1: 0...3 -> weight 1..4 when balancing REQ1 against other classes | |
| 42:43 | RW | RW | CONFIG_WEIGHT_CST1: 0...3 -> weight 1..4 when balancing CST1 against other classes | |
| 44:45 | RW | RW | CONFIG_WEIGHT_PRB1: 0...3 -> weight 1..4 when balancing PRB1 against other classes | |
| 46:47 | RW | RW | CONFIG_WEIGHT_REQ2: 0...3 -> weight 1..4 when balancing REQ2 against other classes | |
| 48:49 | RW | RW | CONFIG_WEIGHT_CST2: 0...3 -> weight 1..4 when balancing CST2 against other classes | |
| 50:51 | RW | RW | CONFIG_WEIGHT_PRB2: 0...3 -> weight 1..4 when balancing PRB2 against other classes | |
| 52:53 | RW | RW | CONFIG_WEIGHT_REQ3: 0...3 -> weight 1..4 when balancing REQ3 against other classes | |
| 54:55 | RW | RW | CONFIG_WEIGHT_CST3: 0...3 -> weight 1..4 when balancing CST3 against other classes | |
| 56:57 | RW | RW | CONFIG_WEIGHT_PRB3: 0...3 -> weight 1..4 when balancing PRB3 against other classes | |
| 58:59 | RW | RW | CONFIG_WEIGHT_REQ4: 0...3 -> weight 1..4 when balancing REQ4 against other classes | |
| 60:61 | RW | RW | CONFIG_WEIGHT_CST4: 0...3 -> weight 1..4 when balancing CST4 against other classes | |
| 62:63 | RW | RW | CONFIG_WEIGHT_PRB4: 0...3 -> weight 1..4 when balancing PRB4 against other classes | |
| Machine Allocation configuration | ||||
|---|---|---|---|---|
| Addr: |
000000001101090D (SCOM) 0000000013420268 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.SNP.MISC.MACHINE_ALLOC | |||
| Constant(s): | ||||
| Comments: | State-Machine configuration and control Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM2.SNP.MISC.MACHINE_ALLOC_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_ENABLE_MACHINE_ALLOC: Enable state-machine allocation Can only be changed 0->1, must stay 1 once set | |
| 1 | RW | RW | CONFIG_ENABLE_EXCEED_HIGH: Enable exceeding high water marks | |
| 2:7 | RW | RW | CONFIG_MAX_MACHINES: Maximum number of state-machines to be used. Must be >= 20 and <= 62 | |
| 8:13 | RW | RW | CONFIG_HIGH_WATER_IDLE: High-water mark for 'Idle' allocation classes | |
| 14:19 | RW | RW | CONFIG_HIGH_BONUS1: Signed 6-bit bonus value to apply to the available machines count prior to division | |
| 20:29 | RW | RW | CONFIG_HIGH_MIN_SHARE: Minimum share after division (machines * 8) | |
| 30:39 | RW | RW | CONFIG_HIGH_BONUS2: Signed 10-bit bonus value to apply to machines count after division (signed machines * 8) | |
| 40:43 | RW | RW | CONFIG_MAX_HIGH_RESERVED: Maximum of state-machines reserved for classes below their high-water marks | |
| 44:48 | RW | RW | CONFIG_SMAL_DEBUG_SEL0: Debug select mux for state-machine-allocation debug output 0 | |
| 49:53 | RW | RW | CONFIG_SMAL_DEBUG_SEL1: Debug select mux for state-machine-allocation debug output 1 | |
| 54:58 | RW | RW | CONFIG_SMAL_DEBUG_SEL2: Debug select mux for state-machine-allocation debug output 2 | |
| 59:63 | RW | RW | CONFIG_SMAL_DEBUG_SEL3: Debug select mux for state-machine-allocation debug output 3 | |
| Perf Config Reg | ||||
|---|---|---|---|---|
| Addr: |
000000001101090E (SCOM) 0000000013420270 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.SNP.MISC.PERF_CONFIG | |||
| Constant(s): | ||||
| Comments: | Performance Event selection | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:35 | PAU3.CS.SM2.SNP.MISC.PERF_CONFIG_Q_0_INST.LATC.L2(0:35) [000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:7 | RW | RW | PERF_CONFIG_EVENT0: Event 0 select 0: count nothing 1: count cycles 2: count # of cycles REQ0 count matches perf_mask/match_alloc 3: count # of cycles CST0 count matches perf_mask/match_alloc 4: count # of cycles PRB0 count matches perf_mask/match_alloc 5: count # of cycles REQ1 count matches perf_mask/match_alloc 6: count # of cycles CST1 count matches perf_mask/match_alloc 7: count # of cycles PRB1 count matches perf_mask/match_alloc 8: count # of cycles REQ2 count matches perf_mask/match_alloc 9: count # of cycles CST2 count matches perf_mask/match_alloc 10: count # of cycles PRB2 count matches perf_mask/match_alloc 11: count # of cycles REQ3 count matches perf_mask/match_alloc 12: count # of cycles CST3 count matches perf_mask/match_alloc 13: count # of cycles PRB3 count matches perf_mask/match_alloc 14: count # of cycles REQ4 count matches perf_mask/match_alloc 15: count # of cycles CST4 count matches perf_mask/match_alloc 16: count # of cycles PRB4 count matches perf_mask/match_alloc 17: count # of cycles PWR0 count matches perf_mask/match_alloc 18: count # of cycles PWR1 count matches perf_mask/match_alloc 19: count # of cycles PWR2 count matches perf_mask/match_alloc 20: count # of cycles XATS count matches perf_mask/match_alloc 21: count # of cycles reserved count matches perf_mask/match_alloc 22: count # of cycles free count matches perf_mask/match_alloc 23: count # of cycles INTS count matches perf_mask/match_alloc 24: count # of RCmds received matching perf_mask/match 25: count # of times PResp=rty_dinc was driven 26: count # of RCmds received from PAU/PAU 27: count # of perf-select RCmds that had cam_hit_pckt_vld_d asserted as an input to the fsnoop_coll table 28: count # of perf-select RCmds that had cam_hit_pckt_vld_nd asserted as an input to the fsnoop_coll table 29: count # of perf-select RCmds that had cam_hit_pckt_vld_ond asserted as an input to the fsnoop_coll table 30: count # of perf-select RCmds that had cam_hit_pckt_win asserted as an input to the fsnoop_coll table 31: count # of perf-select RCmds that had cam_hit_rty_dif asserted as an input to the fsnoop_coll table 32: count # of perf-select RCmds that had cam_hit_rty_dif_mpf asserted as an input to the fsnoop_coll table 33: count # of perf-select RCmds that had cam_hit_pckt_poison asserted as an input to the fsnoop_coll table 34: count # of perf-select RCmds that had cam_hit_rty_lco asserted as an input to the fsnoop_coll table 35: count # of perf-select RCmds that had cam_hit_rty_abbk asserted as an input to the fsnoop_coll table 36: count # of perf-select RCmds that had cam_hit_rty_abbks asserted as an input to the fsnoop_coll table 37: count # of perf-select RCmds that had cam_hit_rty_all asserted as an input to the fsnoop_coll table 38: count # of perf-select RCmds that had cam_hit_snarf_cpm asserted as an input to the fsnoop_coll table 39: count # of perf-select RCmds that had cam_hit_pb_req asserted as an input to the fsnoop_coll table 40: count # of perf-select RCmds that had presp_rty_spec asserted as an output from the fsnoop_coll table 41: count # of perf-select RCmds that had presp_rty_hpc asserted as an output from the fsnoop_coll table 42: count # of perf-select RCmds that had presp_rty_prot asserted as an output from the fsnoop_coll table 43: count # of perf-select RCmds that had presp_rty_r_coll asserted as an output from the fsnoop_coll table 44: count # of perf-select RCmds that had presp_pckt_hit asserted as an output from the fsnoop_coll table 45: count # of perf-select RCmds that had presp_accept asserted as an output from the fsnoop_coll table 46: count # of perf-select RCmds that had cam_hit_mod_addr asserted as an input to the fsnoop_dir table 47: count # of perf-select RCmds that had cam_hit_mod_lock asserted as an input to the fsnoop_dir table 48: count # of perf-select RCmds that had cam_hit_syn_pend asserted as an input to the fsnoop_dir table 49: count # of perf-select RCmds that had cam_hit_sfe_addr asserted as an input to the fsnoop_dir table 50: count # of perf-select RCmds that had cam_hit_sfe_pend asserted as an input to the fsnoop_dir table 51: count # of perf-select RCmds that had cam_hit_co_pend asserted as an input to the fsnoop_dir table 52: count # of perf-select RCmds that had cam_hit_rs_pend asserted as an input to the fsnoop_dir table 53: count # of perf-select RCmds that had cam_hit_row_not_head asserted as an input to the fsnoop_dir table 54: count # of perf-select RCmds that had l2_dir_valid_or_alloc asserted as an input to the fsnoop_dir table 55: count # of perf-select RCmds that had l2_dir_any_pro_note asserted as an input to the fsnoop_dir table 56: count # of perf-select RCmds that had l2_dir_max_e asserted as an input to the fsnoop_dir table 57: count # of perf-select RCmds that had l2_dir_has_s asserted as an input to the fsnoop_dir table 58: count # of perf-select RCmds that had l2_dir_any_cmd_i asserted as an input to the fsnoop_dir table 59: count # of perf-select RCmds that had l2_dir_other_brick_s asserted as an input to the fsnoop_dir table 60: count # of perf-select RCmds that had l2_dir_other_brick_e asserted as an input to the fsnoop_dir table 61: count # of perf-select RCmds that had presp_shd asserted as an output from the fsnoop_dir table 62: count # of perf-select RCmds that had presp_rty asserted as an output from the fsnoop_dir table 63: count # of perf-select RCmds that had presp_m_mu_ix asserted as an output from the fsnoop_dir table 64: count # of perf-select RCmds that had presp_rty_lost_claim asserted as an output from the fsnoop_dir table 65: count # of perf-select RCmds that had lock_snp_sfe asserted as an output from the fsnoop_dir table 66: count # of perf-select RCmds that had lock_snp_mod asserted as an output from the fsnoop_dir table 67: count # of perf-select RCmds that had lock_mod asserted as an output from the fsnoop_dir table 68: count # of perf-select RCmds that had send_mugging asserted as an output from the fsnoop_dir table 69: count # of perf-select RCmds that had block_dir asserted as an input to the psnoop table others: reserved (count nothing) | |
| 8:15 | RW | RW | PERF_CONFIG_EVENT1: Event 1 select See Event 0 select for encodes | |
| 16:23 | RW | RW | PERF_CONFIG_EVENT2: Event 2 select See Event 0 select for encodes | |
| 24:31 | RW | RW | PERF_CONFIG_EVENT3: Event 3 select See Event 0 select for encodes | |
| 32:34 | RW | RW | PERF_CONFIG_RESERVED2: reserved | |
| 35 | RW | RW | PERF_CONFIG_ACT: Enable clock-gates for performance monitor latches | |
| 36:63 | RO | RO | constant=0b0000000000000000000000000000 | |
| Inhibit configuration Register | ||||
|---|---|---|---|---|
| Addr: |
000000001101090F (SCOM) 0000000013420278 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.SNP.MISC.INHIBIT_CONFIG | |||
| Constant(s): | ||||
| Comments: | Configures Inhibits for CQ_SM | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:31 | PAU3.CS.SM2.SNP.MISC.INHIBIT_CONFIG_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:7 | RW | RW | CONFIG_INHIBIT_DEST0: Selects the destination of the inhibit | |
| 8:15 | RW | RW | CONFIG_INHIBIT_DEST1: Selects the destination of the inhibit | |
| 16:23 | RW | RW | CONFIG_INHIBIT_DEST2: Selects the destination of the inhibit | |
| 24:31 | RW | RW | CONFIG_INHIBIT_DEST3: Selects the destination of the inhibit | |
| 32:63 | RO | RO | constant=0b00000000000000000000000000000000 | |
| c_err_rpt Message-0 latches | ||||
|---|---|---|---|---|
| Addr: |
0000000011010910 (SCOM) 0000000013420280 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.SNP.MISC.CERR_MESSAGE0 | |||
| Constant(s): | ||||
| Comments: | Error message/capture register 0 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM2.SNP.MISC.CERR_MESSAGE0_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:63 | RWX_WCLRREG | RWX_WCLRREG | CERR_MESSAGE_BITS0: reserved | |
| c_err_rpt Message-1 latches | ||||
|---|---|---|---|---|
| Addr: |
0000000011010911 (SCOM) 0000000013420288 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.SNP.MISC.CERR_MESSAGE1 | |||
| Constant(s): | ||||
| Comments: | Error message/capture register 1 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM2.SNP.MISC.CERR_MESSAGE1_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:63 | RWX_WCLRREG | RWX_WCLRREG | CERR_MESSAGE_BITS1: reserved | |
| CQ_SM status register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010912 (SCOM) 0000000013420290 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.SNP.MISC.SM_STATUS | |||
| Constant(s): | ||||
| Comments: | Status reporting register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:23 | PAU3.CS.SM2.SNP.MISC.SM_STATUS_Q_0_INST.LATC.L2(0:23) [000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | ROX | ROX | SM_STATUS_PWR0: 1 when PowerBus (non-cp*) allocation is at its idle level | |
| 1 | ROX | ROX | SM_STATUS_PWR1: 1 when PowerBus (cp*) allocation is at its idle level | |
| 2 | ROX | ROX | SM_STATUS_PWR2: 1 when PowerBus (cp*) allocation is at its idle level | |
| 3 | ROX | ROX | SM_STATUS_XATS: 1 when ATS/MISC allocation is at its idle level | |
| 4 | ROX | ROX | SM_STATUS_INTS: 1 when INTS allocation is at its idle level | |
| 5 | ROX | ROX | SM_STATUS_CREQ0: 1 when brick 0 CReq allocation is at its idle level | |
| 6 | ROX | ROX | SM_STATUS_CST0: 1 when brick 0 Castout allocation is at its idle level | |
| 7 | ROX | ROX | SM_STATUS_PRB0: 1 when brick 0 Probe allocation is at its idle level | |
| 8 | ROX | ROX | SM_STATUS_CREQ1: 1 when brick 1 CReq allocation is at its idle level | |
| 9 | ROX | ROX | SM_STATUS_CST1: 1 when brick 1 Castout allocation is at its idle level | |
| 10 | ROX | ROX | SM_STATUS_PRB1: 1 when brick 1 Probe allocation is at its idle level | |
| 11 | ROX | ROX | SM_STATUS_CREQ2: 1 when brick 1 CReq allocation is at its idle level | |
| 12 | ROX | ROX | SM_STATUS_CST2: 1 when brick 1 Castout allocation is at its idle level | |
| 13 | ROX | ROX | SM_STATUS_PRB2: 1 when brick 1 Probe allocation is at its idle level | |
| 14 | ROX | ROX | SM_STATUS_CREQ3: 1 when brick 1 CReq allocation is at its idle level | |
| 15 | ROX | ROX | SM_STATUS_CST3: 1 when brick 1 Castout allocation is at its idle level | |
| 16 | ROX | ROX | SM_STATUS_PRB3: 1 when brick 1 Probe allocation is at its idle level | |
| 17 | ROX | ROX | SM_STATUS_CREQ4: 1 when brick 1 CReq allocation is at its idle level | |
| 18 | ROX | ROX | SM_STATUS_CST4: 1 when brick 1 Castout allocation is at its idle level | |
| 19 | ROX | ROX | SM_STATUS_PRB4: 1 when brick 1 Probe allocation is at its idle level | |
| 20 | ROX | ROX | SM_STATUS_CHGRATE: 1 when chgrate.hang slowdown is being applied to machine allocation | |
| 21:23 | ROX | ROX | SM_STATUS_RESERVED1: reserved | |
| 24:63 | RO | RO | constant=0b0000000000000000000000000000000000000000 | |
| c_err_rpt first-0 latches | ||||
|---|---|---|---|---|
| Addr: |
0000000011010913 (SCOM) 0000000013420298 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.SNP.MISC.CERR_FIRST0 | |||
| Constant(s): | ||||
| Comments: | c_err_rpt first latches read-write-1-clear reg | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:7 | PAU3.CS.SM2.SNP.MISC.CERR_FIRST0_Q_0_INST.LATC.L2(0:7) [00000000] | |||
| 8:15 | PAU3.CS.SM2.SNP.MISC.CERR_FIRST0_Q_8_INST.LATC.L2(8:15) [00000000] | |||
| 16:23 | PAU3.CS.SM2.SNP.MISC.CERR_FIRST0_Q_16_INST.LATC.L2(16:23) [00000000] | |||
| 24:35 | PAU3.CS.SM2.SNP.MISC.CERR_FIRST0_Q_24_INST.LATC.L2(24:35) [000000000000] | |||
| 36:59 | PAU3.CS.SM2.SNP.MISC.CERR_FIRST0_Q_36_INST.LATC.L2(36:59) [000000000000000000000000] | |||
| 60:63 | PAU3.CS.SM2.SNP.MISC.CERR_FIRST0_Q_60_INST.LATC.L2(60:63) [0000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NCF_0: NCF0 An NVLink probe did not match its GPUBar | |
| 1 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NCF_1: NCF1 Epoch timeout while ProNoted L2-dir entry was waiting for castout | |
| 2 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NCF_2: NCF2 (reserved) | |
| 3 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NCF_3: NCF3 NVLink NCF error for brick 0 occurred | |
| 4 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NCF_4: NCF4 NVLink NCF error for brick 1 occurred | |
| 5 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NCF_5: NCF5 NVLink NCF error for brick 2 occurred | |
| 6 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NCF_6: NCF6 NVLink NCF error for brick 3 occurred | |
| 7 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NCF_7: NCF7 NVLink NCF error for brick 4 occurred | |
| 8 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBR_0: PBR0 Addr_Error received for self-lpc command (SSF) | |
| 9 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBR_1: PBR1 (reserved) | |
| 10 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBR_2: PBR2 (reserved) | |
| 11 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBR_3: PBR3 (reserved) | |
| 12 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBR_4: PBR4 Illegal Cmd to GPU Memory received | |
| 13 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBR_5: PBR5 (reserved) | |
| 14 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBR_6: PBR6 (reserved) | |
| 15 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBR_7: PBR7 (reserved) | |
| 16 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBP_0: PBP0 Parity error detected on rcmd ttag field | |
| 17 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBP_1: PBP1 Parity error detected on rcmd addr field | |
| 18 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBP_2: PBP2 Parity error detected on CResp ttag | |
| 19 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBP_3: PBP3 Parity error detected on CResp atag | |
| 20 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBP_4: PBP4 (reserved) | |
| 21 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBP_5: PBP5 (reserved) | |
| 22 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBP_6: PBP6 (reserved) | |
| 23 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBP_7: PBP7 (reserved) | |
| 24 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBC_0: PBC0 (reserved) | |
| 25 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBC_1: PBC1 (reserved) | |
| 26 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBC_2: PBC2 (reserved) | |
| 27 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBC_3: PBC3 (reserved) | |
| 28 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBC_4: PBC4 Reserved (was: RCmd TTag received with illegal group ID) | |
| 29 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBC_5: PBC5 Reserved (was: RCmd TTag received with illegal chip ID) | |
| 30 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBC_6: PBC6 Reserved (was: CResp TTag received with illegal group ID) | |
| 31 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBC_7: PBC7 Reserved (was: CResp TTag received with illegal chip ID) | |
| 32 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBC_8: PBC8 RCmd received with disabled topo-idx in address | |
| 33 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBC_9: PBC9 (reserved) | |
| 34 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBC_10: PBC10 (reserved) | |
| 35 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBC_11: PBC11 (reserved) | |
| 36 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_0: NLG0 RCmd Pre-Snoop table lookup missed the table | |
| 37 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_1: NLG1 (reserved) | |
| 38 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_2: NLG2 Req-in logic dropped an ATS-response | |
| 39 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_3: NLG3 (reserved) | |
| 40 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_4: NLG4 RCmd Final-Snoop Coll-Shd table lookup missed the table | |
| 41 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_5: NLG5 CAM lookup hit multiple snarf-cpm entries (multiple probes received from GPU) | |
| 42 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_6: NLG6 Arb request-in queue overflowed | |
| 43 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_7: NLG7 RCmd Final-Snoop coll collision/lpc table lookup missed the table | |
| 44 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_8: NLG8 RCmd Final-Snoop dir C2/L2-directory table lookup missed the table | |
| 45 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_9: NLG9 RCmd Final-Snoop Coll-Retry-Spec table lookup missed the table | |
| 46 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_10: NLG10 RCmd Final-Snoop Coll-Retry-HPC table lookup missed the table | |
| 47 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_11: NLG11 RCmd Final-Snoop Coll-Retry-Prot table lookup missed the table | |
| 48 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_12: NLG12 RCmd Final-Snoop Coll-Retry-RColl table lookup missed the table | |
| 49 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_13: NLG13 RCmd Final-Snoop Coll-Pocket-Hit table lookup missed the table | |
| 50 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_14: NLG14 RCmd Final-Snoop Coll-Accept table lookup missed the table | |
| 51 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_15: NLG15 RCmd Final-Snoop Dir-Shd table lookup missed the table | |
| 52 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_16: NLG16 RCmd Final-Snoop Dir-Rty table lookup missed the table | |
| 53 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_17: NLG17 RCmd Final-Snoop Dir-MMU(Ix) table lookup missed the table | |
| 54 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_18: NLG18 RCmd Final-Snoop Dir C2/L2 directory impossible command/state combination | |
| 55 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_19: NLG19 RCmd Final-Snoop Dir-Snoop-SFE table lookup missed the table | |
| 56 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_20: NLG20 RCmd Final-Snoop Dir-Snoop-Mod table lookup missed the table | |
| 57 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_21: NLG21 RCmd Final-Snoop Dir-Mod table lookup missed the table | |
| 58 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_22: NLG22 RCmd Final-Snoop CAM-Shared table lookup missed the table | |
| 59 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_23: NLG23 An internal sequencer had an invalid state | |
| 60 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBF_0: PBF0 Addr_Error received for self-lpc command (SSF) | |
| 61 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBF_1: PBF1 (reserved) | |
| 62 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBF_2: PBF2 (reserved) | |
| 63 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBF_3: PBF3 (reserved) | |
| c_err_rpt mask-0 latches | ||||
|---|---|---|---|---|
| Addr: |
0000000011010914 (SCOM) 00000000134202A0 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.SNP.MISC.CERR_MASK0 | |||
| Constant(s): | ||||
| Comments: | c_err_rpt mask reg Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM2.SNP.MISC.CERR_MASK0_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | IDIAL_SNP_MASK_NCF_0: NCF0 An NVLink probe did not match its GPUBar | |
| 1 | RW | RW | IDIAL_SNP_MASK_NCF_1: NCF1 Epoch timeout while ProNoted L2-dir entry was waiting for castout | |
| 2 | RW | RW | IDIAL_SNP_MASK_NCF_2: NCF2 (reserved) | |
| 3 | RW | RW | IDIAL_SNP_MASK_NCF_3: NCF3 NVLink NCF error for brick 0 occurred | |
| 4 | RW | RW | IDIAL_SNP_MASK_NCF_4: NCF4 NVLink NCF error for brick 1 occurred | |
| 5 | RW | RW | IDIAL_SNP_MASK_NCF_5: NCF5 NVLink NCF error for brick 2 occurred | |
| 6 | RW | RW | IDIAL_SNP_MASK_NCF_6: NCF6 NVLink NCF error for brick 3 occurred | |
| 7 | RW | RW | IDIAL_SNP_MASK_NCF_7: NCF7 NVLink NCF error for brick 4 occurred | |
| 8 | RW | RW | IDIAL_SNP_MASK_PBR_0: PBR0 Addr_Error received for self-lpc command (SSF) | |
| 9 | RW | RW | IDIAL_SNP_MASK_PBR_1: PBR1 (reserved) | |
| 10 | RW | RW | IDIAL_SNP_MASK_PBR_2: PBR2 (reserved) | |
| 11 | RW | RW | IDIAL_SNP_MASK_PBR_3: PBR3 (reserved) | |
| 12 | RW | RW | IDIAL_SNP_MASK_PBR_4: PBR4 Illegal Cmd to GPU Memory received | |
| 13 | RW | RW | IDIAL_SNP_MASK_PBR_5: PBR5 (reserved) | |
| 14 | RW | RW | IDIAL_SNP_MASK_PBR_6: PBR6 (reserved) | |
| 15 | RW | RW | IDIAL_SNP_MASK_PBR_7: PBR7 (reserved) | |
| 16 | RW | RW | IDIAL_SNP_MASK_PBP_0: PBP0 Parity error detected on rcmd ttag field | |
| 17 | RW | RW | IDIAL_SNP_MASK_PBP_1: PBP1 Parity error detected on rcmd addr field | |
| 18 | RW | RW | IDIAL_SNP_MASK_PBP_2: PBP2 Parity error detected on CResp ttag | |
| 19 | RW | RW | IDIAL_SNP_MASK_PBP_3: PBP3 Parity error detected on CResp atag | |
| 20 | RW | RW | IDIAL_SNP_MASK_PBP_4: PBP4 (reserved) | |
| 21 | RW | RW | IDIAL_SNP_MASK_PBP_5: PBP5 (reserved) | |
| 22 | RW | RW | IDIAL_SNP_MASK_PBP_6: PBP6 (reserved) | |
| 23 | RW | RW | IDIAL_SNP_MASK_PBP_7: PBP7 (reserved) | |
| 24 | RW | RW | IDIAL_SNP_MASK_PBC_0: PBC0 (reserved) | |
| 25 | RW | RW | IDIAL_SNP_MASK_PBC_1: PBC1 (reserved) | |
| 26 | RW | RW | IDIAL_SNP_MASK_PBC_2: PBC2 (reserved) | |
| 27 | RW | RW | IDIAL_SNP_MASK_PBC_3: PBC3 (reserved) | |
| 28 | RW | RW | IDIAL_SNP_MASK_PBC_4: PBC4 Reserved (was: RCmd TTag received with illegal group ID) | |
| 29 | RW | RW | IDIAL_SNP_MASK_PBC_5: PBC5 Reserved (was: RCmd TTag received with illegal chip ID) | |
| 30 | RW | RW | IDIAL_SNP_MASK_PBC_6: PBC6 Reserved (was: CResp TTag received with illegal group ID) | |
| 31 | RW | RW | IDIAL_SNP_MASK_PBC_7: PBC7 Reserved (was: CResp TTag received with illegal chip ID) | |
| 32 | RW | RW | IDIAL_SNP_MASK_PBC_8: PBC8 RCmd received with disabled topo-idx in address | |
| 33 | RW | RW | IDIAL_SNP_MASK_PBC_9: PBC9 (reserved) | |
| 34 | RW | RW | IDIAL_SNP_MASK_PBC_10: PBC10 (reserved) | |
| 35 | RW | RW | IDIAL_SNP_MASK_PBC_11: PBC11 (reserved) | |
| 36 | RW | RW | IDIAL_SNP_MASK_NLG_0: NLG0 RCmd Pre-Snoop table lookup missed the table | |
| 37 | RW | RW | IDIAL_SNP_MASK_NLG_1: NLG1 (reserved) | |
| 38 | RW | RW | IDIAL_SNP_MASK_NLG_2: NLG2 Req-in logic dropped an ATS-response | |
| 39 | RW | RW | IDIAL_SNP_MASK_NLG_3: NLG3 (reserved) | |
| 40 | RW | RW | IDIAL_SNP_MASK_NLG_4: NLG4 RCmd Final-Snoop Coll-Shd table lookup missed the table | |
| 41 | RW | RW | IDIAL_SNP_MASK_NLG_5: NLG5 CAM lookup hit multiple snarf-cpm entries (multiple probes received from GPU) | |
| 42 | RW | RW | IDIAL_SNP_MASK_NLG_6: NLG6 Arb request-in queue overflowed | |
| 43 | RW | RW | IDIAL_SNP_MASK_NLG_7: NLG7 RCmd Final-Snoop coll collision/lpc table lookup missed the table | |
| 44 | RW | RW | IDIAL_SNP_MASK_NLG_8: NLG8 RCmd Final-Snoop dir C2/L2-directory table lookup missed the table | |
| 45 | RW | RW | IDIAL_SNP_MASK_NLG_9: NLG9 RCmd Final-Snoop Coll-Retry-Spec table lookup missed the table | |
| 46 | RW | RW | IDIAL_SNP_MASK_NLG_10: NLG10 RCmd Final-Snoop Coll-Retry-HPC table lookup missed the table | |
| 47 | RW | RW | IDIAL_SNP_MASK_NLG_11: NLG11 RCmd Final-Snoop Coll-Retry-Prot table lookup missed the table | |
| 48 | RW | RW | IDIAL_SNP_MASK_NLG_12: NLG12 RCmd Final-Snoop Coll-Retry-RColl table lookup missed the table | |
| 49 | RW | RW | IDIAL_SNP_MASK_NLG_13: NLG13 RCmd Final-Snoop Coll-Pocket-Hit table lookup missed the table | |
| 50 | RW | RW | IDIAL_SNP_MASK_NLG_14: NLG14 RCmd Final-Snoop Coll-Accept table lookup missed the table | |
| 51 | RW | RW | IDIAL_SNP_MASK_NLG_15: NLG15 RCmd Final-Snoop Dir-Shd table lookup missed the table | |
| 52 | RW | RW | IDIAL_SNP_MASK_NLG_16: NLG16 RCmd Final-Snoop Dir-Rty table lookup missed the table | |
| 53 | RW | RW | IDIAL_SNP_MASK_NLG_17: NLG17 RCmd Final-Snoop Dir-MMU(Ix) table lookup missed the table | |
| 54 | RW | RW | IDIAL_SNP_MASK_NLG_18: NLG18 RCmd Final-Snoop Dir C2/L2 directory impossible command/state combination | |
| 55 | RW | RW | IDIAL_SNP_MASK_NLG_19: NLG19 RCmd Final-Snoop Dir-Snoop-SFE table lookup missed the table | |
| 56 | RW | RW | IDIAL_SNP_MASK_NLG_20: NLG20 RCmd Final-Snoop Dir-Snoop-Mod table lookup missed the table | |
| 57 | RW | RW | IDIAL_SNP_MASK_NLG_21: NLG21 RCmd Final-Snoop Dir-Mod table lookup missed the table | |
| 58 | RW | RW | IDIAL_SNP_MASK_NLG_22: NLG22 RCmd Final-Snoop CAM-Shared table lookup missed the table | |
| 59 | RW | RW | IDIAL_SNP_MASK_NLG_23: NLG23 An internal sequencer had an invalid state | |
| 60 | RW | RW | IDIAL_SNP_MASK_PBF_0: PBF0 Addr_Error received for self-lpc command (SSF) | |
| 61 | RW | RW | IDIAL_SNP_MASK_PBF_1: PBF1 (reserved) | |
| 62 | RW | RW | IDIAL_SNP_MASK_PBF_2: PBF2 (reserved) | |
| 63 | RW | RW | IDIAL_SNP_MASK_PBF_3: PBF3 (reserved) | |
| c_err_rpt hold-0 latches | ||||
|---|---|---|---|---|
| Addr: |
0000000011010915 (SCOM) 00000000134202A8 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.SNP.MISC.CERR_HOLD0 | |||
| Constant(s): | ||||
| Comments: | c_err_rpt hold latches read-write-clear reg | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:7 | PAU3.CS.SM2.SNP.MISC.CERPT_NCF.HOLD_LATCH_INST.HOLD.LATC.L2(0:7) [00000000] | |||
| 8:15 | PAU3.CS.SM2.SNP.MISC.CERPT_PBR.HOLD_LATCH_INST.HOLD.LATC.L2(0:7) [00000000] | |||
| 16:23 | PAU3.CS.SM2.SNP.MISC.CERPT_PBP.HOLD_LATCH_INST.HOLD.LATC.L2(0:7) [00000000] | |||
| 24:35 | PAU3.CS.SM2.SNP.MISC.CERPT_PBC.HOLD_LATCH_INST.HOLD.LATC.L2(0:11) [000000000000] | |||
| 36:59 | PAU3.CS.SM2.SNP.MISC.CERPT_NLG.HOLD_LATCH_INST.HOLD.LATC.L2(0:23) [000000000000000000000000] | |||
| 60:63 | PAU3.CS.SM2.SNP.MISC.CERPT_PBF.HOLD_LATCH_INST.HOLD.LATC.L2(0:3) [0000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NCF_0: NCF0 An NVLink probe did not match its GPUBar | |
| 1 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NCF_1: NCF1 Epoch timeout while ProNoted L2-dir entry was waiting for castout | |
| 2 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NCF_2: NCF2 (reserved) | |
| 3 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NCF_3: NCF3 NVLink NCF error for brick 0 occurred | |
| 4 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NCF_4: NCF4 NVLink NCF error for brick 1 occurred | |
| 5 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NCF_5: NCF5 NVLink NCF error for brick 2 occurred | |
| 6 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NCF_6: NCF6 NVLink NCF error for brick 3 occurred | |
| 7 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NCF_7: NCF7 NVLink NCF error for brick 4 occurred | |
| 8 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBR_0: PBR0 Addr_Error received for self-lpc command (SSF) | |
| 9 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBR_1: PBR1 (reserved) | |
| 10 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBR_2: PBR2 (reserved) | |
| 11 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBR_3: PBR3 (reserved) | |
| 12 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBR_4: PBR4 Illegal Cmd to GPU Memory received | |
| 13 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBR_5: PBR5 (reserved) | |
| 14 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBR_6: PBR6 (reserved) | |
| 15 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBR_7: PBR7 (reserved) | |
| 16 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBP_0: PBP0 Parity error detected on rcmd ttag field | |
| 17 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBP_1: PBP1 Parity error detected on rcmd addr field | |
| 18 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBP_2: PBP2 Parity error detected on CResp ttag | |
| 19 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBP_3: PBP3 Parity error detected on CResp atag | |
| 20 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBP_4: PBP4 (reserved) | |
| 21 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBP_5: PBP5 (reserved) | |
| 22 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBP_6: PBP6 (reserved) | |
| 23 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBP_7: PBP7 (reserved) | |
| 24 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBC_0: PBC0 (reserved) | |
| 25 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBC_1: PBC1 (reserved) | |
| 26 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBC_2: PBC2 (reserved) | |
| 27 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBC_3: PBC3 (reserved) | |
| 28 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBC_4: PBC4 Reserved (was: RCmd TTag received with illegal group ID) | |
| 29 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBC_5: PBC5 Reserved (was: RCmd TTag received with illegal chip ID) | |
| 30 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBC_6: PBC6 Reserved (was: CResp TTag received with illegal group ID) | |
| 31 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBC_7: PBC7 Reserved (was: CResp TTag received with illegal chip ID) | |
| 32 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBC_8: PBC8 RCmd received with disabled topo-idx in address | |
| 33 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBC_9: PBC9 (reserved) | |
| 34 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBC_10: PBC10 (reserved) | |
| 35 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBC_11: PBC11 (reserved) | |
| 36 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_0: NLG0 RCmd Pre-Snoop table lookup missed the table | |
| 37 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_1: NLG1 (reserved) | |
| 38 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_2: NLG2 Req-in logic dropped an ATS-response | |
| 39 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_3: NLG3 (reserved) | |
| 40 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_4: NLG4 RCmd Final-Snoop Coll-Shd table lookup missed the table | |
| 41 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_5: NLG5 CAM lookup hit multiple snarf-cpm entries (multiple probes received from GPU) | |
| 42 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_6: NLG6 Arb request-in queue overflowed | |
| 43 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_7: NLG7 RCmd Final-Snoop coll collision/lpc table lookup missed the table | |
| 44 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_8: NLG8 RCmd Final-Snoop dir C2/L2-directory table lookup missed the table | |
| 45 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_9: NLG9 RCmd Final-Snoop Coll-Retry-Spec table lookup missed the table | |
| 46 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_10: NLG10 RCmd Final-Snoop Coll-Retry-HPC table lookup missed the table | |
| 47 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_11: NLG11 RCmd Final-Snoop Coll-Retry-Prot table lookup missed the table | |
| 48 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_12: NLG12 RCmd Final-Snoop Coll-Retry-RColl table lookup missed the table | |
| 49 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_13: NLG13 RCmd Final-Snoop Coll-Pocket-Hit table lookup missed the table | |
| 50 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_14: NLG14 RCmd Final-Snoop Coll-Accept table lookup missed the table | |
| 51 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_15: NLG15 RCmd Final-Snoop Dir-Shd table lookup missed the table | |
| 52 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_16: NLG16 RCmd Final-Snoop Dir-Rty table lookup missed the table | |
| 53 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_17: NLG17 RCmd Final-Snoop Dir-MMU(Ix) table lookup missed the table | |
| 54 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_18: NLG18 RCmd Final-Snoop Dir C2/L2 directory impossible command/state combination | |
| 55 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_19: NLG19 RCmd Final-Snoop Dir-Snoop-SFE table lookup missed the table | |
| 56 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_20: NLG20 RCmd Final-Snoop Dir-Snoop-Mod table lookup missed the table | |
| 57 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_21: NLG21 RCmd Final-Snoop Dir-Mod table lookup missed the table | |
| 58 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_22: NLG22 RCmd Final-Snoop CAM-Shared table lookup missed the table | |
| 59 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_23: NLG23 An internal sequencer had an invalid state | |
| 60 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBF_0: PBF0 Addr_Error received for self-lpc command (SSF) | |
| 61 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBF_1: PBF1 (reserved) | |
| 62 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBF_2: PBF2 (reserved) | |
| 63 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBF_3: PBF3 (reserved) | |
| Perf Address Match | ||||
|---|---|---|---|---|
| Addr: |
0000000011010916 (SCOM) 00000000134202B0 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.SNP.MISC.PERF_ADDR_CONFIG | |||
| Constant(s): | ||||
| Comments: | Performance Address Match | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:43 | PAU3.CS.SM2.SNP.MISC.PERF_ADDR_CONFIG_Q_0_INST.LATC.L2(0:43) [00000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:5 | RW | RW | PERF_SIZE_ADDR: Size of address range to match 35 = 64K 34 = 128K ... 25 = 64M 15 = 64G 10 = 2T 0 = 2P | |
| 6:41 | RW | RW | PERF_MATCH_ADDR: Address to match | |
| 42:43 | RW | RW | PERF_ADDR_RESERVED1: reserved | |
| 44:63 | RO | RO | constant=0b00000000000000000000 | |
| Perf Match Reg | ||||
|---|---|---|---|---|
| Addr: |
0000000011010917 (SCOM) 00000000134202B8 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.SNP.MISC.PERF_MATCH_CONFIG | |||
| Constant(s): | ||||
| Comments: | Performance Event Field Match | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:39 | PAU3.CS.SM2.SNP.MISC.PERF_MATCH_CONFIG_Q_0_INST.LATC.L2(0:39) [0000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:4 | RW | RW | PERF_MATCH_ALLOC_CLASS: Allocation Class / Source bus | |
| 5:16 | RW | RW | PERF_MATCH_TTYPE: TType | |
| 17:24 | RW | RW | PERF_MATCH_TSIZE: TSize | |
| 25 | RW | RW | PERF_MATCH_NVBE: NVLink byte enables | |
| 26 | RW | RW | PERF_MATCH_UT: NVLink UT | |
| 27:33 | RW | RW | PERF_MATCH_ATYPE: Address Type | |
| 34:39 | RW | RW | PERF_MATCH_ALLOC: Alloc | |
| 40:63 | RO | RO | constant=0b000000000000000000000000 | |
| Perf Mask Reg | ||||
|---|---|---|---|---|
| Addr: |
0000000011010918 (SCOM) 00000000134202C0 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.SNP.MISC.PERF_MASK_CONFIG | |||
| Constant(s): | ||||
| Comments: | Performance Event Field Mask | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:39 | PAU3.CS.SM2.SNP.MISC.PERF_MASK_CONFIG_Q_0_INST.LATC.L2(0:39) [0000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:4 | RW | RW | PERF_MASK_ALLOC_CLASS: Allocation Class / Source bus | |
| 5:16 | RW | RW | PERF_MASK_TTYPE: TType | |
| 17:24 | RW | RW | PERF_MASK_TSIZE: TSize | |
| 25 | RW | RW | PERF_MASK_NVBE: NVLink byte enables | |
| 26 | RW | RW | PERF_MASK_UT: NVLink UT | |
| 27:33 | RW | RW | PERF_MASK_ATYPE: Address Type | |
| 34:39 | RW | RW | PERF_MASK_ALLOC: Alloc | |
| 40:63 | RO | RO | constant=0b000000000000000000000000 | |
| Debug0 Config Reg | ||||
|---|---|---|---|---|
| Addr: |
0000000011010919 (SCOM) 00000000134202C8 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.SNP.MISC.DEBUG0_CONFIG | |||
| Constant(s): | ||||
| Comments: | Config register for trace-0 chain | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM2.SNP.MISC.DEBUG0_CONFIG_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:4 | RW | RW | DEBUG0_CONFIG_POD0: Mux control for byte 0 of trace-0 | |
| 5:9 | RW | RW | DEBUG0_CONFIG_POD1: Mux control for byte 1 of trace-0 | |
| 10:14 | RW | RW | DEBUG0_CONFIG_POD2: Mux control for byte 2 of trace-0 | |
| 15:19 | RW | RW | DEBUG0_CONFIG_POD3: Mux control for byte 3 of trace-0 | |
| 20:24 | RW | RW | DEBUG0_CONFIG_POD4: Mux control for byte 4 of trace-0 | |
| 25:29 | RW | RW | DEBUG0_CONFIG_POD5: Mux control for byte 5 of trace-0 | |
| 30:34 | RW | RW | DEBUG0_CONFIG_POD6: Mux control for byte 6 of trace-0 | |
| 35:39 | RW | RW | DEBUG0_CONFIG_POD7: Mux control for byte 7 of trace-0 | |
| 40:44 | RW | RW | DEBUG0_CONFIG_POD8: Mux control for byte 8 of trace-0 | |
| 45:49 | RW | RW | DEBUG0_CONFIG_POD9: Mux control for byte 9 of trace-0 | |
| 50:54 | RW | RW | DEBUG0_CONFIG_POD10: Mux control for byte 10 of trace-0 | |
| 55:62 | RW | RW | DEBUG0_CONFIG_RESERVED1: reserved | |
| 63 | RW | RW | DEBUG0_CONFIG_ACT: Enable clock-gates for debug trace latches | |
| Debug1 Config Reg | ||||
|---|---|---|---|---|
| Addr: |
000000001101091A (SCOM) 00000000134202D0 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.SNP.MISC.DEBUG1_CONFIG | |||
| Constant(s): | ||||
| Comments: | Config register for trace-1 chain | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM2.SNP.MISC.DEBUG1_CONFIG_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:4 | RW | RW | DEBUG1_CONFIG_POD0: Mux control for byte 0 of trace-1 | |
| 5:9 | RW | RW | DEBUG1_CONFIG_POD1: Mux control for byte 1 of trace-1 | |
| 10:14 | RW | RW | DEBUG1_CONFIG_POD2: Mux control for byte 2 of trace-1 | |
| 15:19 | RW | RW | DEBUG1_CONFIG_POD3: Mux control for byte 3 of trace-1 | |
| 20:24 | RW | RW | DEBUG1_CONFIG_POD4: Mux control for byte 4 of trace-1 | |
| 25:29 | RW | RW | DEBUG1_CONFIG_POD5: Mux control for byte 5 of trace-1 | |
| 30:34 | RW | RW | DEBUG1_CONFIG_POD6: Mux control for byte 6 of trace-1 | |
| 35:39 | RW | RW | DEBUG1_CONFIG_POD7: Mux control for byte 7 of trace-1 | |
| 40:44 | RW | RW | DEBUG1_CONFIG_POD8: Mux control for byte 8 of trace-1 | |
| 45:49 | RW | RW | DEBUG1_CONFIG_POD9: Mux control for byte 9 of trace-1 | |
| 50:54 | RW | RW | DEBUG1_CONFIG_POD10: Mux control for byte 10 of trace-1 | |
| 55:62 | RW | RW | DEBUG1_CONFIG_RESERVED1: reserved | |
| 63 | RW | RW | DEBUG1_CONFIG_ACT: Enable clock-gates for debug trace latches | |
| L2 Directory SCOM address register | ||||
|---|---|---|---|---|
| Addr: |
000000001101091B (SCOM) 00000000134202D8 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.SNP.MISC.SCOM_L2_ADDR | |||
| Constant(s): | ||||
| Comments: | register to initiate SCOM reads of the L2 direcotry | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:15 | PAU3.CS.SM2.SNP.MISC.SCOM_L2_ADDR_Q_0_INST.LATC.L2(0:15) [0000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX | RWX | SCOM_L2_VALID: Valid read Write 1 initiates a SCOM access Returns to 0 when access is finished and data is available in the DIR scom_l2_data register | |
| 1:3 | RW | RW | SCOM_L2_ADDR_RESERVED1: reserved | |
| 4:13 | RW | RW | SCOM_L2_CCI: Directory Congruence Class Index (aka SRAM address) to read | |
| 14:15 | RW | RW | SCOM_L2_WAY: Directory 'way' to read | |
| 16:63 | RO | RO | constant=0b000000000000000000000000000000000000000000000000 | |
| Topology Table register 0 | ||||
|---|---|---|---|---|
| Addr: |
000000001101091C (SCOM) 00000000134202E0 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.SNP.MISC.TOPOLOGY_TABLE0 | |||
| Constant(s): | ||||
| Comments: | Defines topology mapping for toplogy indexes 0 through 7 Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:39 | PAU3.CS.SM2.SNP.MISC.TOPOLOGY_TABLE0_Q_0_INST.LATC.L2(0:39) [0000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:7 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENABLE_0_7: Enable bit for entries 0 through 7 | |
| 8:11 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY0: Topology ID(0:3) for Topology Index 0 | |
| 12:15 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY1: Topology ID(0:3) for Topology Index 1 | |
| 16:19 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY2: Topology ID(0:3) for Topology Index 2 | |
| 20:23 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY3: Topology ID(0:3) for Topology Index 3 | |
| 24:27 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY4: Topology ID(0:3) for Topology Index 4 | |
| 28:31 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY5: Topology ID(0:3) for Topology Index 5 | |
| 32:35 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY6: Topology ID(0:3) for Topology Index 6 | |
| 36:39 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY7: Topology ID(0:3) for Topology Index 7 | |
| 40:63 | RO | RO | constant=0b000000000000000000000000 | |
| Topology Table register 1 | ||||
|---|---|---|---|---|
| Addr: |
000000001101091D (SCOM) 00000000134202E8 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.SNP.MISC.TOPOLOGY_TABLE1 | |||
| Constant(s): | ||||
| Comments: | Defines topology mapping for toplogy indexes 8 through 15 Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:39 | PAU3.CS.SM2.SNP.MISC.TOPOLOGY_TABLE1_Q_0_INST.LATC.L2(0:39) [0000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:7 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENABLE_8_15: Enable bit for entries 8 through 15 | |
| 8:11 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY8: Topology ID(0:3) for Topology Index 8 | |
| 12:15 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY9: Topology ID(0:3) for Topology Index 9 | |
| 16:19 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY10: Topology ID(0:3) for Topology Index 10 | |
| 20:23 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY11: Topology ID(0:3) for Topology Index 11 | |
| 24:27 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY12: Topology ID(0:3) for Topology Index 12 | |
| 28:31 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY13: Topology ID(0:3) for Topology Index 13 | |
| 32:35 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY14: Topology ID(0:3) for Topology Index 14 | |
| 36:39 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY15: Topology ID(0:3) for Topology Index 15 | |
| 40:63 | RO | RO | constant=0b000000000000000000000000 | |
| Topology Table register 2 | ||||
|---|---|---|---|---|
| Addr: |
000000001101091E (SCOM) 00000000134202F0 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.SNP.MISC.TOPOLOGY_TABLE2 | |||
| Constant(s): | ||||
| Comments: | Defines topology mapping for toplogy indexes 16 through 23 Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:39 | PAU3.CS.SM2.SNP.MISC.TOPOLOGY_TABLE2_Q_0_INST.LATC.L2(0:39) [0000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:7 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENABLE_16_23: Enable bit for entries 16 through 23 | |
| 8:11 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY16: Topology ID(0:3) for Topology Index 16 | |
| 12:15 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY17: Topology ID(0:3) for Topology Index 17 | |
| 16:19 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY18: Topology ID(0:3) for Topology Index 18 | |
| 20:23 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY19: Topology ID(0:3) for Topology Index 19 | |
| 24:27 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY20: Topology ID(0:3) for Topology Index 20 | |
| 28:31 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY21: Topology ID(0:3) for Topology Index 21 | |
| 32:35 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY22: Topology ID(0:3) for Topology Index 22 | |
| 36:39 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY23: Topology ID(0:3) for Topology Index 23 | |
| 40:63 | RO | RO | constant=0b000000000000000000000000 | |
| Topology Table register 3 | ||||
|---|---|---|---|---|
| Addr: |
000000001101091F (SCOM) 00000000134202F8 (PAU_RING) | |||
| Name: | PAU3.CS.SM2.SNP.MISC.TOPOLOGY_TABLE3 | |||
| Constant(s): | ||||
| Comments: | Defines topology mapping for toplogy indexes 24 through 31 Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:39 | PAU3.CS.SM2.SNP.MISC.TOPOLOGY_TABLE3_Q_0_INST.LATC.L2(0:39) [0000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:7 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENABLE_24_31: Enable bit for entries 24 through 31 | |
| 8:11 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY24: Topology ID(0:3) for Topology Index 24 | |
| 12:15 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY25: Topology ID(0:3) for Topology Index 25 | |
| 16:19 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY26: Topology ID(0:3) for Topology Index 26 | |
| 20:23 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY27: Topology ID(0:3) for Topology Index 27 | |
| 24:27 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY28: Topology ID(0:3) for Topology Index 28 | |
| 28:31 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY29: Topology ID(0:3) for Topology Index 29 | |
| 32:35 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY30: Topology ID(0:3) for Topology Index 30 | |
| 36:39 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY31: Topology ID(0:3) for Topology Index 31 | |
| 40:63 | RO | RO | constant=0b000000000000000000000000 | |
| CQ_SM Misc Config register #0 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010920 (SCOM) 0000000013430000 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.MCP.MISC.CONFIG0 | |||
| Constant(s): | ||||
| Comments: | Misc config register Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM3.MCP.MISC.CONFIG0_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_MA_DSA_OPT_CLAIM_UR: 0/1 = use Read.RWC/Upgrade.DN for dclaim/dcbz to GPU Mem | |
| 1 | RW | RW | CONFIG_MA_DSA_OPT_FLUSH_UR: 0/1 = use Read.RWC/Upgrade.DN for dcbf/dcbfc to GPU Mem | |
| 2 | RW | RW | CONFIG_MA_DSA_OPT_RP_MODE: 0/1 = use DMA/Read-Push for Write.NC to Proc Mem | |
| 3 | RW | RW | CONFIG_ADR_BAR_MODE: Reserved (was: PowerBus adr_bar: 0/1 = large-system-mode/small-system-mode) | |
| 4 | RW | RW | CONFIG_DISABLE_NN_RN: PowerBus scope: 0/1 = Enable Nn & Rn scopes / Disable Nn & Rn scopes | |
| 5 | RW | RW | CONFIG_DISABLE_VG_NOT_SYS: PowerBus scope: 0/1 = Enable Vg less than sys / Force all Vg to sys | |
| 6 | RW | RW | CONFIG_DISABLE_G: PowerBus scope: 0/1 = Enable G scope / Disable G scope | |
| 7 | RW | RW | CONFIG_DISABLE_LN: PowerBus scope: 0/1 = Enable Ln scope / Disable Ln scope | |
| 8 | RW | RW | CONFIG_SKIP_G: PowerBus scope: 0/1 = Allow G on rty_inc / Skip G on rty_inc | |
| 9 | RW | RW | CONFIG_MA_MCRESP_OPT_WRP: 0/1 = increase scope on rty_inc to dma_w / use write-read-push on rty_inc to dma_w | |
| 10 | RW | RW | CONFIG_USE_CL_DMA_W: 0/1 = Start cache-line DMA writes using cl_dma_inj / using cl_dma_w | |
| 11 | RW | RW | CONFIG_USE_DMA_PR_W: 0/1 = Start partial-line DMA writes using pr_dma_inj / using dma_pr_w | |
| 12:14 | RW | RW | CONFIG_INC_PRI_MASK: Mask select for priority increase due to rty_drp 0: 100% chance to increase priority 1: 50% chance to increase priority 2: 25% chance to increase priority 3: 12.5% chance to increase priority 4: 6% chance to increase priority 5: 3% chance to increase priority 6,7: 1.5% chance to increase priority | |
| 15 | RW | RW | CONFIG_MACH_CORRENAB: 0/1 = disable/enable state machine array ECC correction | |
| 16 | RW | RW | CONFIG_MACH_INJECT_ENABLE1: 0/1 = disable/enable state machine array ECC error inject bit 1 | |
| 17 | RW | RW | CONFIG_MACH_INJECT_ENABLE2: 0/1 = disable/enable state machine array ECC error inject bit 2 | |
| 18 | RW | RW | CONFIG_RXO_CORRENAB: 0/1 = disable/enable ReqRspOut array ECC correction | |
| 19 | RW | RW | CONFIG_RXO_INJECT_ENABLE1: 0/1 = disable/enable ReqRspOut array ECC error inject bit 1 | |
| 20 | RW | RW | CONFIG_RXO_INJECT_ENABLE2: 0/1 = disable/enable ReqRspOut array ECC error inject bit 2 | |
| 21 | RW | RW | CONFIG_RSI_CORRENAB: 0/1 = disable/enable PB-Rsp-In array ECC correction | |
| 22 | RW | RW | CONFIG_RSI_INJECT_ENABLE1: 0/1 = disable/enable PB-Rsp-In array ECC error inject bit 1 | |
| 23 | RW | RW | CONFIG_RSI_INJECT_ENABLE2: 0/1 = disable/enable PB-Rsp-In array ECC error inject bit 2 | |
| 24 | RW | RW | CONFIG_MA_DSA_OPT_DMA_UPG: 0/1 = non-relaxed dma_w use Read.RWC/Upgrade.DN to acquire pocket-cache state/data | |
| 25 | RW | RW | CONFIG_EVAPORATE_BY_LCO: 0/1 = just free the state-machine without lco/evaporate pocket-cache entries by lco | |
| 26 | RW | RW | CONFIG_ENABLE_PBUS: 0/1 = disable PAU PowerBus RCmd, PResp, and CResp interfaces / enable these interfaces Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 27 | RW | RW | CONFIG_ENABLE_SNARF_CPM: 0/1 = disable/enable Probe.I.MO snarfing a cp_m | |
| 28 | RW | RW | CONFIG_DISABLE_INJECT: 0/1 = enable sending cl,pr_dma_inj / disable sending cl,pr_dma_inj Note: to truly disable sending _inj commands, the following bits must also be set to '0': config_ma_dsa_opt_rp_mode | |
| 29 | RW | RW | CONFIG_DCACHE_MODE: 0/1 = drive data-bus dcache field in basic mode / CAPP mode. | |
| 30 | RW | RW | CONFIG_DCACHE_REPORTS_PHYSICAL: 0/1 = in basic mode, report local masters as near / local. | |
| 31 | RW | RW | CONFIG_RSI_DISABLE_DATIN_FASTPATH: 0/1 = enable rsi PB data-in fastpath/disable fastpath | |
| 32 | RW | RW | CONFIG_FORBID_MMIO_READ_GT_32: 0/1 = Allow GPU->PB MMIOs > 32-bytes / flag-error & brick-fence on MMIOs > 32-bytes | |
| 33 | RW | RW | CONFIG_FORBID_MMIO_ATOMIC: 0/1 = Allow GPU->PB atomics to MMIO space / flag-error & brick-fence on atomics to MMIO space | |
| 34 | RW | RW | CONFIG_DISABLE_HW555363_FASTPATH_AND_FENCE: 0/1 = enable HW555363 fix for fence happening between fastpath RCmd and CResp / disable fix. | |
| 35 | RW | RW | CONFIG0_RESERVED1: reserved | |
| 36 | RW | RW | CONFIG_ENABLE_CONTEXT_LCO: 0/1 = disable LCOing context entries into L3/enable LCOing context entries into L3 | |
| 37 | RW | RW | CONFIG_MA_DSA_OPT_FAIL_WAKE: 0/1 = send wake_host_thread to PB as asb_notify / fail all wake_host_thread w/ thread-not-found status (no PB asb_notify) | |
| 38 | RW | RW | CONFIG_ENABLE_FAST_DIR_UPDATE: 0/1 = disable directory fast update from mach pipe / enable directory fast update from mach pipe | |
| 39 | RW | RW | CONFIG_OPT_MES_USE_GO_M: 0/1 = read_mes w/ RW authority uses rd_go_s/rd_go_m to acquire the line | |
| 40 | RW | RW | CONFIG_OPT_LCO_M_USE_MU: 0/1 = use lco_m to inject a modified line into an L3 / use lco_mu | |
| 41 | RW | RW | CONFIG_OPT_SNOOP_EX_LCO: 0/1 = use cp_* when a castout.push(128B)->I is due to a snoop against an exclusive directory entry / use an lco_m,mu | |
| 42 | RW | RW | CONFIG_ENABLE_CP_ME: 0/1 = disable sending cp_me / enable cp_me when a cleaning E->I and homed off-node. | |
| 43 | RW | RW | CONFIG_FENCE_ON_DERR_MMIO: 0/1 = write SUE data to MMIO on data error from OCAPI / fence brick (note: dual NVF10/OCR7 error flagged) | |
| 44 | RW | RW | CONFIG_BRK0_OCAPI_MODE: 0/1 = Disable OpenCAPI mode / enable OpenCAPI mode for brick 0 (mutually exclusive with config_brk0_nvlink_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 45 | RW | RW | CONFIG_BRK1_OCAPI_MODE: 0/1 = Disable OpenCAPI mode / enable OpenCAPI mode for brick 1 (mutually exclusive with config_brk1_nvlink_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 46 | RW | RW | CONFIG_BRK2_OCAPI_MODE: 0/1 = Disable OpenCAPI mode / enable OpenCAPI mode for brick 2 (mutually exclusive with config_brk2_nvlink_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 47 | RW | RW | CONFIG_BRK3_OCAPI_MODE: 0/1 = Disable OpenCAPI mode / enable OpenCAPI mode for brick 3 (mutually exclusive with config_brk3_nvlink_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 48 | RW | RW | CONFIG_BRK4_OCAPI_MODE: 0/1 = Disable OpenCAPI mode / enable OpenCAPI mode for brick 4 (mutually exclusive with config_brk4_nvlink_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 49 | RW | RW | CONFIG_BRK0_NVLINK_MODE: 0/1 = Disable NVLink mode / enable NVLink mode for brick 0 (mutually exclusive with config_brk0_ocapi_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 50 | RW | RW | CONFIG_BRK1_NVLINK_MODE: 0/1 = Disable NVLink mode / enable NVLink mode for brick 1 (mutually exclusive with config_brk1_ocapi_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 51 | RW | RW | CONFIG_BRK2_NVLINK_MODE: 0/1 = Disable NVLink mode / enable NVLink mode for brick 2 (mutually exclusive with config_brk2_ocapi_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 52 | RW | RW | CONFIG_BRK3_NVLINK_MODE: 0/1 = Disable NVLink mode / enable NVLink mode for brick 3 (mutually exclusive with config_brk3_ocapi_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 53 | RW | RW | CONFIG_BRK4_NVLINK_MODE: 0/1 = Disable NVLink mode / enable NVLink mode for brick 4 (mutually exclusive with config_brk4_ocapi_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 54 | RW | RW | CONFIG_BRK0_POISON_FENCE_L2: 0/1 = write all-ones-good-ECC/all-ones-SUE to E/Ei/M L2 directory entries when brick 0 is fenced Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 55 | RW | RW | CONFIG_BRK1_POISON_FENCE_L2: 0/1 = write all-ones-good-ECC/all-ones-SUE to E/Ei/M L2 directory entries when brick 0 is fenced Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 56:58 | RW | RW | CONFIG0_RESERVED0: reserved | |
| 59 | RW | RW | CONFIG_BRK0_IMP_TAGS_MODE_ENABLE: 0/1 = disable IMP (HAPPI) iseries tags mode / enable tags mode for brick 0 Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 60 | RW | RW | CONFIG_BRK1_IMP_TAGS_MODE_ENABLE: 0/1 = disable IMP (HAPPI) iseries tags mode / enable tags mode for brick 1 Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 61 | RW | RW | CONFIG_BRK2_IMP_TAGS_MODE_ENABLE: 0/1 = disable IMP (HAPPI) iseries tags mode / enable tags mode for brick 2 Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 62 | RW | RW | CONFIG_BRK3_IMP_TAGS_MODE_ENABLE: 0/1 = disable IMP (HAPPI) iseries tags mode / enable tags mode for brick 3 Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 63 | RW | RW | CONFIG_BRK4_IMP_TAGS_MODE_ENABLE: 0/1 = disable IMP (HAPPI) iseries tags mode / enable tags mode for brick 4 Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| CQ_SM Misc Config register #1 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010921 (SCOM) 0000000013430008 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.MCP.MISC.CONFIG1 | |||
| Constant(s): | ||||
| Comments: | Misc config register Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM3.MCP.MISC.CONFIG1_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:3 | RW | RW | CONFIG_RANDOM_BACKOFF_DUR_MASK: Mask for the base random duration of a random retry backoff 0000 -> 0-15 base random duration 0001 -> 0-31 base random duration 0011 -> 0-63 base random duration 0111 -> 0-127 base random duration 1111 -> 0-255 base random duration | |
| 4:7 | RW | RW | CONFIG_CHGRATE_HANG_SLOWDOWN_REQ: Mask for for the slowdown of NTL CReq or OCAPI TLX.vc.3 credits during chgrate.hang 'n' -> 1/(2^(n+1)) cycles average rate Note that for a single PowerBus ramp, the rate is actually 8 times faster since there are 4 RCmd slice x 2 NTL Bricks that get CReq credits. This field is the rate for 1 brick receiving credit from 1 RCmd slice. | |
| 8:11 | RW | RW | CONFIG_CHGRATE_HANG_SLOWDOWN_CST: Mask for for the slowdown of OCAPI TLX.vc.2 credits during chgrate.hang 'n' -> 1/(2^(n+1)) cycles average rate Note that for a single PowerBus ramp, the rate is actually 8 times faster since there are 4 RCmd slice x 2 NTL Bricks that get CReq credits. This field is the rate for 1 brick receiving credit from 1 RCmd slice. | |
| 12:15 | RW | RW | CONFIG_CHGRATE_HANG_SLOWDOWN_PRB: Mask for for the slowdown of NTL Probe or OCAPI TLX.vc.1 credits during chgrate.hang 'n' -> 1/(2^(n+1)) cycles average rate Note that for a single PowerBus ramp, the rate is actually 8 times faster since there are 4 RCmd slice x 2 NTL Bricks that get CReq credits. This field is the rate for 1 brick receiving credit from 1 RCmd slice. | |
| 16:27 | RW | RW | CONFIG_EPSILON_WLN_COUNT: epsilon count for Ln scope CP-Write | |
| 28 | RW | RW | CONFIG_MIMIRROR_MASTER_ENABLE: 0/1 = disable MI mirroring support / enable MI mirroring | |
| 29:31 | RW | RW | CONFIG_MIMIRROR_BRICK_MODE: Primary & Secondary bricks are: 000 = Primary is brick 0, brick 1 not used 001 = Primary is brick 1, brick 0 not used 010 = Primary is brick 0, stores mirror to brick 1 011 = Primary is brick 1, stores mirror to brick 0 100 = Primary is brick 0, stores mirror to brick 1, loads can failover to brick 1 101 = Primary is brick 1, stores mirror to brick 0, loads can failover to brick 0 110 = Primary brick is addr(54), stores mirror to both bricks, loads can failover to the other brick 111 = Primary brick is random, stores mirror to both bricks, loads can failover to the other brick | |
| 32 | RW | RW | CONFIG_MIMIRROR_FENCE_ON_BAD_DATA: 0/1 = don't force fence for bad_data responses / force fence when bad_data arrives in a response. | |
| 33:34 | RW | RW | CONFIG1_RESERVED2: reserved | |
| 35 | RW | RW | CONFIG_PCKT_LONG_CL_DMA_INJ: 0/1 = allow cl_dma_inj to use short pocket-cache timer/ force cl_dma_inj to use long pocket-cache timer | |
| 36 | RW | RW | CONFIG_PCKT_LONG_PR_DMA_INJ: 0/1 = allow pr_dma_inj to use short pocket-cache timer/ force pr_dma_inj to use long pocket-cache timer | |
| 37:42 | RW | RW | CONFIG_PCKT_LONG_MIN_COUNT: Minimum number of state-machine w/ long pocket-cache timers before short timers can be used | |
| 43 | RW | RW | CONFIG_PCKT_LONG_USES_HANG: 0/1 = use config_pocket_long_rate2 / use rpt_hang.poll ticks to drive long pocket-cache timer | |
| 44 | RW | RW | CONFIG_DONT_RETRY_LCO_LONG: reserved (was config_dont_retry_lco_long) | |
| 45 | RW | RW | CONFIG_DONT_RETRY_LCO_LONG_STRESSED: reserved (was config_dont_retry_lco_long_stressed). | |
| 46 | RW | RW | CONFIG_DONT_RETRY_LCO_SHORT: reserved (was config_dont_retry_lco_short) | |
| 47 | RW | RW | CONFIG_DONT_RETRY_LCO_SHORT_STRESSED: reserved (was config_dont_retry_lco_short_stressed). | |
| 48 | RW | RW | CONFIG_STOP_ASB_AT_LN_SCOPE: 0/1 = increase to asb_notify to G scope / stop and return thread-not-found when asb_notify @ Ln scope doesn't find the thread | |
| 49 | RW | RW | CONFIG_STOP_ASB_AT_G_SCOPE: 0/1 = increase to asb_notify to Vg(sys) scope / stop and return thread-not-found when asb_notify @ G scope doesn't find the thread | |
| 50 | RW | RW | CONFIG_INITIAL_HPC_PROBE_PRIORITY: Initial drop_priority value when mastering an hpc_probe | |
| 51 | RW | RW | CONFIG_NVLINK_P10P10_MODE: 0/1 = normal NVLink mode / special lab-debug-only P10-to-P10 NVLink mode | |
| 52 | RW | RW | CONFIG_HANG_ON_ADDRESS_ERRORS: 0/1 = abort and continue on CResp=addr_error / hang state-machine on CResp=addr_error | |
| 53 | RW | RW | CONFIG_DISABLE_HW525464_CLEAN_XUE_FENCE_PB: 0/1 = enable HW525464 fix for cleaning XUE data on fence of pb cmd / disable fix. | |
| 54 | RW | RW | CONFIG_DISABLE_HW517903_BAD_SYNC: 0/1 = handle bad sync in non-4.0 mode / disable fix. | |
| 55 | RW | RW | CONFIG_DISABLE_HW526620_BAD_SYN_DONE: 0/1 = handle mis-aligned synonym_done / disable fix. | |
| 56 | RW | RW | CONFIG_ENABLE_OPENCAPI_NETWORKING: 0/1 = disable networking / enable OpenCAPI MI networking mode. | |
| 57 | RW | RW | CONFIG_NET0_TORUS_MODE: 0/1 = Dragonfly network mode / Torus network mode for brick 0 | |
| 58 | RW | RW | CONFIG_NET1_TORUS_MODE: 0/1 = Dragonfly network mode / Torus network mode for brick 1 | |
| 59 | RW | RW | CONFIG_DISABLE_HW532477_ARMWF_IMP_TAGS_RESET: 0/1 = Enable resetting itags after transmitting armwf data / disable fix | |
| 60 | RW | RW | CONFIG_DISABLE_HW536051_FENCE_HOSPICE_PRONOTE: 0/1 = Enable an extra dirscan before waiting for REQ to drain / disable fix | |
| 61 | RW | RW | CONFIG_DISABLE_HW537584_HOSPICE_QUALIFIER: 0/1 = Enable correctly qualifying hp_vec_empty with dir_allocated to indicate hospice / disable fix | |
| 62 | RW | RW | CONFIG_DISABLE_HW546460_INC_DEC_ALL_ONES: 0/1 = Enable IM-network brick4-fence causing inc/dec atomics to return all ones / disable fix | |
| 63 | RW | RW | CONFIG_ENABLE_HW555343_ALL_PTL_ARE_BE: 0/1 = disable HW555343 fix / enable fix to convert all partial writes to byte-enable writes. | |
| PowerBus Epsilon | ||||
|---|---|---|---|---|
| Addr: |
0000000011010922 (SCOM) 0000000013430010 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.MCP.MISC.EPSILON_CONFIG | |||
| Constant(s): | ||||
| Comments: | PowerBus Epsilon config register Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM3.MCP.MISC.EPSILON_CONFIG_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:3 | RW | RW | CONFIG_EPSILON_RATE: 0 = decrement epsilon count at 1:1 pau_clock_1to1 ... 15 = epsilon count at 1/16 pau_clock_1to1 | |
| 4:15 | RW | RW | CONFIG_EPSILON_W0_COUNT: epsilon count for Nn/G scope CP-Write | |
| 16:27 | RW | RW | CONFIG_EPSILON_W1_COUNT: epsilon count for Rn/Vg scope CP-Write | |
| 28:39 | RW | RW | CONFIG_EPSILON_R0_COUNT: epsilon count for Ln scope Reads | |
| 40:51 | RW | RW | CONFIG_EPSILON_R1_COUNT: epsilon count for Nn/G scope Reads | |
| 52:63 | RW | RW | CONFIG_EPSILON_R2_COUNT: epsilon count for Rn/Vg scope Reads | |
| Timer Config Reg | ||||
|---|---|---|---|---|
| Addr: |
0000000011010923 (SCOM) 0000000013430018 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.MCP.MISC.XTIMER_CONFIG | |||
| Constant(s): | ||||
| Comments: | Timer Configuration Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:59 | PAU3.CS.SM3.MCP.MISC.XTIMER_CONFIG_Q_0_INST.LATC.L2(0:59) [000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:1 | RW | RW | CONFIG_POCKET_LONG_RATE1: Rate_1 for the Long Pocket-Cache timer. The Pocket-Cache timer is used to evaporate pocket-cache entries which are not claimed. The Long timer duration is f(Rate_1)*2^(Rate_2)*5e-10 seconds Unless config_pckt_long_uses_hang=1, then it is f(Rate1)*rpt_hang.poll interval. f(0b00) = 2 f(0b01) = 3 f(0b10) = 4 f(0b11) = 5 | |
| 2:7 | RW | RW | CONFIG_POCKET_LONG_RATE2: Rate_2 for the long timer for Pocket-Cache entries (2^n cycles). | |
| 8:13 | RW | RW | CONFIG_POCKET_SHORT_RATE2: Rate_2 for the short timer for Pocket-Cache entries (2^n cycles). | |
| 14:19 | RW | RW | CONFIG_FWD_PROG_RATE2: Rate_2 for the forward-progress timer (2^n cycles). | |
| 20:25 | RW | RW | CONFIG_XTIMER_RESERVED1: Reserved (was: Rate for CTL timer tick (default 63 = off)) | |
| 26:31 | RW | RW | CONFIG_INH0_TICK: Rate for SM-Inhibit timer tick0 (default 63 = off) Note: This field can/should have different values in each instance. No MDials have been created for this field's IDials | |
| 32:37 | RW | RW | CONFIG_INH1_TICK: Rate for SM-Inhibit timer tick1 (default 63 = off) Note: This field can/should have different values in each instance. No MDials have been created for this field's IDials | |
| 38:39 | RW | RW | CONFIG_NV_RESP_RATE1: Reserved (was: Rate_1 for NV-Response timer) | |
| 40:45 | RW | RW | CONFIG_NV_RESP_RATE2: Rate_2 for the NV-Response timer (2^n cycles). Overall timeout is (3 to 4)*(2^Rate_2)*5e-10 seconds. | |
| 46:47 | RW | RW | CONFIG_POCKET_SHORT_RATE1: Rate_1 for the Short Pocket-Cache timer. The Pocket-Cache timer is used to evaporate pocket-cache entries which are not claimed. the Short timer duration is f(Rate_1)*2^(Rate_2)*5e-10 seconds where f(Rate_1) is: f(0b00) = 7 f(0b01) = 63 f(0b10) = 511 f(0b11) = 4095 | |
| 48:53 | RW | RW | CONFIG_SCAN_WAIT_RATE: Rate for directory-scanning wait-walker 2^Rate cycles per tick | |
| 54:59 | RW | RW | CONFIG_EPOCH_RATE: Rate for epoch-checks Overall timeout is (2 to 3)*(2^Rate)*5e-10 seconds. | |
| 60:63 | RO | RO | constant=0b0000 | |
| Perf Config Reg | ||||
|---|---|---|---|---|
| Addr: |
0000000011010924 (SCOM) 0000000013430020 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.MCP.MISC.PERF_CONFIG | |||
| Constant(s): | ||||
| Comments: | Performance Event selection | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM3.MCP.MISC.PERF_CONFIG_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:8 | RW | RW | PERF_CONFIG_LATSTART: Latency count start event | |
| 9:17 | RW | RW | PERF_CONFIG_LATCANCEL: Latency count abort event | |
| 18:26 | RW | RW | PERF_CONFIG_LATFINISH: Latency count finish event | |
| 27 | RW | RW | PERF_CONFIG_RESERVED1: reserved | |
| 28:35 | RW | RW | PERF_CONFIG_EVENT0: Event 0 select 0: count nothing 1: count cycles 2: count latency events (see latstart/cancel/finish fields) 3: count latency cycles (avg latency = cycles divided by events) 4: count latency aborts (start condition was detected, but finish condition was not) 5: count # Same-address checks detected a collision 6: count # Same-address checks detected no collision 7: count # CResps matching cresp + original command 8: count # of PB Cmds sent w/ matching scope 9: count # CResps matching cresp + scope + master command + original command 10: count # of PB Cmds sent w/ matching scope+command 11: count # of NV/OC Cmds sent w/ matching command 12: count # of NV/OC Resps sent w/ matching response(command) 13: count # of force_evicts sent due to dir-scan / XSL-castouts 14: count # of force_evicts sent due to sfe / PowerBus RCmd snoops 15: count # of force_evicts sent due to the other brick having state (needed by the requesting brick) 16: count # of force_evicts / EF responses sent due to capacity evicts in the L2 directory 17: count # of allocating C2 commands that update state in an existing directory entry (ie cacheline was alreayd present) 18: count # of allocating C2 commands that update state in a new directory entry (ie cacheline was not present in the directory) others: reserved (count nothing) | |
| 36:43 | RW | RW | PERF_CONFIG_EVENT1: Event 1 select See Event 0 select for encodes | |
| 44:51 | RW | RW | PERF_CONFIG_EVENT2: Event 2 select See Event 0 select for encodes | |
| 52:59 | RW | RW | PERF_CONFIG_EVENT3: Event 3 select See Event 0 select for encodes | |
| 60:61 | RW | RW | PERF_CONFIG_RESERVED2: reserved | |
| 62 | RW | RW | PERF_CONFIG_LATFILTER: 0/1 = count max latency events / filter latency events by 1/1024 for bias reduction | |
| 63 | RW | RW | PERF_CONFIG_ACT: Enable clock-gates for performance monitor latches | |
| Inhibit configuration Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010925 (SCOM) 0000000013430028 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.MCP.MISC.INHIBIT_CONFIG | |||
| Constant(s): | ||||
| Comments: | Configures Inhibits for CQ_SM | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM3.MCP.MISC.INHIBIT_CONFIG_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:3 | RW | RW | CONFIG_INHIBIT_LFREQ0: Base LFSR frequency 0: 0..11 = 1/2^(n+1) 12 = 1/2^14 13 = 1/2^16 14 = 1/2^18 15 = 1/2^20 | |
| 4:5 | RW | RW | CONFIG_INHIBIT_PFREQ0: Selects pre frequency 0: 0 = Inhibit timer tick0 1 = inverted Inhibit timer tick0 2 = LFSR 3 = inverted LFSR (-> 1/2, 3/4, 7/8, ...) | |
| 6 | RW | RW | CONFIG_INHIBIT_BLOCKY0: 0/1 = disable blocky mode / enable blocky mode | |
| 7 | RW | RW | CONFIG_INHIBIT_ONESHOT0: 0/1 = continus mode / one-shot mode | |
| 8:15 | RW | RW | CONFIG_INHIBIT_DEST0: Selects the destination of the inhibit | |
| 16:19 | RW | RW | CONFIG_INHIBIT_LFREQ1: Base LFSR frequency 0: 0..12 = 1/2^(n+1) 13 = 1/2^16 14 = 1/2^18 15 = 1/2^20 | |
| 20:21 | RW | RW | CONFIG_INHIBIT_PFREQ1: Selects pre frequency 0: 0 = Inhibit timer tick1 1 = inverted Inhibit timer tick1 2 = LFSR 3 = inverted LFSR (-> 1/2, 3/4, 7/8, ...) | |
| 22 | RW | RW | CONFIG_INHIBIT_BLOCKY1: 0/1 = disable blocky mode / enable blocky mode | |
| 23 | RW | RW | CONFIG_INHIBIT_ONESHOT1: 0/1 = continus mode / one-shot mode | |
| 24:31 | RW | RW | CONFIG_INHIBIT_DEST1: Selects the destination of the inhibit | |
| 32:35 | RW | RW | CONFIG_INHIBIT_LFREQ2: Base LFSR frequency 2: 0..11 = 1/2^(n+1) 12 = 1/2^14 13 = 1/2^16 14 = 1/2^18 15 = 1/2^20 | |
| 36:37 | RW | RW | CONFIG_INHIBIT_PFREQ2: Selects pre frequency 2: 0 = Inhibit timer tick0 1 = inverted Inhibit timer tick0 2 = LFSR 3 = inverted LFSR (-> 1/2, 3/4, 7/8, ...) | |
| 38 | RW | RW | CONFIG_INHIBIT_BLOCKY2: 0/1 = disable blocky mode / enable blocky mode | |
| 39 | RW | RW | CONFIG_INHIBIT_ONESHOT2: 0/1 = continus mode / one-shot mode | |
| 40:47 | RW | RW | CONFIG_INHIBIT_DEST2: Selects the destination of the inhibit | |
| 48:51 | RW | RW | CONFIG_INHIBIT_LFREQ3: Base LFSR frequency 3: 0..12 = 1/2^(n+1) 13 = 1/2^16 14 = 1/2^18 15 = 1/2^20 | |
| 52:53 | RW | RW | CONFIG_INHIBIT_PFREQ3: Selects pre frequency 3: 0 = Inhibit timer tick1 1 = inverted Inhibit timer tick1 2 = LFSR 3 = inverted LFSR (-> 1/2, 3/4, 7/8, ...) | |
| 54 | RW | RW | CONFIG_INHIBIT_BLOCKY3: 0/1 = disable blocky mode / enable blocky mode | |
| 55 | RW | RW | CONFIG_INHIBIT_ONESHOT3: 0/1 = continus mode / one-shot mode | |
| 56:63 | RW | RW | CONFIG_INHIBIT_DEST3: Selects the destination of the inhibit | |
| c_err_rpt Message-0 latches | ||||
|---|---|---|---|---|
| Addr: |
0000000011010926 (SCOM) 0000000013430030 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.MCP.MISC.CERR_MESSAGE0 | |||
| Constant(s): | ||||
| Comments: | Error message/capture register 0 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM3.MCP.MISC.CERR_MESSAGE0_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:63 | RWX_WCLRREG | RWX_WCLRREG | CERR_MESSAGE_BITS0: reserved | |
| c_err_rpt Message-1 latches | ||||
|---|---|---|---|---|
| Addr: |
0000000011010927 (SCOM) 0000000013430038 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.MCP.MISC.CERR_MESSAGE1 | |||
| Constant(s): | ||||
| Comments: | Error message/capture register 1 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM3.MCP.MISC.CERR_MESSAGE1_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:63 | RWX_WCLRREG | RWX_WCLRREG | CERR_MESSAGE_BITS1: reserved | |
| c_err_rpt Message-2 latches | ||||
|---|---|---|---|---|
| Addr: |
0000000011010928 (SCOM) 0000000013430040 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.MCP.MISC.CERR_MESSAGE2 | |||
| Constant(s): | ||||
| Comments: | Error message/capture register 2 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM3.MCP.MISC.CERR_MESSAGE2_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:63 | RWX_WCLRREG | RWX_WCLRREG | CERR_MESSAGE_BITS2: reserved | |
| c_err_rpt Message-3 latches | ||||
|---|---|---|---|---|
| Addr: |
0000000011010929 (SCOM) 0000000013430048 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.MCP.MISC.CERR_MESSAGE3 | |||
| Constant(s): | ||||
| Comments: | Error message/capture register 3 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM3.MCP.MISC.CERR_MESSAGE3_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:63 | RWX_WCLRREG | RWX_WCLRREG | CERR_MESSAGE_BITS3: reserved | |
| c_err_rpt Message-4 latches | ||||
|---|---|---|---|---|
| Addr: |
000000001101092A (SCOM) 0000000013430050 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.MCP.MISC.CERR_MESSAGE4 | |||
| Constant(s): | ||||
| Comments: | Error message/capture register 4 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM3.MCP.MISC.CERR_MESSAGE4_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:63 | RWX_WCLRREG | RWX_WCLRREG | CERR_MESSAGE_BITS4: reserved | |
| c_err_rpt Message-5 latches | ||||
|---|---|---|---|---|
| Addr: |
000000001101092B (SCOM) 0000000013430058 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.MCP.MISC.CERR_MESSAGE5 | |||
| Constant(s): | ||||
| Comments: | Error message/capture register 5 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM3.MCP.MISC.CERR_MESSAGE5_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:63 | RWX_WCLRREG | RWX_WCLRREG | CERR_MESSAGE_BITS5: reserved | |
| c_err_rpt Message-6 latches | ||||
|---|---|---|---|---|
| Addr: |
000000001101092C (SCOM) 0000000013430060 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.MCP.MISC.CERR_MESSAGE6 | |||
| Constant(s): | ||||
| Comments: | Error message/capture register 6 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM3.MCP.MISC.CERR_MESSAGE6_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:63 | RWX_WCLRREG | RWX_WCLRREG | CERR_MESSAGE_BITS6: reserved | |
| c_err_rpt Message-7 latches | ||||
|---|---|---|---|---|
| Addr: |
000000001101092D (SCOM) 0000000013430068 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.MCP.MISC.CERR_MESSAGE7 | |||
| Constant(s): | ||||
| Comments: | Error message/capture register 7 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:39 | PAU3.CS.SM3.MCP.MISC.CERR_MESSAGE7_Q_0_INST.LATC.L2(0:39) [0000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:39 | RWX_WCLRREG | RWX_WCLRREG | CERR_MESSAGE_BITS7: reserved | |
| 40:63 | RO | RO | constant=0b000000000000000000000000 | |
| CQ_SM status register | ||||
|---|---|---|---|---|
| Addr: |
000000001101092E (SCOM) 0000000013430070 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.MCP.MISC.SM_STATUS | |||
| Constant(s): | ||||
| Comments: | Status reporting register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM3.MCP.MISC.SM_STATUS_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:3 | ROX | ROX | SM_STATUS_MRBGP: Master-Retry backoff level for Group-Pump commands | |
| 4:7 | ROX | ROX | SM_STATUS_MRBSP: Master-Retry backoff level for System-Pump commands | |
| 8:11 | ROX | ROX | SM_STATUS_FENCE0: Brick-0 Fence sequencing state 0b0000 = Idle state, completely unfenced 0b0--- = in transition between fenced and not-fenced 0b10-- = in transition between fenced and not-fenced 0b1100 = Fenced state, fence sequencing complete 0b1101 = Flushing pocket-cache entries prior to exiting fence 0b1110 = Flushing pocket-cache entries prior to exiting fence 0b1111 = reserved | |
| 12:15 | ROX | ROX | SM_STATUS_FENCE1: Brick-1 Fence sequencing state 0b0000 = Idle state, completely unfenced 0b0--- = in transition between fenced and not-fenced 0b10-- = in transition between fenced and not-fenced 0b1100 = Fenced state, fence sequencing complete 0b1101 = Flushing pocket-cache entries prior to exiting fence 0b1110 = Flushing pocket-cache entries prior to exiting fence 0b1111 = reserved | |
| 16:19 | ROX | ROX | SM_STATUS_FENCE2: Brick-2 Fence sequencing state 0b0000 = Idle state, completely unfenced 0b0--- = in transition between fenced and not-fenced 0b10-- = in transition between fenced and not-fenced 0b1100 = Fenced state, fence sequencing complete 0b1101 = Flushing pocket-cache entries prior to exiting fence 0b1110 = Flushing pocket-cache entries prior to exiting fence 0b1111 = reserved | |
| 20:23 | ROX | ROX | SM_STATUS_FENCE3: Brick-3 Fence sequencing state 0b0000 = Idle state, completely unfenced 0b0--- = in transition between fenced and not-fenced 0b10-- = in transition between fenced and not-fenced 0b1100 = Fenced state, fence sequencing complete 0b1101 = Flushing pocket-cache entries prior to exiting fence 0b1110 = Flushing pocket-cache entries prior to exiting fence 0b1111 = reserved | |
| 24:27 | ROX | ROX | SM_STATUS_FENCE4: Brick-4 Fence sequencing state 0b0000 = Idle state, completely unfenced 0b0--- = in transition between fenced and not-fenced 0b10-- = in transition between fenced and not-fenced 0b1100 = Fenced state, fence sequencing complete 0b1101 = Flushing pocket-cache entries prior to exiting fence 0b1110 = Flushing pocket-cache entries prior to exiting fence 0b1111 = reserved | |
| 28 | ROX | ROX | SM_STATUS_PBLN: 1 when outbound Ln-scope PowerBus request queue is empty | |
| 29 | ROX | ROX | SM_STATUS_PBNNG: 1 when outbound Nn/G-scope PowerBus request queue is empty | |
| 30 | ROX | ROX | SM_STATUS_PBRNVG: 1 when outbound Rn/Vg-scope PowerBus request queue is empty | |
| 31 | ROX | ROX | SM_STATUS_B0REQ: 1 when outbound brick 0 CReq request queue is empty | |
| 32 | ROX | ROX | SM_STATUS_B0DGD: 1 when outbound brick 0 Downgrade request queue is empty | |
| 33 | ROX | ROX | SM_STATUS_B1REQ: 1 when outbound brick 1 CReq request queue is empty | |
| 34 | ROX | ROX | SM_STATUS_B1DGD: 1 when outbound brick 1 Downgrade request queue is empty | |
| 35 | ROX | ROX | SM_STATUS_B2REQ: 1 when outbound brick 2 CReq request queue is empty | |
| 36 | ROX | ROX | SM_STATUS_B2DGD: 1 when outbound brick 2 Downgrade request queue is empty | |
| 37 | ROX | ROX | SM_STATUS_B3REQ: 1 when outbound brick 3 CReq request queue is empty | |
| 38 | ROX | ROX | SM_STATUS_B3DGD: 1 when outbound brick 3 Downgrade request queue is empty | |
| 39 | ROX | ROX | SM_STATUS_B4REQ: 1 when outbound brick 4 CReq request queue is empty | |
| 40 | ROX | ROX | SM_STATUS_B4DGD: 1 when outbound brick 4 Downgrade request queue is empty | |
| 41 | ROX | ROX | SM_STATUS_MMIO: 1 when outbound MMIO/GenId request queue is empty | |
| 42 | ROX | ROX | SM_STATUS_MMIOSUE: 1 when outbound MMIO-SUE request queue is empty | |
| 43 | ROX | ROX | SM_STATUS_ATSXLATE: 1 when outbound ATS-TCE-Translation request queue is empty | |
| 44 | ROX | ROX | SM_STATUS_REPLAY: 1 when outbound replay-to-directory queue is empty | |
| 45 | ROX | ROX | SM_STATUS_PBRSP: 1 when outbound PowerBus data-response/merge-operation queue is empty | |
| 46 | ROX | ROX | SM_STATUS_B0RSP: 1 when outbound brick 0 response queue is empty | |
| 47 | ROX | ROX | SM_STATUS_B1RSP: 1 when outbound brick 1 response queue is empty | |
| 48 | ROX | ROX | SM_STATUS_B2RSP: 1 when outbound brick 2 response queue is empty | |
| 49 | ROX | ROX | SM_STATUS_B3RSP: 1 when outbound brick 3 response queue is empty | |
| 50 | ROX | ROX | SM_STATUS_B4RSP: 1 when outbound brick 4 response queue is empty | |
| 51 | ROX | ROX | SM_STATUS_XARSP: 1 when outbound ATS/MISC response queue is empty | |
| 52 | ROX | ROX | SM_STATUS_FREE: 1 when Free state machine queue is empty | |
| 53 | ROX | ROX | SM_STATUS_DIRUPD: 1 when Directory-Update queue is empty | |
| 54 | ROX | ROX | SM_STATUS_SACOLL: 1 when Same-Address Collision-Check queue is empty | |
| 55:58 | ROX | ROX | SM_STATUS_MRBCP: Master-Retry backoff level for Chip-Pump commands | |
| 59:60 | ROX | ROX | SM_STATUS_PERF_LSTATE: Performance-counter Latency state | |
| 61:63 | ROX | ROX | SM_STATUS_RESERVED2: reserved | |
| c_err_rpt first-0 latches | ||||
|---|---|---|---|---|
| Addr: |
000000001101092F (SCOM) 0000000013430078 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.MCP.MISC.CERR_FIRST0 | |||
| Constant(s): | ||||
| Comments: | c_err_rpt first latches read-write-1-clear reg | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:55 | PAU3.CS.SM3.MCP.MISC.CERR_FIRST0_Q_0_INST.LATC.L2(0:55) [00000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_0: NVF0 s4: NVLink UT=0 to MMIO space bad cmd/length/alignment | |
| 1 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_1: NVF1 s4: UT=1 to MMIO space bad cmd/length/alignment | |
| 2 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_2: NVF2 s4: Target-Error/Unsupported-Request/Reserved Rsp_Status received in NVLink Response | |
| 3 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_3: NVF3 s4: Unexpected NVLink/OCAPI Response | |
| 4 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_4: NVF4 s4: Bad NV or OC response received (fence brick) | |
| 5 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_5: NVF5 s7: MCP_M_EVAL_DSA: illegal castout/.push arrives vs L2 directory state | |
| 6 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_6: NVF6 s4: Target-Error/Unsupported-Request/Reserved Rsp_Status received in NVLink Trans-Done Response | |
| 7 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_7: NVF7 s4: NVLink or OCAPI response timeout | |
| 8 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_8: NVF8 s4: Bad synonym_done received | |
| 9 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_9: NVF9 s4: OCAPI request to MMIO space bad cmd/length/alignment | |
| 10 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_10: NVF10 s4: DMA write/atomic to MMIO space w/ Data error | |
| 11 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_11: NVF11 s7: MCP_M_EVAL_DSA: Topology-index of the Request address is not valid in the topology-index table | |
| 12 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_12: NVF12 s7: MCP_M_EVAL_DSA: addr_error CResp to posted request | |
| 13 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_13: NVF13 (reserved) | |
| 14 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_14: NVF14 (reserved) | |
| 15 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_15: NVF15 NVLink NVF error for brick 0 occurred | |
| 16 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_16: NVF16 NVLink NVF error for brick 1 occurred | |
| 17 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_17: NVF17 NVLink NVF error for brick 2 occurred | |
| 18 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_18: NVF18 NVLink NVF error for brick 3 occurred | |
| 19 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NVF_19: NVF19 NVLink NVF error for brick 4 occurred | |
| 20 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_ASBE_0: ASBE0 SBE ECC error detected from State-machine array | |
| 21 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_ASBE_1: ASBE1 SBE ECC error detected from Rq/Rs output queue array | |
| 22 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_ASBE_2: ASBE2 SBE ECC error detected from PowerBus data flit combiner array | |
| 23 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_ASBE_3: ASBE3 (reserved) | |
| 24 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_ASBE_4: ASBE4 SBE ECC error detected from L2-Directory SRAM 0 | |
| 25 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_ASBE_5: ASBE5 SBE ECC error detected from L2-Directory SRAM 1 | |
| 26 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_ASBE_6: ASBE6 SBE ECC error detected from L2-Directory SRAM 2 | |
| 27 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_ASBE_7: ASBE7 SBE ECC error detected from L2-Directory SRAM 3 | |
| 28 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBR_0: PBR0 s4: MCP_PC_WT_CRESP: abort_trm(_ed) cresp received to PAU request | |
| 29 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBR_1: PBR1 s4: MCP_PC_BK_WT_CRESP: abort_trm cresp received to PAU BKill request | |
| 30 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBR_2: PBR2 s4: Mis-aligned dma_pr_w/pr_dma_inj to AFU-MMIO space | |
| 31 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBR_3: PBR3 s4: rpt_hang.poll signalled hang condition | |
| 32 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBR_4: PBR4 s4: MCP_PC_WT_CRESP: Addr_Error received for self-lpc command (SSF) | |
| 33 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBR_5: PBR5 (reserved) | |
| 34 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBR_6: PBR6 (reserved) | |
| 35 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBR_7: PBR7 (reserved) | |
| 36 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_REG_0: REG0 s4: Address/Length/Alignment error on MMIO/GenId/Config access | |
| 37 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_REG_1: REG1 (reserved) | |
| 38 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_REG_2: REG2 (reserved) | |
| 39 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_REG_3: REG3 (reserved) | |
| 40 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_OCR_0: OCR0 s4: UT=0 to MMIO space bad cmd/length/alignment | |
| 41 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_OCR_1: OCR1 s4: Bad OC response received | |
| 42 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_OCR_2: OCR2 s4: AFU request w/ bad data received | |
| 43 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_OCR_3: OCR3 s4: Intrp_Req ObjHandle did not map to MMIO space | |
| 44 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_OCR_4: OCR4 s4: NVLink UT=0 to MMIO space bad cmd/length/alignment | |
| 45 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_OCR_5: OCR5 s4: UT=1 to MMIO space bad cmd/length/alignment | |
| 46 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_OCR_6: OCR6 s4: OCAPI request to MMIO space bad cmd/length/alignment | |
| 47 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_OCR_7: OCR7 s4: DMA write/atomic to MMIO space w/ Data error | |
| 48 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_OCR_8: OCR8 Epoch scanning did not complete before the next tick | |
| 49 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_OCR_9: OCR9 (reserved) | |
| 50 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_OCR_10: OCR10 (reserved) | |
| 51 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_OCR_11: OCR11 NVLink OCR error for brick 0 occurred | |
| 52 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_OCR_12: OCR12 NVLink OCR error for brick 1 occurred | |
| 53 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_OCR_13: OCR13 NVLink OCR error for brick 2 occurred | |
| 54 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_OCR_14: OCR14 NVLink OCR error for brick 3 occurred | |
| 55 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_OCR_15: OCR15 NVLink OCR error for brick 4 occurred | |
| 56:63 | RO | RO | constant=0b00000000 | |
| c_err_rpt first-1 latches | ||||
|---|---|---|---|---|
| Addr: |
0000000011010930 (SCOM) 0000000013430080 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.MCP.MISC.CERR_FIRST1 | |||
| Constant(s): | ||||
| Comments: | c_err_rpt first latches read-write-1-clear reg | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:35 | PAU3.CS.SM3.MCP.MISC.CERR_FIRST1_Q_0_INST.LATC.L2(0:35) [000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLGX_0: NLGX0 Unknown xtype in stage s0r of RXO pipe | |
| 1 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLGX_1: NLGX1 Unknown xtype in stage s2r of RXO pipe | |
| 2 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLGX_2: NLGX2 (reserved) | |
| 3 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLGX_3: NLGX3 (reserved) | |
| 4 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_FWD_0: FWD0 s4: Forward progress timer expired | |
| 5 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_FWD_1: FWD1 s4: rpt_hang.data waiting-for-data timeout | |
| 6 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_FWD_2: FWD2 (reserved) | |
| 7 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_FWD_3: FWD3 (reserved) | |
| 8 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_AUE_0: AUE0 UE ECC error detected from State-machine array | |
| 9 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_AUE_1: AUE1 UE ECC error detected from Rq/Rs output queue array | |
| 10 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_AUE_2: AUE2 UE ECC error detected from PowerBus data flit combiner array | |
| 11 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_AUE_3: AUE3 (reserved) | |
| 12 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_AUE_4: AUE4 UE ECC error detected from L2-Directory SRAM 0 | |
| 13 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_AUE_5: AUE5 UE ECC error detected from L2-Directory SRAM 1 | |
| 14 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_AUE_6: AUE6 UE ECC error detected from L2-Directory SRAM 2 | |
| 15 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_AUE_7: AUE7 UE ECC error detected from L2-Directory SRAM 3 | |
| 16 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBF_0: PBF0 s5: MCP_M_WT_CRESP: error cresp received for a command | |
| 17 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBF_1: PBF1 s5: MCP_PC_WT_CRESP: error cresp received for a command | |
| 18 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBF_2: PBF2 s4: MCP_PC_WT_CRESP: Addr_Error received for self-lpc command (SSF) | |
| 19 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBF_3: PBF3 s4: MCP_PC_BK_WT_CRESP: ack_dead cresp received for a bkill | |
| 20 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBF_4: PBF4 s5: MCP_M_RCV_DATA_PTL: not all segments/OWs were received | |
| 21 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBF_5: PBF5 s4: dma_pr_w/pr_dma_inj snooped that crosses 128B boundary | |
| 22 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBF_6: PBF6 s4: SMEV_DATIN: Received data with illegal data_stat value. | |
| 23 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBF_7: PBF7 Unexpected data beat received | |
| 24 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBF_8: PBF8 s7: addr_error CResp to internal PAU request | |
| 25 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBF_9: PBF9 (reserved) | |
| 26 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBF_10: PBF10 s5: Received 64B of data but snooped command wasn't cp_*(m=1) | |
| 27 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_PBF_11: PBF11 s5: Received 64B of data to PAU-mastered command | |
| 28 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_LDA_0: LDA0 s4: MCP_PC_WT_CRESP: Addr_Error received for load command (LD) | |
| 29 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_LDA_1: LDA1 (reserved) | |
| 30 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_LDA_2: LDA2 (reserved) | |
| 31 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_LDA_3: LDA3 (reserved) | |
| 32 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_STA_0: STA0 s4: MCP_PC_WT_CRESP: Addr_Error received for store command (ST) | |
| 33 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_STA_1: STA1 s4: MCP_PC_BK_WT_CRESP: Addr_Error received for bkill command (ST) | |
| 34 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_STA_2: STA2 (reserved) | |
| 35 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_STA_3: STA3 (reserved) | |
| 36:63 | RO | RO | constant=0b0000000000000000000000000000 | |
| c_err_rpt first-2 latches | ||||
|---|---|---|---|---|
| Addr: |
0000000011010931 (SCOM) 0000000013430088 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.MCP.MISC.CERR_FIRST2 | |||
| Constant(s): | ||||
| Comments: | c_err_rpt first latches read-write-1-clear reg | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM3.MCP.MISC.CERR_FIRST2_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_0: NLG0 s4: Rcmd Event received but state machine is not IDLE | |
| 1 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_1: NLG1 s4: Pocket-Hit event but not in MCP_M_PCKT_WAIT_HIT/PC_* state | |
| 2 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_2: NLG2 s4: MCP_M_WT_CRESP: ma_scresp table lookup missed | |
| 3 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_3: NLG3 s4: MCP_M_WT_CRESP: start epsilon, but epsilon already in progress | |
| 4 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_4: NLG4 s5: MCP_M_WT_CRESP: ma_scresp indicated 'evaporate' but have xTL modified data | |
| 5 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_5: NLG5 s5: MCP_M_WT_CRESP: ma_scresp indicated 'evaporate' but have PB modified data | |
| 6 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_6: NLG6 s5: MCP_M_WT_CRESP: bad scenario code from ma_scresp table | |
| 7 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_7: NLG7 s4: snoop Cresp received but not in MCP_M_WT_CRESP state | |
| 8 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_8: NLG8 s4: Dir-Lock Event received but state machine is not MCP_PC_WT_CRESP/MCP_M_WAIT_SYN_PEND/MCP_M_WAIT_DIR_LOCK or bad ttype | |
| 9 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_9: NLG9 s4: MCP_PC_WT_CRESP: ma_mcresp table lookup missed | |
| 10 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_10: NLG10 s4/5: MCP_PC/_BK/_WT_CRESP: Write coll state didn't match early protection state | |
| 11 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_11: NLG11 s4: MCP_PC_WT_CRESP: start epsilon, but epsilon already in progress | |
| 12 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_12: NLG12 s5: MCP_PC_WT_CRESP: bad scenario code from ma_mcresp table | |
| 13 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_13: NLG13 s4: MCP_PC_BK_WT_CRESP: bad next-step for bkill (ack-done) | |
| 14 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_14: NLG14 s4: MCP_PC_BK_WT_CRESP: bad next-step for bkill (retry) | |
| 15 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_15: NLG15 s4: MCP_PC_BK_WT_CRESP: bad cresp for a bkill | |
| 16 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_16: NLG16 s4: master Cresp received but not in MCP_PC_WT_CRESP/MCP_PC_BK_WT_CRESP states | |
| 17 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_17: NLG17 s4: M_IDLE: Invalid DATALEN[3:0] for NVLink data command | |
| 18 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_18: NLG18 s4: M_IDLE: Invalid command type received | |
| 19 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_19: NLG19 s4: AT-translate-Response event but not in wait-translate state | |
| 20 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_20: NLG20 s4: AT-translate-Response event had bad translate status, but cmd not recognized | |
| 21 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_21: NLG21 s4: SA-Done event but not in wait-SA state | |
| 22 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_22: NLG22 s4: MCP_PC_WAIT_DATADONE: bad next-step for PB data transmit | |
| 23 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_23: NLG23 s4: MCP_TD_WAIT_DATADONE: Unknown NVLink Master Command | |
| 24 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_24: NLG24 s4: BuffDone event but not in PB/PC/MG/NR/XATS/MCP_TD_WAIT_DATADONE state | |
| 25 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_25: NLG25 s4: MCP_NC_WT_RESP: Unknown nv-master command for NVLink response | |
| 26 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_26: NLG26 s4: RG-RspIn event but not in MCP_RG_WT_RESP or MCP_NC_WT_RESP* state | |
| 27 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_27: NLG27 s4: Epsilon-In-Progress, but epsilon counter clock is not the epsilon clock | |
| 28 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_28: NLG28 s4: Epsilon counter clock is 'epsilon' but epsilon_ip is not set | |
| 29 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_29: NLG29 s4: MCP_PC_WT_BK_RBACK: bad next-step for bkill | |
| 30 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_30: NLG30 s4: M/RR_BACK timer expired but not in PC_WT(_BK)_RBACK state | |
| 31 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_31: NLG31 s4: Bad epclock value | |
| 32 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_32: NLG32 s4: coll_state is POCKET_RCOLL_ND but master state is not PCKT_WAIT_HIT | |
| 33 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_33: NLG33 s7: Did not find anything to do for a MCMD_COH response | |
| 34 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_34: NLG34 s4: Unknown Event type received | |
| 35 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_35: NLG35 s4: SMEV_DIRDONE received but sm_dir_upd_pending=0 | |
| 36 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_36: NLG36 s7: MCP_M_EVAL_DSA: Unknown merge opcode from dsa table | |
| 37 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_37: NLG37 s7: Unknown State | |
| 38 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_38: NLG38 s4: coll_state is POCKET_RCOLL_OND but master state is not PCKT_WAIT_HIT | |
| 39 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_39: NLG39 s4: Unknown sm_master_state in ESCAN_FENCE event | |
| 40 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_40: NLG40 s4: MCP_FENCE_WT_RESP_FILL: Unknown nv-master command for Fence-Fill-SUE response | |
| 41 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_41: NLG41 s4: MCP_M_WT_CRESP: impossible command/cresp | |
| 42 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_42: NLG42 s4: MCP_PC_WT_CRESP: impossible command/cresp | |
| 43 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_43: NLG43 s7: MCP_M_EVAL_DSA: impossible command/state | |
| 44 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_44: NLG44 s7: Unexpected Error State (bad sub-sequence return) | |
| 45 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_45: NLG45 s5: sfstat-retry but not in retry-abbks collision state | |
| 46 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_46: NLG46 s5: *cond*-retry but not in retry-abbks collision state | |
| 47 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_47: NLG47 s4: Request from CTL/xTL caused bad MMIO alignment, but cmd not recognized | |
| 48 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_48: NLG48 s5: MCP_NC_EXE_RESP: Unknown nv-master command for NVLink response | |
| 49 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_49: NLG49 s7: MCP_M_EVAL_DSA: Topology-index of the Request address is not valid in the topology-index table | |
| 50 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_50: NLG50 s4: Request from CTL/xTL caused bad MMIO alignment, but cmd not recognized | |
| 51 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_51: NLG51 s4: Request from CTL/xTL loaded into non-idle state-machine | |
| 52 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_52: NLG52 s4: POCKET-HIT event but coll_state is not POCKET_WINNER* | |
| 53 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_53: NLG53 s4: Unknown rspin event w/ unknown master-command in MCP_RG_WT_RESP state | |
| 54 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_54: NLG54 s7: Attempt to send PBus request but config_enable_pbus=0 | |
| 55 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_55: NLG55 s4: Invalid SrcBus on response from CTL | |
| 56 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_56: NLG56 s4: Shoulder-tap event but not in MCP_M_WT_SHOULDER_TAP state | |
| 57 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_57: NLG57 s7: MCP_M_EVAL_DSA: ma_dsasfe table lookup missed | |
| 58 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_58: NLG58 s7: MCP_M_EVAL_DSA: ma_dsac2alc table lookup missed | |
| 59 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_59: NLG59 s7: MCP_M_EVAL_DSA: ma_dsac2co table lookup missed | |
| 60 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_60: NLG60 s7: MCP_M_EVAL_DSA: ma_dsaoth table lookup missed | |
| 61 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_61: NLG61 s7: MCP_M_EVAL_DSA: ma_dsascan table lookup missed | |
| 62 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_62: NLG62 s7: Nothing to do after looking in DSA table | |
| 63 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_MCP_FIRST_NLG_63: NLG63 s7: coherence update/response but directory lock is not DLOCK_MOD | |
| c_err_rpt mask-0 latches | ||||
|---|---|---|---|---|
| Addr: |
0000000011010932 (SCOM) 0000000013430090 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.MCP.MISC.CERR_MASK0 | |||
| Constant(s): | ||||
| Comments: | c_err_rpt mask reg Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:55 | PAU3.CS.SM3.MCP.MISC.CERR_MASK0_Q_0_INST.LATC.L2(0:55) [00000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | IDIAL_MCP_MASK_NVF_0: NVF0 s4: NVLink UT=0 to MMIO space bad cmd/length/alignment | |
| 1 | RW | RW | IDIAL_MCP_MASK_NVF_1: NVF1 s4: UT=1 to MMIO space bad cmd/length/alignment | |
| 2 | RW | RW | IDIAL_MCP_MASK_NVF_2: NVF2 s4: Target-Error/Unsupported-Request/Reserved Rsp_Status received in NVLink Response | |
| 3 | RW | RW | IDIAL_MCP_MASK_NVF_3: NVF3 s4: Unexpected NVLink/OCAPI Response | |
| 4 | RW | RW | IDIAL_MCP_MASK_NVF_4: NVF4 s4: Bad NV or OC response received (fence brick) | |
| 5 | RW | RW | IDIAL_MCP_MASK_NVF_5: NVF5 s7: MCP_M_EVAL_DSA: illegal castout/.push arrives vs L2 directory state | |
| 6 | RW | RW | IDIAL_MCP_MASK_NVF_6: NVF6 s4: Target-Error/Unsupported-Request/Reserved Rsp_Status received in NVLink Trans-Done Response | |
| 7 | RW | RW | IDIAL_MCP_MASK_NVF_7: NVF7 s4: NVLink or OCAPI response timeout | |
| 8 | RW | RW | IDIAL_MCP_MASK_NVF_8: NVF8 s4: Bad synonym_done received | |
| 9 | RW | RW | IDIAL_MCP_MASK_NVF_9: NVF9 s4: OCAPI request to MMIO space bad cmd/length/alignment | |
| 10 | RW | RW | IDIAL_MCP_MASK_NVF_10: NVF10 s4: DMA write/atomic to MMIO space w/ Data error | |
| 11 | RW | RW | IDIAL_MCP_MASK_NVF_11: NVF11 s7: MCP_M_EVAL_DSA: Topology-index of the Request address is not valid in the topology-index table | |
| 12 | RW | RW | IDIAL_MCP_MASK_NVF_12: NVF12 s7: MCP_M_EVAL_DSA: addr_error CResp to posted request | |
| 13 | RW | RW | IDIAL_MCP_MASK_NVF_13: NVF13 (reserved) | |
| 14 | RW | RW | IDIAL_MCP_MASK_NVF_14: NVF14 (reserved) | |
| 15 | RW | RW | IDIAL_MCP_MASK_NVF_15: NVF15 NVLink NVF error for brick 0 occurred | |
| 16 | RW | RW | IDIAL_MCP_MASK_NVF_16: NVF16 NVLink NVF error for brick 1 occurred | |
| 17 | RW | RW | IDIAL_MCP_MASK_NVF_17: NVF17 NVLink NVF error for brick 2 occurred | |
| 18 | RW | RW | IDIAL_MCP_MASK_NVF_18: NVF18 NVLink NVF error for brick 3 occurred | |
| 19 | RW | RW | IDIAL_MCP_MASK_NVF_19: NVF19 NVLink NVF error for brick 4 occurred | |
| 20 | RW | RW | IDIAL_MCP_MASK_ASBE_0: ASBE0 SBE ECC error detected from State-machine array | |
| 21 | RW | RW | IDIAL_MCP_MASK_ASBE_1: ASBE1 SBE ECC error detected from Rq/Rs output queue array | |
| 22 | RW | RW | IDIAL_MCP_MASK_ASBE_2: ASBE2 SBE ECC error detected from PowerBus data flit combiner array | |
| 23 | RW | RW | IDIAL_MCP_MASK_ASBE_3: ASBE3 (reserved) | |
| 24 | RW | RW | IDIAL_MCP_MASK_ASBE_4: ASBE4 SBE ECC error detected from L2-Directory SRAM 0 | |
| 25 | RW | RW | IDIAL_MCP_MASK_ASBE_5: ASBE5 SBE ECC error detected from L2-Directory SRAM 1 | |
| 26 | RW | RW | IDIAL_MCP_MASK_ASBE_6: ASBE6 SBE ECC error detected from L2-Directory SRAM 2 | |
| 27 | RW | RW | IDIAL_MCP_MASK_ASBE_7: ASBE7 SBE ECC error detected from L2-Directory SRAM 3 | |
| 28 | RW | RW | IDIAL_MCP_MASK_PBR_0: PBR0 s4: MCP_PC_WT_CRESP: abort_trm(_ed) cresp received to PAU request | |
| 29 | RW | RW | IDIAL_MCP_MASK_PBR_1: PBR1 s4: MCP_PC_BK_WT_CRESP: abort_trm cresp received to PAU BKill request | |
| 30 | RW | RW | IDIAL_MCP_MASK_PBR_2: PBR2 s4: Mis-aligned dma_pr_w/pr_dma_inj to AFU-MMIO space | |
| 31 | RW | RW | IDIAL_MCP_MASK_PBR_3: PBR3 s4: rpt_hang.poll signalled hang condition | |
| 32 | RW | RW | IDIAL_MCP_MASK_PBR_4: PBR4 s4: MCP_PC_WT_CRESP: Addr_Error received for self-lpc command (SSF) | |
| 33 | RW | RW | IDIAL_MCP_MASK_PBR_5: PBR5 (reserved) | |
| 34 | RW | RW | IDIAL_MCP_MASK_PBR_6: PBR6 (reserved) | |
| 35 | RW | RW | IDIAL_MCP_MASK_PBR_7: PBR7 (reserved) | |
| 36 | RW | RW | IDIAL_MCP_MASK_REG_0: REG0 s4: Address/Length/Alignment error on MMIO/GenId/Config access | |
| 37 | RW | RW | IDIAL_MCP_MASK_REG_1: REG1 (reserved) | |
| 38 | RW | RW | IDIAL_MCP_MASK_REG_2: REG2 (reserved) | |
| 39 | RW | RW | IDIAL_MCP_MASK_REG_3: REG3 (reserved) | |
| 40 | RW | RW | IDIAL_MCP_MASK_OCR_0: OCR0 s4: UT=0 to MMIO space bad cmd/length/alignment | |
| 41 | RW | RW | IDIAL_MCP_MASK_OCR_1: OCR1 s4: Bad OC response received | |
| 42 | RW | RW | IDIAL_MCP_MASK_OCR_2: OCR2 s4: AFU request w/ bad data received | |
| 43 | RW | RW | IDIAL_MCP_MASK_OCR_3: OCR3 s4: Intrp_Req ObjHandle did not map to MMIO space | |
| 44 | RW | RW | IDIAL_MCP_MASK_OCR_4: OCR4 s4: NVLink UT=0 to MMIO space bad cmd/length/alignment | |
| 45 | RW | RW | IDIAL_MCP_MASK_OCR_5: OCR5 s4: UT=1 to MMIO space bad cmd/length/alignment | |
| 46 | RW | RW | IDIAL_MCP_MASK_OCR_6: OCR6 s4: OCAPI request to MMIO space bad cmd/length/alignment | |
| 47 | RW | RW | IDIAL_MCP_MASK_OCR_7: OCR7 s4: DMA write/atomic to MMIO space w/ Data error | |
| 48 | RW | RW | IDIAL_MCP_MASK_OCR_8: OCR8 Epoch scanning did not complete before the next tick | |
| 49 | RW | RW | IDIAL_MCP_MASK_OCR_9: OCR9 (reserved) | |
| 50 | RW | RW | IDIAL_MCP_MASK_OCR_10: OCR10 (reserved) | |
| 51 | RW | RW | IDIAL_MCP_MASK_OCR_11: OCR11 NVLink OCR error for brick 0 occurred | |
| 52 | RW | RW | IDIAL_MCP_MASK_OCR_12: OCR12 NVLink OCR error for brick 1 occurred | |
| 53 | RW | RW | IDIAL_MCP_MASK_OCR_13: OCR13 NVLink OCR error for brick 2 occurred | |
| 54 | RW | RW | IDIAL_MCP_MASK_OCR_14: OCR14 NVLink OCR error for brick 3 occurred | |
| 55 | RW | RW | IDIAL_MCP_MASK_OCR_15: OCR15 NVLink OCR error for brick 4 occurred | |
| 56:63 | RO | RO | constant=0b00000000 | |
| c_err_rpt mask-1 latches | ||||
|---|---|---|---|---|
| Addr: |
0000000011010933 (SCOM) 0000000013430098 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.MCP.MISC.CERR_MASK1 | |||
| Constant(s): | ||||
| Comments: | c_err_rpt mask reg Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:35 | PAU3.CS.SM3.MCP.MISC.CERR_MASK1_Q_0_INST.LATC.L2(0:35) [000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | IDIAL_MCP_MASK_NLGX_0: NLGX0 Unknown xtype in stage s0r of RXO pipe | |
| 1 | RW | RW | IDIAL_MCP_MASK_NLGX_1: NLGX1 Unknown xtype in stage s2r of RXO pipe | |
| 2 | RW | RW | IDIAL_MCP_MASK_NLGX_2: NLGX2 (reserved) | |
| 3 | RW | RW | IDIAL_MCP_MASK_NLGX_3: NLGX3 (reserved) | |
| 4 | RW | RW | IDIAL_MCP_MASK_FWD_0: FWD0 s4: Forward progress timer expired | |
| 5 | RW | RW | IDIAL_MCP_MASK_FWD_1: FWD1 s4: rpt_hang.data waiting-for-data timeout | |
| 6 | RW | RW | IDIAL_MCP_MASK_FWD_2: FWD2 (reserved) | |
| 7 | RW | RW | IDIAL_MCP_MASK_FWD_3: FWD3 (reserved) | |
| 8 | RW | RW | IDIAL_MCP_MASK_AUE_0: AUE0 UE ECC error detected from State-machine array | |
| 9 | RW | RW | IDIAL_MCP_MASK_AUE_1: AUE1 UE ECC error detected from Rq/Rs output queue array | |
| 10 | RW | RW | IDIAL_MCP_MASK_AUE_2: AUE2 UE ECC error detected from PowerBus data flit combiner array | |
| 11 | RW | RW | IDIAL_MCP_MASK_AUE_3: AUE3 (reserved) | |
| 12 | RW | RW | IDIAL_MCP_MASK_AUE_4: AUE4 UE ECC error detected from L2-Directory SRAM 0 | |
| 13 | RW | RW | IDIAL_MCP_MASK_AUE_5: AUE5 UE ECC error detected from L2-Directory SRAM 1 | |
| 14 | RW | RW | IDIAL_MCP_MASK_AUE_6: AUE6 UE ECC error detected from L2-Directory SRAM 2 | |
| 15 | RW | RW | IDIAL_MCP_MASK_AUE_7: AUE7 UE ECC error detected from L2-Directory SRAM 3 | |
| 16 | RW | RW | IDIAL_MCP_MASK_PBF_0: PBF0 s5: MCP_M_WT_CRESP: error cresp received for a command | |
| 17 | RW | RW | IDIAL_MCP_MASK_PBF_1: PBF1 s5: MCP_PC_WT_CRESP: error cresp received for a command | |
| 18 | RW | RW | IDIAL_MCP_MASK_PBF_2: PBF2 s4: MCP_PC_WT_CRESP: Addr_Error received for self-lpc command (SSF) | |
| 19 | RW | RW | IDIAL_MCP_MASK_PBF_3: PBF3 s4: MCP_PC_BK_WT_CRESP: ack_dead cresp received for a bkill | |
| 20 | RW | RW | IDIAL_MCP_MASK_PBF_4: PBF4 s5: MCP_M_RCV_DATA_PTL: not all segments/OWs were received | |
| 21 | RW | RW | IDIAL_MCP_MASK_PBF_5: PBF5 s4: dma_pr_w/pr_dma_inj snooped that crosses 128B boundary | |
| 22 | RW | RW | IDIAL_MCP_MASK_PBF_6: PBF6 s4: SMEV_DATIN: Received data with illegal data_stat value. | |
| 23 | RW | RW | IDIAL_MCP_MASK_PBF_7: PBF7 Unexpected data beat received | |
| 24 | RW | RW | IDIAL_MCP_MASK_PBF_8: PBF8 s7: addr_error CResp to internal PAU request | |
| 25 | RW | RW | IDIAL_MCP_MASK_PBF_9: PBF9 (reserved) | |
| 26 | RW | RW | IDIAL_MCP_MASK_PBF_10: PBF10 s5: Received 64B of data but snooped command wasn't cp_*(m=1) | |
| 27 | RW | RW | IDIAL_MCP_MASK_PBF_11: PBF11 s5: Received 64B of data to PAU-mastered command | |
| 28 | RW | RW | IDIAL_MCP_MASK_LDA_0: LDA0 s4: MCP_PC_WT_CRESP: Addr_Error received for load command (LD) | |
| 29 | RW | RW | IDIAL_MCP_MASK_LDA_1: LDA1 (reserved) | |
| 30 | RW | RW | IDIAL_MCP_MASK_LDA_2: LDA2 (reserved) | |
| 31 | RW | RW | IDIAL_MCP_MASK_LDA_3: LDA3 (reserved) | |
| 32 | RW | RW | IDIAL_MCP_MASK_STA_0: STA0 s4: MCP_PC_WT_CRESP: Addr_Error received for store command (ST) | |
| 33 | RW | RW | IDIAL_MCP_MASK_STA_1: STA1 s4: MCP_PC_BK_WT_CRESP: Addr_Error received for bkill command (ST) | |
| 34 | RW | RW | IDIAL_MCP_MASK_STA_2: STA2 (reserved) | |
| 35 | RW | RW | IDIAL_MCP_MASK_STA_3: STA3 (reserved) | |
| 36:63 | RO | RO | constant=0b0000000000000000000000000000 | |
| c_err_rpt mask-2 latches | ||||
|---|---|---|---|---|
| Addr: |
0000000011010934 (SCOM) 00000000134300A0 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.MCP.MISC.CERR_MASK2 | |||
| Constant(s): | ||||
| Comments: | c_err_rpt mask reg Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM3.MCP.MISC.CERR_MASK2_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | IDIAL_MCP_MASK_NLG_0: NLG0 s4: Rcmd Event received but state machine is not IDLE | |
| 1 | RW | RW | IDIAL_MCP_MASK_NLG_1: NLG1 s4: Pocket-Hit event but not in MCP_M_PCKT_WAIT_HIT/PC_* state | |
| 2 | RW | RW | IDIAL_MCP_MASK_NLG_2: NLG2 s4: MCP_M_WT_CRESP: ma_scresp table lookup missed | |
| 3 | RW | RW | IDIAL_MCP_MASK_NLG_3: NLG3 s4: MCP_M_WT_CRESP: start epsilon, but epsilon already in progress | |
| 4 | RW | RW | IDIAL_MCP_MASK_NLG_4: NLG4 s5: MCP_M_WT_CRESP: ma_scresp indicated 'evaporate' but have xTL modified data | |
| 5 | RW | RW | IDIAL_MCP_MASK_NLG_5: NLG5 s5: MCP_M_WT_CRESP: ma_scresp indicated 'evaporate' but have PB modified data | |
| 6 | RW | RW | IDIAL_MCP_MASK_NLG_6: NLG6 s5: MCP_M_WT_CRESP: bad scenario code from ma_scresp table | |
| 7 | RW | RW | IDIAL_MCP_MASK_NLG_7: NLG7 s4: snoop Cresp received but not in MCP_M_WT_CRESP state | |
| 8 | RW | RW | IDIAL_MCP_MASK_NLG_8: NLG8 s4: Dir-Lock Event received but state machine is not MCP_PC_WT_CRESP/MCP_M_WAIT_SYN_PEND/MCP_M_WAIT_DIR_LOCK or bad ttype | |
| 9 | RW | RW | IDIAL_MCP_MASK_NLG_9: NLG9 s4: MCP_PC_WT_CRESP: ma_mcresp table lookup missed | |
| 10 | RW | RW | IDIAL_MCP_MASK_NLG_10: NLG10 s4/5: MCP_PC/_BK/_WT_CRESP: Write coll state didn't match early protection state | |
| 11 | RW | RW | IDIAL_MCP_MASK_NLG_11: NLG11 s4: MCP_PC_WT_CRESP: start epsilon, but epsilon already in progress | |
| 12 | RW | RW | IDIAL_MCP_MASK_NLG_12: NLG12 s5: MCP_PC_WT_CRESP: bad scenario code from ma_mcresp table | |
| 13 | RW | RW | IDIAL_MCP_MASK_NLG_13: NLG13 s4: MCP_PC_BK_WT_CRESP: bad next-step for bkill (ack-done) | |
| 14 | RW | RW | IDIAL_MCP_MASK_NLG_14: NLG14 s4: MCP_PC_BK_WT_CRESP: bad next-step for bkill (retry) | |
| 15 | RW | RW | IDIAL_MCP_MASK_NLG_15: NLG15 s4: MCP_PC_BK_WT_CRESP: bad cresp for a bkill | |
| 16 | RW | RW | IDIAL_MCP_MASK_NLG_16: NLG16 s4: master Cresp received but not in MCP_PC_WT_CRESP/MCP_PC_BK_WT_CRESP states | |
| 17 | RW | RW | IDIAL_MCP_MASK_NLG_17: NLG17 s4: M_IDLE: Invalid DATALEN[3:0] for NVLink data command | |
| 18 | RW | RW | IDIAL_MCP_MASK_NLG_18: NLG18 s4: M_IDLE: Invalid command type received | |
| 19 | RW | RW | IDIAL_MCP_MASK_NLG_19: NLG19 s4: AT-translate-Response event but not in wait-translate state | |
| 20 | RW | RW | IDIAL_MCP_MASK_NLG_20: NLG20 s4: AT-translate-Response event had bad translate status, but cmd not recognized | |
| 21 | RW | RW | IDIAL_MCP_MASK_NLG_21: NLG21 s4: SA-Done event but not in wait-SA state | |
| 22 | RW | RW | IDIAL_MCP_MASK_NLG_22: NLG22 s4: MCP_PC_WAIT_DATADONE: bad next-step for PB data transmit | |
| 23 | RW | RW | IDIAL_MCP_MASK_NLG_23: NLG23 s4: MCP_TD_WAIT_DATADONE: Unknown NVLink Master Command | |
| 24 | RW | RW | IDIAL_MCP_MASK_NLG_24: NLG24 s4: BuffDone event but not in PB/PC/MG/NR/XATS/MCP_TD_WAIT_DATADONE state | |
| 25 | RW | RW | IDIAL_MCP_MASK_NLG_25: NLG25 s4: MCP_NC_WT_RESP: Unknown nv-master command for NVLink response | |
| 26 | RW | RW | IDIAL_MCP_MASK_NLG_26: NLG26 s4: RG-RspIn event but not in MCP_RG_WT_RESP or MCP_NC_WT_RESP* state | |
| 27 | RW | RW | IDIAL_MCP_MASK_NLG_27: NLG27 s4: Epsilon-In-Progress, but epsilon counter clock is not the epsilon clock | |
| 28 | RW | RW | IDIAL_MCP_MASK_NLG_28: NLG28 s4: Epsilon counter clock is 'epsilon' but epsilon_ip is not set | |
| 29 | RW | RW | IDIAL_MCP_MASK_NLG_29: NLG29 s4: MCP_PC_WT_BK_RBACK: bad next-step for bkill | |
| 30 | RW | RW | IDIAL_MCP_MASK_NLG_30: NLG30 s4: M/RR_BACK timer expired but not in PC_WT(_BK)_RBACK state | |
| 31 | RW | RW | IDIAL_MCP_MASK_NLG_31: NLG31 s4: Bad epclock value | |
| 32 | RW | RW | IDIAL_MCP_MASK_NLG_32: NLG32 s4: coll_state is POCKET_RCOLL_ND but master state is not PCKT_WAIT_HIT | |
| 33 | RW | RW | IDIAL_MCP_MASK_NLG_33: NLG33 s7: Did not find anything to do for a MCMD_COH response | |
| 34 | RW | RW | IDIAL_MCP_MASK_NLG_34: NLG34 s4: Unknown Event type received | |
| 35 | RW | RW | IDIAL_MCP_MASK_NLG_35: NLG35 s4: SMEV_DIRDONE received but sm_dir_upd_pending=0 | |
| 36 | RW | RW | IDIAL_MCP_MASK_NLG_36: NLG36 s7: MCP_M_EVAL_DSA: Unknown merge opcode from dsa table | |
| 37 | RW | RW | IDIAL_MCP_MASK_NLG_37: NLG37 s7: Unknown State | |
| 38 | RW | RW | IDIAL_MCP_MASK_NLG_38: NLG38 s4: coll_state is POCKET_RCOLL_OND but master state is not PCKT_WAIT_HIT | |
| 39 | RW | RW | IDIAL_MCP_MASK_NLG_39: NLG39 s4: Unknown sm_master_state in ESCAN_FENCE event | |
| 40 | RW | RW | IDIAL_MCP_MASK_NLG_40: NLG40 s4: MCP_FENCE_WT_RESP_FILL: Unknown nv-master command for Fence-Fill-SUE response | |
| 41 | RW | RW | IDIAL_MCP_MASK_NLG_41: NLG41 s4: MCP_M_WT_CRESP: impossible command/cresp | |
| 42 | RW | RW | IDIAL_MCP_MASK_NLG_42: NLG42 s4: MCP_PC_WT_CRESP: impossible command/cresp | |
| 43 | RW | RW | IDIAL_MCP_MASK_NLG_43: NLG43 s7: MCP_M_EVAL_DSA: impossible command/state | |
| 44 | RW | RW | IDIAL_MCP_MASK_NLG_44: NLG44 s7: Unexpected Error State (bad sub-sequence return) | |
| 45 | RW | RW | IDIAL_MCP_MASK_NLG_45: NLG45 s5: sfstat-retry but not in retry-abbks collision state | |
| 46 | RW | RW | IDIAL_MCP_MASK_NLG_46: NLG46 s5: *cond*-retry but not in retry-abbks collision state | |
| 47 | RW | RW | IDIAL_MCP_MASK_NLG_47: NLG47 s4: Request from CTL/xTL caused bad MMIO alignment, but cmd not recognized | |
| 48 | RW | RW | IDIAL_MCP_MASK_NLG_48: NLG48 s5: MCP_NC_EXE_RESP: Unknown nv-master command for NVLink response | |
| 49 | RW | RW | IDIAL_MCP_MASK_NLG_49: NLG49 s7: MCP_M_EVAL_DSA: Topology-index of the Request address is not valid in the topology-index table | |
| 50 | RW | RW | IDIAL_MCP_MASK_NLG_50: NLG50 s4: Request from CTL/xTL caused bad MMIO alignment, but cmd not recognized | |
| 51 | RW | RW | IDIAL_MCP_MASK_NLG_51: NLG51 s4: Request from CTL/xTL loaded into non-idle state-machine | |
| 52 | RW | RW | IDIAL_MCP_MASK_NLG_52: NLG52 s4: POCKET-HIT event but coll_state is not POCKET_WINNER* | |
| 53 | RW | RW | IDIAL_MCP_MASK_NLG_53: NLG53 s4: Unknown rspin event w/ unknown master-command in MCP_RG_WT_RESP state | |
| 54 | RW | RW | IDIAL_MCP_MASK_NLG_54: NLG54 s7: Attempt to send PBus request but config_enable_pbus=0 | |
| 55 | RW | RW | IDIAL_MCP_MASK_NLG_55: NLG55 s4: Invalid SrcBus on response from CTL | |
| 56 | RW | RW | IDIAL_MCP_MASK_NLG_56: NLG56 s4: Shoulder-tap event but not in MCP_M_WT_SHOULDER_TAP state | |
| 57 | RW | RW | IDIAL_MCP_MASK_NLG_57: NLG57 s7: MCP_M_EVAL_DSA: ma_dsasfe table lookup missed | |
| 58 | RW | RW | IDIAL_MCP_MASK_NLG_58: NLG58 s7: MCP_M_EVAL_DSA: ma_dsac2alc table lookup missed | |
| 59 | RW | RW | IDIAL_MCP_MASK_NLG_59: NLG59 s7: MCP_M_EVAL_DSA: ma_dsac2co table lookup missed | |
| 60 | RW | RW | IDIAL_MCP_MASK_NLG_60: NLG60 s7: MCP_M_EVAL_DSA: ma_dsaoth table lookup missed | |
| 61 | RW | RW | IDIAL_MCP_MASK_NLG_61: NLG61 s7: MCP_M_EVAL_DSA: ma_dsascan table lookup missed | |
| 62 | RW | RW | IDIAL_MCP_MASK_NLG_62: NLG62 s7: Nothing to do after looking in DSA table | |
| 63 | RW | RW | IDIAL_MCP_MASK_NLG_63: NLG63 s7: coherence update/response but directory lock is not DLOCK_MOD | |
| c_err_rpt hold-0 latches | ||||
|---|---|---|---|---|
| Addr: |
0000000011010935 (SCOM) 00000000134300A8 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.MCP.MISC.CERR_HOLD0 | |||
| Constant(s): | ||||
| Comments: | c_err_rpt hold latches read-write-clear reg | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:19 | PAU3.CS.SM3.MCP.MISC.CERPT_NVF.HOLD_LATCH_INST.HOLD.LATC.L2(0:19) [00000000000000000000] | |||
| 20:27 | PAU3.CS.SM3.MCP.MISC.CERPT_ASBE.HOLD_LATCH_INST.HOLD.LATC.L2(0:7) [00000000] | |||
| 28:35 | PAU3.CS.SM3.MCP.MISC.CERPT_PBR.HOLD_LATCH_INST.HOLD.LATC.L2(0:7) [00000000] | |||
| 36:39 | PAU3.CS.SM3.MCP.MISC.CERPT_REG.HOLD_LATCH_INST.HOLD.LATC.L2(0:3) [0000] | |||
| 40:55 | PAU3.CS.SM3.MCP.MISC.CERPT_OCR.HOLD_LATCH_INST.HOLD.LATC.L2(0:15) [0000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_0: NVF0 s4: NVLink UT=0 to MMIO space bad cmd/length/alignment | |
| 1 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_1: NVF1 s4: UT=1 to MMIO space bad cmd/length/alignment | |
| 2 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_2: NVF2 s4: Target-Error/Unsupported-Request/Reserved Rsp_Status received in NVLink Response | |
| 3 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_3: NVF3 s4: Unexpected NVLink/OCAPI Response | |
| 4 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_4: NVF4 s4: Bad NV or OC response received (fence brick) | |
| 5 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_5: NVF5 s7: MCP_M_EVAL_DSA: illegal castout/.push arrives vs L2 directory state | |
| 6 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_6: NVF6 s4: Target-Error/Unsupported-Request/Reserved Rsp_Status received in NVLink Trans-Done Response | |
| 7 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_7: NVF7 s4: NVLink or OCAPI response timeout | |
| 8 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_8: NVF8 s4: Bad synonym_done received | |
| 9 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_9: NVF9 s4: OCAPI request to MMIO space bad cmd/length/alignment | |
| 10 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_10: NVF10 s4: DMA write/atomic to MMIO space w/ Data error | |
| 11 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_11: NVF11 s7: MCP_M_EVAL_DSA: Topology-index of the Request address is not valid in the topology-index table | |
| 12 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_12: NVF12 s7: MCP_M_EVAL_DSA: addr_error CResp to posted request | |
| 13 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_13: NVF13 (reserved) | |
| 14 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_14: NVF14 (reserved) | |
| 15 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_15: NVF15 NVLink NVF error for brick 0 occurred | |
| 16 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_16: NVF16 NVLink NVF error for brick 1 occurred | |
| 17 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_17: NVF17 NVLink NVF error for brick 2 occurred | |
| 18 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_18: NVF18 NVLink NVF error for brick 3 occurred | |
| 19 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NVF_19: NVF19 NVLink NVF error for brick 4 occurred | |
| 20 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_ASBE_0: ASBE0 SBE ECC error detected from State-machine array | |
| 21 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_ASBE_1: ASBE1 SBE ECC error detected from Rq/Rs output queue array | |
| 22 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_ASBE_2: ASBE2 SBE ECC error detected from PowerBus data flit combiner array | |
| 23 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_ASBE_3: ASBE3 (reserved) | |
| 24 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_ASBE_4: ASBE4 SBE ECC error detected from L2-Directory SRAM 0 | |
| 25 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_ASBE_5: ASBE5 SBE ECC error detected from L2-Directory SRAM 1 | |
| 26 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_ASBE_6: ASBE6 SBE ECC error detected from L2-Directory SRAM 2 | |
| 27 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_ASBE_7: ASBE7 SBE ECC error detected from L2-Directory SRAM 3 | |
| 28 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBR_0: PBR0 s4: MCP_PC_WT_CRESP: abort_trm(_ed) cresp received to PAU request | |
| 29 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBR_1: PBR1 s4: MCP_PC_BK_WT_CRESP: abort_trm cresp received to PAU BKill request | |
| 30 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBR_2: PBR2 s4: Mis-aligned dma_pr_w/pr_dma_inj to AFU-MMIO space | |
| 31 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBR_3: PBR3 s4: rpt_hang.poll signalled hang condition | |
| 32 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBR_4: PBR4 s4: MCP_PC_WT_CRESP: Addr_Error received for self-lpc command (SSF) | |
| 33 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBR_5: PBR5 (reserved) | |
| 34 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBR_6: PBR6 (reserved) | |
| 35 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBR_7: PBR7 (reserved) | |
| 36 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_REG_0: REG0 s4: Address/Length/Alignment error on MMIO/GenId/Config access | |
| 37 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_REG_1: REG1 (reserved) | |
| 38 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_REG_2: REG2 (reserved) | |
| 39 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_REG_3: REG3 (reserved) | |
| 40 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_OCR_0: OCR0 s4: UT=0 to MMIO space bad cmd/length/alignment | |
| 41 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_OCR_1: OCR1 s4: Bad OC response received | |
| 42 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_OCR_2: OCR2 s4: AFU request w/ bad data received | |
| 43 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_OCR_3: OCR3 s4: Intrp_Req ObjHandle did not map to MMIO space | |
| 44 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_OCR_4: OCR4 s4: NVLink UT=0 to MMIO space bad cmd/length/alignment | |
| 45 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_OCR_5: OCR5 s4: UT=1 to MMIO space bad cmd/length/alignment | |
| 46 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_OCR_6: OCR6 s4: OCAPI request to MMIO space bad cmd/length/alignment | |
| 47 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_OCR_7: OCR7 s4: DMA write/atomic to MMIO space w/ Data error | |
| 48 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_OCR_8: OCR8 Epoch scanning did not complete before the next tick | |
| 49 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_OCR_9: OCR9 (reserved) | |
| 50 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_OCR_10: OCR10 (reserved) | |
| 51 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_OCR_11: OCR11 NVLink OCR error for brick 0 occurred | |
| 52 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_OCR_12: OCR12 NVLink OCR error for brick 1 occurred | |
| 53 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_OCR_13: OCR13 NVLink OCR error for brick 2 occurred | |
| 54 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_OCR_14: OCR14 NVLink OCR error for brick 3 occurred | |
| 55 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_OCR_15: OCR15 NVLink OCR error for brick 4 occurred | |
| 56:63 | RO | RO | constant=0b00000000 | |
| c_err_rpt hold-1 latches | ||||
|---|---|---|---|---|
| Addr: |
0000000011010936 (SCOM) 00000000134300B0 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.MCP.MISC.CERR_HOLD1 | |||
| Constant(s): | ||||
| Comments: | c_err_rpt hold latches read-write-clear reg | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:3 | PAU3.CS.SM3.MCP.MISC.CERPT_NLGX.HOLD_LATCH_INST.HOLD.LATC.L2(0:3) [0000] | |||
| 4:7 | PAU3.CS.SM3.MCP.MISC.CERPT_FWD.HOLD_LATCH_INST.HOLD.LATC.L2(0:3) [0000] | |||
| 8:15 | PAU3.CS.SM3.MCP.MISC.CERPT_AUE.HOLD_LATCH_INST.HOLD.LATC.L2(0:7) [00000000] | |||
| 16:27 | PAU3.CS.SM3.MCP.MISC.CERPT_PBF.HOLD_LATCH_INST.HOLD.LATC.L2(0:11) [000000000000] | |||
| 28:31 | PAU3.CS.SM3.MCP.MISC.CERPT_LDA.HOLD_LATCH_INST.HOLD.LATC.L2(0:3) [0000] | |||
| 32:35 | PAU3.CS.SM3.MCP.MISC.CERPT_STA.HOLD_LATCH_INST.HOLD.LATC.L2(0:3) [0000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLGX_0: NLGX0 Unknown xtype in stage s0r of RXO pipe | |
| 1 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLGX_1: NLGX1 Unknown xtype in stage s2r of RXO pipe | |
| 2 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLGX_2: NLGX2 (reserved) | |
| 3 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLGX_3: NLGX3 (reserved) | |
| 4 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_FWD_0: FWD0 s4: Forward progress timer expired | |
| 5 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_FWD_1: FWD1 s4: rpt_hang.data waiting-for-data timeout | |
| 6 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_FWD_2: FWD2 (reserved) | |
| 7 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_FWD_3: FWD3 (reserved) | |
| 8 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_AUE_0: AUE0 UE ECC error detected from State-machine array | |
| 9 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_AUE_1: AUE1 UE ECC error detected from Rq/Rs output queue array | |
| 10 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_AUE_2: AUE2 UE ECC error detected from PowerBus data flit combiner array | |
| 11 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_AUE_3: AUE3 (reserved) | |
| 12 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_AUE_4: AUE4 UE ECC error detected from L2-Directory SRAM 0 | |
| 13 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_AUE_5: AUE5 UE ECC error detected from L2-Directory SRAM 1 | |
| 14 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_AUE_6: AUE6 UE ECC error detected from L2-Directory SRAM 2 | |
| 15 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_AUE_7: AUE7 UE ECC error detected from L2-Directory SRAM 3 | |
| 16 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBF_0: PBF0 s5: MCP_M_WT_CRESP: error cresp received for a command | |
| 17 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBF_1: PBF1 s5: MCP_PC_WT_CRESP: error cresp received for a command | |
| 18 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBF_2: PBF2 s4: MCP_PC_WT_CRESP: Addr_Error received for self-lpc command (SSF) | |
| 19 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBF_3: PBF3 s4: MCP_PC_BK_WT_CRESP: ack_dead cresp received for a bkill | |
| 20 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBF_4: PBF4 s5: MCP_M_RCV_DATA_PTL: not all segments/OWs were received | |
| 21 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBF_5: PBF5 s4: dma_pr_w/pr_dma_inj snooped that crosses 128B boundary | |
| 22 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBF_6: PBF6 s4: SMEV_DATIN: Received data with illegal data_stat value. | |
| 23 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBF_7: PBF7 Unexpected data beat received | |
| 24 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBF_8: PBF8 s7: addr_error CResp to internal PAU request | |
| 25 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBF_9: PBF9 (reserved) | |
| 26 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBF_10: PBF10 s5: Received 64B of data but snooped command wasn't cp_*(m=1) | |
| 27 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_PBF_11: PBF11 s5: Received 64B of data to PAU-mastered command | |
| 28 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_LDA_0: LDA0 s4: MCP_PC_WT_CRESP: Addr_Error received for load command (LD) | |
| 29 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_LDA_1: LDA1 (reserved) | |
| 30 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_LDA_2: LDA2 (reserved) | |
| 31 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_LDA_3: LDA3 (reserved) | |
| 32 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_STA_0: STA0 s4: MCP_PC_WT_CRESP: Addr_Error received for store command (ST) | |
| 33 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_STA_1: STA1 s4: MCP_PC_BK_WT_CRESP: Addr_Error received for bkill command (ST) | |
| 34 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_STA_2: STA2 (reserved) | |
| 35 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_STA_3: STA3 (reserved) | |
| 36:63 | RO | RO | constant=0b0000000000000000000000000000 | |
| c_err_rpt hold-2 latches | ||||
|---|---|---|---|---|
| Addr: |
0000000011010937 (SCOM) 00000000134300B8 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.MCP.MISC.CERR_HOLD2 | |||
| Constant(s): | ||||
| Comments: | c_err_rpt hold latches read-write-clear reg | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM3.MCP.MISC.CERPT_NLG.HOLD_LATCH_INST.HOLD.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_0: NLG0 s4: Rcmd Event received but state machine is not IDLE | |
| 1 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_1: NLG1 s4: Pocket-Hit event but not in MCP_M_PCKT_WAIT_HIT/PC_* state | |
| 2 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_2: NLG2 s4: MCP_M_WT_CRESP: ma_scresp table lookup missed | |
| 3 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_3: NLG3 s4: MCP_M_WT_CRESP: start epsilon, but epsilon already in progress | |
| 4 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_4: NLG4 s5: MCP_M_WT_CRESP: ma_scresp indicated 'evaporate' but have xTL modified data | |
| 5 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_5: NLG5 s5: MCP_M_WT_CRESP: ma_scresp indicated 'evaporate' but have PB modified data | |
| 6 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_6: NLG6 s5: MCP_M_WT_CRESP: bad scenario code from ma_scresp table | |
| 7 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_7: NLG7 s4: snoop Cresp received but not in MCP_M_WT_CRESP state | |
| 8 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_8: NLG8 s4: Dir-Lock Event received but state machine is not MCP_PC_WT_CRESP/MCP_M_WAIT_SYN_PEND/MCP_M_WAIT_DIR_LOCK or bad ttype | |
| 9 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_9: NLG9 s4: MCP_PC_WT_CRESP: ma_mcresp table lookup missed | |
| 10 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_10: NLG10 s4/5: MCP_PC/_BK/_WT_CRESP: Write coll state didn't match early protection state | |
| 11 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_11: NLG11 s4: MCP_PC_WT_CRESP: start epsilon, but epsilon already in progress | |
| 12 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_12: NLG12 s5: MCP_PC_WT_CRESP: bad scenario code from ma_mcresp table | |
| 13 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_13: NLG13 s4: MCP_PC_BK_WT_CRESP: bad next-step for bkill (ack-done) | |
| 14 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_14: NLG14 s4: MCP_PC_BK_WT_CRESP: bad next-step for bkill (retry) | |
| 15 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_15: NLG15 s4: MCP_PC_BK_WT_CRESP: bad cresp for a bkill | |
| 16 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_16: NLG16 s4: master Cresp received but not in MCP_PC_WT_CRESP/MCP_PC_BK_WT_CRESP states | |
| 17 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_17: NLG17 s4: M_IDLE: Invalid DATALEN[3:0] for NVLink data command | |
| 18 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_18: NLG18 s4: M_IDLE: Invalid command type received | |
| 19 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_19: NLG19 s4: AT-translate-Response event but not in wait-translate state | |
| 20 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_20: NLG20 s4: AT-translate-Response event had bad translate status, but cmd not recognized | |
| 21 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_21: NLG21 s4: SA-Done event but not in wait-SA state | |
| 22 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_22: NLG22 s4: MCP_PC_WAIT_DATADONE: bad next-step for PB data transmit | |
| 23 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_23: NLG23 s4: MCP_TD_WAIT_DATADONE: Unknown NVLink Master Command | |
| 24 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_24: NLG24 s4: BuffDone event but not in PB/PC/MG/NR/XATS/MCP_TD_WAIT_DATADONE state | |
| 25 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_25: NLG25 s4: MCP_NC_WT_RESP: Unknown nv-master command for NVLink response | |
| 26 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_26: NLG26 s4: RG-RspIn event but not in MCP_RG_WT_RESP or MCP_NC_WT_RESP* state | |
| 27 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_27: NLG27 s4: Epsilon-In-Progress, but epsilon counter clock is not the epsilon clock | |
| 28 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_28: NLG28 s4: Epsilon counter clock is 'epsilon' but epsilon_ip is not set | |
| 29 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_29: NLG29 s4: MCP_PC_WT_BK_RBACK: bad next-step for bkill | |
| 30 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_30: NLG30 s4: M/RR_BACK timer expired but not in PC_WT(_BK)_RBACK state | |
| 31 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_31: NLG31 s4: Bad epclock value | |
| 32 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_32: NLG32 s4: coll_state is POCKET_RCOLL_ND but master state is not PCKT_WAIT_HIT | |
| 33 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_33: NLG33 s7: Did not find anything to do for a MCMD_COH response | |
| 34 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_34: NLG34 s4: Unknown Event type received | |
| 35 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_35: NLG35 s4: SMEV_DIRDONE received but sm_dir_upd_pending=0 | |
| 36 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_36: NLG36 s7: MCP_M_EVAL_DSA: Unknown merge opcode from dsa table | |
| 37 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_37: NLG37 s7: Unknown State | |
| 38 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_38: NLG38 s4: coll_state is POCKET_RCOLL_OND but master state is not PCKT_WAIT_HIT | |
| 39 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_39: NLG39 s4: Unknown sm_master_state in ESCAN_FENCE event | |
| 40 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_40: NLG40 s4: MCP_FENCE_WT_RESP_FILL: Unknown nv-master command for Fence-Fill-SUE response | |
| 41 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_41: NLG41 s4: MCP_M_WT_CRESP: impossible command/cresp | |
| 42 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_42: NLG42 s4: MCP_PC_WT_CRESP: impossible command/cresp | |
| 43 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_43: NLG43 s7: MCP_M_EVAL_DSA: impossible command/state | |
| 44 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_44: NLG44 s7: Unexpected Error State (bad sub-sequence return) | |
| 45 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_45: NLG45 s5: sfstat-retry but not in retry-abbks collision state | |
| 46 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_46: NLG46 s5: *cond*-retry but not in retry-abbks collision state | |
| 47 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_47: NLG47 s4: Request from CTL/xTL caused bad MMIO alignment, but cmd not recognized | |
| 48 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_48: NLG48 s5: MCP_NC_EXE_RESP: Unknown nv-master command for NVLink response | |
| 49 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_49: NLG49 s7: MCP_M_EVAL_DSA: Topology-index of the Request address is not valid in the topology-index table | |
| 50 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_50: NLG50 s4: Request from CTL/xTL caused bad MMIO alignment, but cmd not recognized | |
| 51 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_51: NLG51 s4: Request from CTL/xTL loaded into non-idle state-machine | |
| 52 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_52: NLG52 s4: POCKET-HIT event but coll_state is not POCKET_WINNER* | |
| 53 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_53: NLG53 s4: Unknown rspin event w/ unknown master-command in MCP_RG_WT_RESP state | |
| 54 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_54: NLG54 s7: Attempt to send PBus request but config_enable_pbus=0 | |
| 55 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_55: NLG55 s4: Invalid SrcBus on response from CTL | |
| 56 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_56: NLG56 s4: Shoulder-tap event but not in MCP_M_WT_SHOULDER_TAP state | |
| 57 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_57: NLG57 s7: MCP_M_EVAL_DSA: ma_dsasfe table lookup missed | |
| 58 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_58: NLG58 s7: MCP_M_EVAL_DSA: ma_dsac2alc table lookup missed | |
| 59 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_59: NLG59 s7: MCP_M_EVAL_DSA: ma_dsac2co table lookup missed | |
| 60 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_60: NLG60 s7: MCP_M_EVAL_DSA: ma_dsaoth table lookup missed | |
| 61 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_61: NLG61 s7: MCP_M_EVAL_DSA: ma_dsascan table lookup missed | |
| 62 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_62: NLG62 s7: Nothing to do after looking in DSA table | |
| 63 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MCP_HOLD_NLG_63: NLG63 s7: coherence update/response but directory lock is not DLOCK_MOD | |
| Perf Match Reg | ||||
|---|---|---|---|---|
| Addr: |
0000000011010938 (SCOM) 00000000134300C0 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.MCP.MISC.PERF_MATCH_CONFIG | |||
| Constant(s): | ||||
| Comments: | Performance Event Field Match | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:43 | PAU3.CS.SM3.MCP.MISC.PERF_MATCH_CONFIG_Q_0_INST.LATC.L2(0:43) [00000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:23 | RW | RW | PERF_MATCH_RESERVED2: reserved | |
| 24:28 | RW | RW | PERF_MATCH_CRESP: CResp | |
| 29:31 | RW | RW | PERF_MATCH_SCOPE: Scope | |
| 32:41 | RW | RW | PERF_MATCH_MCMD: MCmd | |
| 42:43 | RW | RW | PERF_MATCH_RESERVED1: reserved | |
| 44:63 | RO | RO | constant=0b00000000000000000000 | |
| Perf Mask Reg | ||||
|---|---|---|---|---|
| Addr: |
0000000011010939 (SCOM) 00000000134300C8 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.MCP.MISC.PERF_MASK_CONFIG | |||
| Constant(s): | ||||
| Comments: | Performance Event Field Mask | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:43 | PAU3.CS.SM3.MCP.MISC.PERF_MASK_CONFIG_Q_0_INST.LATC.L2(0:43) [00000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:23 | RW | RW | PERF_MASK_RESERVED2: reserved | |
| 24:28 | RW | RW | PERF_MASK_CRESP: CResp | |
| 29:31 | RW | RW | PERF_MASK_SCOPE: Scope | |
| 32:41 | RW | RW | PERF_MASK_MCMD: MCmd | |
| 42:43 | RW | RW | PERF_MASK_RESERVED1: reserved | |
| 44:63 | RO | RO | constant=0b00000000000000000000 | |
| Debug0 Config Reg | ||||
|---|---|---|---|---|
| Addr: |
000000001101093A (SCOM) 00000000134300D0 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.MCP.MISC.DEBUG0_CONFIG | |||
| Constant(s): | ||||
| Comments: | Config register for trace-0 chain | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM3.MCP.MISC.DEBUG0_CONFIG_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:4 | RW | RW | DEBUG0_CONFIG_POD0: Mux control for byte 0 of trace-0 | |
| 5:9 | RW | RW | DEBUG0_CONFIG_POD1: Mux control for byte 1 of trace-0 | |
| 10:14 | RW | RW | DEBUG0_CONFIG_POD2: Mux control for byte 2 of trace-0 | |
| 15:19 | RW | RW | DEBUG0_CONFIG_POD3: Mux control for byte 3 of trace-0 | |
| 20:24 | RW | RW | DEBUG0_CONFIG_POD4: Mux control for byte 4 of trace-0 | |
| 25:29 | RW | RW | DEBUG0_CONFIG_POD5: Mux control for byte 5 of trace-0 | |
| 30:34 | RW | RW | DEBUG0_CONFIG_POD6: Mux control for byte 6 of trace-0 | |
| 35:39 | RW | RW | DEBUG0_CONFIG_POD7: Mux control for byte 7 of trace-0 | |
| 40:44 | RW | RW | DEBUG0_CONFIG_POD8: Mux control for byte 8 of trace-0 | |
| 45:49 | RW | RW | DEBUG0_CONFIG_POD9: Mux control for byte 9 of trace-0 | |
| 50:54 | RW | RW | DEBUG0_CONFIG_POD10: Mux control for byte 10 of trace-0 | |
| 55:62 | RW | RW | DEBUG0_CONFIG_RESERVED1: reserved | |
| 63 | RW | RW | DEBUG0_CONFIG_ACT: Enable clock-gates for debug trace latches | |
| Debug1 Config Reg | ||||
|---|---|---|---|---|
| Addr: |
000000001101093B (SCOM) 00000000134300D8 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.MCP.MISC.DEBUG1_CONFIG | |||
| Constant(s): | ||||
| Comments: | Config register for trace-1 chain | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM3.MCP.MISC.DEBUG1_CONFIG_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:4 | RW | RW | DEBUG1_CONFIG_POD0: Mux control for byte 0 of trace-1 | |
| 5:9 | RW | RW | DEBUG1_CONFIG_POD1: Mux control for byte 1 of trace-1 | |
| 10:14 | RW | RW | DEBUG1_CONFIG_POD2: Mux control for byte 2 of trace-1 | |
| 15:19 | RW | RW | DEBUG1_CONFIG_POD3: Mux control for byte 3 of trace-1 | |
| 20:24 | RW | RW | DEBUG1_CONFIG_POD4: Mux control for byte 4 of trace-1 | |
| 25:29 | RW | RW | DEBUG1_CONFIG_POD5: Mux control for byte 5 of trace-1 | |
| 30:34 | RW | RW | DEBUG1_CONFIG_POD6: Mux control for byte 6 of trace-1 | |
| 35:39 | RW | RW | DEBUG1_CONFIG_POD7: Mux control for byte 7 of trace-1 | |
| 40:44 | RW | RW | DEBUG1_CONFIG_POD8: Mux control for byte 8 of trace-1 | |
| 45:49 | RW | RW | DEBUG1_CONFIG_POD9: Mux control for byte 9 of trace-1 | |
| 50:54 | RW | RW | DEBUG1_CONFIG_POD10: Mux control for byte 10 of trace-1 | |
| 55:62 | RW | RW | DEBUG1_CONFIG_RESERVED1: reserved | |
| 63 | RW | RW | DEBUG1_CONFIG_ACT: Enable clock-gates for debug trace latches | |
| Debug Machine-Pipe config 3 | ||||
|---|---|---|---|---|
| Addr: |
000000001101093C (SCOM) 00000000134300E0 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.MCP.MISC.DEBUG3_CONFIG | |||
| Constant(s): | ||||
| Comments: | Config register for machine-pipe fields into internal-group 4 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM3.MCP.MISC.DEBUG3_CONFIG_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:6 | RW | RW | DEBUG_CONFIG_MACH_BYTE0: Mux control for mach byte 0 | |
| 7:13 | RW | RW | DEBUG_CONFIG_MACH_BYTE1: Mux control for mach byte 1 | |
| 14:20 | RW | RW | DEBUG_CONFIG_MACH_BYTE2: Mux control for mach byte 2 | |
| 21:27 | RW | RW | DEBUG_CONFIG_MACH_BYTE3: Mux control for mach byte 3 | |
| 28:34 | RW | RW | DEBUG_CONFIG_MACH_BYTE4: Mux control for mach byte 4 | |
| 35:41 | RW | RW | DEBUG_CONFIG_MACH_BYTE5: Mux control for mach byte 5 | |
| 42:48 | RW | RW | DEBUG_CONFIG_MACH_BYTE6: Mux control for mach byte 6 | |
| 49:55 | RW | RW | DEBUG_CONFIG_MACH_BYTE7: Mux control for mach byte 7 | |
| 56:62 | RW | RW | DEBUG_CONFIG_MACH_BYTE8: Mux control for mach byte 8 | |
| 63 | RW | RW | DEBUG_CONFIG_MACH_ACT: Clock-gate enable for mach byte latches | |
| Debug Machine-Pipe config 4 | ||||
|---|---|---|---|---|
| Addr: |
000000001101093D (SCOM) 00000000134300E8 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.MCP.MISC.DEBUG4_CONFIG | |||
| Constant(s): | ||||
| Comments: | Config register for machine-pipe fields into internal-group 4 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:51 | PAU3.CS.SM3.MCP.MISC.DEBUG4_CONFIG_Q_0_INST.LATC.L2(0:51) [0000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:6 | RW | RW | DEBUG_CONFIG_MACH_BYTE9: Mux control for mach byte 9 | |
| 7:13 | RW | RW | DEBUG_CONFIG_MACH_BYTE10: Mux control for mach byte 10 | |
| 14:20 | RW | RW | DEBUG_CONFIG_MACH_BYTE11: Mux control for mach byte 11 | |
| 21:27 | RW | RW | DEBUG_CONFIG_MACH_BYTE12: Mux control for mach byte 12 | |
| 28:34 | RW | RW | DEBUG_CONFIG_MACH_BYTE13: Mux control for mach byte 13 | |
| 35:41 | RW | RW | DEBUG_CONFIG_MACH_BYTE14: Mux control for mach byte 14 | |
| 42:48 | RW | RW | DEBUG_CONFIG_MACH_BYTE15: Mux control for mach byte 15 | |
| 49:51 | RW | RW | DEBUG_CONFIG_MACH_RESERVED1: reserved | |
| 52:63 | RO | RO | constant=0b000000000000 | |
| CQ_SM Misc Config register #2 | ||||
|---|---|---|---|---|
| Addr: |
000000001101093E (SCOM) 00000000134300F0 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.MCP.MISC.CONFIG2 | |||
| Constant(s): | ||||
| Comments: | Misc config register Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM3.MCP.MISC.CONFIG2_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:11 | RW | RW | CONFIG_MCP_FIR_TO_INHIBIT_MASK: Mask of FIR bits that should force inhibit-all Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 12 | RW | RW | CONFIG_BRK0_FENCE_TO_INHIBIT_MASK: 0/1 = brick-0 fence operates normally / brick-0 fence inhibits everything Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 13 | RW | RW | CONFIG_BRK1_FENCE_TO_INHIBIT_MASK: 0/1 = brick-1 fence operates normally / brick-1 fence inhibits everything Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 14 | RW | RW | CONFIG_BRK2_FENCE_TO_INHIBIT_MASK: 0/1 = brick-2 fence operates normally / brick-2 fence inhibits everything Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 15 | RW | RW | CONFIG_BRK3_FENCE_TO_INHIBIT_MASK: 0/1 = brick-3 fence operates normally / brick-3 fence inhibits everything Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 16 | RW | RW | CONFIG_BRK4_FENCE_TO_INHIBIT_MASK: 0/1 = brick-4 fence operates normally / brick-4 fence inhibits everything Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 17 | RW | RW | CONFIG_ENABLE_PHASE1_DCBF: 0/1 = disable DCARM (PB V5 arch sec 9.6) protocol for dcbf,dcbfc,dcbfps (group 1) / enable dcarm protocol | |
| 18 | RW | RW | CONFIG_ENABLE_PHASE1_CLEAN: 0/1 = disable DCARM (PB V5 arch sec 9.6) protocol for dcbfstp (group 2) / enable dcarm protocol | |
| 19 | RW | RW | CONFIG_ENABLE_PHASE1_AMO: 0/1 = disable DCARM (PB V5 arch sec 9.6) protocol for armw*,armwf* (group 3) / enable dcarm protocol | |
| 20:31 | RW | RW | CONFIG_DCARM_TIMER: timeout value for DCARM phase-2 measured in PowerBus epsilon steps | |
| 32:33 | RW | RW | CONFIG_BRK0_EXT_MEM_TAGS: Even and Odd iSeries tag bits for brick-0 OCAPI 128B dma_w (Extended memory) | |
| 34:35 | RW | RW | CONFIG_BRK1_EXT_MEM_TAGS: Even and Odd iSeries tag bits for brick-1 OCAPI 128B dma_w (Extended memory) | |
| 36:37 | RW | RW | CONFIG_BRK2_EXT_MEM_TAGS: Even and Odd iSeries tag bits for brick-2 OCAPI 128B dma_w (Extended memory) | |
| 38:39 | RW | RW | CONFIG_BRK3_EXT_MEM_TAGS: Even and Odd iSeries tag bits for brick-3 OCAPI 128B dma_w (Extended memory) | |
| 40:41 | RW | RW | CONFIG_BRK4_EXT_MEM_TAGS: Even and Odd iSeries tag bits for brick-4 OCAPI 128B dma_w (Extended memory) | |
| 42 | RW | RW | CONFIG_PB_TO_OC_FASTPATH_MASTER_ENABLE: 0/1 = disable sending OC read request at RCmd / enable sending early OC read request before CResp | |
| 43 | RW | RW | CONFIG_PB_TO_OC_FASTPATH_ENABLE_READ: 0/1 = disable sending fastpath oc read for rd_go_s, rd_go_m, rd_larx / enable fastpath. | |
| 44 | RW | RW | CONFIG_PB_TO_OC_FASTPATH_ENABLE_PREF: 0/1 = disable sending fastpath oc read for pref_go_s, pref_go_m / enable fastpath. | |
| 45 | RW | RW | CONFIG_PB_TO_OC_FASTPATH_ENABLE_DMA: 0/1 = disable sending fastpath oc read for cl_dma_rd, cl_rd_nc / enable fastpath. | |
| 46 | RW | RW | CONFIG_PB_TO_OC_FASTPATH_ENABLE_RWITM: 0/1 = disable sending fastpath oc read for rwitm, rwitm_stwx / enable fastpath. | |
| 47 | RW | RW | CONFIG_PB_TO_OC_FASTPATH_ENABLE_CI: 0/1 = disable sending fastpath oc read for ci_pr_rd / enable fastpath. | |
| 48 | RW | RW | CONFIG_PB_TO_OC_FASTPATH_REQUIRE_QOS_1: 0/1 = for fastpath oc reads, don't-care the q (QoS) bit in reads / require the q bit to be '1' if it exists. | |
| 49 | RW | RW | CONFIG_PB_TO_OC_FASTPATH_REQUIRE_HINT_0: 0/1 = for fastpath oc reads, don't-care the h (hint) bit in reads / require the h bit to be '0' if it exists. | |
| 50:51 | RW | RW | CONFIG_PB_TO_OC_FASTPATH_REQUIRE_CL: for fastpath oc reads, require the cl0/cl1 field (if it exists) to be >= this value. | |
| 52 | RW | RW | CONFIG_PB_TO_OC_FASTPATH_REQUIRE_LD_PR_1: 0/1 = for fastpath oc reads, don't-care the ld_pr (load promote) bit in reads / require the ld_pr bit to be '1' if it exists. | |
| 53 | RW | RW | CONFIG_PB_TO_OC_FASTPATH_REQUIRE_RXO_EMPTY: 0/1 = for fastpath oc reads, don't require the RXO queue to be empty / require the RXO request-out queue to be empty | |
| 54 | RW | RW | CONFIG_DISABLE_HW551717_PTLA_TO_UCI: 0/1 = enable swapping pr_wr_mem_ptla_uco to pr_wr_mem_ptla_uci / disable fix | |
| 55 | RW | RW | CONFIG_DISABLE_HW552185_BKRETRY_TO_RMA: 0/1 = enable using COLL_RMA in place of bkretry / disable fix | |
| 56 | RW | RW | CONFIG_ENABLE_HW549830_MI_RETRY_NON_CP: 0/1 = disable hw549830 fix / enable retrying non-cp commands back to requesting PAU when retried on the PowerBus. | |
| 57:60 | RW | RW | CONFIG_HW549830_MI_RETRY_THRESH: Number of retries on the PowerBus before retrying the non-cp command back to the source PAU. | |
| 61:63 | RW | RW | CONFIG2_RESERVED: Reserved | |
| Timer Config Reg 2 | ||||
|---|---|---|---|---|
| Addr: |
000000001101093F (SCOM) 00000000134300F8 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.MCP.MISC.XTIMER2_CONFIG | |||
| Constant(s): | ||||
| Comments: | Timer Configuration Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:11 | PAU3.CS.SM3.MCP.MISC.XTIMER2_CONFIG_Q_0_INST.LATC.L2(0:11) [000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:5 | RW | RW | CONFIG_INH2_TICK: Rate for SM-Inhibit timer tick 2 (default 63=off) | |
| 6:11 | RW | RW | CONFIG_INH3_TICK: Rate for SM-Inhibit timer tick 3 (default 63=off) | |
| 12:63 | RO | RO | constant=0b0000000000000000000000000000000000000000000000000000 | |
| CQ_DIR Misc Config register #0 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010948 (SCOM) 0000000013430140 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.DIR.MISC.CONFIG0 | |||
| Constant(s): | ||||
| Comments: | Misc config register Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM3.DIR.MISC.CONFIG0Q.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:3 | RW | RW | CONFIG_HOST_TAG_SIZE: Configured host tag size (in bits) Must be less than or equal to the maximum host tag size supported by the AFUs connected to this PAU. 15 = maximum host tag size supported 6 = minimum host tag size supported 5..0 = reserved values, do not use | |
| 4:62 | RW | RW | CONFIG0_RESERVED: Reserved | |
| 63 | RW | RW | CONFIG_DEBUG0_ACT: Clock-gate enable for debug0 latches | |
| Perf Config Reg | ||||
|---|---|---|---|---|
| Addr: |
0000000011010949 (SCOM) 0000000013430148 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.DIR.MISC.PERF_CONFIG | |||
| Constant(s): | ||||
| Comments: | Performance Event selection | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM3.DIR.MISC.PERF_CONFIGQ.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:27 | RW | RW | PERF_CONFIG_RESERVED1: reserved | |
| 28:35 | RW | RW | PERF_CONFIG_EVENT0: Event 0 select 0: count nothing 1: count cycles others: reserved (count nothing) | |
| 36:43 | RW | RW | PERF_CONFIG_EVENT1: Event 1 select See Event 0 select for encodes | |
| 44:51 | RW | RW | PERF_CONFIG_EVENT2: Event 2 select See Event 0 select for encodes | |
| 52:59 | RW | RW | PERF_CONFIG_EVENT3: Event 3 select See Event 0 select for encodes | |
| 60:62 | RW | RW | PERF_CONFIG_RESERVED2: reserved | |
| 63 | RW | RW | PERF_CONFIG_ACT: Enable clock-gates for performance monitor latches | |
| Debug0 Config Reg | ||||
|---|---|---|---|---|
| Addr: |
000000001101094A (SCOM) 0000000013430150 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.DIR.MISC.DEBUG0_CONFIG | |||
| Constant(s): | ||||
| Comments: | Config register for trace-0 chain | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM3.DIR.MISC.DEBUG0_CONFIGQ.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:4 | RW | RW | DEBUG0_CONFIG_POD0: Mux control for byte 0 of trace-0 | |
| 5:9 | RW | RW | DEBUG0_CONFIG_POD1: Mux control for byte 1 of trace-0 | |
| 10:14 | RW | RW | DEBUG0_CONFIG_POD2: Mux control for byte 2 of trace-0 | |
| 15:19 | RW | RW | DEBUG0_CONFIG_POD3: Mux control for byte 3 of trace-0 | |
| 20:24 | RW | RW | DEBUG0_CONFIG_POD4: Mux control for byte 4 of trace-0 | |
| 25:29 | RW | RW | DEBUG0_CONFIG_POD5: Mux control for byte 5 of trace-0 | |
| 30:34 | RW | RW | DEBUG0_CONFIG_POD6: Mux control for byte 6 of trace-0 | |
| 35:39 | RW | RW | DEBUG0_CONFIG_POD7: Mux control for byte 7 of trace-0 | |
| 40:44 | RW | RW | DEBUG0_CONFIG_POD8: Mux control for byte 8 of trace-0 | |
| 45:49 | RW | RW | DEBUG0_CONFIG_POD9: Mux control for byte 9 of trace-0 | |
| 50:54 | RW | RW | DEBUG0_CONFIG_POD10: Mux control for byte 10 of trace-0 | |
| 55:62 | RW | RW | DEBUG0_CONFIG_RESERVED1: reserved | |
| 63 | RW | RW | DEBUG0_CONFIG_ACT: Enable clock-gates for debug trace latches | |
| Debug1 Config Reg | ||||
|---|---|---|---|---|
| Addr: |
000000001101094B (SCOM) 0000000013430158 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.DIR.MISC.DEBUG1_CONFIG | |||
| Constant(s): | ||||
| Comments: | Config register for trace-1 chain | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM3.DIR.MISC.DEBUG1_CONFIGQ.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:4 | RW | RW | DEBUG1_CONFIG_POD0: Mux control for byte 0 of trace-1 | |
| 5:9 | RW | RW | DEBUG1_CONFIG_POD1: Mux control for byte 1 of trace-1 | |
| 10:14 | RW | RW | DEBUG1_CONFIG_POD2: Mux control for byte 2 of trace-1 | |
| 15:19 | RW | RW | DEBUG1_CONFIG_POD3: Mux control for byte 3 of trace-1 | |
| 20:24 | RW | RW | DEBUG1_CONFIG_POD4: Mux control for byte 4 of trace-1 | |
| 25:29 | RW | RW | DEBUG1_CONFIG_POD5: Mux control for byte 5 of trace-1 | |
| 30:34 | RW | RW | DEBUG1_CONFIG_POD6: Mux control for byte 6 of trace-1 | |
| 35:39 | RW | RW | DEBUG1_CONFIG_POD7: Mux control for byte 7 of trace-1 | |
| 40:44 | RW | RW | DEBUG1_CONFIG_POD8: Mux control for byte 8 of trace-1 | |
| 45:49 | RW | RW | DEBUG1_CONFIG_POD9: Mux control for byte 9 of trace-1 | |
| 50:54 | RW | RW | DEBUG1_CONFIG_POD10: Mux control for byte 10 of trace-1 | |
| 55:62 | RW | RW | DEBUG1_CONFIG_RESERVED1: reserved | |
| 63 | RW | RW | DEBUG1_CONFIG_ACT: Enable clock-gates for debug trace latches | |
| SCOM L2 Data Reg | ||||
|---|---|---|---|---|
| Addr: |
000000001101094C (SCOM) 0000000013430160 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.DIR.MISC.SCOM_L2_DATA | |||
| Constant(s): | ||||
| Comments: | Read-only register for SCOM reads of the L2 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM3.DIR.MISC.SCOM_L2_DATAQ.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:63 | ROX | ROX | L2_SCOM_READ_DATA: Data read out of the L2 directory by the SCOM interface | |
| CQ_SM Misc Config register #0 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010950 (SCOM) 0000000013430180 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.SNP.MISC.CONFIG0 | |||
| Constant(s): | ||||
| Comments: | Misc config register Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM3.SNP.MISC.CONFIG0_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:1 | RW | RW | CONFIG_MA_RSNOOP_OPT_DCLAIM: 0 = partial-respond to dclaim to GPU Mem with lpc_ack 1 = (deprecated - do not use) partial-respond to dclaim to GPU Mem with lpc_ack+rty_lost_claim Nv: 2 = partial-respond to dclaim to GPU Mem with lpc_ack+rty_lpc+start pocket cache Oc: 2 = reserved (must not be set when config_ocapi_mode=1 for this stack) 3 = reserved | |
| 2 | RW | RW | CONFIG_ENABLE_PBUS: 0/1 = disable PAU PowerBus RCmd, PResp, and CResp interfaces / enable these interfaces Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 3 | RW | RW | CONFIG_BRAZOS_MODE: Reserved (was: brazos_mode 0/1 = non-brazos 4-group;2-chip mode / brazos 2-group;4-chip mode) | |
| 4 | RW | RW | CONFIG_PCKT_BLK_PRB: 0/1 = valid pocket-cache entries do not block probes / probes are blocked | |
| 5 | RW | RW | CONFIG_ADR_BAR_MODE: Reserved (was: PowerBus adr_bar: 0/1 = large-system-mode/small-system-mode) | |
| 6 | RW | RW | CONFIG_RESTRICT_CHIP_GROUP: Reserved (was: 0/1 = support all 16 groups and all 8 chips / restrict chip/group to 4/2 or 2/4) | |
| 7 | RW | RW | CONFIG_DISABLE_HW552185_BKRETRY_TO_RMA: 0/1 = 'or' hit_rma into hit_bk_rty_abbk and hit_pckt_win signals / disable fix | |
| 8 | RW | RW | CONFIG0_RESERVED3: reserved | |
| 9:15 | RW | RW | CONFIG_SNP_FIR_TO_INHIBIT_MASK: Mask of FIR bits that should force inhibit-all Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 16 | RW | RW | CONFIG_BRK0_FENCE_TO_INHIBIT_MASK: 0/1 = brick-0 fence operates normally / brick-0 fence inhibits everything Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 17 | RW | RW | CONFIG_BRK1_FENCE_TO_INHIBIT_MASK: 0/1 = brick-1 fence operates normally / brick-1 fence inhibits everything Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 18 | RW | RW | CONFIG_BRK2_FENCE_TO_INHIBIT_MASK: 0/1 = brick-2 fence operates normally / brick-2 fence inhibits everything Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 19 | RW | RW | CONFIG_BRK3_FENCE_TO_INHIBIT_MASK: 0/1 = brick-3 fence operates normally / brick-3 fence inhibits everything Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 20 | RW | RW | CONFIG_BRK4_FENCE_TO_INHIBIT_MASK: 0/1 = brick-4 fence operates normally / brick-4 fence inhibits everything Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 21 | RW | RW | CONFIG_MRBGP_TRACK_ALL: 0/1 = master-retry-backoff group-pump track only this stack's/all-this-chips retry responses | |
| 22 | RW | RW | CONFIG_MRBSP_TRACK_ALL: 0/1 = master-retry-backoff system-pump track only this stack's/all-this-chips retry responses | |
| 23 | RW | RW | CONFIG_MRBCP_TRACK_ALL: 0/1 = master-retry-backoff chip-pump track only this stack's/all-this-chips retry responses | |
| 24:30 | RW | RW | CONFIG_ADDR_EX_MASK_ENA: Reserved (was: Mask for address bits to ignore when checking for different-group/different-chip when calculating initial scope.) aka config_chip_address_extension_mask_enable(15:21) | |
| 31 | RW | RW | CONFIG_SINGLE_AFU_DUAL_BRICK: 0/1 = AFU(s) use only one brick / 1 AFU is using both bricks on this ramp (the only effect of this bit is to 'wildcard' brick numbers when processing XSL-castouts) | |
| 32 | RW | RW | CONFIG_BRK0_OCAPI_MODE: 0/1 = Disable OpenCAPI mode / enable OpenCAPI mode for brick 0 (mutually exclusive with config_brk0_nvlink_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 33 | RW | RW | CONFIG_BRK1_OCAPI_MODE: 0/1 = Disable OpenCAPI mode / enable OpenCAPI mode for brick 1 (mutually exclusive with config_brk1_nvlink_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 34 | RW | RW | CONFIG_BRK2_OCAPI_MODE: 0/1 = Disable OpenCAPI mode / enable OpenCAPI mode for brick 2 (mutually exclusive with config_brk2_nvlink_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 35 | RW | RW | CONFIG_BRK3_OCAPI_MODE: 0/1 = Disable OpenCAPI mode / enable OpenCAPI mode for brick 3 (mutually exclusive with config_brk3_nvlink_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 36 | RW | RW | CONFIG_BRK4_OCAPI_MODE: 0/1 = Disable OpenCAPI mode / enable OpenCAPI mode for brick 4 (mutually exclusive with config_brk4_nvlink_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 37 | RW | RW | CONFIG_BRK0_NVLINK_MODE: 0/1 = Disable NVLink mode / enable NVLink mode for brick 0 (mutually exclusive with config_brk0_ocapi_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 38 | RW | RW | CONFIG_BRK1_NVLINK_MODE: 0/1 = Disable NVLink mode / enable NVLink mode for brick 1 (mutually exclusive with config_brk1_ocapi_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 39 | RW | RW | CONFIG_BRK2_NVLINK_MODE: 0/1 = Disable NVLink mode / enable NVLink mode for brick 2 (mutually exclusive with config_brk2_ocapi_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 40 | RW | RW | CONFIG_BRK3_NVLINK_MODE: 0/1 = Disable NVLink mode / enable NVLink mode for brick 3 (mutually exclusive with config_brk3_ocapi_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 41 | RW | RW | CONFIG_BRK4_NVLINK_MODE: 0/1 = Disable NVLink mode / enable NVLink mode for brick 4 (mutually exclusive with config_brk4_ocapi_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 42 | RW | RW | CONFIG_ENABLE_BLOCKING_RCMD_DIR: 0/1 = disable blocking RCmd dir lookups to give bandwidth to internal accesses / enable blocking | |
| 43 | RW | RW | CONFIG_DISABLE_DIR_POWERSAVE: 0/1 = allow clock-gating empty directory lookups to save power / disable clock-gating | |
| 44 | RW | RW | CONFIG_DISABLE_PRESP_POWERSAVE: 0/1 = allow clock-gating empty CAM+DIR PResps to save power / disable clock-gating | |
| 45 | RW | RW | CONFIG_ENABLE_BRK0_OCAPI_C2: 0/1 = disable receiving OCAPI C2 opcodes / enable receiving on brick 0 | |
| 46 | RW | RW | CONFIG_ENABLE_BRK1_OCAPI_C2: 0/1 = disable receiving OCAPI C2 opcodes / enable receiving on brick 1 | |
| 47 | RW | RW | CONFIG_ENABLE_BRK2_OCAPI_C2: 0/1 = disable receiving OCAPI C2 opcodes / enable receiving on brick 2 | |
| 48 | RW | RW | CONFIG_ENABLE_BRK3_OCAPI_C2: 0/1 = disable receiving OCAPI C2 opcodes / enable receiving on brick 3 | |
| 49 | RW | RW | CONFIG_ENABLE_BRK4_OCAPI_C2: 0/1 = disable receiving OCAPI C2 opcodes / enable receiving on brick 4 | |
| 50 | RW | RW | CONFIG_DISABLE_CAN_BY_CP: 0/1 = enable cancel-by-cp logic / disable cancel-by-cp logic | |
| 51 | RW | RW | CONFIG0_RESERVED1: reserved (was: chicken switch hw483005) | |
| 52 | RW | RW | CONFIG0_RESERVED2: reserved (was: chicken switch hw484205) | |
| 53 | RW | RW | CONFIG0_RESERVED4: reserved (was: chicken switch hw484205) | |
| 54 | RW | RW | CONFIG0_RESERVED5: reserved (was: chicken switch hw484205) | |
| 55 | RW | RW | CONFIG0_RESERVED6: reserved (was: chicken switch hw484099) | |
| 56 | RW | RW | CONFIG0_RESERVED7: reserved (was: chicken switch hw484668) | |
| 57 | RW | RW | CONFIG0_RESERVED8: reserved (was: chicken switch hw484695) | |
| 58 | RW | RW | CONFIG0_RESERVED9: reserved (was: chicken switch hw484972) | |
| 59 | RW | RW | CONFIG0_RESERVED10: reserved (was: chicken switch hw485798) | |
| 60 | RW | RW | CONFIG_DISABLE_CAN_BY_PROBE: 0/1 = enable cancel-by-probe logic / disable cancel-by-probe logic | |
| 61 | RW | RW | CONFIG_HANG_ON_ADDRESS_ERRORS: 0/1 = abort and continue on CResp=addr_error / hang state-machine on CResp=addr_error | |
| 62 | RW | RW | CONFIG_DISABLE_HW521165_SFE_BLOCKS_CASTOUT: 0/1 = enable hw521165 fix / disable and allow SFE to block castouts | |
| 63 | RW | RW | CONFIG_DISABLE_HW517982_PSNOOP_MISS_PRESP_NULL: 0/1 = enable hw517982 fix to force PResp=null for psnoop table miss / disable fix. | |
| CQ_SM Misc Config register #1 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010951 (SCOM) 0000000013430188 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.SNP.MISC.CONFIG1 | |||
| Constant(s): | ||||
| Comments: | Misc config register Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM3.SNP.MISC.CONFIG1_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:3 | RW | RW | CONFIG_SCALE_RPT_HANG_POLL: Scaling factor for rpt_hang.poll 0 = 1:1 PowerBus rpt_hang.polls received 1 = 1:2 PowerBus rpt_hang.polls received ... 15 = 1:16 PowerBus rpt_hang.polls received | |
| 4:7 | RW | RW | CONFIG_SCALE_RPT_HANG_DATA: Scaling factor for rpt_hang.data 0 = 1:1 PowerBus rpt_hang.datas received 1 = 1:2 PowerBus rpt_hang.datas received ... 15 = 1:16 PowerBus rpt_hang.datas received | |
| 8:11 | RW | RW | CONFIG_HOST_TAG_SIZE: Configured host tag size (in bits) Must be less than or equal to the maximum host tag size supported by the AFUs connected to this PAU. 15 = maximum host tag size supported 6 = minimum host tag size supported 5..0 = reserved values, do not use | |
| 12:15 | RW | RW | CONFIG_ARB_NONCRR_SAFETY: Safety valve for non-cresp/non-reqin events going down the arb pipe. after N+1 reqin events go through the arbiter while a non-crr event is waiting, reqin events are blocked to give non-crr events a chance. | |
| 16:18 | RW | RW | CONFIG_REPLAY_IP_LIMIT: Limit on number of replays in-progress in the snoop/directory pipe. Must not be set to zero | |
| 19 | RW | RW | CONFIG1_RESERVED1: Reserved | |
| 20:23 | RW | RW | CONFIG_BLOCK_FOR_REPLAY_TIME: Controls the # of cycles to count before forcing an opportunity for a 'replay' to access the directory 0 = 16 cycles 1 = 15 cycles ... 15 = 1 cycle | |
| 24:27 | RW | RW | CONFIG_BLOCK_FOR_DIRSCAN_TIME: Controls the # of cycles to count before forcing an opportunity for a directory-scan to access the directory 0 = 16 cycles 1 = 15 cycles ... 15 = 1 cycle | |
| 28:29 | RW | RW | CONFIG_THROT_ADDR_HASH: select the addr hash crc function used for PWR0/1/2 throttling | |
| 30 | RW | RW | CONFIG_DISABLE_HW510185_DIR_WALKER_REF_COUNT: 0/1 = enable hw510185 dir walker ref counts / disable and return to single-threaded evicts. | |
| 31 | RW | RW | CONFIG_ENABLE_OPENCAPI_NETWORKING: 0/1 = disable networking / enable OpenCAPI MI networking mode. | |
| 32 | RW | RW | CONFIG_NETWORKING_GVC_LOCATION: 0/1 = GVC in PowerBus RA(8:11) / GVC in PowerBus RA(20:23) | |
| 33 | RW | RW | CONFIG_TORUS_ENABLE_E_TO_A: 0/1 = Disable Torus from transferring VC-E into VC-A / Enable Torus to tranfer VC-E into VC-A. | |
| 34 | RW | RW | CONFIG_NETWORKING_SUPPRESS_CAM: 0/1 = Allow CAM results to retry networking RCmds / Disable CAM results for networking RCmds. | |
| 35 | RW | RW | CONFIG_DISABLE_HW532135_FENCE_SHARED_C2_ALC: 0/1 = enable shared state for c2-allocating requests when fenced / disable fix | |
| 36 | RW | RW | CONFIG_TORUS_ENABLE_VC_A: 0/1 = disable torus mode using VC-A (only use VC-E & VC-HP) / enable torus using VC-A | |
| 37 | RW | RW | CONFIG_TORUS_ENABLE_FAIRNESS: 0/1 = disable torus continuation vs new-insertion fairness / enable fairness mechanism | |
| 38:39 | RW | RW | CONFIG1_RESERVED2: Reserved | |
| 40:43 | RW | RW | CONFIG_BRK0_TORUS_NEW_INS_ACC_DEC: (brick 0) Amount to subtract (x4+3) from the fairness counter when a new-insertion is accepted. | |
| 44:47 | RW | RW | CONFIG_BRK0_TORUS_NEW_INS_REJ_INC: (brick 0) Amount to add to the fairness counter when a new-insertion is rejected and the counter is primed. | |
| 48:51 | RW | RW | CONFIG_BRK0_TORUS_CONT_ACC_INC: (brick 0) Amount to add to the fairness counter when a continuation is accepted in the forward-progress state. | |
| 52:55 | RW | RW | CONFIG_BRK1_TORUS_NEW_INS_ACC_DEC: (brick 1) Amount to subtract (x4+3) from the fairness counter when a new-insertion is accepted. | |
| 56:59 | RW | RW | CONFIG_BRK1_TORUS_NEW_INS_REJ_INC: (brick 1) Amount to add to the fairness counter when a new-insertion is rejected and the counter is primed. | |
| 60:63 | RW | RW | CONFIG_BRK1_TORUS_CONT_ACC_INC: (brick 1) Amount to add to the fairness counter when a continuation is accepted in the forward-progress state. | |
| GPU0-Memory BAR | ||||
|---|---|---|---|---|
| Addr: |
0000000011010952 (SCOM) 0000000013430190 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.SNP.MISC.GPU0_BAR | |||
| Constant(s): | ||||
| Comments: | BAR register defining GPU Mem addresses serviced by brick 0 connected to this stack. Note: This register should be set to the same value for each brick/stack. MDials have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:51 | PAU3.CS.SM3.SNP.MISC.GPU0_BAR_Q_0_INST.LATC.L2(0:51) [0000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_GPU0_BAR_ENABLE: Enable for this BAR (0=disabled, 1=enabled) for brick 0 | |
| 1:35 | RW | RW | CONFIG_GPU0_BAR_ADDR_MASK: BAR Address/Mask bits 1:35 for brick 0 In Small-BAR mode (see bit 36): 1:7 = Base_Addr(13:19) = 16T slice 8:21 = Base_Addr(20:33) = 1G address in slice 22:35 = Base_Mask(20:33) = 1G...16T BAR size. (Note: Mask limited to 1G...4T in Axone and P10 w/ GPU systems) In Large-BAR mode (see bit 36): 1 = '1' to match MemSel = addr(13:14) = 0b00 2 = '1' to match MemSel = addr(13:14) = 0b01 3 = '1' to match MemSel = addr(13:14) = 0b10 4:35 = Topology_Id_Mask(0:31) when chip_eq_group=0, TIM(0:31) bit 'i' corresponds to addr(15:19) = 'i' when chip_eq_group=1, TIM(0:31) bit 'i' corresponds to (addr(15:16) & addr(19:21)) = 'i' | |
| 36 | RW | RW | CONFIG_GPU0_BAR_SL_MODE: 0/1 = Small-BAR/Large-BAR Mode selector | |
| 37 | RW | RW | CONFIG_GPU0_BAR_4T_LIMIT: 0 = no limit, 16T slices can be used. 1 = limit slices to 4T. -> when chip_eq_group=0, addr(20:21) must match bar_4t_select -> when chip_eq_group=1, addr(17:18) must match bar_4t_select limit=1 is used in P10 systems w/ a GPU or in Axone systems | |
| 38:39 | RW | RW | CONFIG_GPU0_BAR_4T_SELECT: when bar_4t_limit=1 this field selects the value in addr(20:21) to match | |
| 40:43 | RW | RW | CONFIG_GPU0_BAR_MODE: Hash mode of the BAR for brick 0: if bar_extended_mode == 0: 0 = (single) match on all address in addr/size 1 = (dual.0) match if hashbits(7)=0 2 = (dual.1) match if hashbits(7)=1 3 = (triple.0) match if hashbits%3=0 4 = (triple.1) match if hashbits%3=1 5 = (triple.2) match if hashbits%3=2 6 = (quad.0) match if hashbits(6:7)=0 7 = (quad.1) match if hashbits(6:7)=1 8 = (quad.2) match if hashbits(6:7)=2 9 = (quad.3) match if hashbits(6:7)=3 10 = (six.0) match if hashbits%3=0 and hashbits(7)=0 11 = (six.1) match if hashbits%3=0 and hashbits(7)=1 12 = (six.2) match if hashbits%3=1 and hashbits(7)=0 13 = (six.3) match if hashbits%3=1 and hashbits(7)=1 14 = (six.4) match if hashbits%3=2 and hashbits(7)=0 15 = (six.5) match if hashbits%3=2 and hashbits(7)=1 if bar_extended_mode == 1: 0 = (oct.0) match if hashbits(5:7)=0 1 = (oct.1) match if hashbits(5:7)=1 2 = (oct.2) match if hashbits(5:7)=2 3 = (oct.3) match if hashbits(5:7)=3 4 = (oct.4) match if hashbits(5:7)=4 5 = (oct.5) match if hashbits(5:7)=5 6 = (oct.6) match if hashbits(5:7)=6 7 = (oct.7) match if hashbits(5:7)=7 others = reserved | |
| 44 | RW | RW | CONFIG_GPU0_BAR_GRANULE: Hash boundary for brick 0: 0 = hash on 512B boundary (hashbits(0:7)=addr(47:54)) 1 = hash on 1024B boundary (hashbits(0:7)=addr(46:53)) | |
| 45 | RW | RW | CONFIG_GPU0_BAR_POISON: on failed access return all ones 0/1 = with good ECC / with SUE ECC. | |
| 46 | RW | RW | CONFIG_GPU0_BAR_M2MODE: 0 = OpenCAPI AFU M1 mode / 1 = OpenCAPI AFU M2 mode Has no effect when in NVLink mode | |
| 47 | RW | RW | CONFIG_GPU0_BAR_PA_IGNORE_MODE: Set to '1' for RA-to-PA conversion to ignore the mode field | |
| 48 | RW | RW | CONFIG_GPU0_BAR_SECURE_A12: P10 Only: this specifies the addr(12) value to match for this BAR. Can only be set to one in P10 and only when SMF_CONFIG=0b11. | |
| 49 | RW | RW | CONFIG_GPU0_BAR_CHIP_EQ_GROUP: Axone Only: this specifies that the system is in chip=group mode. This bit should only be set when sl_mode=1 and 4t_limit=1. 0/1 = TIM(0:31) applies to addr(15:19) / TIM(0:31) applies to (addr(15:16) & addr(19:21)). | |
| 50 | RW | RW | CONFIG_GPU0_BAR_EXTENDED_MODE: 0/1 = bar_mode selects 1,2,3,4,6 way hashing / bar_mode selects 8-way hashing | |
| 51 | RW | RW | CONFIG_GPU0_BAR_RESERVED: reserved | |
| 52:63 | RO | RO | constant=0b000000000000 | |
| GPU1-Memory BAR | ||||
|---|---|---|---|---|
| Addr: |
0000000011010953 (SCOM) 0000000013430198 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.SNP.MISC.GPU1_BAR | |||
| Constant(s): | ||||
| Comments: | BAR register defining GPU Mem addresses serviced by brick 1 connected to this stack. Note: This register should be set to the same value for each brick/stack. MDials have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:51 | PAU3.CS.SM3.SNP.MISC.GPU1_BAR_Q_0_INST.LATC.L2(0:51) [0000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_GPU1_BAR_ENABLE: Enable for this BAR (0=disabled, 1=enabled) for brick 1 | |
| 1:35 | RW | RW | CONFIG_GPU1_BAR_ADDR_MASK: BAR Address/Mask bits 1:35 for brick 1 In Small-BAR mode (see bit 36): 1:7 = Base_Addr(13:19) = 16T slice 8:21 = Base_Addr(20:33) = 1G address in slice 22:35 = Base_Mask(20:33) = 1G...16T BAR size. (Note: Mask limited to 1G...4T in Axone and P10 w/ GPU systems) In Large-BAR mode (see bit 36): 1 = '1' to match MemSel = addr(13:14) = 0b00 2 = '1' to match MemSel = addr(13:14) = 0b01 3 = '1' to match MemSel = addr(13:14) = 0b10 4:35 = Topology_Id_Mask(0:31) when chip_eq_group=0, TIM(0:31) bit 'i' corresponds to addr(15:19) = 'i' when chip_eq_group=1, TIM(0:31) bit 'i' corresponds to (addr(15:16) & addr(19:21)) = 'i' | |
| 36 | RW | RW | CONFIG_GPU1_BAR_SL_MODE: 0/1 = Small-BAR/Large-BAR Mode selector | |
| 37 | RW | RW | CONFIG_GPU1_BAR_4T_LIMIT: 0 = no limit, 16T slices can be used. 1 = limit slices to 4T. -> when chip_eq_group=0, addr(20:21) must match bar_4t_select -> when chip_eq_group=1, addr(17:18) must match bar_4t_select limit=1 is used in P10 systems w/ a GPU or in Axone systems | |
| 38:39 | RW | RW | CONFIG_GPU1_BAR_4T_SELECT: when bar_4t_limit=1 this field selects the value in addr(20:21) to match | |
| 40:43 | RW | RW | CONFIG_GPU1_BAR_MODE: Hash mode of the BAR for brick 1: if bar_extended_mode == 0: 0 = (single) match on all address in addr/size 1 = (dual.0) match if hashbits(7)=0 2 = (dual.1) match if hashbits(7)=1 3 = (triple.0) match if hashbits%3=0 4 = (triple.1) match if hashbits%3=1 5 = (triple.2) match if hashbits%3=2 6 = (quad.0) match if hashbits(6:7)=0 7 = (quad.1) match if hashbits(6:7)=1 8 = (quad.2) match if hashbits(6:7)=2 9 = (quad.3) match if hashbits(6:7)=3 10 = (six.0) match if hashbits%3=0 and hashbits(7)=0 11 = (six.1) match if hashbits%3=0 and hashbits(7)=1 12 = (six.2) match if hashbits%3=1 and hashbits(7)=0 13 = (six.3) match if hashbits%3=1 and hashbits(7)=1 14 = (six.4) match if hashbits%3=2 and hashbits(7)=0 15 = (six.5) match if hashbits%3=2 and hashbits(7)=1 if bar_extended_mode == 1: 0 = (oct.0) match if hashbits(5:7)=0 1 = (oct.1) match if hashbits(5:7)=1 2 = (oct.2) match if hashbits(5:7)=2 3 = (oct.3) match if hashbits(5:7)=3 4 = (oct.4) match if hashbits(5:7)=4 5 = (oct.5) match if hashbits(5:7)=5 6 = (oct.6) match if hashbits(5:7)=6 7 = (oct.7) match if hashbits(5:7)=7 others = reserved | |
| 44 | RW | RW | CONFIG_GPU1_BAR_GRANULE: Hash boundary for brick 1: 0 = hash on 512B boundary (hashbits(0:7)=addr(47:54)) 1 = hash on 1024B boundary (hashbits(0:7)=addr(46:53)) | |
| 45 | RW | RW | CONFIG_GPU1_BAR_POISON: on failed access return all ones 0/1 = with good ECC / with SUE ECC. | |
| 46 | RW | RW | CONFIG_GPU1_BAR_M2MODE: 0 = OpenCAPI AFU M1 mode / 1 = OpenCAPI AFU M2 mode Has no effect when in NVLink mode | |
| 47 | RW | RW | CONFIG_GPU1_BAR_PA_IGNORE_MODE: Set to '1' for RA-to-PA conversion to ignore the mode field | |
| 48 | RW | RW | CONFIG_GPU1_BAR_SECURE_A12: P10 Only: this specifies the addr(12) value to match for this BAR. Can only be set to one in P10 and only when SMF_CONFIG=0b11. | |
| 49 | RW | RW | CONFIG_GPU1_BAR_CHIP_EQ_GROUP: Axone Only: this specifies that the system is in chip=group mode. This bit should only be set when sl_mode=1 and 4t_limit=1. 0/1 = TIM(0:31) applies to addr(15:19) / TIM(0:31) applies to (addr(15:16) & addr(19:21)). | |
| 50 | RW | RW | CONFIG_GPU1_BAR_EXTENDED_MODE: 0/1 = bar_mode selects 1,2,3,4,6 way hashing / bar_mode selects 8-way hashing | |
| 51 | RW | RW | CONFIG_GPU1_BAR_RESERVED: reserved | |
| 52:63 | RO | RO | constant=0b000000000000 | |
| GPU2-Memory BAR | ||||
|---|---|---|---|---|
| Addr: |
0000000011010954 (SCOM) 00000000134301A0 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.SNP.MISC.GPU2_BAR | |||
| Constant(s): | ||||
| Comments: | BAR register defining GPU Mem addresses serviced by brick 2 connected to this stack. Note: This register should be set to the same value for each brick/stack. MDials have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:51 | PAU3.CS.SM3.SNP.MISC.GPU2_BAR_Q_0_INST.LATC.L2(0:51) [0000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_GPU2_BAR_ENABLE: Enable for this BAR (0=disabled, 1=enabled) for brick 2 | |
| 1:35 | RW | RW | CONFIG_GPU2_BAR_ADDR_MASK: BAR Address/Mask bits 1:35 for brick 2 In Small-BAR mode (see bit 36): 1:7 = Base_Addr(13:19) = 16T slice 8:21 = Base_Addr(20:33) = 1G address in slice 22:35 = Base_Mask(20:33) = 1G...16T BAR size. (Note: Mask limited to 1G...4T in Axone and P10 w/ GPU systems) In Large-BAR mode (see bit 36): 1 = '1' to match MemSel = addr(13:14) = 0b00 2 = '1' to match MemSel = addr(13:14) = 0b01 3 = '1' to match MemSel = addr(13:14) = 0b10 4:35 = Topology_Id_Mask(0:31) when chip_eq_group=0, TIM(0:31) bit 'i' corresponds to addr(15:19) = 'i' when chip_eq_group=1, TIM(0:31) bit 'i' corresponds to (addr(15:16) & addr(19:21)) = 'i' | |
| 36 | RW | RW | CONFIG_GPU2_BAR_SL_MODE: 0/1 = Small-BAR/Large-BAR Mode selector | |
| 37 | RW | RW | CONFIG_GPU2_BAR_4T_LIMIT: 0 = no limit, 16T slices can be used. 1 = limit slices to 4T. -> when chip_eq_group=0, addr(20:21) must match bar_4t_select -> when chip_eq_group=1, addr(17:18) must match bar_4t_select limit=1 is used in P10 systems w/ a GPU or in Axone systems | |
| 38:39 | RW | RW | CONFIG_GPU2_BAR_4T_SELECT: when bar_4t_limit=1 this field selects the value in addr(20:21) to match | |
| 40:43 | RW | RW | CONFIG_GPU2_BAR_MODE: Hash mode of the BAR for brick 2: if bar_extended_mode == 0: 0 = (single) match on all address in addr/size 1 = (dual.0) match if hashbits(7)=0 2 = (dual.1) match if hashbits(7)=1 3 = (triple.0) match if hashbits%3=0 4 = (triple.1) match if hashbits%3=1 5 = (triple.2) match if hashbits%3=2 6 = (quad.0) match if hashbits(6:7)=0 7 = (quad.1) match if hashbits(6:7)=1 8 = (quad.2) match if hashbits(6:7)=2 9 = (quad.3) match if hashbits(6:7)=3 10 = (six.0) match if hashbits%3=0 and hashbits(7)=0 11 = (six.1) match if hashbits%3=0 and hashbits(7)=1 12 = (six.2) match if hashbits%3=1 and hashbits(7)=0 13 = (six.3) match if hashbits%3=1 and hashbits(7)=1 14 = (six.4) match if hashbits%3=2 and hashbits(7)=0 15 = (six.5) match if hashbits%3=2 and hashbits(7)=1 if bar_extended_mode == 1: 0 = (oct.0) match if hashbits(5:7)=0 1 = (oct.1) match if hashbits(5:7)=1 2 = (oct.2) match if hashbits(5:7)=2 3 = (oct.3) match if hashbits(5:7)=3 4 = (oct.4) match if hashbits(5:7)=4 5 = (oct.5) match if hashbits(5:7)=5 6 = (oct.6) match if hashbits(5:7)=6 7 = (oct.7) match if hashbits(5:7)=7 others = reserved | |
| 44 | RW | RW | CONFIG_GPU2_BAR_GRANULE: Hash boundary for brick 2: 0 = hash on 512B boundary (hashbits(0:7)=addr(47:54)) 1 = hash on 1024B boundary (hashbits(0:7)=addr(46:53)) | |
| 45 | RW | RW | CONFIG_GPU2_BAR_POISON: on failed access return all ones 0/1 = with good ECC / with SUE ECC. | |
| 46 | RW | RW | CONFIG_GPU2_BAR_M2MODE: 0 = OpenCAPI AFU M1 mode / 1 = OpenCAPI AFU M2 mode Has no effect when in NVLink mode | |
| 47 | RW | RW | CONFIG_GPU2_BAR_PA_IGNORE_MODE: Set to '1' for RA-to-PA conversion to ignore the mode field | |
| 48 | RW | RW | CONFIG_GPU2_BAR_SECURE_A12: P10 Only: this specifies the addr(12) value to match for this BAR. Can only be set to one in P10 and only when SMF_CONFIG=0b11. | |
| 49 | RW | RW | CONFIG_GPU2_BAR_CHIP_EQ_GROUP: Axone Only: this specifies that the system is in chip=group mode. This bit should only be set when sl_mode=1 and 4t_limit=1. 0/1 = TIM(0:31) applies to addr(15:19) / TIM(0:31) applies to (addr(15:16) & addr(19:21)). | |
| 50 | RW | RW | CONFIG_GPU2_BAR_EXTENDED_MODE: 0/1 = bar_mode selects 1,2,3,4,6 way hashing / bar_mode selects 8-way hashing | |
| 51 | RW | RW | CONFIG_GPU2_BAR_RESERVED: reserved | |
| 52:63 | RO | RO | constant=0b000000000000 | |
| GPU3-Memory BAR | ||||
|---|---|---|---|---|
| Addr: |
0000000011010955 (SCOM) 00000000134301A8 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.SNP.MISC.GPU3_BAR | |||
| Constant(s): | ||||
| Comments: | BAR register defining GPU Mem addresses serviced by brick 3 connected to this stack. Note: This register should be set to the same value for each brick/stack. MDials have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:51 | PAU3.CS.SM3.SNP.MISC.GPU3_BAR_Q_0_INST.LATC.L2(0:51) [0000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_GPU3_BAR_ENABLE: Enable for this BAR (0=disabled, 1=enabled) for brick 3 | |
| 1:35 | RW | RW | CONFIG_GPU3_BAR_ADDR_MASK: BAR Address/Mask bits 1:35 for brick 3 In Small-BAR mode (see bit 36): 1:7 = Base_Addr(13:19) = 16T slice 8:21 = Base_Addr(20:33) = 1G address in slice 22:35 = Base_Mask(20:33) = 1G...16T BAR size. (Note: Mask limited to 1G...4T in Axone and P10 w/ GPU systems) In Large-BAR mode (see bit 36): 1 = '1' to match MemSel = addr(13:14) = 0b00 2 = '1' to match MemSel = addr(13:14) = 0b01 3 = '1' to match MemSel = addr(13:14) = 0b10 4:35 = Topology_Id_Mask(0:31) when chip_eq_group=0, TIM(0:31) bit 'i' corresponds to addr(15:19) = 'i' when chip_eq_group=1, TIM(0:31) bit 'i' corresponds to (addr(15:16) & addr(19:21)) = 'i' | |
| 36 | RW | RW | CONFIG_GPU3_BAR_SL_MODE: 0/1 = Small-BAR/Large-BAR Mode selector | |
| 37 | RW | RW | CONFIG_GPU3_BAR_4T_LIMIT: 0 = no limit, 16T slices can be used. 1 = limit slices to 4T. -> when chip_eq_group=0, addr(20:21) must match bar_4t_select -> when chip_eq_group=1, addr(17:18) must match bar_4t_select limit=1 is used in P10 systems w/ a GPU or in Axone systems | |
| 38:39 | RW | RW | CONFIG_GPU3_BAR_4T_SELECT: when bar_4t_limit=1 this field selects the value in addr(20:21) to match | |
| 40:43 | RW | RW | CONFIG_GPU3_BAR_MODE: Hash mode of the BAR for brick 3: if bar_extended_mode == 0: 0 = (single) match on all address in addr/size 1 = (dual.0) match if hashbits(7)=0 2 = (dual.1) match if hashbits(7)=1 3 = (triple.0) match if hashbits%3=0 4 = (triple.1) match if hashbits%3=1 5 = (triple.2) match if hashbits%3=2 6 = (quad.0) match if hashbits(6:7)=0 7 = (quad.1) match if hashbits(6:7)=1 8 = (quad.2) match if hashbits(6:7)=2 9 = (quad.3) match if hashbits(6:7)=3 10 = (six.0) match if hashbits%3=0 and hashbits(7)=0 11 = (six.1) match if hashbits%3=0 and hashbits(7)=1 12 = (six.2) match if hashbits%3=1 and hashbits(7)=0 13 = (six.3) match if hashbits%3=1 and hashbits(7)=1 14 = (six.4) match if hashbits%3=2 and hashbits(7)=0 15 = (six.5) match if hashbits%3=2 and hashbits(7)=1 if bar_extended_mode == 1: 0 = (oct.0) match if hashbits(5:7)=0 1 = (oct.1) match if hashbits(5:7)=1 2 = (oct.2) match if hashbits(5:7)=2 3 = (oct.3) match if hashbits(5:7)=3 4 = (oct.4) match if hashbits(5:7)=4 5 = (oct.5) match if hashbits(5:7)=5 6 = (oct.6) match if hashbits(5:7)=6 7 = (oct.7) match if hashbits(5:7)=7 others = reserved | |
| 44 | RW | RW | CONFIG_GPU3_BAR_GRANULE: Hash boundary for brick 3: 0 = hash on 512B boundary (hashbits(0:7)=addr(47:54)) 1 = hash on 1024B boundary (hashbits(0:7)=addr(46:53)) | |
| 45 | RW | RW | CONFIG_GPU3_BAR_POISON: on failed access return all ones 0/1 = with good ECC / with SUE ECC. | |
| 46 | RW | RW | CONFIG_GPU3_BAR_M2MODE: 0 = OpenCAPI AFU M1 mode / 1 = OpenCAPI AFU M2 mode Has no effect when in NVLink mode | |
| 47 | RW | RW | CONFIG_GPU3_BAR_PA_IGNORE_MODE: Set to '1' for RA-to-PA conversion to ignore the mode field | |
| 48 | RW | RW | CONFIG_GPU3_BAR_SECURE_A12: P10 Only: this specifies the addr(12) value to match for this BAR. Can only be set to one in P10 and only when SMF_CONFIG=0b11. | |
| 49 | RW | RW | CONFIG_GPU3_BAR_CHIP_EQ_GROUP: Axone Only: this specifies that the system is in chip=group mode. This bit should only be set when sl_mode=1 and 4t_limit=1. 0/1 = TIM(0:31) applies to addr(15:19) / TIM(0:31) applies to (addr(15:16) & addr(19:21)). | |
| 50 | RW | RW | CONFIG_GPU3_BAR_EXTENDED_MODE: 0/1 = bar_mode selects 1,2,3,4,6 way hashing / bar_mode selects 8-way hashing | |
| 51 | RW | RW | CONFIG_GPU3_BAR_RESERVED: reserved | |
| 52:63 | RO | RO | constant=0b000000000000 | |
| GPU4-Memory BAR | ||||
|---|---|---|---|---|
| Addr: |
0000000011010956 (SCOM) 00000000134301B0 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.SNP.MISC.GPU4_BAR | |||
| Constant(s): | ||||
| Comments: | BAR register defining GPU Mem addresses serviced by brick 4 connected to this stack. Note: This register should be set to the same value for each brick/stack. MDials have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:51 | PAU3.CS.SM3.SNP.MISC.GPU4_BAR_Q_0_INST.LATC.L2(0:51) [0000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_GPU4_BAR_ENABLE: Enable for this BAR (0=disabled, 1=enabled) for brick 4 | |
| 1:35 | RW | RW | CONFIG_GPU4_BAR_ADDR_MASK: BAR Address/Mask bits 1:35 for brick 4 In Small-BAR mode (see bit 36): 1:7 = Base_Addr(13:19) = 16T slice 8:21 = Base_Addr(20:33) = 1G address in slice 22:35 = Base_Mask(20:33) = 1G...16T BAR size. (Note: Mask limited to 1G...4T in Axone and P10 w/ GPU systems) In Large-BAR mode (see bit 36): 1 = '1' to match MemSel = addr(13:14) = 0b00 2 = '1' to match MemSel = addr(13:14) = 0b01 3 = '1' to match MemSel = addr(13:14) = 0b10 4:35 = Topology_Id_Mask(0:31) when chip_eq_group=0, TIM(0:31) bit 'i' corresponds to addr(15:19) = 'i' when chip_eq_group=1, TIM(0:31) bit 'i' corresponds to (addr(15:16) & addr(19:21)) = 'i' | |
| 36 | RW | RW | CONFIG_GPU4_BAR_SL_MODE: 0/1 = Small-BAR/Large-BAR Mode selector | |
| 37 | RW | RW | CONFIG_GPU4_BAR_4T_LIMIT: 0 = no limit, 16T slices can be used. 1 = limit slices to 4T. -> when chip_eq_group=0, addr(20:21) must match bar_4t_select -> when chip_eq_group=1, addr(17:18) must match bar_4t_select limit=1 is used in P10 systems w/ a GPU or in Axone systems | |
| 38:39 | RW | RW | CONFIG_GPU4_BAR_4T_SELECT: when bar_4t_limit=1 this field selects the value in addr(20:21) to match | |
| 40:43 | RW | RW | CONFIG_GPU4_BAR_MODE: Hash mode of the BAR for brick 4: if bar_extended_mode == 0: 0 = (single) match on all address in addr/size 1 = (dual.0) match if hashbits(7)=0 2 = (dual.1) match if hashbits(7)=1 3 = (triple.0) match if hashbits%3=0 4 = (triple.1) match if hashbits%3=1 5 = (triple.2) match if hashbits%3=2 6 = (quad.0) match if hashbits(6:7)=0 7 = (quad.1) match if hashbits(6:7)=1 8 = (quad.2) match if hashbits(6:7)=2 9 = (quad.3) match if hashbits(6:7)=3 10 = (six.0) match if hashbits%3=0 and hashbits(7)=0 11 = (six.1) match if hashbits%3=0 and hashbits(7)=1 12 = (six.2) match if hashbits%3=1 and hashbits(7)=0 13 = (six.3) match if hashbits%3=1 and hashbits(7)=1 14 = (six.4) match if hashbits%3=2 and hashbits(7)=0 15 = (six.5) match if hashbits%3=2 and hashbits(7)=1 if bar_extended_mode == 1: 0 = (oct.0) match if hashbits(5:7)=0 1 = (oct.1) match if hashbits(5:7)=1 2 = (oct.2) match if hashbits(5:7)=2 3 = (oct.3) match if hashbits(5:7)=3 4 = (oct.4) match if hashbits(5:7)=4 5 = (oct.5) match if hashbits(5:7)=5 6 = (oct.6) match if hashbits(5:7)=6 7 = (oct.7) match if hashbits(5:7)=7 others = reserved | |
| 44 | RW | RW | CONFIG_GPU4_BAR_GRANULE: Hash boundary for brick 4: 0 = hash on 512B boundary (hashbits(0:7)=addr(47:54)) 1 = hash on 1024B boundary (hashbits(0:7)=addr(46:53)) | |
| 45 | RW | RW | CONFIG_GPU4_BAR_POISON: on failed access return all ones 0/1 = with good ECC / with SUE ECC. | |
| 46 | RW | RW | CONFIG_GPU4_BAR_M2MODE: 0 = OpenCAPI AFU M1 mode / 1 = OpenCAPI AFU M2 mode Has no effect when in NVLink mode | |
| 47 | RW | RW | CONFIG_GPU4_BAR_PA_IGNORE_MODE: Set to '1' for RA-to-PA conversion to ignore the mode field | |
| 48 | RW | RW | CONFIG_GPU4_BAR_SECURE_A12: P10 Only: this specifies the addr(12) value to match for this BAR. Can only be set to one in P10 and only when SMF_CONFIG=0b11. | |
| 49 | RW | RW | CONFIG_GPU4_BAR_CHIP_EQ_GROUP: Axone Only: this specifies that the system is in chip=group mode. This bit should only be set when sl_mode=1 and 4t_limit=1. 0/1 = TIM(0:31) applies to addr(15:19) / TIM(0:31) applies to (addr(15:16) & addr(19:21)). | |
| 50 | RW | RW | CONFIG_GPU4_BAR_EXTENDED_MODE: 0/1 = bar_mode selects 1,2,3,4,6 way hashing / bar_mode selects 8-way hashing | |
| 51 | RW | RW | CONFIG_GPU4_BAR_RESERVED: reserved | |
| 52:63 | RO | RO | constant=0b000000000000 | |
| NTL0/NDL0 MMIO BAR | ||||
|---|---|---|---|---|
| Addr: |
0000000011010957 (SCOM) 00000000134301B8 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.SNP.MISC.NDT0_BAR | |||
| Constant(s): | ||||
| Comments: | BAR register defining NDL/NTL MMIO (NVLink) or AFU MMIO (OpenCAPI) range for brick 0 connected to this stack Note: This register should be set to the same value for each brick/stack. MDials have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:43 | PAU3.CS.SM3.SNP.MISC.NDT0_BAR_Q_0_INST.LATC.L2(0:43) [00000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_NDT0_BAR_ENABLE: 0/1 = disable/enable BAR for brick 0 | |
| 1 | RW | RW | CONFIG_NDT0_BAR_SECURE_A12: P10 Only: this specifies the addr(12) value to match for this BAR. Can only be set to one in P10 and only when SMF_CONFIG=0b11. | |
| 2 | RW | RW | NDT0_RESERVED1: reserved | |
| 3:35 | RW | RW | CONFIG_NDT0_BAR_ADDR: 64K aligned address of BAR for brick 0's 64K range | |
| 36 | RW | RW | CONFIG_NDT0_BAR_POISON: on failed access return all ones 0/1 = with good ECC / with SUE ECC. | |
| 37:38 | RW | RW | NDT0_RESERVED2: reserved | |
| 39:43 | RW | RW | CONFIG_NDT0_BAR_SIZE: Size of BAR region. 0 = 64K 1 = 128K (NVLink must select this size) 2 = 256K ... 26 = 4T others = reserved | |
| 44:63 | RO | RO | constant=0b00000000000000000000 | |
| NTL1/NDL1 MMIO BAR | ||||
|---|---|---|---|---|
| Addr: |
0000000011010958 (SCOM) 00000000134301C0 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.SNP.MISC.NDT1_BAR | |||
| Constant(s): | ||||
| Comments: | BAR register defining NDL/NTL MMIO (NVLink) or AFU MMIO (OpenCAPI) range for brick 1 connected to this stack Note: This register should be set to the same value for each brick/stack. MDials have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:43 | PAU3.CS.SM3.SNP.MISC.NDT1_BAR_Q_0_INST.LATC.L2(0:43) [00000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_NDT1_BAR_ENABLE: 0/1 = disable/enable BAR for brick 1 | |
| 1 | RW | RW | CONFIG_NDT1_BAR_SECURE_A12: P10 Only: this specifies the addr(12) value to match for this BAR. Can only be set to one in P10 and only when SMF_CONFIG=0b11. | |
| 2 | RW | RW | NDT1_RESERVED1: reserved | |
| 3:35 | RW | RW | CONFIG_NDT1_BAR_ADDR: 64K aligned address of BAR for brick 1's 64K range | |
| 36 | RW | RW | CONFIG_NDT1_BAR_POISON: on failed access return all ones 0/1 = with good ECC / with SUE ECC. | |
| 37:38 | RW | RW | NDT1_RESERVED2: reserved | |
| 39:43 | RW | RW | CONFIG_NDT1_BAR_SIZE: Size of BAR region. 0 = 64K 1 = 128K (NVLink must select this size) 2 = 256K ... 26 = 4T others = reserved | |
| 44:63 | RO | RO | constant=0b00000000000000000000 | |
| NTL2/NDL2 MMIO BAR | ||||
|---|---|---|---|---|
| Addr: |
0000000011010959 (SCOM) 00000000134301C8 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.SNP.MISC.NDT2_BAR | |||
| Constant(s): | ||||
| Comments: | BAR register defining NDL/NTL MMIO (NVLink) or AFU MMIO (OpenCAPI) range for brick 2 connected to this stack Note: This register should be set to the same value for each brick/stack. MDials have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:43 | PAU3.CS.SM3.SNP.MISC.NDT2_BAR_Q_0_INST.LATC.L2(0:43) [00000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_NDT2_BAR_ENABLE: 0/1 = disable/enable BAR for brick 2 | |
| 1 | RW | RW | CONFIG_NDT2_BAR_SECURE_A12: P10 Only: this specifies the addr(12) value to match for this BAR. Can only be set to one in P10 and only when SMF_CONFIG=0b11. | |
| 2 | RW | RW | NDT2_RESERVED1: reserved | |
| 3:35 | RW | RW | CONFIG_NDT2_BAR_ADDR: 64K aligned address of BAR for brick 2's 64K range | |
| 36 | RW | RW | CONFIG_NDT2_BAR_POISON: on failed access return all ones 0/1 = with good ECC / with SUE ECC. | |
| 37:38 | RW | RW | NDT2_RESERVED2: reserved | |
| 39:43 | RW | RW | CONFIG_NDT2_BAR_SIZE: Size of BAR region. 0 = 64K 1 = 128K (NVLink must select this size) 2 = 256K ... 26 = 4T others = reserved | |
| 44:63 | RO | RO | constant=0b00000000000000000000 | |
| NTL3/NDL3 MMIO BAR | ||||
|---|---|---|---|---|
| Addr: |
000000001101095A (SCOM) 00000000134301D0 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.SNP.MISC.NDT3_BAR | |||
| Constant(s): | ||||
| Comments: | BAR register defining NDL/NTL MMIO (NVLink) or AFU MMIO (OpenCAPI) range for brick 3 connected to this stack Note: This register should be set to the same value for each brick/stack. MDials have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:43 | PAU3.CS.SM3.SNP.MISC.NDT3_BAR_Q_0_INST.LATC.L2(0:43) [00000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_NDT3_BAR_ENABLE: 0/1 = disable/enable BAR for brick 3 | |
| 1 | RW | RW | CONFIG_NDT3_BAR_SECURE_A12: P10 Only: this specifies the addr(12) value to match for this BAR. Can only be set to one in P10 and only when SMF_CONFIG=0b11. | |
| 2 | RW | RW | NDT3_RESERVED1: reserved | |
| 3:35 | RW | RW | CONFIG_NDT3_BAR_ADDR: 64K aligned address of BAR for brick 3's 64K range | |
| 36 | RW | RW | CONFIG_NDT3_BAR_POISON: on failed access return all ones 0/1 = with good ECC / with SUE ECC. | |
| 37:38 | RW | RW | NDT3_RESERVED2: reserved | |
| 39:43 | RW | RW | CONFIG_NDT3_BAR_SIZE: Size of BAR region. 0 = 64K 1 = 128K (NVLink must select this size) 2 = 256K ... 26 = 4T others = reserved | |
| 44:63 | RO | RO | constant=0b00000000000000000000 | |
| NTL4/NDL4 MMIO BAR | ||||
|---|---|---|---|---|
| Addr: |
000000001101095B (SCOM) 00000000134301D8 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.SNP.MISC.NDT4_BAR | |||
| Constant(s): | ||||
| Comments: | BAR register defining NDL/NTL MMIO (NVLink) or AFU MMIO (OpenCAPI) range for brick 4 connected to this stack Note: This register should be set to the same value for each brick/stack. MDials have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:43 | PAU3.CS.SM3.SNP.MISC.NDT4_BAR_Q_0_INST.LATC.L2(0:43) [00000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_NDT4_BAR_ENABLE: 0/1 = disable/enable BAR for brick 4 | |
| 1 | RW | RW | CONFIG_NDT4_BAR_SECURE_A12: P10 Only: this specifies the addr(12) value to match for this BAR. Can only be set to one in P10 and only when SMF_CONFIG=0b11. | |
| 2 | RW | RW | NDT4_RESERVED1: reserved | |
| 3:35 | RW | RW | CONFIG_NDT4_BAR_ADDR: 64K aligned address of BAR for brick 4's 64K range | |
| 36 | RW | RW | CONFIG_NDT4_BAR_POISON: on failed access return all ones 0/1 = with good ECC / with SUE ECC. | |
| 37:38 | RW | RW | NDT4_RESERVED2: reserved | |
| 39:43 | RW | RW | CONFIG_NDT4_BAR_SIZE: Size of BAR region. 0 = 64K 1 = 128K (NVLink must select this size) 2 = 256K ... 26 = 4T others = reserved | |
| 44:63 | RO | RO | constant=0b00000000000000000000 | |
| PAU MMIO BAR | ||||
|---|---|---|---|---|
| Addr: |
000000001101095C (SCOM) 00000000134301E0 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.SNP.MISC.PAUMMIO_BAR | |||
| Constant(s): | ||||
| Comments: | BAR register definingPAU MMIO range Note: This register should be set to the same value for each brick/stack. MDials have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:31 | PAU3.CS.SM3.SNP.MISC.PAUMMIO_BAR_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_PAUMMIO_BAR_ENABLE: 0/1 = disable/enable PAUMMIO_BAR | |
| 1 | RW | RW | CONFIG_PAUMMIO_BAR_SECURE_A12: P10 Only: this specifies the addr(12) value to match for this BAR. Can only be set to one in P10 and only when SMF_CONFIG=0b11. | |
| 2 | RW | RW | PAUMMIO_RESERVED1: reserved | |
| 3:27 | RW | RW | CONFIG_PAUMMIO_BAR_ADDR: 16M aligned address of this PAUMMIO_BAR's 16M range. Bits 15:39 of the RA | |
| 28:30 | RW | RW | PAUMMIO_RESERVED2: reserved | |
| 31 | RW | RW | CONFIG_PAUMMIO_BAR_POISON: On failed access return all ones 0/1 = with good ECC / with SUE ECC. | |
| 32:63 | RO | RO | constant=0b00000000000000000000000000000000 | |
| Generation-ID Registers MMIO BAR | ||||
|---|---|---|---|---|
| Addr: |
000000001101095D (SCOM) 00000000134301E8 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.SNP.MISC.GENID_BAR | |||
| Constant(s): | ||||
| Comments: | NVLink mode: BAR register defining Generation-ID registers for this stack/ramp OCAPI mode: BAR register defining Config space + Generation-ID registers registers for this stack/ramp Note: This register should be set to the same value for each brick/stack. MDials have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:35 | PAU3.CS.SM3.SNP.MISC.GENID_BAR_Q_0_INST.LATC.L2(0:35) [000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_GENID_BAR_ENABLE: 0/1 = disable/enable this BAR | |
| 1 | RW | RW | CONFIG_GENID_BAR_SECURE_A12: P10 Only: this specifies the addr(12) value to match for this BAR. Can only be set to one in P10 and only when SMF_CONFIG=0b11. | |
| 2 | RW | RW | GENID_RESERVED1: reserved | |
| 3:32 | RW | RW | CONFIG_GENID_BAR_ADDR: 512K aligned address +0K = Brick 0 Gen-Id Registers +64K = Brick 1 Gen-Id Registers +128K = Brick 2 Gen-Id Registers +192K = Brick 3 Gen-Id Registers +256K = Brick 4 Gen-Id Registers +320K = Bricks 0-4 Config Addr/Data registers for OCAPI links +384K = reserved +448K = reserved | |
| 33:34 | RW | RW | GENID_RESERVED2: reserved | |
| 35 | RW | RW | CONFIG_GENID_BAR_POISON: on failed access return all ones 0/1 = with good ECC / with SUE ECC. | |
| 36:63 | RO | RO | constant=0b0000000000000000000000000000 | |
| Relexed-Ordering Source 0 Config | ||||
|---|---|---|---|---|
| Addr: |
000000001101095E (SCOM) 00000000134301F0 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.SNP.MISC.CONFIG_RELAXED_SRC0 | |||
| Constant(s): | ||||
| Comments: | Configure relaxed-ordering source Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM3.SNP.MISC.CONFIG_RELAXED_SRC0_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:13 | RW | RW | CONFIG_RELAXED_SOURCE0_TAG: P10: Match against ('00' & ttag(0:11)). | |
| 14:27 | RW | RW | CONFIG_RELAXED_SOURCE0_TAGMASK: Mask on tag(0:13). 0=must-match, 1=don't-care. | |
| 28 | RW | RW | CONFIG_RELAXED_SOURCE0_MASK_PAU: P10: match ttag(7:9)=000,001,111 | |
| 29 | RW | RW | CONFIG_RELAXED_SOURCE0_MASK_PCIE: P10: reserved | |
| 30 | RW | RW | CONFIG_RELAXED_SOURCE0_MASK_L2L3: P10: reserved | |
| 31 | RW | RW | CONFIG_RELAXED_SOURCE0_RESERVED1: reserved | |
| 32:39 | RW | RW | CONFIG_RELAXED_SOURCE0_RDSTART: P10: ttag(12:19) start-of-read-tags value (first tag) | |
| 40:47 | RW | RW | CONFIG_RELAXED_SOURCE0_RDEND: P10: ttag(12:19) end-of-read-tags value (last tag) | |
| 48:55 | RW | RW | CONFIG_RELAXED_SOURCE0_WRSTART: P10: ttag(12:19) start-of-write-tags value (first tag) | |
| 56:63 | RW | RW | CONFIG_RELAXED_SOURCE0_WREND: P10: ttag(12:19) end-of-write-tags value (last tag) | |
| Relexed-Ordering Source 1 Config | ||||
|---|---|---|---|---|
| Addr: |
000000001101095F (SCOM) 00000000134301F8 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.SNP.MISC.CONFIG_RELAXED_SRC1 | |||
| Constant(s): | ||||
| Comments: | Configure relaxed-ordering source Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM3.SNP.MISC.CONFIG_RELAXED_SRC1_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:13 | RW | RW | CONFIG_RELAXED_SOURCE1_TAG: P10: Match against ('00' & ttag(0:11)). | |
| 14:27 | RW | RW | CONFIG_RELAXED_SOURCE1_TAGMASK: Mask on tag(0:13). 0=must-match, 1=don't-care. | |
| 28 | RW | RW | CONFIG_RELAXED_SOURCE1_MASK_PAU: P10: match ttag(7:9)=000,001,111 | |
| 29 | RW | RW | CONFIG_RELAXED_SOURCE1_MASK_PCIE: P10: reserved | |
| 30 | RW | RW | CONFIG_RELAXED_SOURCE1_MASK_L2L3: P10: reserved | |
| 31 | RW | RW | CONFIG_RELAXED_SOURCE1_RESERVED1: reserved | |
| 32:39 | RW | RW | CONFIG_RELAXED_SOURCE1_RDSTART: P10: ttag(12:19) start-of-read-tags value (first tag) | |
| 40:47 | RW | RW | CONFIG_RELAXED_SOURCE1_RDEND: P10: ttag(12:19) end-of-read-tags value (last tag) | |
| 48:55 | RW | RW | CONFIG_RELAXED_SOURCE1_WRSTART: P10: ttag(12:19) start-of-write-tags value (first tag) | |
| 56:63 | RW | RW | CONFIG_RELAXED_SOURCE1_WREND: P10: ttag(12:19) end-of-write-tags value (last tag) | |
| Relexed-Ordering Source 2 Config | ||||
|---|---|---|---|---|
| Addr: |
0000000011010960 (SCOM) 0000000013430200 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.SNP.MISC.CONFIG_RELAXED_SRC2 | |||
| Constant(s): | ||||
| Comments: | Configure relaxed-ordering source Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM3.SNP.MISC.CONFIG_RELAXED_SRC2_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:13 | RW | RW | CONFIG_RELAXED_SOURCE2_TAG: P10: Match against ('00' & ttag(0:11)). | |
| 14:27 | RW | RW | CONFIG_RELAXED_SOURCE2_TAGMASK: Mask on tag(0:13). 0=must-match, 1=don't-care. | |
| 28 | RW | RW | CONFIG_RELAXED_SOURCE2_MASK_PAU: P10: match ttag(7:9)=000,001,111 | |
| 29 | RW | RW | CONFIG_RELAXED_SOURCE2_MASK_PCIE: P10: reserved | |
| 30 | RW | RW | CONFIG_RELAXED_SOURCE2_MASK_L2L3: P10: reserved | |
| 31 | RW | RW | CONFIG_RELAXED_SOURCE2_RESERVED1: reserved | |
| 32:39 | RW | RW | CONFIG_RELAXED_SOURCE2_RDSTART: P10: ttag(12:19) start-of-read-tags value (first tag) | |
| 40:47 | RW | RW | CONFIG_RELAXED_SOURCE2_RDEND: P10: ttag(12:19) end-of-read-tags value (last tag) | |
| 48:55 | RW | RW | CONFIG_RELAXED_SOURCE2_WRSTART: P10: ttag(12:19) start-of-write-tags value (first tag) | |
| 56:63 | RW | RW | CONFIG_RELAXED_SOURCE2_WREND: P10: ttag(12:19) end-of-write-tags value (last tag) | |
| Relexed-Ordering Source 3 Config | ||||
|---|---|---|---|---|
| Addr: |
0000000011010961 (SCOM) 0000000013430208 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.SNP.MISC.CONFIG_RELAXED_SRC3 | |||
| Constant(s): | ||||
| Comments: | Configure relaxed-ordering source Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM3.SNP.MISC.CONFIG_RELAXED_SRC3_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:13 | RW | RW | CONFIG_RELAXED_SOURCE3_TAG: P10: Match against ('00' & ttag(0:11)). | |
| 14:27 | RW | RW | CONFIG_RELAXED_SOURCE3_TAGMASK: Mask on tag(0:13). 0=must-match, 1=don't-care. | |
| 28 | RW | RW | CONFIG_RELAXED_SOURCE3_MASK_PAU: P10: match ttag(7:9)=000,001,111 | |
| 29 | RW | RW | CONFIG_RELAXED_SOURCE3_MASK_PCIE: P10: reserved | |
| 30 | RW | RW | CONFIG_RELAXED_SOURCE3_MASK_L2L3: P10: reserved | |
| 31 | RW | RW | CONFIG_RELAXED_SOURCE3_RESERVED1: reserved | |
| 32:39 | RW | RW | CONFIG_RELAXED_SOURCE3_RDSTART: P10: ttag(12:19) start-of-read-tags value (first tag) | |
| 40:47 | RW | RW | CONFIG_RELAXED_SOURCE3_RDEND: P10: ttag(12:19) end-of-read-tags value (last tag) | |
| 48:55 | RW | RW | CONFIG_RELAXED_SOURCE3_WRSTART: P10: ttag(12:19) start-of-write-tags value (first tag) | |
| 56:63 | RW | RW | CONFIG_RELAXED_SOURCE3_WREND: P10: ttag(12:19) end-of-write-tags value (last tag) | |
| Relexed-Ordering Source 4 Config | ||||
|---|---|---|---|---|
| Addr: |
0000000011010962 (SCOM) 0000000013430210 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.SNP.MISC.CONFIG_RELAXED_SRC4 | |||
| Constant(s): | ||||
| Comments: | Configure relaxed-ordering source Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM3.SNP.MISC.CONFIG_RELAXED_SRC4_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:13 | RW | RW | CONFIG_RELAXED_SOURCE4_TAG: P10: Match against ('00' & ttag(0:11)). | |
| 14:27 | RW | RW | CONFIG_RELAXED_SOURCE4_TAGMASK: Mask on tag(0:13). 0=must-match, 1=don't-care. | |
| 28 | RW | RW | CONFIG_RELAXED_SOURCE4_MASK_PAU: P10: match ttag(7:9)=000,001,111 | |
| 29 | RW | RW | CONFIG_RELAXED_SOURCE4_MASK_PCIE: P10: reserved | |
| 30 | RW | RW | CONFIG_RELAXED_SOURCE4_MASK_L2L3: P10: reserved | |
| 31 | RW | RW | CONFIG_RELAXED_SOURCE4_RESERVED1: reserved | |
| 32:39 | RW | RW | CONFIG_RELAXED_SOURCE4_RDSTART: P10: ttag(12:19) start-of-read-tags value (first tag) | |
| 40:47 | RW | RW | CONFIG_RELAXED_SOURCE4_RDEND: P10: ttag(12:19) end-of-read-tags value (last tag) | |
| 48:55 | RW | RW | CONFIG_RELAXED_SOURCE4_WRSTART: P10: ttag(12:19) start-of-write-tags value (first tag) | |
| 56:63 | RW | RW | CONFIG_RELAXED_SOURCE4_WREND: P10: ttag(12:19) end-of-write-tags value (last tag) | |
| Relexed-Ordering Source 5 Config | ||||
|---|---|---|---|---|
| Addr: |
0000000011010963 (SCOM) 0000000013430218 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.SNP.MISC.CONFIG_RELAXED_SRC5 | |||
| Constant(s): | ||||
| Comments: | Configure relaxed-ordering source Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM3.SNP.MISC.CONFIG_RELAXED_SRC5_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:13 | RW | RW | CONFIG_RELAXED_SOURCE5_TAG: P10: Match against ('00' & ttag(0:11)). | |
| 14:27 | RW | RW | CONFIG_RELAXED_SOURCE5_TAGMASK: Mask on tag(0:13). 0=must-match, 1=don't-care. | |
| 28 | RW | RW | CONFIG_RELAXED_SOURCE5_MASK_PAU: P10: match ttag(7:9)=000,001,111 | |
| 29 | RW | RW | CONFIG_RELAXED_SOURCE5_MASK_PCIE: P10: reserved | |
| 30 | RW | RW | CONFIG_RELAXED_SOURCE5_MASK_L2L3: P10: reserved | |
| 31 | RW | RW | CONFIG_RELAXED_SOURCE5_RESERVED1: reserved | |
| 32:39 | RW | RW | CONFIG_RELAXED_SOURCE5_RDSTART: P10: ttag(12:19) start-of-read-tags value (first tag) | |
| 40:47 | RW | RW | CONFIG_RELAXED_SOURCE5_RDEND: P10: ttag(12:19) end-of-read-tags value (last tag) | |
| 48:55 | RW | RW | CONFIG_RELAXED_SOURCE5_WRSTART: P10: ttag(12:19) start-of-write-tags value (first tag) | |
| 56:63 | RW | RW | CONFIG_RELAXED_SOURCE5_WREND: P10: ttag(12:19) end-of-write-tags value (last tag) | |
| Relexed-Ordering Source 6 Config | ||||
|---|---|---|---|---|
| Addr: |
0000000011010964 (SCOM) 0000000013430220 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.SNP.MISC.CONFIG_RELAXED_SRC6 | |||
| Constant(s): | ||||
| Comments: | Configure relaxed-ordering source Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM3.SNP.MISC.CONFIG_RELAXED_SRC6_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:13 | RW | RW | CONFIG_RELAXED_SOURCE6_TAG: P10: Match against ('00' & ttag(0:11)). | |
| 14:27 | RW | RW | CONFIG_RELAXED_SOURCE6_TAGMASK: Mask on tag(0:13). 0=must-match, 1=don't-care. | |
| 28 | RW | RW | CONFIG_RELAXED_SOURCE6_MASK_PAU: P10: match ttag(7:9)=000,001,111 | |
| 29 | RW | RW | CONFIG_RELAXED_SOURCE6_MASK_PCIE: P10: reserved | |
| 30 | RW | RW | CONFIG_RELAXED_SOURCE6_MASK_L2L3: P10: reserved | |
| 31 | RW | RW | CONFIG_RELAXED_SOURCE6_RESERVED1: reserved | |
| 32:39 | RW | RW | CONFIG_RELAXED_SOURCE6_RDSTART: P10: ttag(12:19) start-of-read-tags value (first tag) | |
| 40:47 | RW | RW | CONFIG_RELAXED_SOURCE6_RDEND: P10: ttag(12:19) end-of-read-tags value (last tag) | |
| 48:55 | RW | RW | CONFIG_RELAXED_SOURCE6_WRSTART: P10: ttag(12:19) start-of-write-tags value (first tag) | |
| 56:63 | RW | RW | CONFIG_RELAXED_SOURCE6_WREND: P10: ttag(12:19) end-of-write-tags value (last tag) | |
| Relexed-Ordering Source 7 Config | ||||
|---|---|---|---|---|
| Addr: |
0000000011010965 (SCOM) 0000000013430228 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.SNP.MISC.CONFIG_RELAXED_SRC7 | |||
| Constant(s): | ||||
| Comments: | Configure relaxed-ordering source Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM3.SNP.MISC.CONFIG_RELAXED_SRC7_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:13 | RW | RW | CONFIG_RELAXED_SOURCE7_TAG: P10: Match against ('00' & ttag(0:11)). | |
| 14:27 | RW | RW | CONFIG_RELAXED_SOURCE7_TAGMASK: Mask on tag(0:13). 0=must-match, 1=don't-care. | |
| 28 | RW | RW | CONFIG_RELAXED_SOURCE7_MASK_PAU: P10: match ttag(7:9)=000,001,111 | |
| 29 | RW | RW | CONFIG_RELAXED_SOURCE7_MASK_PCIE: P10: reserved | |
| 30 | RW | RW | CONFIG_RELAXED_SOURCE7_MASK_L2L3: P10: reserved | |
| 31 | RW | RW | CONFIG_RELAXED_SOURCE7_RESERVED1: reserved | |
| 32:39 | RW | RW | CONFIG_RELAXED_SOURCE7_RDSTART: P10: ttag(12:19) start-of-read-tags value (first tag) | |
| 40:47 | RW | RW | CONFIG_RELAXED_SOURCE7_RDEND: P10: ttag(12:19) end-of-read-tags value (last tag) | |
| 48:55 | RW | RW | CONFIG_RELAXED_SOURCE7_WRSTART: P10: ttag(12:19) start-of-write-tags value (first tag) | |
| 56:63 | RW | RW | CONFIG_RELAXED_SOURCE7_WREND: P10: ttag(12:19) end-of-write-tags value (last tag) | |
| Relaxed-Ordering Config2 brick 0 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010966 (SCOM) 0000000013430230 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.SNP.MISC.CONFIG_RELAXED_BRK0 | |||
| Constant(s): | ||||
| Comments: | Configure relaxed-ordering Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM3.SNP.MISC.CONFIG_RELAXED_BRK0_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_RELAXED_BRK0_CMD_CL_DMA_W: enable relaxed ordering for (non-atomic write) cl_dma_w (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 1 | RW | RW | CONFIG_RELAXED_BRK0_CMD_CL_DMA_W_HP: Reserved. (was: enable relaxed ordering for (non-atomic write) cl_dma_w_hp (only valid for GPU and AFU-M2 memory)) | |
| 2 | RW | RW | CONFIG_RELAXED_BRK0_CMD_CL_DMA_INJ: enable relaxed ordering for (non-atomic write) cl_dma_inj (only valid for GPU and AFU-M2 memory) | |
| 3 | RW | RW | CONFIG_RELAXED_BRK0_CMD_PR_DMA_INJ: enable relaxed ordering for (non-atomic write) pr_dma_inj (only valid for GPU and AFU-M2 memory) | |
| 4 | RW | RW | CONFIG_RELAXED_BRK0_CMD_DMA_PR_W: enable relaxed ordering for (non-atomic write) dma_pr_w (only valid for GPU and AFU-M2 memory) | |
| 5 | RW | RW | CONFIG_RELAXED_BRK0_CMD_CL_RD_NC_F0: enable relaxed ordering for (non-atomic read) cl_rd_nc(F=0) (only valid for GPU and AFU-M2 memory) | |
| 6 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMW_CAS_IMAX_U: enable relaxed ordering for (atomic write) armw_cas_imax_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 7 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMW_CAS_IMAX_S: enable relaxed ordering for (atomic write) armw_cas_imax_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 8 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMW_CAS_IMIN_U: enable relaxed ordering for (atomic write) armw_cas_imin_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 9 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMW_CAS_IMIN_S: enable relaxed ordering for (atomic write) armw_cas_imin_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 10 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMW_ADD: enable relaxed ordering for (atomic write) armw_add (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 11 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMW_AND: enable relaxed ordering for (atomic write) armw_and (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 12 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMW_OR: enable relaxed ordering for (atomic write) armw_or (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 13 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMW_XOR: enable relaxed ordering for (atomic write) armw_xor (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 14 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMWF_CAS_IMAX_U: enable relaxed ordering for (atomic read) armwf_cas_imax_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 15 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMWF_CAS_IMAX_S: enable relaxed ordering for (atomic read) armwf_cas_imax_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 16 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMWF_CAS_IMIN_U: enable relaxed ordering for (atomic read) armwf_cas_imin_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 17 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMWF_CAS_IMIN_S: enable relaxed ordering for (atomic read) armwf_cas_imin_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 18 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMWF_ADD: enable relaxed ordering for (atomic read) armwf_add (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 19 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMWF_AND: enable relaxed ordering for (atomic read) armwf_and (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 20 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMWF_OR: enable relaxed ordering for (atomic read) armwf_or (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 21 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMWF_XOR: enable relaxed ordering for (atomic read) armwf_xor (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 22 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMWF_CAS_E: enable relaxed ordering for (atomic read) armwf_cas_e (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 23 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMWF_CAS_U: enable relaxed ordering for (atomic read) armwf_cas_u (only valid for OCAPI AFU-M1 or AFU-M2 memory) (errata HW367501 requires this bit to be 0 for GPU memory) | |
| 24 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMW_CAS_T: enable relaxed ordering for (atomic write) armw_cas_t (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 25 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMWF_CAS_NE: enable relaxed ordering for (atomic read) armwf_cas_ne (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 26 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMWF_INC_B: enable relaxed ordering for (atomic read) armwf_inc_b (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 27 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMWF_INC_E: enable relaxed ordering for (atomic read) armwf_inc_e (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 28 | RW | RW | CONFIG_RELAXED_BRK0_CMD_ARMWF_DEC_B: enable relaxed ordering for (atomic read) armwf_dec_b (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 29:31 | RW | RW | CONFIG_RELAXED_BRK0_RESERVED1: reserved | |
| 32 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE0_WRENA: 0/1 = disable/enable relaxed source 0 for (non-atomic) write operations | |
| 33 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE0_RDENA: 0/1 = disable/enable relaxed source 0 for (non-atomic) read operations | |
| 34 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE0_AWENA: 0/1 = disable/enable relaxed source 0 for atomic (write) operations | |
| 35 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE0_ARENA: 0/1 = disable/enable relaxed source 0 for atomic (read) operations | |
| 36 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE1_WRENA: 0/1 = disable/enable relaxed source 1 for (non-atomic) write operations | |
| 37 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE1_RDENA: 0/1 = disable/enable relaxed source 1 for (non-atomic) read operations | |
| 38 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE1_AWENA: 0/1 = disable/enable relaxed source 1 for atomic (write) operations | |
| 39 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE1_ARENA: 0/1 = disable/enable relaxed source 1 for atomic (read) operations | |
| 40 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE2_WRENA: 0/1 = disable/enable relaxed source 2 for (non-atomic) write operations | |
| 41 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE2_RDENA: 0/1 = disable/enable relaxed source 2 for (non-atomic) read operations | |
| 42 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE2_AWENA: 0/1 = disable/enable relaxed source 2 for atomic (write) operations | |
| 43 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE2_ARENA: 0/1 = disable/enable relaxed source 2 for atomic (read) operations | |
| 44 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE3_WRENA: 0/1 = disable/enable relaxed source 3 for (non-atomic) write operations | |
| 45 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE3_RDENA: 0/1 = disable/enable relaxed source 3 for (non-atomic) read operations | |
| 46 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE3_AWENA: 0/1 = disable/enable relaxed source 3 for atomic (write) operations | |
| 47 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE3_ARENA: 0/1 = disable/enable relaxed source 3 for atomic (read) operations | |
| 48 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE4_WRENA: 0/1 = disable/enable relaxed source 4 for (non-atomic) write operations | |
| 49 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE4_RDENA: 0/1 = disable/enable relaxed source 4 for (non-atomic) read operations | |
| 50 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE4_AWENA: 0/1 = disable/enable relaxed source 4 for atomic (write) operations | |
| 51 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE4_ARENA: 0/1 = disable/enable relaxed source 4 for atomic (read) operations | |
| 52 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE5_WRENA: 0/1 = disable/enable relaxed source 5 for (non-atomic) write operations | |
| 53 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE5_RDENA: 0/1 = disable/enable relaxed source 5 for (non-atomic) read operations | |
| 54 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE5_AWENA: 0/1 = disable/enable relaxed source 5 for atomic (write) operations | |
| 55 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE5_ARENA: 0/1 = disable/enable relaxed source 5 for atomic (read) operations | |
| 56 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE6_WRENA: 0/1 = disable/enable relaxed source 6 for (non-atomic) write operations | |
| 57 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE6_RDENA: 0/1 = disable/enable relaxed source 6 for (non-atomic) read operations | |
| 58 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE6_AWENA: 0/1 = disable/enable relaxed source 6 for atomic (write) operations | |
| 59 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE6_ARENA: 0/1 = disable/enable relaxed source 6 for atomic (read) operations | |
| 60 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE7_WRENA: 0/1 = disable/enable relaxed source 7 for (non-atomic) write operations | |
| 61 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE7_RDENA: 0/1 = disable/enable relaxed source 7 for (non-atomic) read operations | |
| 62 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE7_AWENA: 0/1 = disable/enable relaxed source 7 for atomic (write) operations | |
| 63 | RW | RW | CONFIG_RELAXED_BRK0_SOURCE7_ARENA: 0/1 = disable/enable relaxed source 7 for atomic (read) operations | |
| Relaxed-Ordering Config2 brick 1 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010967 (SCOM) 0000000013430238 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.SNP.MISC.CONFIG_RELAXED_BRK1 | |||
| Constant(s): | ||||
| Comments: | Configure relaxed-ordering Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM3.SNP.MISC.CONFIG_RELAXED_BRK1_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_RELAXED_BRK1_CMD_CL_DMA_W: enable relaxed ordering for (non-atomic write) cl_dma_w (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 1 | RW | RW | CONFIG_RELAXED_BRK1_CMD_CL_DMA_W_HP: Reserved. (was: enable relaxed ordering for (non-atomic write) cl_dma_w_hp (only valid for GPU and AFU-M2 memory)) | |
| 2 | RW | RW | CONFIG_RELAXED_BRK1_CMD_CL_DMA_INJ: enable relaxed ordering for (non-atomic write) cl_dma_inj (only valid for GPU and AFU-M2 memory) | |
| 3 | RW | RW | CONFIG_RELAXED_BRK1_CMD_PR_DMA_INJ: enable relaxed ordering for (non-atomic write) pr_dma_inj (only valid for GPU and AFU-M2 memory) | |
| 4 | RW | RW | CONFIG_RELAXED_BRK1_CMD_DMA_PR_W: enable relaxed ordering for (non-atomic write) dma_pr_w (only valid for GPU and AFU-M2 memory) | |
| 5 | RW | RW | CONFIG_RELAXED_BRK1_CMD_CL_RD_NC_F0: enable relaxed ordering for (non-atomic read) cl_rd_nc(F=0) (only valid for GPU and AFU-M2 memory) | |
| 6 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMW_CAS_IMAX_U: enable relaxed ordering for (atomic write) armw_cas_imax_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 7 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMW_CAS_IMAX_S: enable relaxed ordering for (atomic write) armw_cas_imax_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 8 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMW_CAS_IMIN_U: enable relaxed ordering for (atomic write) armw_cas_imin_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 9 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMW_CAS_IMIN_S: enable relaxed ordering for (atomic write) armw_cas_imin_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 10 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMW_ADD: enable relaxed ordering for (atomic write) armw_add (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 11 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMW_AND: enable relaxed ordering for (atomic write) armw_and (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 12 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMW_OR: enable relaxed ordering for (atomic write) armw_or (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 13 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMW_XOR: enable relaxed ordering for (atomic write) armw_xor (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 14 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMWF_CAS_IMAX_U: enable relaxed ordering for (atomic read) armwf_cas_imax_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 15 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMWF_CAS_IMAX_S: enable relaxed ordering for (atomic read) armwf_cas_imax_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 16 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMWF_CAS_IMIN_U: enable relaxed ordering for (atomic read) armwf_cas_imin_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 17 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMWF_CAS_IMIN_S: enable relaxed ordering for (atomic read) armwf_cas_imin_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 18 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMWF_ADD: enable relaxed ordering for (atomic read) armwf_add (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 19 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMWF_AND: enable relaxed ordering for (atomic read) armwf_and (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 20 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMWF_OR: enable relaxed ordering for (atomic read) armwf_or (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 21 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMWF_XOR: enable relaxed ordering for (atomic read) armwf_xor (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 22 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMWF_CAS_E: enable relaxed ordering for (atomic read) armwf_cas_e (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 23 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMWF_CAS_U: enable relaxed ordering for (atomic read) armwf_cas_u (only valid for OCAPI AFU-M1 or AFU-M2 memory) (errata HW367501 requires this bit to be 0 for GPU memory) | |
| 24 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMW_CAS_T: enable relaxed ordering for (atomic write) armw_cas_t (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 25 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMWF_CAS_NE: enable relaxed ordering for (atomic read) armwf_cas_ne (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 26 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMWF_INC_B: enable relaxed ordering for (atomic read) armwf_inc_b (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 27 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMWF_INC_E: enable relaxed ordering for (atomic read) armwf_inc_e (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 28 | RW | RW | CONFIG_RELAXED_BRK1_CMD_ARMWF_DEC_B: enable relaxed ordering for (atomic read) armwf_dec_b (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 29:31 | RW | RW | CONFIG_RELAXED_BRK1_RESERVED1: reserved | |
| 32 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE0_WRENA: 0/1 = disable/enable relaxed source 0 for (non-atomic) write operations | |
| 33 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE0_RDENA: 0/1 = disable/enable relaxed source 0 for (non-atomic) read operations | |
| 34 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE0_AWENA: 0/1 = disable/enable relaxed source 0 for atomic (write) operations | |
| 35 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE0_ARENA: 0/1 = disable/enable relaxed source 0 for atomic (read) operations | |
| 36 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE1_WRENA: 0/1 = disable/enable relaxed source 1 for (non-atomic) write operations | |
| 37 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE1_RDENA: 0/1 = disable/enable relaxed source 1 for (non-atomic) read operations | |
| 38 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE1_AWENA: 0/1 = disable/enable relaxed source 1 for atomic (write) operations | |
| 39 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE1_ARENA: 0/1 = disable/enable relaxed source 1 for atomic (read) operations | |
| 40 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE2_WRENA: 0/1 = disable/enable relaxed source 2 for (non-atomic) write operations | |
| 41 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE2_RDENA: 0/1 = disable/enable relaxed source 2 for (non-atomic) read operations | |
| 42 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE2_AWENA: 0/1 = disable/enable relaxed source 2 for atomic (write) operations | |
| 43 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE2_ARENA: 0/1 = disable/enable relaxed source 2 for atomic (read) operations | |
| 44 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE3_WRENA: 0/1 = disable/enable relaxed source 3 for (non-atomic) write operations | |
| 45 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE3_RDENA: 0/1 = disable/enable relaxed source 3 for (non-atomic) read operations | |
| 46 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE3_AWENA: 0/1 = disable/enable relaxed source 3 for atomic (write) operations | |
| 47 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE3_ARENA: 0/1 = disable/enable relaxed source 3 for atomic (read) operations | |
| 48 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE4_WRENA: 0/1 = disable/enable relaxed source 4 for (non-atomic) write operations | |
| 49 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE4_RDENA: 0/1 = disable/enable relaxed source 4 for (non-atomic) read operations | |
| 50 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE4_AWENA: 0/1 = disable/enable relaxed source 4 for atomic (write) operations | |
| 51 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE4_ARENA: 0/1 = disable/enable relaxed source 4 for atomic (read) operations | |
| 52 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE5_WRENA: 0/1 = disable/enable relaxed source 5 for (non-atomic) write operations | |
| 53 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE5_RDENA: 0/1 = disable/enable relaxed source 5 for (non-atomic) read operations | |
| 54 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE5_AWENA: 0/1 = disable/enable relaxed source 5 for atomic (write) operations | |
| 55 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE5_ARENA: 0/1 = disable/enable relaxed source 5 for atomic (read) operations | |
| 56 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE6_WRENA: 0/1 = disable/enable relaxed source 6 for (non-atomic) write operations | |
| 57 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE6_RDENA: 0/1 = disable/enable relaxed source 6 for (non-atomic) read operations | |
| 58 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE6_AWENA: 0/1 = disable/enable relaxed source 6 for atomic (write) operations | |
| 59 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE6_ARENA: 0/1 = disable/enable relaxed source 6 for atomic (read) operations | |
| 60 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE7_WRENA: 0/1 = disable/enable relaxed source 7 for (non-atomic) write operations | |
| 61 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE7_RDENA: 0/1 = disable/enable relaxed source 7 for (non-atomic) read operations | |
| 62 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE7_AWENA: 0/1 = disable/enable relaxed source 7 for atomic (write) operations | |
| 63 | RW | RW | CONFIG_RELAXED_BRK1_SOURCE7_ARENA: 0/1 = disable/enable relaxed source 7 for atomic (read) operations | |
| Relaxed-Ordering Config2 brick 2 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010968 (SCOM) 0000000013430240 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.SNP.MISC.CONFIG_RELAXED_BRK2 | |||
| Constant(s): | ||||
| Comments: | Configure relaxed-ordering Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM3.SNP.MISC.CONFIG_RELAXED_BRK2_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_RELAXED_BRK2_CMD_CL_DMA_W: enable relaxed ordering for (non-atomic write) cl_dma_w (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 1 | RW | RW | CONFIG_RELAXED_BRK2_CMD_CL_DMA_W_HP: Reserved. (was: enable relaxed ordering for (non-atomic write) cl_dma_w_hp (only valid for GPU and AFU-M2 memory)) | |
| 2 | RW | RW | CONFIG_RELAXED_BRK2_CMD_CL_DMA_INJ: enable relaxed ordering for (non-atomic write) cl_dma_inj (only valid for GPU and AFU-M2 memory) | |
| 3 | RW | RW | CONFIG_RELAXED_BRK2_CMD_PR_DMA_INJ: enable relaxed ordering for (non-atomic write) pr_dma_inj (only valid for GPU and AFU-M2 memory) | |
| 4 | RW | RW | CONFIG_RELAXED_BRK2_CMD_DMA_PR_W: enable relaxed ordering for (non-atomic write) dma_pr_w (only valid for GPU and AFU-M2 memory) | |
| 5 | RW | RW | CONFIG_RELAXED_BRK2_CMD_CL_RD_NC_F0: enable relaxed ordering for (non-atomic read) cl_rd_nc(F=0) (only valid for GPU and AFU-M2 memory) | |
| 6 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMW_CAS_IMAX_U: enable relaxed ordering for (atomic write) armw_cas_imax_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 7 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMW_CAS_IMAX_S: enable relaxed ordering for (atomic write) armw_cas_imax_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 8 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMW_CAS_IMIN_U: enable relaxed ordering for (atomic write) armw_cas_imin_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 9 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMW_CAS_IMIN_S: enable relaxed ordering for (atomic write) armw_cas_imin_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 10 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMW_ADD: enable relaxed ordering for (atomic write) armw_add (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 11 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMW_AND: enable relaxed ordering for (atomic write) armw_and (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 12 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMW_OR: enable relaxed ordering for (atomic write) armw_or (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 13 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMW_XOR: enable relaxed ordering for (atomic write) armw_xor (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 14 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMWF_CAS_IMAX_U: enable relaxed ordering for (atomic read) armwf_cas_imax_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 15 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMWF_CAS_IMAX_S: enable relaxed ordering for (atomic read) armwf_cas_imax_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 16 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMWF_CAS_IMIN_U: enable relaxed ordering for (atomic read) armwf_cas_imin_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 17 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMWF_CAS_IMIN_S: enable relaxed ordering for (atomic read) armwf_cas_imin_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 18 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMWF_ADD: enable relaxed ordering for (atomic read) armwf_add (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 19 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMWF_AND: enable relaxed ordering for (atomic read) armwf_and (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 20 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMWF_OR: enable relaxed ordering for (atomic read) armwf_or (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 21 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMWF_XOR: enable relaxed ordering for (atomic read) armwf_xor (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 22 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMWF_CAS_E: enable relaxed ordering for (atomic read) armwf_cas_e (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 23 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMWF_CAS_U: enable relaxed ordering for (atomic read) armwf_cas_u (only valid for OCAPI AFU-M1 or AFU-M2 memory) (errata HW367501 requires this bit to be 0 for GPU memory) | |
| 24 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMW_CAS_T: enable relaxed ordering for (atomic write) armw_cas_t (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 25 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMWF_CAS_NE: enable relaxed ordering for (atomic read) armwf_cas_ne (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 26 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMWF_INC_B: enable relaxed ordering for (atomic read) armwf_inc_b (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 27 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMWF_INC_E: enable relaxed ordering for (atomic read) armwf_inc_e (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 28 | RW | RW | CONFIG_RELAXED_BRK2_CMD_ARMWF_DEC_B: enable relaxed ordering for (atomic read) armwf_dec_b (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 29:31 | RW | RW | CONFIG_RELAXED_BRK2_RESERVED1: reserved | |
| 32 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE0_WRENA: 0/1 = disable/enable relaxed source 0 for (non-atomic) write operations | |
| 33 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE0_RDENA: 0/1 = disable/enable relaxed source 0 for (non-atomic) read operations | |
| 34 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE0_AWENA: 0/1 = disable/enable relaxed source 0 for atomic (write) operations | |
| 35 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE0_ARENA: 0/1 = disable/enable relaxed source 0 for atomic (read) operations | |
| 36 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE1_WRENA: 0/1 = disable/enable relaxed source 1 for (non-atomic) write operations | |
| 37 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE1_RDENA: 0/1 = disable/enable relaxed source 1 for (non-atomic) read operations | |
| 38 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE1_AWENA: 0/1 = disable/enable relaxed source 1 for atomic (write) operations | |
| 39 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE1_ARENA: 0/1 = disable/enable relaxed source 1 for atomic (read) operations | |
| 40 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE2_WRENA: 0/1 = disable/enable relaxed source 2 for (non-atomic) write operations | |
| 41 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE2_RDENA: 0/1 = disable/enable relaxed source 2 for (non-atomic) read operations | |
| 42 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE2_AWENA: 0/1 = disable/enable relaxed source 2 for atomic (write) operations | |
| 43 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE2_ARENA: 0/1 = disable/enable relaxed source 2 for atomic (read) operations | |
| 44 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE3_WRENA: 0/1 = disable/enable relaxed source 3 for (non-atomic) write operations | |
| 45 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE3_RDENA: 0/1 = disable/enable relaxed source 3 for (non-atomic) read operations | |
| 46 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE3_AWENA: 0/1 = disable/enable relaxed source 3 for atomic (write) operations | |
| 47 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE3_ARENA: 0/1 = disable/enable relaxed source 3 for atomic (read) operations | |
| 48 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE4_WRENA: 0/1 = disable/enable relaxed source 4 for (non-atomic) write operations | |
| 49 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE4_RDENA: 0/1 = disable/enable relaxed source 4 for (non-atomic) read operations | |
| 50 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE4_AWENA: 0/1 = disable/enable relaxed source 4 for atomic (write) operations | |
| 51 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE4_ARENA: 0/1 = disable/enable relaxed source 4 for atomic (read) operations | |
| 52 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE5_WRENA: 0/1 = disable/enable relaxed source 5 for (non-atomic) write operations | |
| 53 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE5_RDENA: 0/1 = disable/enable relaxed source 5 for (non-atomic) read operations | |
| 54 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE5_AWENA: 0/1 = disable/enable relaxed source 5 for atomic (write) operations | |
| 55 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE5_ARENA: 0/1 = disable/enable relaxed source 5 for atomic (read) operations | |
| 56 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE6_WRENA: 0/1 = disable/enable relaxed source 6 for (non-atomic) write operations | |
| 57 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE6_RDENA: 0/1 = disable/enable relaxed source 6 for (non-atomic) read operations | |
| 58 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE6_AWENA: 0/1 = disable/enable relaxed source 6 for atomic (write) operations | |
| 59 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE6_ARENA: 0/1 = disable/enable relaxed source 6 for atomic (read) operations | |
| 60 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE7_WRENA: 0/1 = disable/enable relaxed source 7 for (non-atomic) write operations | |
| 61 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE7_RDENA: 0/1 = disable/enable relaxed source 7 for (non-atomic) read operations | |
| 62 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE7_AWENA: 0/1 = disable/enable relaxed source 7 for atomic (write) operations | |
| 63 | RW | RW | CONFIG_RELAXED_BRK2_SOURCE7_ARENA: 0/1 = disable/enable relaxed source 7 for atomic (read) operations | |
| Relaxed-Ordering Config2 brick 3 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010969 (SCOM) 0000000013430248 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.SNP.MISC.CONFIG_RELAXED_BRK3 | |||
| Constant(s): | ||||
| Comments: | Configure relaxed-ordering Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM3.SNP.MISC.CONFIG_RELAXED_BRK3_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_RELAXED_BRK3_CMD_CL_DMA_W: enable relaxed ordering for (non-atomic write) cl_dma_w (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 1 | RW | RW | CONFIG_RELAXED_BRK3_CMD_CL_DMA_W_HP: Reserved. (was: enable relaxed ordering for (non-atomic write) cl_dma_w_hp (only valid for GPU and AFU-M2 memory)) | |
| 2 | RW | RW | CONFIG_RELAXED_BRK3_CMD_CL_DMA_INJ: enable relaxed ordering for (non-atomic write) cl_dma_inj (only valid for GPU and AFU-M2 memory) | |
| 3 | RW | RW | CONFIG_RELAXED_BRK3_CMD_PR_DMA_INJ: enable relaxed ordering for (non-atomic write) pr_dma_inj (only valid for GPU and AFU-M2 memory) | |
| 4 | RW | RW | CONFIG_RELAXED_BRK3_CMD_DMA_PR_W: enable relaxed ordering for (non-atomic write) dma_pr_w (only valid for GPU and AFU-M2 memory) | |
| 5 | RW | RW | CONFIG_RELAXED_BRK3_CMD_CL_RD_NC_F0: enable relaxed ordering for (non-atomic read) cl_rd_nc(F=0) (only valid for GPU and AFU-M2 memory) | |
| 6 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMW_CAS_IMAX_U: enable relaxed ordering for (atomic write) armw_cas_imax_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 7 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMW_CAS_IMAX_S: enable relaxed ordering for (atomic write) armw_cas_imax_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 8 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMW_CAS_IMIN_U: enable relaxed ordering for (atomic write) armw_cas_imin_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 9 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMW_CAS_IMIN_S: enable relaxed ordering for (atomic write) armw_cas_imin_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 10 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMW_ADD: enable relaxed ordering for (atomic write) armw_add (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 11 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMW_AND: enable relaxed ordering for (atomic write) armw_and (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 12 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMW_OR: enable relaxed ordering for (atomic write) armw_or (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 13 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMW_XOR: enable relaxed ordering for (atomic write) armw_xor (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 14 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMWF_CAS_IMAX_U: enable relaxed ordering for (atomic read) armwf_cas_imax_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 15 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMWF_CAS_IMAX_S: enable relaxed ordering for (atomic read) armwf_cas_imax_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 16 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMWF_CAS_IMIN_U: enable relaxed ordering for (atomic read) armwf_cas_imin_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 17 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMWF_CAS_IMIN_S: enable relaxed ordering for (atomic read) armwf_cas_imin_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 18 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMWF_ADD: enable relaxed ordering for (atomic read) armwf_add (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 19 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMWF_AND: enable relaxed ordering for (atomic read) armwf_and (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 20 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMWF_OR: enable relaxed ordering for (atomic read) armwf_or (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 21 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMWF_XOR: enable relaxed ordering for (atomic read) armwf_xor (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 22 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMWF_CAS_E: enable relaxed ordering for (atomic read) armwf_cas_e (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 23 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMWF_CAS_U: enable relaxed ordering for (atomic read) armwf_cas_u (only valid for OCAPI AFU-M1 or AFU-M2 memory) (errata HW367501 requires this bit to be 0 for GPU memory) | |
| 24 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMW_CAS_T: enable relaxed ordering for (atomic write) armw_cas_t (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 25 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMWF_CAS_NE: enable relaxed ordering for (atomic read) armwf_cas_ne (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 26 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMWF_INC_B: enable relaxed ordering for (atomic read) armwf_inc_b (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 27 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMWF_INC_E: enable relaxed ordering for (atomic read) armwf_inc_e (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 28 | RW | RW | CONFIG_RELAXED_BRK3_CMD_ARMWF_DEC_B: enable relaxed ordering for (atomic read) armwf_dec_b (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 29:31 | RW | RW | CONFIG_RELAXED_BRK3_RESERVED1: reserved | |
| 32 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE0_WRENA: 0/1 = disable/enable relaxed source 0 for (non-atomic) write operations | |
| 33 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE0_RDENA: 0/1 = disable/enable relaxed source 0 for (non-atomic) read operations | |
| 34 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE0_AWENA: 0/1 = disable/enable relaxed source 0 for atomic (write) operations | |
| 35 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE0_ARENA: 0/1 = disable/enable relaxed source 0 for atomic (read) operations | |
| 36 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE1_WRENA: 0/1 = disable/enable relaxed source 1 for (non-atomic) write operations | |
| 37 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE1_RDENA: 0/1 = disable/enable relaxed source 1 for (non-atomic) read operations | |
| 38 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE1_AWENA: 0/1 = disable/enable relaxed source 1 for atomic (write) operations | |
| 39 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE1_ARENA: 0/1 = disable/enable relaxed source 1 for atomic (read) operations | |
| 40 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE2_WRENA: 0/1 = disable/enable relaxed source 2 for (non-atomic) write operations | |
| 41 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE2_RDENA: 0/1 = disable/enable relaxed source 2 for (non-atomic) read operations | |
| 42 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE2_AWENA: 0/1 = disable/enable relaxed source 2 for atomic (write) operations | |
| 43 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE2_ARENA: 0/1 = disable/enable relaxed source 2 for atomic (read) operations | |
| 44 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE3_WRENA: 0/1 = disable/enable relaxed source 3 for (non-atomic) write operations | |
| 45 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE3_RDENA: 0/1 = disable/enable relaxed source 3 for (non-atomic) read operations | |
| 46 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE3_AWENA: 0/1 = disable/enable relaxed source 3 for atomic (write) operations | |
| 47 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE3_ARENA: 0/1 = disable/enable relaxed source 3 for atomic (read) operations | |
| 48 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE4_WRENA: 0/1 = disable/enable relaxed source 4 for (non-atomic) write operations | |
| 49 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE4_RDENA: 0/1 = disable/enable relaxed source 4 for (non-atomic) read operations | |
| 50 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE4_AWENA: 0/1 = disable/enable relaxed source 4 for atomic (write) operations | |
| 51 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE4_ARENA: 0/1 = disable/enable relaxed source 4 for atomic (read) operations | |
| 52 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE5_WRENA: 0/1 = disable/enable relaxed source 5 for (non-atomic) write operations | |
| 53 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE5_RDENA: 0/1 = disable/enable relaxed source 5 for (non-atomic) read operations | |
| 54 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE5_AWENA: 0/1 = disable/enable relaxed source 5 for atomic (write) operations | |
| 55 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE5_ARENA: 0/1 = disable/enable relaxed source 5 for atomic (read) operations | |
| 56 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE6_WRENA: 0/1 = disable/enable relaxed source 6 for (non-atomic) write operations | |
| 57 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE6_RDENA: 0/1 = disable/enable relaxed source 6 for (non-atomic) read operations | |
| 58 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE6_AWENA: 0/1 = disable/enable relaxed source 6 for atomic (write) operations | |
| 59 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE6_ARENA: 0/1 = disable/enable relaxed source 6 for atomic (read) operations | |
| 60 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE7_WRENA: 0/1 = disable/enable relaxed source 7 for (non-atomic) write operations | |
| 61 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE7_RDENA: 0/1 = disable/enable relaxed source 7 for (non-atomic) read operations | |
| 62 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE7_AWENA: 0/1 = disable/enable relaxed source 7 for atomic (write) operations | |
| 63 | RW | RW | CONFIG_RELAXED_BRK3_SOURCE7_ARENA: 0/1 = disable/enable relaxed source 7 for atomic (read) operations | |
| Relaxed-Ordering Config2 brick 4 | ||||
|---|---|---|---|---|
| Addr: |
000000001101096A (SCOM) 0000000013430250 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.SNP.MISC.CONFIG_RELAXED_BRK4 | |||
| Constant(s): | ||||
| Comments: | Configure relaxed-ordering Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM3.SNP.MISC.CONFIG_RELAXED_BRK4_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_RELAXED_BRK4_CMD_CL_DMA_W: enable relaxed ordering for (non-atomic write) cl_dma_w (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 1 | RW | RW | CONFIG_RELAXED_BRK4_CMD_CL_DMA_W_HP: Reserved. (was: enable relaxed ordering for (non-atomic write) cl_dma_w_hp (only valid for GPU and AFU-M2 memory)) | |
| 2 | RW | RW | CONFIG_RELAXED_BRK4_CMD_CL_DMA_INJ: enable relaxed ordering for (non-atomic write) cl_dma_inj (only valid for GPU and AFU-M2 memory) | |
| 3 | RW | RW | CONFIG_RELAXED_BRK4_CMD_PR_DMA_INJ: enable relaxed ordering for (non-atomic write) pr_dma_inj (only valid for GPU and AFU-M2 memory) | |
| 4 | RW | RW | CONFIG_RELAXED_BRK4_CMD_DMA_PR_W: enable relaxed ordering for (non-atomic write) dma_pr_w (only valid for GPU and AFU-M2 memory) | |
| 5 | RW | RW | CONFIG_RELAXED_BRK4_CMD_CL_RD_NC_F0: enable relaxed ordering for (non-atomic read) cl_rd_nc(F=0) (only valid for GPU and AFU-M2 memory) | |
| 6 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMW_CAS_IMAX_U: enable relaxed ordering for (atomic write) armw_cas_imax_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 7 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMW_CAS_IMAX_S: enable relaxed ordering for (atomic write) armw_cas_imax_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 8 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMW_CAS_IMIN_U: enable relaxed ordering for (atomic write) armw_cas_imin_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 9 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMW_CAS_IMIN_S: enable relaxed ordering for (atomic write) armw_cas_imin_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 10 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMW_ADD: enable relaxed ordering for (atomic write) armw_add (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 11 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMW_AND: enable relaxed ordering for (atomic write) armw_and (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 12 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMW_OR: enable relaxed ordering for (atomic write) armw_or (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 13 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMW_XOR: enable relaxed ordering for (atomic write) armw_xor (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 14 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMWF_CAS_IMAX_U: enable relaxed ordering for (atomic read) armwf_cas_imax_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 15 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMWF_CAS_IMAX_S: enable relaxed ordering for (atomic read) armwf_cas_imax_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 16 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMWF_CAS_IMIN_U: enable relaxed ordering for (atomic read) armwf_cas_imin_u (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 17 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMWF_CAS_IMIN_S: enable relaxed ordering for (atomic read) armwf_cas_imin_s (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 18 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMWF_ADD: enable relaxed ordering for (atomic read) armwf_add (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 19 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMWF_AND: enable relaxed ordering for (atomic read) armwf_and (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 20 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMWF_OR: enable relaxed ordering for (atomic read) armwf_or (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 21 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMWF_XOR: enable relaxed ordering for (atomic read) armwf_xor (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 22 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMWF_CAS_E: enable relaxed ordering for (atomic read) armwf_cas_e (valid with any memory: GPU, AFU-M1, or AFU-M2) | |
| 23 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMWF_CAS_U: enable relaxed ordering for (atomic read) armwf_cas_u (only valid for OCAPI AFU-M1 or AFU-M2 memory) (errata HW367501 requires this bit to be 0 for GPU memory) | |
| 24 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMW_CAS_T: enable relaxed ordering for (atomic write) armw_cas_t (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 25 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMWF_CAS_NE: enable relaxed ordering for (atomic read) armwf_cas_ne (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 26 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMWF_INC_B: enable relaxed ordering for (atomic read) armwf_inc_b (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 27 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMWF_INC_E: enable relaxed ordering for (atomic read) armwf_inc_e (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 28 | RW | RW | CONFIG_RELAXED_BRK4_CMD_ARMWF_DEC_B: enable relaxed ordering for (atomic read) armwf_dec_b (only valid for OCAPI AFU-M1 or AFU-M2 memory) | |
| 29:31 | RW | RW | CONFIG_RELAXED_BRK4_RESERVED1: reserved | |
| 32 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE0_WRENA: 0/1 = disable/enable relaxed source 0 for (non-atomic) write operations | |
| 33 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE0_RDENA: 0/1 = disable/enable relaxed source 0 for (non-atomic) read operations | |
| 34 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE0_AWENA: 0/1 = disable/enable relaxed source 0 for atomic (write) operations | |
| 35 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE0_ARENA: 0/1 = disable/enable relaxed source 0 for atomic (read) operations | |
| 36 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE1_WRENA: 0/1 = disable/enable relaxed source 1 for (non-atomic) write operations | |
| 37 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE1_RDENA: 0/1 = disable/enable relaxed source 1 for (non-atomic) read operations | |
| 38 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE1_AWENA: 0/1 = disable/enable relaxed source 1 for atomic (write) operations | |
| 39 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE1_ARENA: 0/1 = disable/enable relaxed source 1 for atomic (read) operations | |
| 40 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE2_WRENA: 0/1 = disable/enable relaxed source 2 for (non-atomic) write operations | |
| 41 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE2_RDENA: 0/1 = disable/enable relaxed source 2 for (non-atomic) read operations | |
| 42 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE2_AWENA: 0/1 = disable/enable relaxed source 2 for atomic (write) operations | |
| 43 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE2_ARENA: 0/1 = disable/enable relaxed source 2 for atomic (read) operations | |
| 44 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE3_WRENA: 0/1 = disable/enable relaxed source 3 for (non-atomic) write operations | |
| 45 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE3_RDENA: 0/1 = disable/enable relaxed source 3 for (non-atomic) read operations | |
| 46 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE3_AWENA: 0/1 = disable/enable relaxed source 3 for atomic (write) operations | |
| 47 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE3_ARENA: 0/1 = disable/enable relaxed source 3 for atomic (read) operations | |
| 48 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE4_WRENA: 0/1 = disable/enable relaxed source 4 for (non-atomic) write operations | |
| 49 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE4_RDENA: 0/1 = disable/enable relaxed source 4 for (non-atomic) read operations | |
| 50 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE4_AWENA: 0/1 = disable/enable relaxed source 4 for atomic (write) operations | |
| 51 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE4_ARENA: 0/1 = disable/enable relaxed source 4 for atomic (read) operations | |
| 52 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE5_WRENA: 0/1 = disable/enable relaxed source 5 for (non-atomic) write operations | |
| 53 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE5_RDENA: 0/1 = disable/enable relaxed source 5 for (non-atomic) read operations | |
| 54 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE5_AWENA: 0/1 = disable/enable relaxed source 5 for atomic (write) operations | |
| 55 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE5_ARENA: 0/1 = disable/enable relaxed source 5 for atomic (read) operations | |
| 56 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE6_WRENA: 0/1 = disable/enable relaxed source 6 for (non-atomic) write operations | |
| 57 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE6_RDENA: 0/1 = disable/enable relaxed source 6 for (non-atomic) read operations | |
| 58 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE6_AWENA: 0/1 = disable/enable relaxed source 6 for atomic (write) operations | |
| 59 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE6_ARENA: 0/1 = disable/enable relaxed source 6 for atomic (read) operations | |
| 60 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE7_WRENA: 0/1 = disable/enable relaxed source 7 for (non-atomic) write operations | |
| 61 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE7_RDENA: 0/1 = disable/enable relaxed source 7 for (non-atomic) read operations | |
| 62 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE7_AWENA: 0/1 = disable/enable relaxed source 7 for atomic (write) operations | |
| 63 | RW | RW | CONFIG_RELAXED_BRK4_SOURCE7_ARENA: 0/1 = disable/enable relaxed source 7 for atomic (read) operations | |
| Low-Water Marks | ||||
|---|---|---|---|---|
| Addr: |
000000001101096B (SCOM) 0000000013430258 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.SNP.MISC.LOW_WATER | |||
| Constant(s): | ||||
| Comments: | State-Machine allocation Low-Water Marks the sum of the Low-Water marks must be less than config_max_machines Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM3.SNP.MISC.LOW_WATER_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_LOW_WATER_PWR0: Low-Water mark for PowerBus rd/dclaim/atomic/etc. requests | |
| 1 | RW | RW | CONFIG_LOW_WATER_PWR1: Low-Water mark for PowerBus cp (castout-push) requests. | |
| 2 | RW | RW | CONFIG_LOW_WATER_PWR2: Low-Water mark for PowerBus snoops for force-evict requests. | |
| 3 | RW | RW | CONFIG_LOW_WATER_XATS: Low-Water mark for ATS/XSL PowerBus requests | |
| 4 | RW | RW | CONFIG_LOW_WATER_INTS: Low-Water mark for MISC Interrupt requests | |
| 5 | RW | RW | CONFIG_LOW_WATER_REQ0: Low-Water mark for brick-0 NVLink brick-0 Req channel or OCAPI TLX.vc.3 requests | |
| 6 | RW | RW | CONFIG_LOW_WATER_CST0: Low-Water mark for brick-0 OCAPI Castout requests | |
| 7 | RW | RW | CONFIG_LOW_WATER_PRB0: Low-Water mark for brick-0 NVLink Probe or OCAPI mem_pa_flush requests | |
| 8 | RW | RW | CONFIG_LOW_WATER_REQ1: Low-Water mark for brick-1 NVLink Req channel or OCAPI TLX.vc.3 requests | |
| 9 | RW | RW | CONFIG_LOW_WATER_CST1: Low-Water mark for brick-1 OCAPI Castout requests | |
| 10 | RW | RW | CONFIG_LOW_WATER_PRB1: Low-Water mark for brick-1 NVLink Probe or OCAPI mem_pa_flush requests | |
| 11 | RW | RW | CONFIG_LOW_WATER_REQ2: Low-Water mark for brick-2 NVLink brick-0 Req channel or OCAPI TLX.vc.3 requests | |
| 12 | RW | RW | CONFIG_LOW_WATER_CST2: Low-Water mark for brick-2 OCAPI Castout requests | |
| 13 | RW | RW | CONFIG_LOW_WATER_PRB2: Low-Water mark for brick-2 NVLink Probe or OCAPI mem_pa_flush requests | |
| 14 | RW | RW | CONFIG_LOW_WATER_REQ3: Low-Water mark for brick-3 NVLink Req channel or OCAPI TLX.vc.3 requests | |
| 15 | RW | RW | CONFIG_LOW_WATER_CST3: Low-Water mark for brick-3 OCAPI Castout requests | |
| 16 | RW | RW | CONFIG_LOW_WATER_PRB3: Low-Water mark for brick-3 NVLink Probe or OCAPI mem_pa_flush requests | |
| 17 | RW | RW | CONFIG_LOW_WATER_REQ4: Low-Water mark for brick-4 NVLink brick-0 Req channel or OCAPI TLX.vc.3 requests | |
| 18 | RW | RW | CONFIG_LOW_WATER_CST4: Low-Water mark for brick-4 OCAPI Castout requests | |
| 19 | RW | RW | CONFIG_LOW_WATER_PRB4: Low-Water mark for brick-4 NVLink Probe or OCAPI mem_pa_flush requests | |
| 20 | RW | RW | CONFIG_LOW_WATER_XI_SHARED: shared Low-Water mark for ATS/XSL/MISC-INT requests if set to 1, the only one of config_low_water_{xats,ints} should be set to 1 | |
| 21 | RW | RW | CONFIG_LOW_WATER_REQX_SHARED: shared Low-Water mark for req0...req4 if set to 1, the only one of config_low_water_{req0...req4} should be set to 1 | |
| 22 | RW | RW | CONFIG_LOW_WATER_CSTX_SHARED: shared Low-Water mark for cst0...cst4 if set to 1, the only one of config_low_water_{cst0...cst4} should be set to 1 | |
| 23 | RW | RW | CONFIG_LOW_WATER_PRBX_SHARED: shared Low-Water mark for prb0...prb4 if set to 1, the only one of config_low_water_{prb0...prb4} should be set to 1 | |
| 24:25 | RW | RW | CONFIG_WEIGHT_PWR0: 0...3 -> weight 1..4 when balancing PWR0 against other classes | |
| 26:27 | RW | RW | CONFIG_WEIGHT_PWR1: 0...3 -> weight 1..4 when balancing PWR1 against other classes | |
| 28:29 | RW | RW | CONFIG_WEIGHT_PWR2: 0...3 -> weight 1..4 when balancing PWR2 against other classes | |
| 30:31 | RW | RW | CONFIG_WEIGHT_XATS: 0...3 -> weight 1..4 when balancing XATS against other classes | |
| 32:33 | RW | RW | CONFIG_WEIGHT_INTS: 0...3 -> weight 1..4 when balancing INTS against other classes | |
| 34:35 | RW | RW | CONFIG_WEIGHT_REQ0: 0...3 -> weight 1..4 when balancing REQ0 against other classes | |
| 36:37 | RW | RW | CONFIG_WEIGHT_CST0: 0...3 -> weight 1..4 when balancing CST0 against other classes | |
| 38:39 | RW | RW | CONFIG_WEIGHT_PRB0: 0...3 -> weight 1..4 when balancing PRB0 against other classes | |
| 40:41 | RW | RW | CONFIG_WEIGHT_REQ1: 0...3 -> weight 1..4 when balancing REQ1 against other classes | |
| 42:43 | RW | RW | CONFIG_WEIGHT_CST1: 0...3 -> weight 1..4 when balancing CST1 against other classes | |
| 44:45 | RW | RW | CONFIG_WEIGHT_PRB1: 0...3 -> weight 1..4 when balancing PRB1 against other classes | |
| 46:47 | RW | RW | CONFIG_WEIGHT_REQ2: 0...3 -> weight 1..4 when balancing REQ2 against other classes | |
| 48:49 | RW | RW | CONFIG_WEIGHT_CST2: 0...3 -> weight 1..4 when balancing CST2 against other classes | |
| 50:51 | RW | RW | CONFIG_WEIGHT_PRB2: 0...3 -> weight 1..4 when balancing PRB2 against other classes | |
| 52:53 | RW | RW | CONFIG_WEIGHT_REQ3: 0...3 -> weight 1..4 when balancing REQ3 against other classes | |
| 54:55 | RW | RW | CONFIG_WEIGHT_CST3: 0...3 -> weight 1..4 when balancing CST3 against other classes | |
| 56:57 | RW | RW | CONFIG_WEIGHT_PRB3: 0...3 -> weight 1..4 when balancing PRB3 against other classes | |
| 58:59 | RW | RW | CONFIG_WEIGHT_REQ4: 0...3 -> weight 1..4 when balancing REQ4 against other classes | |
| 60:61 | RW | RW | CONFIG_WEIGHT_CST4: 0...3 -> weight 1..4 when balancing CST4 against other classes | |
| 62:63 | RW | RW | CONFIG_WEIGHT_PRB4: 0...3 -> weight 1..4 when balancing PRB4 against other classes | |
| Machine Allocation configuration | ||||
|---|---|---|---|---|
| Addr: |
000000001101096D (SCOM) 0000000013430268 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.SNP.MISC.MACHINE_ALLOC | |||
| Constant(s): | ||||
| Comments: | State-Machine configuration and control Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM3.SNP.MISC.MACHINE_ALLOC_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_ENABLE_MACHINE_ALLOC: Enable state-machine allocation Can only be changed 0->1, must stay 1 once set | |
| 1 | RW | RW | CONFIG_ENABLE_EXCEED_HIGH: Enable exceeding high water marks | |
| 2:7 | RW | RW | CONFIG_MAX_MACHINES: Maximum number of state-machines to be used. Must be >= 20 and <= 62 | |
| 8:13 | RW | RW | CONFIG_HIGH_WATER_IDLE: High-water mark for 'Idle' allocation classes | |
| 14:19 | RW | RW | CONFIG_HIGH_BONUS1: Signed 6-bit bonus value to apply to the available machines count prior to division | |
| 20:29 | RW | RW | CONFIG_HIGH_MIN_SHARE: Minimum share after division (machines * 8) | |
| 30:39 | RW | RW | CONFIG_HIGH_BONUS2: Signed 10-bit bonus value to apply to machines count after division (signed machines * 8) | |
| 40:43 | RW | RW | CONFIG_MAX_HIGH_RESERVED: Maximum of state-machines reserved for classes below their high-water marks | |
| 44:48 | RW | RW | CONFIG_SMAL_DEBUG_SEL0: Debug select mux for state-machine-allocation debug output 0 | |
| 49:53 | RW | RW | CONFIG_SMAL_DEBUG_SEL1: Debug select mux for state-machine-allocation debug output 1 | |
| 54:58 | RW | RW | CONFIG_SMAL_DEBUG_SEL2: Debug select mux for state-machine-allocation debug output 2 | |
| 59:63 | RW | RW | CONFIG_SMAL_DEBUG_SEL3: Debug select mux for state-machine-allocation debug output 3 | |
| Perf Config Reg | ||||
|---|---|---|---|---|
| Addr: |
000000001101096E (SCOM) 0000000013430270 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.SNP.MISC.PERF_CONFIG | |||
| Constant(s): | ||||
| Comments: | Performance Event selection | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:35 | PAU3.CS.SM3.SNP.MISC.PERF_CONFIG_Q_0_INST.LATC.L2(0:35) [000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:7 | RW | RW | PERF_CONFIG_EVENT0: Event 0 select 0: count nothing 1: count cycles 2: count # of cycles REQ0 count matches perf_mask/match_alloc 3: count # of cycles CST0 count matches perf_mask/match_alloc 4: count # of cycles PRB0 count matches perf_mask/match_alloc 5: count # of cycles REQ1 count matches perf_mask/match_alloc 6: count # of cycles CST1 count matches perf_mask/match_alloc 7: count # of cycles PRB1 count matches perf_mask/match_alloc 8: count # of cycles REQ2 count matches perf_mask/match_alloc 9: count # of cycles CST2 count matches perf_mask/match_alloc 10: count # of cycles PRB2 count matches perf_mask/match_alloc 11: count # of cycles REQ3 count matches perf_mask/match_alloc 12: count # of cycles CST3 count matches perf_mask/match_alloc 13: count # of cycles PRB3 count matches perf_mask/match_alloc 14: count # of cycles REQ4 count matches perf_mask/match_alloc 15: count # of cycles CST4 count matches perf_mask/match_alloc 16: count # of cycles PRB4 count matches perf_mask/match_alloc 17: count # of cycles PWR0 count matches perf_mask/match_alloc 18: count # of cycles PWR1 count matches perf_mask/match_alloc 19: count # of cycles PWR2 count matches perf_mask/match_alloc 20: count # of cycles XATS count matches perf_mask/match_alloc 21: count # of cycles reserved count matches perf_mask/match_alloc 22: count # of cycles free count matches perf_mask/match_alloc 23: count # of cycles INTS count matches perf_mask/match_alloc 24: count # of RCmds received matching perf_mask/match 25: count # of times PResp=rty_dinc was driven 26: count # of RCmds received from PAU/PAU 27: count # of perf-select RCmds that had cam_hit_pckt_vld_d asserted as an input to the fsnoop_coll table 28: count # of perf-select RCmds that had cam_hit_pckt_vld_nd asserted as an input to the fsnoop_coll table 29: count # of perf-select RCmds that had cam_hit_pckt_vld_ond asserted as an input to the fsnoop_coll table 30: count # of perf-select RCmds that had cam_hit_pckt_win asserted as an input to the fsnoop_coll table 31: count # of perf-select RCmds that had cam_hit_rty_dif asserted as an input to the fsnoop_coll table 32: count # of perf-select RCmds that had cam_hit_rty_dif_mpf asserted as an input to the fsnoop_coll table 33: count # of perf-select RCmds that had cam_hit_pckt_poison asserted as an input to the fsnoop_coll table 34: count # of perf-select RCmds that had cam_hit_rty_lco asserted as an input to the fsnoop_coll table 35: count # of perf-select RCmds that had cam_hit_rty_abbk asserted as an input to the fsnoop_coll table 36: count # of perf-select RCmds that had cam_hit_rty_abbks asserted as an input to the fsnoop_coll table 37: count # of perf-select RCmds that had cam_hit_rty_all asserted as an input to the fsnoop_coll table 38: count # of perf-select RCmds that had cam_hit_snarf_cpm asserted as an input to the fsnoop_coll table 39: count # of perf-select RCmds that had cam_hit_pb_req asserted as an input to the fsnoop_coll table 40: count # of perf-select RCmds that had presp_rty_spec asserted as an output from the fsnoop_coll table 41: count # of perf-select RCmds that had presp_rty_hpc asserted as an output from the fsnoop_coll table 42: count # of perf-select RCmds that had presp_rty_prot asserted as an output from the fsnoop_coll table 43: count # of perf-select RCmds that had presp_rty_r_coll asserted as an output from the fsnoop_coll table 44: count # of perf-select RCmds that had presp_pckt_hit asserted as an output from the fsnoop_coll table 45: count # of perf-select RCmds that had presp_accept asserted as an output from the fsnoop_coll table 46: count # of perf-select RCmds that had cam_hit_mod_addr asserted as an input to the fsnoop_dir table 47: count # of perf-select RCmds that had cam_hit_mod_lock asserted as an input to the fsnoop_dir table 48: count # of perf-select RCmds that had cam_hit_syn_pend asserted as an input to the fsnoop_dir table 49: count # of perf-select RCmds that had cam_hit_sfe_addr asserted as an input to the fsnoop_dir table 50: count # of perf-select RCmds that had cam_hit_sfe_pend asserted as an input to the fsnoop_dir table 51: count # of perf-select RCmds that had cam_hit_co_pend asserted as an input to the fsnoop_dir table 52: count # of perf-select RCmds that had cam_hit_rs_pend asserted as an input to the fsnoop_dir table 53: count # of perf-select RCmds that had cam_hit_row_not_head asserted as an input to the fsnoop_dir table 54: count # of perf-select RCmds that had l2_dir_valid_or_alloc asserted as an input to the fsnoop_dir table 55: count # of perf-select RCmds that had l2_dir_any_pro_note asserted as an input to the fsnoop_dir table 56: count # of perf-select RCmds that had l2_dir_max_e asserted as an input to the fsnoop_dir table 57: count # of perf-select RCmds that had l2_dir_has_s asserted as an input to the fsnoop_dir table 58: count # of perf-select RCmds that had l2_dir_any_cmd_i asserted as an input to the fsnoop_dir table 59: count # of perf-select RCmds that had l2_dir_other_brick_s asserted as an input to the fsnoop_dir table 60: count # of perf-select RCmds that had l2_dir_other_brick_e asserted as an input to the fsnoop_dir table 61: count # of perf-select RCmds that had presp_shd asserted as an output from the fsnoop_dir table 62: count # of perf-select RCmds that had presp_rty asserted as an output from the fsnoop_dir table 63: count # of perf-select RCmds that had presp_m_mu_ix asserted as an output from the fsnoop_dir table 64: count # of perf-select RCmds that had presp_rty_lost_claim asserted as an output from the fsnoop_dir table 65: count # of perf-select RCmds that had lock_snp_sfe asserted as an output from the fsnoop_dir table 66: count # of perf-select RCmds that had lock_snp_mod asserted as an output from the fsnoop_dir table 67: count # of perf-select RCmds that had lock_mod asserted as an output from the fsnoop_dir table 68: count # of perf-select RCmds that had send_mugging asserted as an output from the fsnoop_dir table 69: count # of perf-select RCmds that had block_dir asserted as an input to the psnoop table others: reserved (count nothing) | |
| 8:15 | RW | RW | PERF_CONFIG_EVENT1: Event 1 select See Event 0 select for encodes | |
| 16:23 | RW | RW | PERF_CONFIG_EVENT2: Event 2 select See Event 0 select for encodes | |
| 24:31 | RW | RW | PERF_CONFIG_EVENT3: Event 3 select See Event 0 select for encodes | |
| 32:34 | RW | RW | PERF_CONFIG_RESERVED2: reserved | |
| 35 | RW | RW | PERF_CONFIG_ACT: Enable clock-gates for performance monitor latches | |
| 36:63 | RO | RO | constant=0b0000000000000000000000000000 | |
| Inhibit configuration Register | ||||
|---|---|---|---|---|
| Addr: |
000000001101096F (SCOM) 0000000013430278 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.SNP.MISC.INHIBIT_CONFIG | |||
| Constant(s): | ||||
| Comments: | Configures Inhibits for CQ_SM | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:31 | PAU3.CS.SM3.SNP.MISC.INHIBIT_CONFIG_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:7 | RW | RW | CONFIG_INHIBIT_DEST0: Selects the destination of the inhibit | |
| 8:15 | RW | RW | CONFIG_INHIBIT_DEST1: Selects the destination of the inhibit | |
| 16:23 | RW | RW | CONFIG_INHIBIT_DEST2: Selects the destination of the inhibit | |
| 24:31 | RW | RW | CONFIG_INHIBIT_DEST3: Selects the destination of the inhibit | |
| 32:63 | RO | RO | constant=0b00000000000000000000000000000000 | |
| c_err_rpt Message-0 latches | ||||
|---|---|---|---|---|
| Addr: |
0000000011010970 (SCOM) 0000000013430280 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.SNP.MISC.CERR_MESSAGE0 | |||
| Constant(s): | ||||
| Comments: | Error message/capture register 0 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM3.SNP.MISC.CERR_MESSAGE0_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:63 | RWX_WCLRREG | RWX_WCLRREG | CERR_MESSAGE_BITS0: reserved | |
| c_err_rpt Message-1 latches | ||||
|---|---|---|---|---|
| Addr: |
0000000011010971 (SCOM) 0000000013430288 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.SNP.MISC.CERR_MESSAGE1 | |||
| Constant(s): | ||||
| Comments: | Error message/capture register 1 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM3.SNP.MISC.CERR_MESSAGE1_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:63 | RWX_WCLRREG | RWX_WCLRREG | CERR_MESSAGE_BITS1: reserved | |
| CQ_SM status register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010972 (SCOM) 0000000013430290 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.SNP.MISC.SM_STATUS | |||
| Constant(s): | ||||
| Comments: | Status reporting register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:23 | PAU3.CS.SM3.SNP.MISC.SM_STATUS_Q_0_INST.LATC.L2(0:23) [000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | ROX | ROX | SM_STATUS_PWR0: 1 when PowerBus (non-cp*) allocation is at its idle level | |
| 1 | ROX | ROX | SM_STATUS_PWR1: 1 when PowerBus (cp*) allocation is at its idle level | |
| 2 | ROX | ROX | SM_STATUS_PWR2: 1 when PowerBus (cp*) allocation is at its idle level | |
| 3 | ROX | ROX | SM_STATUS_XATS: 1 when ATS/MISC allocation is at its idle level | |
| 4 | ROX | ROX | SM_STATUS_INTS: 1 when INTS allocation is at its idle level | |
| 5 | ROX | ROX | SM_STATUS_CREQ0: 1 when brick 0 CReq allocation is at its idle level | |
| 6 | ROX | ROX | SM_STATUS_CST0: 1 when brick 0 Castout allocation is at its idle level | |
| 7 | ROX | ROX | SM_STATUS_PRB0: 1 when brick 0 Probe allocation is at its idle level | |
| 8 | ROX | ROX | SM_STATUS_CREQ1: 1 when brick 1 CReq allocation is at its idle level | |
| 9 | ROX | ROX | SM_STATUS_CST1: 1 when brick 1 Castout allocation is at its idle level | |
| 10 | ROX | ROX | SM_STATUS_PRB1: 1 when brick 1 Probe allocation is at its idle level | |
| 11 | ROX | ROX | SM_STATUS_CREQ2: 1 when brick 1 CReq allocation is at its idle level | |
| 12 | ROX | ROX | SM_STATUS_CST2: 1 when brick 1 Castout allocation is at its idle level | |
| 13 | ROX | ROX | SM_STATUS_PRB2: 1 when brick 1 Probe allocation is at its idle level | |
| 14 | ROX | ROX | SM_STATUS_CREQ3: 1 when brick 1 CReq allocation is at its idle level | |
| 15 | ROX | ROX | SM_STATUS_CST3: 1 when brick 1 Castout allocation is at its idle level | |
| 16 | ROX | ROX | SM_STATUS_PRB3: 1 when brick 1 Probe allocation is at its idle level | |
| 17 | ROX | ROX | SM_STATUS_CREQ4: 1 when brick 1 CReq allocation is at its idle level | |
| 18 | ROX | ROX | SM_STATUS_CST4: 1 when brick 1 Castout allocation is at its idle level | |
| 19 | ROX | ROX | SM_STATUS_PRB4: 1 when brick 1 Probe allocation is at its idle level | |
| 20 | ROX | ROX | SM_STATUS_CHGRATE: 1 when chgrate.hang slowdown is being applied to machine allocation | |
| 21:23 | ROX | ROX | SM_STATUS_RESERVED1: reserved | |
| 24:63 | RO | RO | constant=0b0000000000000000000000000000000000000000 | |
| c_err_rpt first-0 latches | ||||
|---|---|---|---|---|
| Addr: |
0000000011010973 (SCOM) 0000000013430298 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.SNP.MISC.CERR_FIRST0 | |||
| Constant(s): | ||||
| Comments: | c_err_rpt first latches read-write-1-clear reg | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:7 | PAU3.CS.SM3.SNP.MISC.CERR_FIRST0_Q_0_INST.LATC.L2(0:7) [00000000] | |||
| 8:15 | PAU3.CS.SM3.SNP.MISC.CERR_FIRST0_Q_8_INST.LATC.L2(8:15) [00000000] | |||
| 16:23 | PAU3.CS.SM3.SNP.MISC.CERR_FIRST0_Q_16_INST.LATC.L2(16:23) [00000000] | |||
| 24:35 | PAU3.CS.SM3.SNP.MISC.CERR_FIRST0_Q_24_INST.LATC.L2(24:35) [000000000000] | |||
| 36:59 | PAU3.CS.SM3.SNP.MISC.CERR_FIRST0_Q_36_INST.LATC.L2(36:59) [000000000000000000000000] | |||
| 60:63 | PAU3.CS.SM3.SNP.MISC.CERR_FIRST0_Q_60_INST.LATC.L2(60:63) [0000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NCF_0: NCF0 An NVLink probe did not match its GPUBar | |
| 1 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NCF_1: NCF1 Epoch timeout while ProNoted L2-dir entry was waiting for castout | |
| 2 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NCF_2: NCF2 (reserved) | |
| 3 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NCF_3: NCF3 NVLink NCF error for brick 0 occurred | |
| 4 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NCF_4: NCF4 NVLink NCF error for brick 1 occurred | |
| 5 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NCF_5: NCF5 NVLink NCF error for brick 2 occurred | |
| 6 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NCF_6: NCF6 NVLink NCF error for brick 3 occurred | |
| 7 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NCF_7: NCF7 NVLink NCF error for brick 4 occurred | |
| 8 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBR_0: PBR0 Addr_Error received for self-lpc command (SSF) | |
| 9 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBR_1: PBR1 (reserved) | |
| 10 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBR_2: PBR2 (reserved) | |
| 11 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBR_3: PBR3 (reserved) | |
| 12 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBR_4: PBR4 Illegal Cmd to GPU Memory received | |
| 13 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBR_5: PBR5 (reserved) | |
| 14 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBR_6: PBR6 (reserved) | |
| 15 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBR_7: PBR7 (reserved) | |
| 16 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBP_0: PBP0 Parity error detected on rcmd ttag field | |
| 17 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBP_1: PBP1 Parity error detected on rcmd addr field | |
| 18 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBP_2: PBP2 Parity error detected on CResp ttag | |
| 19 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBP_3: PBP3 Parity error detected on CResp atag | |
| 20 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBP_4: PBP4 (reserved) | |
| 21 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBP_5: PBP5 (reserved) | |
| 22 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBP_6: PBP6 (reserved) | |
| 23 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBP_7: PBP7 (reserved) | |
| 24 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBC_0: PBC0 (reserved) | |
| 25 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBC_1: PBC1 (reserved) | |
| 26 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBC_2: PBC2 (reserved) | |
| 27 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBC_3: PBC3 (reserved) | |
| 28 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBC_4: PBC4 Reserved (was: RCmd TTag received with illegal group ID) | |
| 29 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBC_5: PBC5 Reserved (was: RCmd TTag received with illegal chip ID) | |
| 30 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBC_6: PBC6 Reserved (was: CResp TTag received with illegal group ID) | |
| 31 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBC_7: PBC7 Reserved (was: CResp TTag received with illegal chip ID) | |
| 32 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBC_8: PBC8 RCmd received with disabled topo-idx in address | |
| 33 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBC_9: PBC9 (reserved) | |
| 34 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBC_10: PBC10 (reserved) | |
| 35 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBC_11: PBC11 (reserved) | |
| 36 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_0: NLG0 RCmd Pre-Snoop table lookup missed the table | |
| 37 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_1: NLG1 (reserved) | |
| 38 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_2: NLG2 Req-in logic dropped an ATS-response | |
| 39 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_3: NLG3 (reserved) | |
| 40 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_4: NLG4 RCmd Final-Snoop Coll-Shd table lookup missed the table | |
| 41 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_5: NLG5 CAM lookup hit multiple snarf-cpm entries (multiple probes received from GPU) | |
| 42 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_6: NLG6 Arb request-in queue overflowed | |
| 43 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_7: NLG7 RCmd Final-Snoop coll collision/lpc table lookup missed the table | |
| 44 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_8: NLG8 RCmd Final-Snoop dir C2/L2-directory table lookup missed the table | |
| 45 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_9: NLG9 RCmd Final-Snoop Coll-Retry-Spec table lookup missed the table | |
| 46 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_10: NLG10 RCmd Final-Snoop Coll-Retry-HPC table lookup missed the table | |
| 47 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_11: NLG11 RCmd Final-Snoop Coll-Retry-Prot table lookup missed the table | |
| 48 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_12: NLG12 RCmd Final-Snoop Coll-Retry-RColl table lookup missed the table | |
| 49 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_13: NLG13 RCmd Final-Snoop Coll-Pocket-Hit table lookup missed the table | |
| 50 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_14: NLG14 RCmd Final-Snoop Coll-Accept table lookup missed the table | |
| 51 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_15: NLG15 RCmd Final-Snoop Dir-Shd table lookup missed the table | |
| 52 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_16: NLG16 RCmd Final-Snoop Dir-Rty table lookup missed the table | |
| 53 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_17: NLG17 RCmd Final-Snoop Dir-MMU(Ix) table lookup missed the table | |
| 54 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_18: NLG18 RCmd Final-Snoop Dir C2/L2 directory impossible command/state combination | |
| 55 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_19: NLG19 RCmd Final-Snoop Dir-Snoop-SFE table lookup missed the table | |
| 56 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_20: NLG20 RCmd Final-Snoop Dir-Snoop-Mod table lookup missed the table | |
| 57 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_21: NLG21 RCmd Final-Snoop Dir-Mod table lookup missed the table | |
| 58 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_22: NLG22 RCmd Final-Snoop CAM-Shared table lookup missed the table | |
| 59 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_NLG_23: NLG23 An internal sequencer had an invalid state | |
| 60 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBF_0: PBF0 Addr_Error received for self-lpc command (SSF) | |
| 61 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBF_1: PBF1 (reserved) | |
| 62 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBF_2: PBF2 (reserved) | |
| 63 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_SNP_FIRST_PBF_3: PBF3 (reserved) | |
| c_err_rpt mask-0 latches | ||||
|---|---|---|---|---|
| Addr: |
0000000011010974 (SCOM) 00000000134302A0 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.SNP.MISC.CERR_MASK0 | |||
| Constant(s): | ||||
| Comments: | c_err_rpt mask reg Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM3.SNP.MISC.CERR_MASK0_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | IDIAL_SNP_MASK_NCF_0: NCF0 An NVLink probe did not match its GPUBar | |
| 1 | RW | RW | IDIAL_SNP_MASK_NCF_1: NCF1 Epoch timeout while ProNoted L2-dir entry was waiting for castout | |
| 2 | RW | RW | IDIAL_SNP_MASK_NCF_2: NCF2 (reserved) | |
| 3 | RW | RW | IDIAL_SNP_MASK_NCF_3: NCF3 NVLink NCF error for brick 0 occurred | |
| 4 | RW | RW | IDIAL_SNP_MASK_NCF_4: NCF4 NVLink NCF error for brick 1 occurred | |
| 5 | RW | RW | IDIAL_SNP_MASK_NCF_5: NCF5 NVLink NCF error for brick 2 occurred | |
| 6 | RW | RW | IDIAL_SNP_MASK_NCF_6: NCF6 NVLink NCF error for brick 3 occurred | |
| 7 | RW | RW | IDIAL_SNP_MASK_NCF_7: NCF7 NVLink NCF error for brick 4 occurred | |
| 8 | RW | RW | IDIAL_SNP_MASK_PBR_0: PBR0 Addr_Error received for self-lpc command (SSF) | |
| 9 | RW | RW | IDIAL_SNP_MASK_PBR_1: PBR1 (reserved) | |
| 10 | RW | RW | IDIAL_SNP_MASK_PBR_2: PBR2 (reserved) | |
| 11 | RW | RW | IDIAL_SNP_MASK_PBR_3: PBR3 (reserved) | |
| 12 | RW | RW | IDIAL_SNP_MASK_PBR_4: PBR4 Illegal Cmd to GPU Memory received | |
| 13 | RW | RW | IDIAL_SNP_MASK_PBR_5: PBR5 (reserved) | |
| 14 | RW | RW | IDIAL_SNP_MASK_PBR_6: PBR6 (reserved) | |
| 15 | RW | RW | IDIAL_SNP_MASK_PBR_7: PBR7 (reserved) | |
| 16 | RW | RW | IDIAL_SNP_MASK_PBP_0: PBP0 Parity error detected on rcmd ttag field | |
| 17 | RW | RW | IDIAL_SNP_MASK_PBP_1: PBP1 Parity error detected on rcmd addr field | |
| 18 | RW | RW | IDIAL_SNP_MASK_PBP_2: PBP2 Parity error detected on CResp ttag | |
| 19 | RW | RW | IDIAL_SNP_MASK_PBP_3: PBP3 Parity error detected on CResp atag | |
| 20 | RW | RW | IDIAL_SNP_MASK_PBP_4: PBP4 (reserved) | |
| 21 | RW | RW | IDIAL_SNP_MASK_PBP_5: PBP5 (reserved) | |
| 22 | RW | RW | IDIAL_SNP_MASK_PBP_6: PBP6 (reserved) | |
| 23 | RW | RW | IDIAL_SNP_MASK_PBP_7: PBP7 (reserved) | |
| 24 | RW | RW | IDIAL_SNP_MASK_PBC_0: PBC0 (reserved) | |
| 25 | RW | RW | IDIAL_SNP_MASK_PBC_1: PBC1 (reserved) | |
| 26 | RW | RW | IDIAL_SNP_MASK_PBC_2: PBC2 (reserved) | |
| 27 | RW | RW | IDIAL_SNP_MASK_PBC_3: PBC3 (reserved) | |
| 28 | RW | RW | IDIAL_SNP_MASK_PBC_4: PBC4 Reserved (was: RCmd TTag received with illegal group ID) | |
| 29 | RW | RW | IDIAL_SNP_MASK_PBC_5: PBC5 Reserved (was: RCmd TTag received with illegal chip ID) | |
| 30 | RW | RW | IDIAL_SNP_MASK_PBC_6: PBC6 Reserved (was: CResp TTag received with illegal group ID) | |
| 31 | RW | RW | IDIAL_SNP_MASK_PBC_7: PBC7 Reserved (was: CResp TTag received with illegal chip ID) | |
| 32 | RW | RW | IDIAL_SNP_MASK_PBC_8: PBC8 RCmd received with disabled topo-idx in address | |
| 33 | RW | RW | IDIAL_SNP_MASK_PBC_9: PBC9 (reserved) | |
| 34 | RW | RW | IDIAL_SNP_MASK_PBC_10: PBC10 (reserved) | |
| 35 | RW | RW | IDIAL_SNP_MASK_PBC_11: PBC11 (reserved) | |
| 36 | RW | RW | IDIAL_SNP_MASK_NLG_0: NLG0 RCmd Pre-Snoop table lookup missed the table | |
| 37 | RW | RW | IDIAL_SNP_MASK_NLG_1: NLG1 (reserved) | |
| 38 | RW | RW | IDIAL_SNP_MASK_NLG_2: NLG2 Req-in logic dropped an ATS-response | |
| 39 | RW | RW | IDIAL_SNP_MASK_NLG_3: NLG3 (reserved) | |
| 40 | RW | RW | IDIAL_SNP_MASK_NLG_4: NLG4 RCmd Final-Snoop Coll-Shd table lookup missed the table | |
| 41 | RW | RW | IDIAL_SNP_MASK_NLG_5: NLG5 CAM lookup hit multiple snarf-cpm entries (multiple probes received from GPU) | |
| 42 | RW | RW | IDIAL_SNP_MASK_NLG_6: NLG6 Arb request-in queue overflowed | |
| 43 | RW | RW | IDIAL_SNP_MASK_NLG_7: NLG7 RCmd Final-Snoop coll collision/lpc table lookup missed the table | |
| 44 | RW | RW | IDIAL_SNP_MASK_NLG_8: NLG8 RCmd Final-Snoop dir C2/L2-directory table lookup missed the table | |
| 45 | RW | RW | IDIAL_SNP_MASK_NLG_9: NLG9 RCmd Final-Snoop Coll-Retry-Spec table lookup missed the table | |
| 46 | RW | RW | IDIAL_SNP_MASK_NLG_10: NLG10 RCmd Final-Snoop Coll-Retry-HPC table lookup missed the table | |
| 47 | RW | RW | IDIAL_SNP_MASK_NLG_11: NLG11 RCmd Final-Snoop Coll-Retry-Prot table lookup missed the table | |
| 48 | RW | RW | IDIAL_SNP_MASK_NLG_12: NLG12 RCmd Final-Snoop Coll-Retry-RColl table lookup missed the table | |
| 49 | RW | RW | IDIAL_SNP_MASK_NLG_13: NLG13 RCmd Final-Snoop Coll-Pocket-Hit table lookup missed the table | |
| 50 | RW | RW | IDIAL_SNP_MASK_NLG_14: NLG14 RCmd Final-Snoop Coll-Accept table lookup missed the table | |
| 51 | RW | RW | IDIAL_SNP_MASK_NLG_15: NLG15 RCmd Final-Snoop Dir-Shd table lookup missed the table | |
| 52 | RW | RW | IDIAL_SNP_MASK_NLG_16: NLG16 RCmd Final-Snoop Dir-Rty table lookup missed the table | |
| 53 | RW | RW | IDIAL_SNP_MASK_NLG_17: NLG17 RCmd Final-Snoop Dir-MMU(Ix) table lookup missed the table | |
| 54 | RW | RW | IDIAL_SNP_MASK_NLG_18: NLG18 RCmd Final-Snoop Dir C2/L2 directory impossible command/state combination | |
| 55 | RW | RW | IDIAL_SNP_MASK_NLG_19: NLG19 RCmd Final-Snoop Dir-Snoop-SFE table lookup missed the table | |
| 56 | RW | RW | IDIAL_SNP_MASK_NLG_20: NLG20 RCmd Final-Snoop Dir-Snoop-Mod table lookup missed the table | |
| 57 | RW | RW | IDIAL_SNP_MASK_NLG_21: NLG21 RCmd Final-Snoop Dir-Mod table lookup missed the table | |
| 58 | RW | RW | IDIAL_SNP_MASK_NLG_22: NLG22 RCmd Final-Snoop CAM-Shared table lookup missed the table | |
| 59 | RW | RW | IDIAL_SNP_MASK_NLG_23: NLG23 An internal sequencer had an invalid state | |
| 60 | RW | RW | IDIAL_SNP_MASK_PBF_0: PBF0 Addr_Error received for self-lpc command (SSF) | |
| 61 | RW | RW | IDIAL_SNP_MASK_PBF_1: PBF1 (reserved) | |
| 62 | RW | RW | IDIAL_SNP_MASK_PBF_2: PBF2 (reserved) | |
| 63 | RW | RW | IDIAL_SNP_MASK_PBF_3: PBF3 (reserved) | |
| c_err_rpt hold-0 latches | ||||
|---|---|---|---|---|
| Addr: |
0000000011010975 (SCOM) 00000000134302A8 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.SNP.MISC.CERR_HOLD0 | |||
| Constant(s): | ||||
| Comments: | c_err_rpt hold latches read-write-clear reg | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:7 | PAU3.CS.SM3.SNP.MISC.CERPT_NCF.HOLD_LATCH_INST.HOLD.LATC.L2(0:7) [00000000] | |||
| 8:15 | PAU3.CS.SM3.SNP.MISC.CERPT_PBR.HOLD_LATCH_INST.HOLD.LATC.L2(0:7) [00000000] | |||
| 16:23 | PAU3.CS.SM3.SNP.MISC.CERPT_PBP.HOLD_LATCH_INST.HOLD.LATC.L2(0:7) [00000000] | |||
| 24:35 | PAU3.CS.SM3.SNP.MISC.CERPT_PBC.HOLD_LATCH_INST.HOLD.LATC.L2(0:11) [000000000000] | |||
| 36:59 | PAU3.CS.SM3.SNP.MISC.CERPT_NLG.HOLD_LATCH_INST.HOLD.LATC.L2(0:23) [000000000000000000000000] | |||
| 60:63 | PAU3.CS.SM3.SNP.MISC.CERPT_PBF.HOLD_LATCH_INST.HOLD.LATC.L2(0:3) [0000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NCF_0: NCF0 An NVLink probe did not match its GPUBar | |
| 1 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NCF_1: NCF1 Epoch timeout while ProNoted L2-dir entry was waiting for castout | |
| 2 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NCF_2: NCF2 (reserved) | |
| 3 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NCF_3: NCF3 NVLink NCF error for brick 0 occurred | |
| 4 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NCF_4: NCF4 NVLink NCF error for brick 1 occurred | |
| 5 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NCF_5: NCF5 NVLink NCF error for brick 2 occurred | |
| 6 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NCF_6: NCF6 NVLink NCF error for brick 3 occurred | |
| 7 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NCF_7: NCF7 NVLink NCF error for brick 4 occurred | |
| 8 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBR_0: PBR0 Addr_Error received for self-lpc command (SSF) | |
| 9 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBR_1: PBR1 (reserved) | |
| 10 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBR_2: PBR2 (reserved) | |
| 11 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBR_3: PBR3 (reserved) | |
| 12 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBR_4: PBR4 Illegal Cmd to GPU Memory received | |
| 13 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBR_5: PBR5 (reserved) | |
| 14 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBR_6: PBR6 (reserved) | |
| 15 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBR_7: PBR7 (reserved) | |
| 16 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBP_0: PBP0 Parity error detected on rcmd ttag field | |
| 17 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBP_1: PBP1 Parity error detected on rcmd addr field | |
| 18 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBP_2: PBP2 Parity error detected on CResp ttag | |
| 19 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBP_3: PBP3 Parity error detected on CResp atag | |
| 20 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBP_4: PBP4 (reserved) | |
| 21 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBP_5: PBP5 (reserved) | |
| 22 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBP_6: PBP6 (reserved) | |
| 23 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBP_7: PBP7 (reserved) | |
| 24 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBC_0: PBC0 (reserved) | |
| 25 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBC_1: PBC1 (reserved) | |
| 26 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBC_2: PBC2 (reserved) | |
| 27 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBC_3: PBC3 (reserved) | |
| 28 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBC_4: PBC4 Reserved (was: RCmd TTag received with illegal group ID) | |
| 29 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBC_5: PBC5 Reserved (was: RCmd TTag received with illegal chip ID) | |
| 30 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBC_6: PBC6 Reserved (was: CResp TTag received with illegal group ID) | |
| 31 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBC_7: PBC7 Reserved (was: CResp TTag received with illegal chip ID) | |
| 32 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBC_8: PBC8 RCmd received with disabled topo-idx in address | |
| 33 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBC_9: PBC9 (reserved) | |
| 34 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBC_10: PBC10 (reserved) | |
| 35 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBC_11: PBC11 (reserved) | |
| 36 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_0: NLG0 RCmd Pre-Snoop table lookup missed the table | |
| 37 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_1: NLG1 (reserved) | |
| 38 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_2: NLG2 Req-in logic dropped an ATS-response | |
| 39 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_3: NLG3 (reserved) | |
| 40 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_4: NLG4 RCmd Final-Snoop Coll-Shd table lookup missed the table | |
| 41 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_5: NLG5 CAM lookup hit multiple snarf-cpm entries (multiple probes received from GPU) | |
| 42 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_6: NLG6 Arb request-in queue overflowed | |
| 43 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_7: NLG7 RCmd Final-Snoop coll collision/lpc table lookup missed the table | |
| 44 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_8: NLG8 RCmd Final-Snoop dir C2/L2-directory table lookup missed the table | |
| 45 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_9: NLG9 RCmd Final-Snoop Coll-Retry-Spec table lookup missed the table | |
| 46 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_10: NLG10 RCmd Final-Snoop Coll-Retry-HPC table lookup missed the table | |
| 47 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_11: NLG11 RCmd Final-Snoop Coll-Retry-Prot table lookup missed the table | |
| 48 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_12: NLG12 RCmd Final-Snoop Coll-Retry-RColl table lookup missed the table | |
| 49 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_13: NLG13 RCmd Final-Snoop Coll-Pocket-Hit table lookup missed the table | |
| 50 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_14: NLG14 RCmd Final-Snoop Coll-Accept table lookup missed the table | |
| 51 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_15: NLG15 RCmd Final-Snoop Dir-Shd table lookup missed the table | |
| 52 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_16: NLG16 RCmd Final-Snoop Dir-Rty table lookup missed the table | |
| 53 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_17: NLG17 RCmd Final-Snoop Dir-MMU(Ix) table lookup missed the table | |
| 54 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_18: NLG18 RCmd Final-Snoop Dir C2/L2 directory impossible command/state combination | |
| 55 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_19: NLG19 RCmd Final-Snoop Dir-Snoop-SFE table lookup missed the table | |
| 56 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_20: NLG20 RCmd Final-Snoop Dir-Snoop-Mod table lookup missed the table | |
| 57 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_21: NLG21 RCmd Final-Snoop Dir-Mod table lookup missed the table | |
| 58 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_22: NLG22 RCmd Final-Snoop CAM-Shared table lookup missed the table | |
| 59 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_NLG_23: NLG23 An internal sequencer had an invalid state | |
| 60 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBF_0: PBF0 Addr_Error received for self-lpc command (SSF) | |
| 61 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBF_1: PBF1 (reserved) | |
| 62 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBF_2: PBF2 (reserved) | |
| 63 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_SNP_HOLD_PBF_3: PBF3 (reserved) | |
| Perf Address Match | ||||
|---|---|---|---|---|
| Addr: |
0000000011010976 (SCOM) 00000000134302B0 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.SNP.MISC.PERF_ADDR_CONFIG | |||
| Constant(s): | ||||
| Comments: | Performance Address Match | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:43 | PAU3.CS.SM3.SNP.MISC.PERF_ADDR_CONFIG_Q_0_INST.LATC.L2(0:43) [00000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:5 | RW | RW | PERF_SIZE_ADDR: Size of address range to match 35 = 64K 34 = 128K ... 25 = 64M 15 = 64G 10 = 2T 0 = 2P | |
| 6:41 | RW | RW | PERF_MATCH_ADDR: Address to match | |
| 42:43 | RW | RW | PERF_ADDR_RESERVED1: reserved | |
| 44:63 | RO | RO | constant=0b00000000000000000000 | |
| Perf Match Reg | ||||
|---|---|---|---|---|
| Addr: |
0000000011010977 (SCOM) 00000000134302B8 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.SNP.MISC.PERF_MATCH_CONFIG | |||
| Constant(s): | ||||
| Comments: | Performance Event Field Match | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:39 | PAU3.CS.SM3.SNP.MISC.PERF_MATCH_CONFIG_Q_0_INST.LATC.L2(0:39) [0000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:4 | RW | RW | PERF_MATCH_ALLOC_CLASS: Allocation Class / Source bus | |
| 5:16 | RW | RW | PERF_MATCH_TTYPE: TType | |
| 17:24 | RW | RW | PERF_MATCH_TSIZE: TSize | |
| 25 | RW | RW | PERF_MATCH_NVBE: NVLink byte enables | |
| 26 | RW | RW | PERF_MATCH_UT: NVLink UT | |
| 27:33 | RW | RW | PERF_MATCH_ATYPE: Address Type | |
| 34:39 | RW | RW | PERF_MATCH_ALLOC: Alloc | |
| 40:63 | RO | RO | constant=0b000000000000000000000000 | |
| Perf Mask Reg | ||||
|---|---|---|---|---|
| Addr: |
0000000011010978 (SCOM) 00000000134302C0 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.SNP.MISC.PERF_MASK_CONFIG | |||
| Constant(s): | ||||
| Comments: | Performance Event Field Mask | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:39 | PAU3.CS.SM3.SNP.MISC.PERF_MASK_CONFIG_Q_0_INST.LATC.L2(0:39) [0000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:4 | RW | RW | PERF_MASK_ALLOC_CLASS: Allocation Class / Source bus | |
| 5:16 | RW | RW | PERF_MASK_TTYPE: TType | |
| 17:24 | RW | RW | PERF_MASK_TSIZE: TSize | |
| 25 | RW | RW | PERF_MASK_NVBE: NVLink byte enables | |
| 26 | RW | RW | PERF_MASK_UT: NVLink UT | |
| 27:33 | RW | RW | PERF_MASK_ATYPE: Address Type | |
| 34:39 | RW | RW | PERF_MASK_ALLOC: Alloc | |
| 40:63 | RO | RO | constant=0b000000000000000000000000 | |
| Debug0 Config Reg | ||||
|---|---|---|---|---|
| Addr: |
0000000011010979 (SCOM) 00000000134302C8 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.SNP.MISC.DEBUG0_CONFIG | |||
| Constant(s): | ||||
| Comments: | Config register for trace-0 chain | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM3.SNP.MISC.DEBUG0_CONFIG_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:4 | RW | RW | DEBUG0_CONFIG_POD0: Mux control for byte 0 of trace-0 | |
| 5:9 | RW | RW | DEBUG0_CONFIG_POD1: Mux control for byte 1 of trace-0 | |
| 10:14 | RW | RW | DEBUG0_CONFIG_POD2: Mux control for byte 2 of trace-0 | |
| 15:19 | RW | RW | DEBUG0_CONFIG_POD3: Mux control for byte 3 of trace-0 | |
| 20:24 | RW | RW | DEBUG0_CONFIG_POD4: Mux control for byte 4 of trace-0 | |
| 25:29 | RW | RW | DEBUG0_CONFIG_POD5: Mux control for byte 5 of trace-0 | |
| 30:34 | RW | RW | DEBUG0_CONFIG_POD6: Mux control for byte 6 of trace-0 | |
| 35:39 | RW | RW | DEBUG0_CONFIG_POD7: Mux control for byte 7 of trace-0 | |
| 40:44 | RW | RW | DEBUG0_CONFIG_POD8: Mux control for byte 8 of trace-0 | |
| 45:49 | RW | RW | DEBUG0_CONFIG_POD9: Mux control for byte 9 of trace-0 | |
| 50:54 | RW | RW | DEBUG0_CONFIG_POD10: Mux control for byte 10 of trace-0 | |
| 55:62 | RW | RW | DEBUG0_CONFIG_RESERVED1: reserved | |
| 63 | RW | RW | DEBUG0_CONFIG_ACT: Enable clock-gates for debug trace latches | |
| Debug1 Config Reg | ||||
|---|---|---|---|---|
| Addr: |
000000001101097A (SCOM) 00000000134302D0 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.SNP.MISC.DEBUG1_CONFIG | |||
| Constant(s): | ||||
| Comments: | Config register for trace-1 chain | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.SM3.SNP.MISC.DEBUG1_CONFIG_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:4 | RW | RW | DEBUG1_CONFIG_POD0: Mux control for byte 0 of trace-1 | |
| 5:9 | RW | RW | DEBUG1_CONFIG_POD1: Mux control for byte 1 of trace-1 | |
| 10:14 | RW | RW | DEBUG1_CONFIG_POD2: Mux control for byte 2 of trace-1 | |
| 15:19 | RW | RW | DEBUG1_CONFIG_POD3: Mux control for byte 3 of trace-1 | |
| 20:24 | RW | RW | DEBUG1_CONFIG_POD4: Mux control for byte 4 of trace-1 | |
| 25:29 | RW | RW | DEBUG1_CONFIG_POD5: Mux control for byte 5 of trace-1 | |
| 30:34 | RW | RW | DEBUG1_CONFIG_POD6: Mux control for byte 6 of trace-1 | |
| 35:39 | RW | RW | DEBUG1_CONFIG_POD7: Mux control for byte 7 of trace-1 | |
| 40:44 | RW | RW | DEBUG1_CONFIG_POD8: Mux control for byte 8 of trace-1 | |
| 45:49 | RW | RW | DEBUG1_CONFIG_POD9: Mux control for byte 9 of trace-1 | |
| 50:54 | RW | RW | DEBUG1_CONFIG_POD10: Mux control for byte 10 of trace-1 | |
| 55:62 | RW | RW | DEBUG1_CONFIG_RESERVED1: reserved | |
| 63 | RW | RW | DEBUG1_CONFIG_ACT: Enable clock-gates for debug trace latches | |
| L2 Directory SCOM address register | ||||
|---|---|---|---|---|
| Addr: |
000000001101097B (SCOM) 00000000134302D8 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.SNP.MISC.SCOM_L2_ADDR | |||
| Constant(s): | ||||
| Comments: | register to initiate SCOM reads of the L2 direcotry | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:15 | PAU3.CS.SM3.SNP.MISC.SCOM_L2_ADDR_Q_0_INST.LATC.L2(0:15) [0000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX | RWX | SCOM_L2_VALID: Valid read Write 1 initiates a SCOM access Returns to 0 when access is finished and data is available in the DIR scom_l2_data register | |
| 1:3 | RW | RW | SCOM_L2_ADDR_RESERVED1: reserved | |
| 4:13 | RW | RW | SCOM_L2_CCI: Directory Congruence Class Index (aka SRAM address) to read | |
| 14:15 | RW | RW | SCOM_L2_WAY: Directory 'way' to read | |
| 16:63 | RO | RO | constant=0b000000000000000000000000000000000000000000000000 | |
| Topology Table register 0 | ||||
|---|---|---|---|---|
| Addr: |
000000001101097C (SCOM) 00000000134302E0 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.SNP.MISC.TOPOLOGY_TABLE0 | |||
| Constant(s): | ||||
| Comments: | Defines topology mapping for toplogy indexes 0 through 7 Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:39 | PAU3.CS.SM3.SNP.MISC.TOPOLOGY_TABLE0_Q_0_INST.LATC.L2(0:39) [0000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:7 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENABLE_0_7: Enable bit for entries 0 through 7 | |
| 8:11 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY0: Topology ID(0:3) for Topology Index 0 | |
| 12:15 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY1: Topology ID(0:3) for Topology Index 1 | |
| 16:19 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY2: Topology ID(0:3) for Topology Index 2 | |
| 20:23 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY3: Topology ID(0:3) for Topology Index 3 | |
| 24:27 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY4: Topology ID(0:3) for Topology Index 4 | |
| 28:31 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY5: Topology ID(0:3) for Topology Index 5 | |
| 32:35 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY6: Topology ID(0:3) for Topology Index 6 | |
| 36:39 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY7: Topology ID(0:3) for Topology Index 7 | |
| 40:63 | RO | RO | constant=0b000000000000000000000000 | |
| Topology Table register 1 | ||||
|---|---|---|---|---|
| Addr: |
000000001101097D (SCOM) 00000000134302E8 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.SNP.MISC.TOPOLOGY_TABLE1 | |||
| Constant(s): | ||||
| Comments: | Defines topology mapping for toplogy indexes 8 through 15 Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:39 | PAU3.CS.SM3.SNP.MISC.TOPOLOGY_TABLE1_Q_0_INST.LATC.L2(0:39) [0000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:7 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENABLE_8_15: Enable bit for entries 8 through 15 | |
| 8:11 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY8: Topology ID(0:3) for Topology Index 8 | |
| 12:15 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY9: Topology ID(0:3) for Topology Index 9 | |
| 16:19 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY10: Topology ID(0:3) for Topology Index 10 | |
| 20:23 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY11: Topology ID(0:3) for Topology Index 11 | |
| 24:27 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY12: Topology ID(0:3) for Topology Index 12 | |
| 28:31 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY13: Topology ID(0:3) for Topology Index 13 | |
| 32:35 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY14: Topology ID(0:3) for Topology Index 14 | |
| 36:39 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY15: Topology ID(0:3) for Topology Index 15 | |
| 40:63 | RO | RO | constant=0b000000000000000000000000 | |
| Topology Table register 2 | ||||
|---|---|---|---|---|
| Addr: |
000000001101097E (SCOM) 00000000134302F0 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.SNP.MISC.TOPOLOGY_TABLE2 | |||
| Constant(s): | ||||
| Comments: | Defines topology mapping for toplogy indexes 16 through 23 Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:39 | PAU3.CS.SM3.SNP.MISC.TOPOLOGY_TABLE2_Q_0_INST.LATC.L2(0:39) [0000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:7 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENABLE_16_23: Enable bit for entries 16 through 23 | |
| 8:11 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY16: Topology ID(0:3) for Topology Index 16 | |
| 12:15 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY17: Topology ID(0:3) for Topology Index 17 | |
| 16:19 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY18: Topology ID(0:3) for Topology Index 18 | |
| 20:23 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY19: Topology ID(0:3) for Topology Index 19 | |
| 24:27 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY20: Topology ID(0:3) for Topology Index 20 | |
| 28:31 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY21: Topology ID(0:3) for Topology Index 21 | |
| 32:35 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY22: Topology ID(0:3) for Topology Index 22 | |
| 36:39 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY23: Topology ID(0:3) for Topology Index 23 | |
| 40:63 | RO | RO | constant=0b000000000000000000000000 | |
| Topology Table register 3 | ||||
|---|---|---|---|---|
| Addr: |
000000001101097F (SCOM) 00000000134302F8 (PAU_RING) | |||
| Name: | PAU3.CS.SM3.SNP.MISC.TOPOLOGY_TABLE3 | |||
| Constant(s): | ||||
| Comments: | Defines topology mapping for toplogy indexes 24 through 31 Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:39 | PAU3.CS.SM3.SNP.MISC.TOPOLOGY_TABLE3_Q_0_INST.LATC.L2(0:39) [0000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:7 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENABLE_24_31: Enable bit for entries 24 through 31 | |
| 8:11 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY24: Topology ID(0:3) for Topology Index 24 | |
| 12:15 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY25: Topology ID(0:3) for Topology Index 25 | |
| 16:19 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY26: Topology ID(0:3) for Topology Index 26 | |
| 20:23 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY27: Topology ID(0:3) for Topology Index 27 | |
| 24:27 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY28: Topology ID(0:3) for Topology Index 28 | |
| 28:31 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY29: Topology ID(0:3) for Topology Index 29 | |
| 32:35 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY30: Topology ID(0:3) for Topology Index 30 | |
| 36:39 | RW | RW | CONFIG_TOPOLOGY_TABLE_ENTRY31: Topology ID(0:3) for Topology Index 31 | |
| 40:63 | RO | RO | constant=0b000000000000000000000000 | |
| CQ_CTL Misc Config register #0 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010980 (SCOM) 0000000013440000 (PAU_RING) | |||
| Name: | PAU3.CS.CTL.MISC.CONFIG0 | |||
| Constant(s): | ||||
| Comments: | Misc config register Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.CTL.MISC.CONFIG0_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG0_RESERVED0: reserved - was 1dot0 mode | |
| 1:3 | RW | RW | CONFIG0_RESERVED1: reserved | |
| 4 | RW | RW | CONFIG_ADR_BAR_MODE: Reserved (was: PowerBus adr_bar: 0/1 = large-system-mode/small-system-mode) | |
| 5:9 | RW | RW | CONFIG_GEN_HEAD_DELAY: Reserved (was: Number of cycles to wait for generation-done when reading) | |
| 10 | RW | RW | CONFIG_MRBGP_DIV2_COUNT_AT_EXP: 0/1 = reset-to-zero/divide-by-two the master-retry-backoff retry count when the sample period expires for group-pump | |
| 11 | RW | RW | CONFIG_MRBSP_DIV2_COUNT_AT_EXP: 0/1 = reset-to-zero/divide-by-two the master-retry-backoff retry count when the sample period expires for system-pump | |
| 12 | RW | RW | CONFIG_MRBGP_DIS_DYN_ADJ: 0/1 = enable/disable dynamically adjusting the master-retry-backoff sample period based on level for group-pump | |
| 13 | RW | RW | CONFIG_MRBSP_DIS_DYN_ADJ: 0/1 = enable/disable dynamically adjusting the master-retry-backoff sample period based on level for system-pump | |
| 14 | RW | RW | CONFIG_MRBGP_DIS_DYN_LVL_ADJ: 0/1 = enable/disable dynamically adjusting the master-retry-backoff thresholds based on level for group-pump | |
| 15 | RW | RW | CONFIG_MRBSP_DIS_DYN_LVL_ADJ: 0/1 = enable/disable dynamically adjusting the master-retry-backoff thresholds based on level for system-pump | |
| 16:21 | RW | RW | CONFIG_MRBGP_THRESH1: Master-retry-backoff retry-count threshold at which to reduce the level for group-pump | |
| 22:27 | RW | RW | CONFIG_MRBGP_THRESH2: Master-retry-backoff retry-count threshold at which to increase the level for group-pump Note: make sure that thresh2 > thresh1, or backoff level will only increase. | |
| 28:33 | RW | RW | CONFIG_MRBSP_THRESH1: Master-retry-backoff retry-count threshold at which to reduce the level for system-pump | |
| 34:39 | RW | RW | CONFIG_MRBSP_THRESH2: Master-retry-backoff retry-count threshold at which to increase the level for system-pump Note: make sure that thresh2 > thresh1, or backoff level will only increase. | |
| 40:43 | RW | RW | CONFIG_MRBGP_MAX_LEVEL: Master-retry-backoff maximum level for group-pump | |
| 44:47 | RW | RW | CONFIG_MRBSP_MAX_LEVEL: Master-retry-backoff maximum level for system-pump | |
| 48 | RW | RW | CONFIG_BRAZOS_MODE: Reserved (was: Brazos addr compression 0/1 = non-brazos 4-group;2-chip mode / brazos 2-group;4-chip mode) | |
| 49 | RW | RW | CONFIG_DISABLE_PBM_ECC_COR: 0/1 = enable ECC correction of MMIO store data / disable ECC correction | |
| 50 | RW | RW | CONFIG_LAB_RANDOMIZE_PE_01: 0/1 = don't randomize PE(0:1) / randomize PE(0:1) | |
| 51 | RW | RW | CONFIG_LAB_RANDOMIZE_PE_23: 0/1 = don't randomize PE(2:3) / randomize PE(2:3) | |
| 52 | RW | RW | CONFIG_OTL0_ENABLE: 0/1 = OTL0 is disabled / OTL0 is enabled when disabling change CTL's bit first, then OTL's when enabling change OTL's bit first, then CTL's Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 53 | RW | RW | CONFIG_OTL1_ENABLE: 0/1 = OTL1 is disabled / OTL1 is enabled when disabling change CTL's bit first, then OTL's when enabling change OTL's bit first, then CTL's Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 54 | RW | RW | CONFIG_OTL2_ENABLE: 0/1 = OTL2 is disabled / OTL1 is enabled when disabling change CTL's bit first, then OTL's when enabling change OTL's bit first, then CTL's Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 55 | RW | RW | CONFIG_OTL3_ENABLE: 0/1 = OTL3 is disabled / OTL1 is enabled when disabling change CTL's bit first, then OTL's when enabling change OTL's bit first, then CTL's Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 56 | RW | RW | CONFIG_OTL4_ENABLE: 0/1 = OTL4 is disabled / OTL1 is enabled when disabling change CTL's bit first, then OTL's when enabling change OTL's bit first, then CTL's Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 57 | RW | RW | CONFIG_DISABLE_2CREDS_TO_OTL: Chicken switch to disable sending 2 (request-in) credits/slice to OTL ('0'=2 credits, '1'=1 credit) | |
| 58 | RW | RW | CONFIG_RESTRICT_RSPIN_CREDIT_TO1: Chicken switch to disable sending 2 (response-in) credits/slice to OTL ('0'=2 credits, '1'=1 credit) | |
| 59 | RW | RW | CONFIG_ENABLE_XSL_QUICK_FENCE: 0/1 = disable xsl quick_fence signal from starting fence / enable xsl quick_fence to cause fence | |
| 60 | RW | RW | CONFIG_ENABLE_NCF_QUICK_FENCE: 0/1 = disable NCF errors from starting fence quickly / enable NCF errors to start fence quickly | |
| 61 | RW | RW | CONFIG_ENABLE_NVF_QUICK_FENCE: 0/1 = disable NVF errors from starting fence quickly / enable NVF errors to start fence quickly | |
| 62 | RW | RW | CONFIG_RANDOMIZE_INT_SLICE: 0/1 = tie MISC int addr(55:56) to zero / randomize addr(55:56) | |
| 63 | RW | RW | CONFIG_NVLINK_P10P10_MODE: 0/1 = normal NVLink mode / special lab-debug-only P10-to-P10 NVLink mode | |
| CQ_CTL Misc Config register #1 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010981 (SCOM) 0000000013440008 (PAU_RING) | |||
| Name: | PAU3.CS.CTL.MISC.CONFIG1 | |||
| Constant(s): | ||||
| Comments: | Misc config register Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.CTL.MISC.CONFIG1_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_MRBCP_DIV2_COUNT_AT_EXP: 0/1 = reset-to-zero/divide-by-two the master-retry-backoff retry count when the sample period expires for chip-pump | |
| 1 | RW | RW | CONFIG_MRBCP_DIS_DYN_ADJ: 0/1 = enable/disable dynamically adjusting the master-retry-backoff sample period based on level for chip-pump | |
| 2 | RW | RW | CONFIG_MRBCP_DIS_DYN_LVL_ADJ: 0/1 = enable/disable dynamically adjusting the master-retry-backoff thresholds based on level for chip-pump | |
| 3:8 | RW | RW | CONFIG_MRBCP_THRESH1: Master-retry-backoff retry-count threshold at which to reduce the level for chip-pump | |
| 9:14 | RW | RW | CONFIG_MRBCP_THRESH2: Master-retry-backoff retry-count threshold at which to increase the level for chip-pump Note: make sure that thresh2 > thresh1, or backoff level will only increase. | |
| 15:18 | RW | RW | CONFIG_MRBCP_MAX_LEVEL: Master-retry-backoff maximum level for chip-pump | |
| 19 | RW | RW | CONFIG_BRK0_FENCE_TO_INHIBIT_MASK: 0/1 = brick-0 fence operates normally / brick-0 fence inhibits everything Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 20 | RW | RW | CONFIG_BRK1_FENCE_TO_INHIBIT_MASK: 0/1 = brick-1 fence operates normally / brick-1 fence inhibits everything Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 21 | RW | RW | CONFIG_BRK2_FENCE_TO_INHIBIT_MASK: 0/1 = brick-2 fence operates normally / brick-2 fence inhibits everything Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 22 | RW | RW | CONFIG_BRK3_FENCE_TO_INHIBIT_MASK: 0/1 = brick-3 fence operates normally / brick-3 fence inhibits everything Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 23 | RW | RW | CONFIG_BRK4_FENCE_TO_INHIBIT_MASK: 0/1 = brick-4 fence operates normally / brick-4 fence inhibits everything Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 24:39 | RW | RW | CONFIG_CTL_FIR_TO_INHIBIT_MASK: Mask of FIR bits that should force inhibit-all Note: This field can/should have different values in each instance. No MDials have been created for this field's IDials | |
| 40:43 | RW | RW | CONFIG_HOST_TAG_SIZE: Configured host tag size (in bits) Must be less than or equal to the maximum host tag size supported by the AFUs connected to this PAU. 15 = maximum host tag size supported 6 = minimum host tag size supported 5..0 = reserved values, do not use | |
| 44 | RW | RW | CONFIG_PSHT_CORRENAB: 0/1 = disable/enable pre-sync head-tail array ECC correction | |
| 45 | RW | RW | CONFIG_PSHT_INJECT_ENABLE1: 0/1 = disable/enable pre-sync head-tail array ECC error inject bit 1 | |
| 46 | RW | RW | CONFIG_PSHT_INJECT_ENABLE2: 0/1 = disable/enable pre-sync head-tail array ECC error inject bit 2 | |
| 47 | RW | RW | CONFIG_PSNX_CORRENAB: 0/1 = disable/enable pre-sync next-pointer array ECC correction | |
| 48 | RW | RW | CONFIG_PSNX_INJECT_ENABLE1: 0/1 = disable/enable pre-sync next-pointer array ECC error inject bit 1 | |
| 49 | RW | RW | CONFIG_PSNX_INJECT_ENABLE2: 0/1 = disable/enable pre-sync next-pointer array ECC error inject bit 2 | |
| 50 | RW | RW | CONFIG_PSPV_CORRENAB: 0/1 = disable/enable pre-sync previous-pointer array ECC correction | |
| 51 | RW | RW | CONFIG_PSPV_INJECT_ENABLE1: 0/1 = disable/enable pre-sync previous-pointer array ECC error inject bit 1 | |
| 52 | RW | RW | CONFIG_PSPV_INJECT_ENABLE2: 0/1 = disable/enable pre-sync previous-pointer array ECC error inject bit 2 | |
| 53 | RW | RW | CONFIG_XSL_QUICK_FENCE_TO_INHIBIT_MASK: 0/1 = XSL quick-fence operates normally / XSL quick-fence inhibits everything | |
| 54 | RW | RW | CONFIG_ENABLE_TRUSTED: 0/1 = disable driving trusted=1 for L2 fence castouts / enable driving trusted=1 | |
| 55 | RW | RW | CONFIG_CL_DMA_INJ_D_BIT: P10: Value to drive in the 'd' bit of cl_dma_inj (tsize(7)) for non-presync requests | |
| 56 | RW | RW | CONFIG_PR_DMA_INJ_D_BIT: P10: Value to drive in the 'd' bit of pr_dma_inj (tsize(7)) for non-presync requests | |
| 57 | RW | RW | CONFIG_CL_DMA_INJ_PRESYNC_D_BIT: P10: Value to drive in the 'd' bit of cl_dma_inj (tsize(7)) for presync requests | |
| 58 | RW | RW | CONFIG_PR_DMA_INJ_PRESYNC_D_BIT: P10: Value to drive in the 'd' bit of pr_dma_inj (tsize(7)) for presync requests | |
| 59 | RW | RW | CONFIG_FORCE_OW_ENA_MASK_1111: 0/1 = use ow_mask_ena to clean data / force ow_ena_mask to all ones | |
| 60 | RW | RW | CONFIG_NVLINK_16CHIP_MODE: 0/1 = compress & decompress NVLink addresses for 8-chip support / 16-chip support | |
| 61 | RW | RW | CONFIG_ENABLE_OPENCAPI_NETWORKING: 0/1 = disable networking / enable OpenCAPI MI networking mode. | |
| 62 | RW | RW | CONFIG_NETWORKING_GVC_LOCATION: 0/1 = GVC in PowerBus RA(8:11) / GVC in PowerBus RA(20:23) | |
| 63 | RW | RW | CONFIG1_RESERVED3: Reserved | |
| CQ_CTL Misc Config register #2 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010982 (SCOM) 0000000013440010 (PAU_RING) | |||
| Name: | PAU3.CS.CTL.MISC.CONFIG2 | |||
| Constant(s): | ||||
| Comments: | Misc config register Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.CTL.MISC.CONFIG2_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_BRK0_OCAPI_MODE: 0/1 = Disable OpenCAPI mode / enable OpenCAPI mode for brick 0 (mutually exclusive with config_brk0_nvlink_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 1 | RW | RW | CONFIG_BRK1_OCAPI_MODE: 0/1 = Disable OpenCAPI mode / enable OpenCAPI mode for brick 1 (mutually exclusive with config_brk1_nvlink_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 2 | RW | RW | CONFIG_BRK2_OCAPI_MODE: 0/1 = Disable OpenCAPI mode / enable OpenCAPI mode for brick 2 (mutually exclusive with config_brk2_nvlink_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 3 | RW | RW | CONFIG_BRK3_OCAPI_MODE: 0/1 = Disable OpenCAPI mode / enable OpenCAPI mode for brick 3 (mutually exclusive with config_brk3_nvlink_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 4 | RW | RW | CONFIG_BRK4_OCAPI_MODE: 0/1 = Disable OpenCAPI mode / enable OpenCAPI mode for brick 4 (mutually exclusive with config_brk4_nvlink_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 5 | RW | RW | CONFIG_BRK0_NVLINK_MODE: 0/1 = Disable NVLink mode / enable NVLink mode for brick 0 (mutually exclusive with config_brk0_ocapi_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 6 | RW | RW | CONFIG_BRK1_NVLINK_MODE: 0/1 = Disable NVLink mode / enable NVLink mode for brick 1 (mutually exclusive with config_brk1_ocapi_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 7 | RW | RW | CONFIG_BRK2_NVLINK_MODE: 0/1 = Disable NVLink mode / enable NVLink mode for brick 2 (mutually exclusive with config_brk2_ocapi_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 8 | RW | RW | CONFIG_BRK3_NVLINK_MODE: 0/1 = Disable NVLink mode / enable NVLink mode for brick 3 (mutually exclusive with config_brk3_ocapi_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 9 | RW | RW | CONFIG_BRK4_NVLINK_MODE: 0/1 = Disable NVLink mode / enable NVLink mode for brick 4 (mutually exclusive with config_brk4_ocapi_mode) Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 10 | RW | RW | CONFIG_ENABLE_BRK0_OCAPI_4: 0/1 = disable receiving OCAPI v4.0 opcodes / enable receiving on brick 0 | |
| 11 | RW | RW | CONFIG_ENABLE_BRK1_OCAPI_4: 0/1 = disable receiving OCAPI v4.0 opcodes / enable receiving on brick 1 | |
| 12 | RW | RW | CONFIG_ENABLE_BRK2_OCAPI_4: 0/1 = disable receiving OCAPI v4.0 opcodes / enable receiving on brick 2 | |
| 13 | RW | RW | CONFIG_ENABLE_BRK3_OCAPI_4: 0/1 = disable receiving OCAPI v4.0 opcodes / enable receiving on brick 3 | |
| 14 | RW | RW | CONFIG_ENABLE_BRK4_OCAPI_4: 0/1 = disable receiving OCAPI v4.0 opcodes / enable receiving on brick 4 | |
| 15 | RW | RW | CONFIG_ENABLE_BRK0_OCAPI_C2: 0/1 = disable receiving OCAPI C2 opcodes / enable receiving on brick 0 | |
| 16 | RW | RW | CONFIG_ENABLE_BRK1_OCAPI_C2: 0/1 = disable receiving OCAPI C2 opcodes / enable receiving on brick 1 | |
| 17 | RW | RW | CONFIG_ENABLE_BRK2_OCAPI_C2: 0/1 = disable receiving OCAPI C2 opcodes / enable receiving on brick 2 | |
| 18 | RW | RW | CONFIG_ENABLE_BRK3_OCAPI_C2: 0/1 = disable receiving OCAPI C2 opcodes / enable receiving on brick 3 | |
| 19 | RW | RW | CONFIG_ENABLE_BRK4_OCAPI_C2: 0/1 = disable receiving OCAPI C2 opcodes / enable receiving on brick 4 | |
| 20 | RW | RW | CONFIG_ENABLE_BRK0_OCAPI_AMO: 0/1 = disable receiving OCAPI AMO opcodes / enable receiving on brick 0 | |
| 21 | RW | RW | CONFIG_ENABLE_BRK1_OCAPI_AMO: 0/1 = disable receiving OCAPI AMO opcodes / enable receiving on brick 1 | |
| 22 | RW | RW | CONFIG_ENABLE_BRK2_OCAPI_AMO: 0/1 = disable receiving OCAPI AMO opcodes / enable receiving on brick 2 | |
| 23 | RW | RW | CONFIG_ENABLE_BRK3_OCAPI_AMO: 0/1 = disable receiving OCAPI AMO opcodes / enable receiving on brick 3 | |
| 24 | RW | RW | CONFIG_ENABLE_BRK4_OCAPI_AMO: 0/1 = disable receiving OCAPI AMO opcodes / enable receiving on brick 4 | |
| 25 | RW | RW | CONFIG_WRITE_MEM_OS_BIT_BRK0: The value of the 'Os' bit in OCAPI write_mem (128B) packets sent by the PAU to brick 0. | |
| 26 | RW | RW | CONFIG_WRITE_MEM_OS_BIT_BRK1: The value of the 'Os' bit in OCAPI write_mem (128B) packets sent by the PAU to brick 1. | |
| 27 | RW | RW | CONFIG_WRITE_MEM_OS_BIT_BRK2: The value of the 'Os' bit in OCAPI write_mem (128B) packets sent by the PAU to brick 2. | |
| 28 | RW | RW | CONFIG_WRITE_MEM_OS_BIT_BRK3: The value of the 'Os' bit in OCAPI write_mem (128B) packets sent by the PAU to brick 3. | |
| 29 | RW | RW | CONFIG_WRITE_MEM_OS_BIT_BRK4: The value of the 'Os' bit in OCAPI write_mem (128B) packets sent by the PAU to brick 4. | |
| 30:31 | RW | RW | CONFIG_GENID_SYNC_SCOPE: Scope to use for genid_sync commands 00 - Ln scope 01 - G scope 1- - Vg(sys) scope | |
| 32 | RW | RW | CONFIG_GENID_SYNC_FORCE_RCMD0: 0/1 = genid_sync cmds use all 4 RCmdx busses / genid_sync cmds use only RCmd0 | |
| 33 | RW | RW | CONFIG_BRK0_IMP_TAGS_MODE_ENABLE: 0/1 = disable IMP (HAPPI) iseries tags mode / enable tags mode for brick 0 Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 34 | RW | RW | CONFIG_BRK1_IMP_TAGS_MODE_ENABLE: 0/1 = disable IMP (HAPPI) iseries tags mode / enable tags mode for brick 1 Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 35 | RW | RW | CONFIG_BRK2_IMP_TAGS_MODE_ENABLE: 0/1 = disable IMP (HAPPI) iseries tags mode / enable tags mode for brick 2 Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 36 | RW | RW | CONFIG_BRK3_IMP_TAGS_MODE_ENABLE: 0/1 = disable IMP (HAPPI) iseries tags mode / enable tags mode for brick 3 Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 37 | RW | RW | CONFIG_BRK4_IMP_TAGS_MODE_ENABLE: 0/1 = disable IMP (HAPPI) iseries tags mode / enable tags mode for brick 4 Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this field's IDials | |
| 38 | RW | RW | CONFIG_ENABLE_CP_2CRED: 0/1 = enable 1 credit per RCmd for chip-pump outgoing commands / enable 2 credits per RCmd | |
| 39 | RW | RW | CONFIG_ENABLE_GP_2CRED: 0/1 = enable 1 credit per RCmd for group-pump outgoing commands / enable 2 credits per RCmd | |
| 40 | RW | RW | CONFIG_ENABLE_SP_2CRED: 0/1 = enable 1 credit per RCmd for system-pump outgoing commands / enable 2 credits per RCmd | |
| 41 | RW | RW | CONFIG_ENABLE_PB_BACK2BACK: 0/1 = limit pa_pb_cmd_* interface to 1 command every other cycle / allow back-to-back commands | |
| 42 | RW | RW | CONFIG_DISABLE_HW531747_CAS_T_IMP_TAGS: 0/1 = Fix iTags for write_mem.be due to cas_t in imp-tags mode / disable fix | |
| 43 | RW | RW | CONFIG_DISABLE_HW539321_SM_REQIN_CREDIT_DROP: 0/1 = Fix sm reqin credit-drop problem / disable fix | |
| 44 | RW | RW | CONFIG_DISABLE_HW539464_BACK_TO_BACK_SYNC_DONE: 0/1 = Prevent back-to-back sync_dones to OTL / disable fix | |
| 45 | RW | RW | CONFIG_ENABLE_HW549830_MI_RETRY_NON_CP: 0/1 = disable hw549830 fix / enable retrying non-cp commands back to requesting PAU when retried on the PowerBus. | |
| 46 | RW | RW | CONFIG_DISABLE_HW551717_ZERO_CO_FIELD: 0/1 = Zero out CO field / disable fix and allow CO field non-zero | |
| 47 | RW | RW | CONFIG2_RESERVED1: reserved. | |
| 48:55 | RW | RW | CONFIG_GENID_RATE_INC: Genid-sync command rate increment term. Genid-sync commands will be rate-limited to 1 every (rate_inc*64)/rate_dec cycles | |
| 56:63 | RW | RW | CONFIG_GENID_RATE_DEC: Genid-sync command rate decrement term. | |
| CQ_CTL Misc Config register #3 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010983 (SCOM) 0000000013440018 (PAU_RING) | |||
| Name: | PAU3.CS.CTL.MISC.CONFIG3 | |||
| Constant(s): | ||||
| Comments: | Misc config register Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.CTL.MISC.CONFIG3_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:2 | RW | RW | CONFIG_THROTTLE_MODE_PWR0: Throttle setting for PWR0 (normal LPC ops) allocation: 000 = disabled/none, no allocation/preallocation allowed 001 = low, preallocate 1 machine at all times, no recalls allowed 010 = med, preallocate 2 machines at all times, no recalls allowed 011 = high, preallocate 3 machines at all times, no recalls allowed 100 = auto-lmh, auto-throttle allowed to set low, med, and high. recalls allowed 101 = auto-low, auto-throttle allowed to set on-demand and low. recalls allowed 110 = auto-med, auto-throttle allowed to set on-demand, low, and med. recalls allowed 111 = auto-high, auto-throttle allowed to set on-demand, low, med, and high. recalls allowed | |
| 3:5 | RW | RW | CONFIG_THROTTLE_MODE_PWR1: Throttle setting for PWR1 (cp_* ops) allocation | |
| 6:8 | RW | RW | CONFIG_THROTTLE_MODE_PWR2: Throttle setting for PWR2 (snooped for force_evict) allocation | |
| 9:11 | RW | RW | CONFIG_THROTTLE_MODE_XATS: Throttle setting for XSL/ATS allocation | |
| 12:14 | RW | RW | CONFIG_THROTTLE_MODE_INTS: Throttle setting for INTS allocation | |
| 15:17 | RW | RW | CONFIG_THROTTLE_MODE_REQ0: Throttle setting for brick-0 REQ/TLX.vc.3 allocation | |
| 18:20 | RW | RW | CONFIG_THROTTLE_MODE_CST0: Throttle setting for brick-0 CST/TLX.vc.2 allocation | |
| 21:23 | RW | RW | CONFIG_THROTTLE_MODE_PRB0: Throttle setting for brick-0 PRB/TLX.vc.1 allocation | |
| 24:26 | RW | RW | CONFIG_THROTTLE_MODE_REQ1: Throttle setting for brick-1 REQ/TLX.vc.3 allocation | |
| 27:29 | RW | RW | CONFIG_THROTTLE_MODE_CST1: Throttle setting for brick-1 CST/TLX.vc.2 allocation | |
| 30:32 | RW | RW | CONFIG_THROTTLE_MODE_PRB1: Throttle setting for brick-1 PRB/TLX.vc.1 allocation | |
| 33:35 | RW | RW | CONFIG_THROTTLE_MODE_REQ2: Throttle setting for brick-2 REQ/TLX.vc.3 allocation | |
| 36:38 | RW | RW | CONFIG_THROTTLE_MODE_CST2: Throttle setting for brick-2 CST/TLX.vc.2 allocation | |
| 39:41 | RW | RW | CONFIG_THROTTLE_MODE_PRB2: Throttle setting for brick-2 PRB/TLX.vc.1 allocation | |
| 42:44 | RW | RW | CONFIG_THROTTLE_MODE_REQ3: Throttle setting for brick-3 REQ/TLX.vc.3 allocation | |
| 45:47 | RW | RW | CONFIG_THROTTLE_MODE_CST3: Throttle setting for brick-3 CST/TLX.vc.2 allocation | |
| 48:50 | RW | RW | CONFIG_THROTTLE_MODE_PRB3: Throttle setting for brick-3 PRB/TLX.vc.1 allocation | |
| 51:53 | RW | RW | CONFIG_THROTTLE_MODE_REQ4: Throttle setting for brick-4 REQ/TLX.vc.3 allocation | |
| 54:56 | RW | RW | CONFIG_THROTTLE_MODE_CST4: Throttle setting for brick-4 CST/TLX.vc.2 allocation | |
| 57:59 | RW | RW | CONFIG_THROTTLE_MODE_PRB4: Throttle setting for brick-4 PRB/TLX.vc.1 allocation | |
| 60:63 | RW | RW | CONFIG3_RESERVED1: reserved | |
| Perf Match Reg | ||||
|---|---|---|---|---|
| Addr: |
0000000011010984 (SCOM) 0000000013440020 (PAU_RING) | |||
| Name: | PAU3.CS.CTL.MISC.PERF_MATCH_CONFIG | |||
| Constant(s): | ||||
| Comments: | Performance Event Field Match | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:27 | PAU3.CS.CTL.MISC.PERF_MATCH_CONFIG_Q_0_INST.LATC.L2(0:27) [0000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:11 | RW | RW | PERF_MATCH_TTYPE: TType (PAU-CQ encoding) | |
| 12:19 | RW | RW | PERF_MATCH_TSIZE: TSize (PAU-CQ encoding) | |
| 20:23 | RW | RW | PERF_MATCH_PE: PE | |
| 24 | RW | RW | PERF_MATCH_BE: Byte-Enables | |
| 25:27 | RW | RW | PERF_MATCH_RESERVED: reserved | |
| 28:63 | RO | RO | constant=0b000000000000000000000000000000000000 | |
| Perf Mask Reg | ||||
|---|---|---|---|---|
| Addr: |
0000000011010985 (SCOM) 0000000013440028 (PAU_RING) | |||
| Name: | PAU3.CS.CTL.MISC.PERF_MASK_CONFIG | |||
| Constant(s): | ||||
| Comments: | Performance Event Field Mask | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:27 | PAU3.CS.CTL.MISC.PERF_MASK_CONFIG_Q_0_INST.LATC.L2(0:27) [0000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:11 | RW | RW | PERF_MASK_TTYPE: TType (PAU-CQ encoding) | |
| 12:19 | RW | RW | PERF_MASK_TSIZE: TSize (PAU-CQ encoding) | |
| 20:23 | RW | RW | PERF_MASK_PE: PE | |
| 24 | RW | RW | PERF_MASK_BE: Byte-Enables | |
| 25:27 | RW | RW | PERF_MASK_RESERVED: reserved | |
| 28:63 | RO | RO | constant=0b000000000000000000000000000000000000 | |
| CQ_CTL PMULet Counts | ||||
|---|---|---|---|---|
| Addr: |
0000000011010986 (SCOM) 0000000013440030 (PAU_RING) | |||
| Name: | PAU3.CS.CTL.MISC.PERF_COUNT | |||
| Constant(s): | ||||
| Comments: | PMULet Count values | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:15 | PAU3.CS.CTL.MISC.PMLET.COUNTER0_CNT_Q_0_INST.LATC.L2(0:15) [0000000000000000] | |||
| 16:31 | PAU3.CS.CTL.MISC.PMLET.COUNTER1_CNT_Q_0_INST.LATC.L2(0:15) [0000000000000000] | |||
| 32:47 | PAU3.CS.CTL.MISC.PMLET.COUNTER2_CNT_Q_0_INST.LATC.L2(0:15) [0000000000000000] | |||
| 48:63 | PAU3.CS.CTL.MISC.PMLET.COUNTER3_CNT_Q_0_INST.LATC.L2(0:15) [0000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:15 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_PERF_COUNT0: Performance Counter 0 | |
| 16:31 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_PERF_COUNT1: Performance Counter 1 | |
| 32:47 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_PERF_COUNT2: Performance Counter 2 | |
| 48:63 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_PERF_COUNT3: Performance Counter 3 | |
| Perf Config Reg | ||||
|---|---|---|---|---|
| Addr: |
0000000011010987 (SCOM) 0000000013440038 (PAU_RING) | |||
| Name: | PAU3.CS.CTL.MISC.PERF_CONFIG | |||
| Constant(s): | ||||
| Comments: | Performance Event selection | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.CTL.MISC.PERF_CONFIG_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | PERF_CONFIG_ENABLE: PMULet Enable (clocks enable) | |
| 1 | RW | RW | PERF_CONFIG_RESETMODE: 0/1 = reset-on-read/reset-on-write | |
| 2 | RW | RW | PERF_CONFIG_FREEZEMODE: 0/1 = freerun-mode/freeze-on-any-max | |
| 3 | RW | RW | PERF_CONFIG_DISABLE_PMISC: 0/1 = enable-pmisc/disable-pmisc control of counters | |
| 4 | RW | RW | PERF_CONFIG_PMISC_MODE: 0/1 = global pmu pmisc no reset/global pmu misc reset-on-enable | |
| 5:7 | RW | RW | PERF_CONFIG_CASCADE: pmulet cascade config | |
| 8:9 | RW | RW | PERF_CONFIG_PRESCALE_C0: prescale config for counter 0 | |
| 10:11 | RW | RW | PERF_CONFIG_PRESCALE_C1: prescale config for counter 1 | |
| 12:13 | RW | RW | PERF_CONFIG_PRESCALE_C2: prescale config for counter 2 | |
| 14:15 | RW | RW | PERF_CONFIG_PRESCALE_C3: prescale config for counter 3 | |
| 16:23 | RW | RW | PERF_CONFIG_EVENT0: Event 0 select | |
| 24:31 | RW | RW | PERF_CONFIG_EVENT1: Event 0 select | |
| 32:39 | RW | RW | PERF_CONFIG_EVENT2: Event 0 select | |
| 40:47 | RW | RW | PERF_CONFIG_EVENT3: Event 0 select | |
| 48:52 | RW | RW | PERF_CONFIG_LATSTART: Latency count start event | |
| 53:57 | RW | RW | PERF_CONFIG_LATCANCEL: Latency count abort event | |
| 58:62 | RW | RW | PERF_CONFIG_LATFINISH: Latency count finish event | |
| 63 | RW | RW | PERF_CONFIG_LATFILTER: 0/1 = count max latency events / filter latency events by 1/1024 for bias reduction | |
| Debug0 Config Reg | ||||
|---|---|---|---|---|
| Addr: |
0000000011010988 (SCOM) 0000000013440040 (PAU_RING) | |||
| Name: | PAU3.CS.CTL.MISC.DEBUG0_CONFIG | |||
| Constant(s): | ||||
| Comments: | Config register for trace-0 chain | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.CTL.MISC.DEBUG0_CONFIG_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:4 | RW | RW | DEBUG0_CONFIG_POD0: Mux control for byte 0 of trace-0 | |
| 5:9 | RW | RW | DEBUG0_CONFIG_POD1: Mux control for byte 1 of trace-0 | |
| 10:14 | RW | RW | DEBUG0_CONFIG_POD2: Mux control for byte 2 of trace-0 | |
| 15:19 | RW | RW | DEBUG0_CONFIG_POD3: Mux control for byte 3 of trace-0 | |
| 20:24 | RW | RW | DEBUG0_CONFIG_POD4: Mux control for byte 4 of trace-0 | |
| 25:29 | RW | RW | DEBUG0_CONFIG_POD5: Mux control for byte 5 of trace-0 | |
| 30:34 | RW | RW | DEBUG0_CONFIG_POD6: Mux control for byte 6 of trace-0 | |
| 35:39 | RW | RW | DEBUG0_CONFIG_POD7: Mux control for byte 7 of trace-0 | |
| 40:44 | RW | RW | DEBUG0_CONFIG_POD8: Mux control for byte 8 of trace-0 | |
| 45:49 | RW | RW | DEBUG0_CONFIG_POD9: Mux control for byte 9 of trace-0 | |
| 50:54 | RW | RW | DEBUG0_CONFIG_POD10: Mux control for byte 10 of trace-0 | |
| 55 | RW | RW | DEBUG0_CONFIG_RESERVED1: reserved | |
| 56 | RW | RW | CONFIG_DEBUG_MUX_ENABLE_REQIN: Enable TDM tracing of request-in path | |
| 57 | RW | RW | CONFIG_DEBUG_MUX_ENABLE_REQIN2: Enable TDM tracing of request-in path, 2nd cycle | |
| 58 | RW | RW | CONFIG_DEBUG_MUX_ENABLE_RSPIN: Enable TDM tracing of response-in path | |
| 59 | RW | RW | CONFIG_DEBUG_MUX_ENABLE_REQOUT: Enable TDM tracing of request-out path | |
| 60 | RW | RW | CONFIG_DEBUG_MUX_ENABLE_RSPOUT: Enable TDM tracing of response-out path | |
| 61:62 | RW | RW | DEBUG0_CONFIG_RESERVED2: reserved | |
| 63 | RW | RW | DEBUG0_CONFIG_ACT: Enable clock-gates for debug trace latches | |
| Debug1 Config Reg | ||||
|---|---|---|---|---|
| Addr: |
0000000011010989 (SCOM) 0000000013440048 (PAU_RING) | |||
| Name: | PAU3.CS.CTL.MISC.DEBUG1_CONFIG | |||
| Constant(s): | ||||
| Comments: | Config register for trace-1 chain | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.CTL.MISC.DEBUG1_CONFIG_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:4 | RW | RW | DEBUG1_CONFIG_POD0: Mux control for byte 0 of trace-1 | |
| 5:9 | RW | RW | DEBUG1_CONFIG_POD1: Mux control for byte 1 of trace-1 | |
| 10:14 | RW | RW | DEBUG1_CONFIG_POD2: Mux control for byte 2 of trace-1 | |
| 15:19 | RW | RW | DEBUG1_CONFIG_POD3: Mux control for byte 3 of trace-1 | |
| 20:24 | RW | RW | DEBUG1_CONFIG_POD4: Mux control for byte 4 of trace-1 | |
| 25:29 | RW | RW | DEBUG1_CONFIG_POD5: Mux control for byte 5 of trace-1 | |
| 30:34 | RW | RW | DEBUG1_CONFIG_POD6: Mux control for byte 6 of trace-1 | |
| 35:39 | RW | RW | DEBUG1_CONFIG_POD7: Mux control for byte 7 of trace-1 | |
| 40:44 | RW | RW | DEBUG1_CONFIG_POD8: Mux control for byte 8 of trace-1 | |
| 45:49 | RW | RW | DEBUG1_CONFIG_POD9: Mux control for byte 9 of trace-1 | |
| 50:54 | RW | RW | DEBUG1_CONFIG_POD10: Mux control for byte 10 of trace-1 | |
| 55:62 | RW | RW | DEBUG1_CONFIG_RESERVED1: reserved | |
| 63 | RW | RW | DEBUG1_CONFIG_ACT: Enable clock-gates for debug trace latches | |
| LPC-Threshold config register | ||||
|---|---|---|---|---|
| Addr: |
000000001101098A (SCOM) 0000000013440050 (PAU_RING) | |||
| Name: | PAU3.CS.CTL.MISC.LPCTH_CONFIG | |||
| Constant(s): | ||||
| Comments: | PowerBus spec E.2 Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:35 | PAU3.CS.CTL.MISC.LPCTH_CONFIG_Q_0_INST.LATC.L2(0:35) [000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_LPCTH_BUSY_ENABLE: 0/1 = disable thresholding/enable thresholding | |
| 1:3 | RW | RW | CONFIG_LPCTH_WINDOW_SELECT: 001 = 256 cycle window 010 = 512 cycle window 100 = 1024 cycle window | |
| 4:13 | RW | RW | CONFIG_LPCTH_THRESH_0: Busy counter threshold 0. When this threshold is exceeded, the LPC_th field in the partial response aTag is set to '01' | |
| 14:23 | RW | RW | CONFIG_LPCTH_THRESH_1: Busy counter threshold 1. When this threshold is exceeded, the LPC_th field in the partial response aTag is set to '10' | |
| 24:33 | RW | RW | CONFIG_LPCTH_THRESH_2: Busy counter threshold 2. When this threshold is exceeded, the LPC_th field in the partial response aTag is set to '11' | |
| 34:35 | RW | RW | CONFIG_LPCTH_RESERVED1: reserved | |
| 36:63 | RO | RO | constant=0b0000000000000000000000000000 | |
| Inhibit configuration Register | ||||
|---|---|---|---|---|
| Addr: |
000000001101098B (SCOM) 0000000013440058 (PAU_RING) | |||
| Name: | PAU3.CS.CTL.MISC.INHIBIT_CONFIG | |||
| Constant(s): | ||||
| Comments: | Configures Inhibits for CQ_CTL | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.CTL.MISC.INHIBIT_CONFIG_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:3 | RW | RW | CONFIG_INHIBIT_LFREQ0: Base LFSR frequency 0: 0..11 = 1/2^(n+1) 12 = 1/2^14 13 = 1/2^16 14 = 1/2^18 15 = 1/2^20 | |
| 4:5 | RW | RW | CONFIG_INHIBIT_PFREQ0: Selects pre frequency 0: 0 = Inh0 timer tick (config_ctl_inh0_tick) timer tick 1 = inverted config_ctl_inh0_tick timer tick 2 = LFSR 3 = inverted LFSR (-> 1/2, 3/4, 7/8, ...) | |
| 6 | RW | RW | CONFIG_INHIBIT_BLOCKY0: 0/1 = disable blocky mode / enable blocky mode | |
| 7 | RW | RW | CONFIG_INHIBIT_ONESHOT0: 0/1 = continus mode / one-shot mode | |
| 8:15 | RW | RW | CONFIG_INHIBIT_DEST0: Selects the destination of the inhibit | |
| 16:19 | RW | RW | CONFIG_INHIBIT_LFREQ1: Base LFSR frequency 0: 0..11 = 1/2^(n+1) 12 = 1/2^14 13 = 1/2^16 14 = 1/2^18 15 = 1/2^20 | |
| 20:21 | RW | RW | CONFIG_INHIBIT_PFREQ1: Selects pre frequency 0: 0 = Inh1 timer tick (config_ctl_inh1_tick) timer tick 1 = inverted config_ctl_inh1_tick timer tick 2 = LFSR 3 = inverted LFSR (-> 1/2, 3/4, 7/8, ...) | |
| 22 | RW | RW | CONFIG_INHIBIT_BLOCKY1: 0/1 = disable blocky mode / enable blocky mode | |
| 23 | RW | RW | CONFIG_INHIBIT_ONESHOT1: 0/1 = continus mode / one-shot mode | |
| 24:31 | RW | RW | CONFIG_INHIBIT_DEST1: Selects the destination of the inhibit | |
| 32:35 | RW | RW | CONFIG_INHIBIT_LFREQ2: Base LFSR frequency 2: 0..11 = 1/2^(n+1) 12 = 1/2^14 13 = 1/2^16 14 = 1/2^18 15 = 1/2^20 | |
| 36:37 | RW | RW | CONFIG_INHIBIT_PFREQ2: Selects pre frequency 2: 0 = Inh2 timer tick (config_ctl_inh2_tick) timer tick 1 = inverted config_ctl_inh2_tick timer tick 2 = LFSR 3 = inverted LFSR (-> 1/2, 3/4, 7/8, ...) | |
| 38 | RW | RW | CONFIG_INHIBIT_BLOCKY2: 0/1 = disable blocky mode / enable blocky mode | |
| 39 | RW | RW | CONFIG_INHIBIT_ONESHOT2: 0/1 = continus mode / one-shot mode | |
| 40:47 | RW | RW | CONFIG_INHIBIT_DEST2: Selects the destination of the inhibit | |
| 48:51 | RW | RW | CONFIG_INHIBIT_LFREQ3: Base LFSR frequency 3: 0..11 = 1/2^(n+1) 12 = 1/2^14 13 = 1/2^16 14 = 1/2^18 15 = 1/2^20 | |
| 52:53 | RW | RW | CONFIG_INHIBIT_PFREQ3: Selects pre frequency 3: 0 = Inh3 timer tick (config_ctl_inh2_tick) timer tick 1 = inverted config_ctl_inh3_tick timer tick 2 = LFSR 3 = inverted LFSR (-> 1/2, 3/4, 7/8, ...) | |
| 54 | RW | RW | CONFIG_INHIBIT_BLOCKY3: 0/1 = disable blocky mode / enable blocky mode | |
| 55 | RW | RW | CONFIG_INHIBIT_ONESHOT3: 0/1 = continus mode / one-shot mode | |
| 56:63 | RW | RW | CONFIG_INHIBIT_DEST3: Selects the destination of the inhibit | |
| CQ_CTL status register 1 | ||||
|---|---|---|---|---|
| Addr: |
000000001101098C (SCOM) 0000000013440060 (PAU_RING) | |||
| Name: | PAU3.CS.CTL.MISC.CTL_STATUS1 | |||
| Constant(s): | ||||
| Comments: | Status reporting register number 1 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:47 | PAU3.CS.CTL.MISC.CTL_STATUS1_Q_0_INST.LATC.L2(0:47) [000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | ROX | ROX | CTL_STATUS_SM_MMIO0: 1 when SM slice 0 has an MMIO pending | |
| 1 | ROX | ROX | CTL_STATUS_SM_MMIO1: 1 when SM slice 1 has an MMIO pending | |
| 2 | ROX | ROX | CTL_STATUS_SM_MMIO2: 1 when SM slice 2 has an MMIO pending | |
| 3 | ROX | ROX | CTL_STATUS_SM_MMIO3: 1 when SM slice 3 has an MMIO pending | |
| 4:7 | ROX | ROX | CTL_STATUS_MRBGP: Master-Retry backoff level for Group-Pump commands | |
| 8:11 | ROX | ROX | CTL_STATUS_MRBSP: Master-Retry backoff level for System-Pump commands | |
| 12:15 | ROX | ROX | CTL_STATUS_MRBCP: Master-Retry backoff level for Chip-Pump commands | |
| 16:17 | ROX | ROX | CTL_STATUS_LPCTH: LPC-Threshold value driven in partial-responses | |
| 18 | ROX | ROX | CTL_STATUS_ATS_SYNC: 1 when ATS-Sync is idle | |
| 19 | ROX | ROX | CTL_STATUS_NMMU: 1 when NMMU outbound-message is idle | |
| 20 | ROX | ROX | CTL_STATUS_PBLN: 1 when outbound PowerBus Ln-scope queue is empty | |
| 21 | ROX | ROX | CTL_STATUS_PBNNG: 1 when outbound PowerBus Nn/G-scope queue is empty | |
| 22 | ROX | ROX | CTL_STATUS_PBRNVG: 1 when outbound PowerBus Rn/Vg-scope queue is empty | |
| 23 | ROX | ROX | CTL_STATUS_ATSREQ: 1 when outbound ATS-TCE-Translate request queue is empty | |
| 24 | ROX | ROX | CTL_STATUS_MMIO: 1 when MMIO/GenId state machine is idle | |
| 25 | ROX | ROX | CTL_STATUS_MMIOSUE: 1 when MMIO/GenId state machine is idle (SUE data) | |
| 26 | ROX | ROX | CTL_STATUS_PBRS: 1 when outbound PB-Response/Merge queue is empty | |
| 27 | ROX | ROX | CTL_STATUS_XARS: 1 when outbound ATS/MISC response queue is empty | |
| 28 | ROX | ROX | CTL_STATUS_ATRR: 1 when outbound ATR-Response logic is idle | |
| 29 | ROX | ROX | CTL_STATUS_REPLAY: 1 when the internal replay (directory results/lock) queue is empty | |
| 30 | ROX | ROX | CTL_STATUS_XSL_FAST_FENCE: fast-fence signal from XSL | |
| 31 | ROX | ROX | CTL_STATUS_RESERVED: reserved | |
| 32:36 | ROX | ROX | CTL_STATUS_FENCE0: Brick-0 Fence sequencing state 0b00000 = Idle state, completely unfenced 0b10000 = Fenced state, fence sequencing complete 0b10001 = Disabled state, xTL's Enable bit must be off 0b10100 = Half-Fenced state, NTL is un-fenced others = in transition between states | |
| 37 | ROX | ROX | CTL_STATUS_BRK0_RLX: 1 when brick-0 Gen-Id/relaxed-ordering is idle | |
| 38 | ROX | ROX | CTL_STATUS_NVREQ0: 1 when outbound brick 0 request queue is empty | |
| 39 | ROX | ROX | CTL_STATUS_NVDGD0: 1 when outbound brick 0 downgrade queue is empty | |
| 40 | ROX | ROX | CTL_STATUS_NVRS0: 1 when outbound brick 0 response queue is empty | |
| 41:42 | ROX | ROX | CTL_STATUS_BRK0_AM_FENCED: Status of fence on brick 0 00 - Reset disabled 11 - Reset (Fence) both OTL/NTL and the PowerBus for this Brick 10 - Reset (Fence) only the PowerBus for this Brick, OTL/NTL will be operational 01 - Reserved | |
| 43:44 | ROX | ROX | CTL_STATUS_BRK0_NTL_REQ_FENCE: NTL Request for fence of brick 0 00 - Reset disabled 11 - Reset (Fence) both OTL/NTL and the PowerBus for this Brick 10 - Reset (Fence) only the PowerBus for this Brick, OTL/NTL will be operational 01 - Reserved | |
| 45 | ROX | ROX | CTL_STATUS_BRK0_MISC_FENCE: brick 0 fence signal from pau-misc | |
| 46:47 | ROX | ROX | CTL_STATUS_BRK0_RESERVED: reserved | |
| 48:63 | RO | RO | constant=0b0000000000000000 | |
| CQ_CTL status register 2 | ||||
|---|---|---|---|---|
| Addr: |
000000001101098D (SCOM) 0000000013440068 (PAU_RING) | |||
| Name: | PAU3.CS.CTL.MISC.CTL_STATUS2 | |||
| Constant(s): | ||||
| Comments: | Status reporting register number 2 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.CTL.MISC.CTL_STATUS2_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:4 | ROX | ROX | CTL_STATUS_FENCE1: Brick-1 Fence sequencing state 0b00000 = Idle state, completely unfenced 0b10000 = Fenced state, fence sequencing complete 0b10001 = Disabled state, xTL's Enable bit must be off 0b10100 = Half-Fenced state, NTL is un-fenced others = in transition between states | |
| 5 | ROX | ROX | CTL_STATUS_BRK1_RLX: 1 when brick-1 Gen-Id/relaxed-ordering is idle | |
| 6 | ROX | ROX | CTL_STATUS_NVREQ1: 1 when outbound brick 1 request queue is empty | |
| 7 | ROX | ROX | CTL_STATUS_NVDGD1: 1 when outbound brick 1 downgrade queue is empty | |
| 8 | ROX | ROX | CTL_STATUS_NVRS1: 1 when outbound brick 1 response queue is empty | |
| 9:10 | ROX | ROX | CTL_STATUS_BRK1_AM_FENCED: Status of fence on brick 1 00 - Reset disabled 11 - Reset (Fence) both OTL/NTL and the PowerBus for this Brick 10 - Reset (Fence) only the PowerBus for this Brick, OTL/NTL will be operational 01 - Reserved | |
| 11:12 | ROX | ROX | CTL_STATUS_BRK1_NTL_REQ_FENCE: NTL Request for fence of brick 1 00 - Reset disabled 11 - Reset (Fence) both OTL/NTL and the PowerBus for this Brick 10 - Reset (Fence) only the PowerBus for this Brick, OTL/NTL will be operational 01 - Reserved | |
| 13 | ROX | ROX | CTL_STATUS_BRK1_MISC_FENCE: brick 1 fence signal from pau-misc | |
| 14:15 | ROX | ROX | CTL_STATUS_BRK1_RESERVED: reserved | |
| 16:20 | ROX | ROX | CTL_STATUS_FENCE2: Brick-2 Fence sequencing state 0b00000 = Idle state, completely unfenced 0b10000 = Fenced state, fence sequencing complete 0b10001 = Disabled state, xTL's Enable bit must be off 0b10100 = Half-Fenced state, NTL is un-fenced others = in transition between states | |
| 21 | ROX | ROX | CTL_STATUS_BRK2_RLX: 1 when brick-2 Gen-Id/relaxed-ordering is idle | |
| 22 | ROX | ROX | CTL_STATUS_NVREQ2: 1 when outbound brick 2 request queue is empty | |
| 23 | ROX | ROX | CTL_STATUS_NVDGD2: 1 when outbound brick 2 downgrade queue is empty | |
| 24 | ROX | ROX | CTL_STATUS_NVRS2: 1 when outbound brick 2 response queue is empty | |
| 25:26 | ROX | ROX | CTL_STATUS_BRK2_AM_FENCED: Status of fence on brick 2 00 - Reset disabled 11 - Reset (Fence) both OTL/NTL and the PowerBus for this Brick 10 - Reset (Fence) only the PowerBus for this Brick, OTL/NTL will be operational 01 - Reserved | |
| 27:28 | ROX | ROX | CTL_STATUS_BRK2_NTL_REQ_FENCE: NTL Request for fence of brick 2 00 - Reset disabled 11 - Reset (Fence) both OTL/NTL and the PowerBus for this Brick 10 - Reset (Fence) only the PowerBus for this Brick, OTL/NTL will be operational 01 - Reserved | |
| 29 | ROX | ROX | CTL_STATUS_BRK2_MISC_FENCE: brick 2 fence signal from pau-misc | |
| 30:31 | ROX | ROX | CTL_STATUS_BRK2_RESERVED: reserved | |
| 32:36 | ROX | ROX | CTL_STATUS_FENCE3: Brick-3 Fence sequencing state 0b00000 = Idle state, completely unfenced 0b10000 = Fenced state, fence sequencing complete 0b10001 = Disabled state, xTL's Enable bit must be off 0b10100 = Half-Fenced state, NTL is un-fenced others = in transition between states | |
| 37 | ROX | ROX | CTL_STATUS_BRK3_RLX: 1 when brick-3 Gen-Id/relaxed-ordering is idle | |
| 38 | ROX | ROX | CTL_STATUS_NVREQ3: 1 when outbound brick 3 request queue is empty | |
| 39 | ROX | ROX | CTL_STATUS_NVDGD3: 1 when outbound brick 3 downgrade queue is empty | |
| 40 | ROX | ROX | CTL_STATUS_NVRS3: 1 when outbound brick 3 response queue is empty | |
| 41:42 | ROX | ROX | CTL_STATUS_BRK3_AM_FENCED: Status of fence on brick 3 00 - Reset disabled 11 - Reset (Fence) both OTL/NTL and the PowerBus for this Brick 10 - Reset (Fence) only the PowerBus for this Brick, OTL/NTL will be operational 01 - Reserved | |
| 43:44 | ROX | ROX | CTL_STATUS_BRK3_NTL_REQ_FENCE: NTL Request for fence of brick 3 00 - Reset disabled 11 - Reset (Fence) both OTL/NTL and the PowerBus for this Brick 10 - Reset (Fence) only the PowerBus for this Brick, OTL/NTL will be operational 01 - Reserved | |
| 45 | ROX | ROX | CTL_STATUS_BRK3_MISC_FENCE: brick 3 fence signal from pau-misc | |
| 46:47 | ROX | ROX | CTL_STATUS_BRK3_RESERVED: reserved | |
| 48:52 | ROX | ROX | CTL_STATUS_FENCE4: Brick-4 Fence sequencing state 0b00000 = Idle state, completely unfenced 0b10000 = Fenced state, fence sequencing complete 0b10001 = Disabled state, xTL's Enable bit must be off 0b10100 = Half-Fenced state, NTL is un-fenced others = in transition between states | |
| 53 | ROX | ROX | CTL_STATUS_BRK4_RLX: 1 when brick-4 Gen-Id/relaxed-ordering is idle | |
| 54 | ROX | ROX | CTL_STATUS_NVREQ4: 1 when outbound brick 4 request queue is empty | |
| 55 | ROX | ROX | CTL_STATUS_NVDGD4: 1 when outbound brick 4 downgrade queue is empty | |
| 56 | ROX | ROX | CTL_STATUS_NVRS4: 1 when outbound brick 4 response queue is empty | |
| 57:58 | ROX | ROX | CTL_STATUS_BRK4_AM_FENCED: Status of fence on brick 4 00 - Reset disabled 11 - Reset (Fence) both OTL/NTL and the PowerBus for this Brick 10 - Reset (Fence) only the PowerBus for this Brick, OTL/NTL will be operational 01 - Reserved | |
| 59:60 | ROX | ROX | CTL_STATUS_BRK4_NTL_REQ_FENCE: NTL Request for fence of brick 4 00 - Reset disabled 11 - Reset (Fence) both OTL/NTL and the PowerBus for this Brick 10 - Reset (Fence) only the PowerBus for this Brick, OTL/NTL will be operational 01 - Reserved | |
| 61 | ROX | ROX | CTL_STATUS_BRK4_MISC_FENCE: brick 4 fence signal from pau-misc | |
| 62:63 | ROX | ROX | CTL_STATUS_BRK4_RESERVED: reserved | |
| GPU0-Memory BAR | ||||
|---|---|---|---|---|
| Addr: |
000000001101098E (SCOM) 0000000013440070 (PAU_RING) | |||
| Name: | PAU3.CS.CTL.MISC.GPU0_BAR | |||
| Constant(s): | ||||
| Comments: | BAR register defining GPU Mem addresses serviced by brick 0 connected to this stack. Note: This register should be set to the same value for each brick/stack. MDials have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:51 | PAU3.CS.CTL.MISC.GPU0_BAR_Q_0_INST.LATC.L2(0:51) [0000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_GPU0_BAR_ENABLE: Enable for this BAR (0=disabled, 1=enabled) for brick 0 | |
| 1:35 | RW | RW | CONFIG_GPU0_BAR_ADDR_MASK: BAR Address/Mask bits 1:35 for brick 0 In Small-BAR mode (see bit 36): 1:7 = Base_Addr(13:19) = 16T slice 8:21 = Base_Addr(20:33) = 1G address in slice 22:35 = Base_Mask(20:33) = 1G...16T BAR size. (Note: Mask limited to 1G...4T in Axone and P10 w/ GPU systems) In Large-BAR mode (see bit 36): 1 = '1' to match MemSel = addr(13:14) = 0b00 2 = '1' to match MemSel = addr(13:14) = 0b01 3 = '1' to match MemSel = addr(13:14) = 0b10 4:35 = Topology_Id_Mask(0:31) when chip_eq_group=0, TIM(0:31) bit 'i' corresponds to addr(15:19) = 'i' when chip_eq_group=1, TIM(0:31) bit 'i' corresponds to (addr(15:16) & addr(19:21)) = 'i' | |
| 36 | RW | RW | CONFIG_GPU0_BAR_SL_MODE: 0/1 = Small-BAR/Large-BAR Mode selector | |
| 37 | RW | RW | CONFIG_GPU0_BAR_4T_LIMIT: 0 = no limit, 16T slices can be used. 1 = limit slices to 4T. -> when chip_eq_group=0, addr(20:21) must match bar_4t_select -> when chip_eq_group=1, addr(17:18) must match bar_4t_select limit=1 is used in P10 systems w/ a GPU or in Axone systems | |
| 38:39 | RW | RW | CONFIG_GPU0_BAR_4T_SELECT: when bar_4t_limit=1 this field selects the value in addr(20:21) or addr(17:18) to match | |
| 40:43 | RW | RW | CONFIG_GPU0_BAR_MODE: Hash mode of the BAR for brick 0: if bar_extended_mode == 0: 0 = (single) match on all address in addr/size 1 = (dual.0) match if hashbits(7)=0 2 = (dual.1) match if hashbits(7)=1 3 = (triple.0) match if hashbits%3=0 4 = (triple.1) match if hashbits%3=1 5 = (triple.2) match if hashbits%3=2 6 = (quad.0) match if hashbits(6:7)=0 7 = (quad.1) match if hashbits(6:7)=1 8 = (quad.2) match if hashbits(6:7)=2 9 = (quad.3) match if hashbits(6:7)=3 10 = (six.0) match if hashbits%3=0 and hashbits(7)=0 11 = (six.1) match if hashbits%3=0 and hashbits(7)=1 12 = (six.2) match if hashbits%3=1 and hashbits(7)=0 13 = (six.3) match if hashbits%3=1 and hashbits(7)=1 14 = (six.4) match if hashbits%3=2 and hashbits(7)=0 15 = (six.5) match if hashbits%3=2 and hashbits(7)=1 if bar_extended_mode == 1: 0 = (oct.0) match if hashbits(5:7)=0 1 = (oct.1) match if hashbits(5:7)=1 2 = (oct.2) match if hashbits(5:7)=2 3 = (oct.3) match if hashbits(5:7)=3 4 = (oct.4) match if hashbits(5:7)=4 5 = (oct.5) match if hashbits(5:7)=5 6 = (oct.6) match if hashbits(5:7)=6 7 = (oct.7) match if hashbits(5:7)=7 others = reserved | |
| 44 | RW | RW | CONFIG_GPU0_BAR_GRANULE: Hash boundary for brick 0: 0 = hash on 512B boundary (hashbits(0:7)=addr(47:54)) 1 = hash on 1024B boundary (hashbits(0:7)=addr(46:53)) | |
| 45 | RW | RW | CONFIG_GPU0_BAR_POISON: on failed access return all ones 0/1 = with good ECC / with SUE ECC. | |
| 46 | RW | RW | CONFIG_GPU0_BAR_M2MODE: 0 = OpenCAPI AFU M1 mode / 1 = OpenCAPI AFU M2 mode Has no effect when in NVLink mode | |
| 47 | RW | RW | CONFIG_GPU0_BAR_PA_IGNORE_MODE: Set to '1' for RA-to-PA conversion to ignore the mode field | |
| 48 | RW | RW | CONFIG_GPU0_BAR_SECURE_A12: P10 Only: this specifies the addr(12) value to match for this BAR. Can only be set to one in P10 and only when SMF_CONFIG=0b11. | |
| 49 | RW | RW | CONFIG_GPU0_BAR_CHIP_EQ_GROUP: Axone Only: this specifies that the system is in chip=group mode. This bit should only be set when sl_mode=1 and 4t_limit=1. 0/1 = TIM(0:31) applies to addr(15:19) / TIM(0:31) applies to (addr(15:16) & addr(19:21)). | |
| 50 | RW | RW | CONFIG_GPU0_BAR_EXTENDED_MODE: 0/1 = bar_mode selects 1,2,3,4,6 way hashing / bar_mode selects 8-way hashing | |
| 51 | RW | RW | CONFIG_GPU0_BAR_RESERVED: reserved | |
| 52:63 | RO | RO | constant=0b000000000000 | |
| GPU1-Memory BAR | ||||
|---|---|---|---|---|
| Addr: |
000000001101098F (SCOM) 0000000013440078 (PAU_RING) | |||
| Name: | PAU3.CS.CTL.MISC.GPU1_BAR | |||
| Constant(s): | ||||
| Comments: | BAR register defining GPU Mem addresses serviced by brick 1 connected to this stack. Note: This register should be set to the same value for each brick/stack. MDials have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:51 | PAU3.CS.CTL.MISC.GPU1_BAR_Q_0_INST.LATC.L2(0:51) [0000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_GPU1_BAR_ENABLE: Enable for this BAR (0=disabled, 1=enabled) for brick 1 | |
| 1:35 | RW | RW | CONFIG_GPU1_BAR_ADDR_MASK: BAR Address/Mask bits 1:35 for brick 1 In Small-BAR mode (see bit 36): 1:7 = Base_Addr(13:19) = 16T slice 8:21 = Base_Addr(20:33) = 1G address in slice 22:35 = Base_Mask(20:33) = 1G...16T BAR size. (Note: Mask limited to 1G...4T in Axone and P10 w/ GPU systems) In Large-BAR mode (see bit 36): 1 = '1' to match MemSel = addr(13:14) = 0b00 2 = '1' to match MemSel = addr(13:14) = 0b01 3 = '1' to match MemSel = addr(13:14) = 0b10 4:35 = Topology_Id_Mask(0:31) when chip_eq_group=0, TIM(0:31) bit 'i' corresponds to addr(15:19) = 'i' when chip_eq_group=1, TIM(0:31) bit 'i' corresponds to (addr(15:16) & addr(19:21)) = 'i' | |
| 36 | RW | RW | CONFIG_GPU1_BAR_SL_MODE: 0/1 = Small-BAR/Large-BAR Mode selector | |
| 37 | RW | RW | CONFIG_GPU1_BAR_4T_LIMIT: 0 = no limit, 16T slices can be used. 1 = limit slices to 4T. -> when chip_eq_group=0, addr(20:21) must match bar_4t_select -> when chip_eq_group=1, addr(17:18) must match bar_4t_select limit=1 is used in P10 systems w/ a GPU or in Axone systems | |
| 38:39 | RW | RW | CONFIG_GPU1_BAR_4T_SELECT: when bar_4t_limit=1 this field selects the value in addr(20:21) or addr(17:18) to match | |
| 40:43 | RW | RW | CONFIG_GPU1_BAR_MODE: Hash mode of the BAR for brick 1: if bar_extended_mode == 0: 0 = (single) match on all address in addr/size 1 = (dual.0) match if hashbits(7)=0 2 = (dual.1) match if hashbits(7)=1 3 = (triple.0) match if hashbits%3=0 4 = (triple.1) match if hashbits%3=1 5 = (triple.2) match if hashbits%3=2 6 = (quad.0) match if hashbits(6:7)=0 7 = (quad.1) match if hashbits(6:7)=1 8 = (quad.2) match if hashbits(6:7)=2 9 = (quad.3) match if hashbits(6:7)=3 10 = (six.0) match if hashbits%3=0 and hashbits(7)=0 11 = (six.1) match if hashbits%3=0 and hashbits(7)=1 12 = (six.2) match if hashbits%3=1 and hashbits(7)=0 13 = (six.3) match if hashbits%3=1 and hashbits(7)=1 14 = (six.4) match if hashbits%3=2 and hashbits(7)=0 15 = (six.5) match if hashbits%3=2 and hashbits(7)=1 if bar_extended_mode == 1: 0 = (oct.0) match if hashbits(5:7)=0 1 = (oct.1) match if hashbits(5:7)=1 2 = (oct.2) match if hashbits(5:7)=2 3 = (oct.3) match if hashbits(5:7)=3 4 = (oct.4) match if hashbits(5:7)=4 5 = (oct.5) match if hashbits(5:7)=5 6 = (oct.6) match if hashbits(5:7)=6 7 = (oct.7) match if hashbits(5:7)=7 others = reserved | |
| 44 | RW | RW | CONFIG_GPU1_BAR_GRANULE: Hash boundary for brick 1: 0 = hash on 512B boundary (hashbits(0:7)=addr(47:54)) 1 = hash on 1024B boundary (hashbits(0:7)=addr(46:53)) | |
| 45 | RW | RW | CONFIG_GPU1_BAR_POISON: on failed access return all ones 0/1 = with good ECC / with SUE ECC. | |
| 46 | RW | RW | CONFIG_GPU1_BAR_M2MODE: 0 = OpenCAPI AFU M1 mode / 1 = OpenCAPI AFU M2 mode Has no effect when in NVLink mode | |
| 47 | RW | RW | CONFIG_GPU1_BAR_PA_IGNORE_MODE: Set to '1' for RA-to-PA conversion to ignore the mode field | |
| 48 | RW | RW | CONFIG_GPU1_BAR_SECURE_A12: P10 Only: this specifies the addr(12) value to match for this BAR. Can only be set to one in P10 and only when SMF_CONFIG=0b11. | |
| 49 | RW | RW | CONFIG_GPU1_BAR_CHIP_EQ_GROUP: Axone Only: this specifies that the system is in chip=group mode. This bit should only be set when sl_mode=1 and 4t_limit=1. 0/1 = TIM(0:31) applies to addr(15:19) / TIM(0:31) applies to (addr(15:16) & addr(19:21)). | |
| 50 | RW | RW | CONFIG_GPU1_BAR_EXTENDED_MODE: 0/1 = bar_mode selects 1,2,3,4,6 way hashing / bar_mode selects 8-way hashing | |
| 51 | RW | RW | CONFIG_GPU1_BAR_RESERVED: reserved | |
| 52:63 | RO | RO | constant=0b000000000000 | |
| GPU4-Memory BAR | ||||
|---|---|---|---|---|
| Addr: |
0000000011010992 (SCOM) 0000000013440090 (PAU_RING) | |||
| Name: | PAU3.CS.CTL.MISC.GPU4_BAR | |||
| Constant(s): | ||||
| Comments: | BAR register defining GPU Mem addresses serviced by brick 4 connected to this stack. Note: This register should be set to the same value for each brick/stack. MDials have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:51 | PAU3.CS.CTL.MISC.GPU4_BAR_Q_0_INST.LATC.L2(0:51) [0000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_GPU4_BAR_ENABLE: Enable for this BAR (0=disabled, 1=enabled) for brick 4 | |
| 1:35 | RW | RW | CONFIG_GPU4_BAR_ADDR_MASK: BAR Address/Mask bits 1:35 for brick 4 In Small-BAR mode (see bit 36): 1:7 = Base_Addr(13:19) = 16T slice 8:21 = Base_Addr(20:33) = 1G address in slice 22:35 = Base_Mask(20:33) = 1G...16T BAR size. (Note: Mask limited to 1G...4T in Axone and P10 w/ GPU systems) In Large-BAR mode (see bit 36): 1 = '1' to match MemSel = addr(13:14) = 0b00 2 = '1' to match MemSel = addr(13:14) = 0b01 3 = '1' to match MemSel = addr(13:14) = 0b10 4:35 = Topology_Id_Mask(0:31) when chip_eq_group=0, TIM(0:31) bit 'i' corresponds to addr(15:19) = 'i' when chip_eq_group=1, TIM(0:31) bit 'i' corresponds to (addr(15:16) & addr(19:21)) = 'i' | |
| 36 | RW | RW | CONFIG_GPU4_BAR_SL_MODE: 0/1 = Small-BAR/Large-BAR Mode selector | |
| 37 | RW | RW | CONFIG_GPU4_BAR_4T_LIMIT: 0 = no limit, 16T slices can be used. 1 = limit slices to 4T. -> when chip_eq_group=0, addr(20:21) must match bar_4t_select -> when chip_eq_group=1, addr(17:18) must match bar_4t_select limit=1 is used in P10 systems w/ a GPU or in Axone systems | |
| 38:39 | RW | RW | CONFIG_GPU4_BAR_4T_SELECT: when bar_4t_limit=1 this field selects the value in addr(20:21) or addr(17:18) to match | |
| 40:43 | RW | RW | CONFIG_GPU4_BAR_MODE: Hash mode of the BAR for brick 4: if bar_extended_mode == 0: 0 = (single) match on all address in addr/size 1 = (dual.0) match if hashbits(7)=0 2 = (dual.1) match if hashbits(7)=1 3 = (triple.0) match if hashbits%3=0 4 = (triple.1) match if hashbits%3=1 5 = (triple.2) match if hashbits%3=2 6 = (quad.0) match if hashbits(6:7)=0 7 = (quad.1) match if hashbits(6:7)=1 8 = (quad.2) match if hashbits(6:7)=2 9 = (quad.3) match if hashbits(6:7)=3 10 = (six.0) match if hashbits%3=0 and hashbits(7)=0 11 = (six.1) match if hashbits%3=0 and hashbits(7)=1 12 = (six.2) match if hashbits%3=1 and hashbits(7)=0 13 = (six.3) match if hashbits%3=1 and hashbits(7)=1 14 = (six.4) match if hashbits%3=2 and hashbits(7)=0 15 = (six.5) match if hashbits%3=2 and hashbits(7)=1 if bar_extended_mode == 1: 0 = (oct.0) match if hashbits(5:7)=0 1 = (oct.1) match if hashbits(5:7)=1 2 = (oct.2) match if hashbits(5:7)=2 3 = (oct.3) match if hashbits(5:7)=3 4 = (oct.4) match if hashbits(5:7)=4 5 = (oct.5) match if hashbits(5:7)=5 6 = (oct.6) match if hashbits(5:7)=6 7 = (oct.7) match if hashbits(5:7)=7 others = reserved | |
| 44 | RW | RW | CONFIG_GPU4_BAR_GRANULE: Hash boundary for brick 4: 0 = hash on 512B boundary (hashbits(0:7)=addr(47:54)) 1 = hash on 1024B boundary (hashbits(0:7)=addr(46:53)) | |
| 45 | RW | RW | CONFIG_GPU4_BAR_POISON: on failed access return all ones 0/1 = with good ECC / with SUE ECC. | |
| 46 | RW | RW | CONFIG_GPU4_BAR_M2MODE: 0 = OpenCAPI AFU M1 mode / 1 = OpenCAPI AFU M2 mode Has no effect when in NVLink mode | |
| 47 | RW | RW | CONFIG_GPU4_BAR_PA_IGNORE_MODE: Set to '1' for RA-to-PA conversion to ignore the mode field | |
| 48 | RW | RW | CONFIG_GPU4_BAR_SECURE_A12: P10 Only: this specifies the addr(12) value to match for this BAR. Can only be set to one in P10 and only when SMF_CONFIG=0b11. | |
| 49 | RW | RW | CONFIG_GPU4_BAR_CHIP_EQ_GROUP: Axone Only: this specifies that the system is in chip=group mode. This bit should only be set when sl_mode=1 and 4t_limit=1. 0/1 = TIM(0:31) applies to addr(15:19) / TIM(0:31) applies to (addr(15:16) & addr(19:21)). | |
| 50 | RW | RW | CONFIG_GPU4_BAR_EXTENDED_MODE: 0/1 = bar_mode selects 1,2,3,4,6 way hashing / bar_mode selects 8-way hashing | |
| 51 | RW | RW | CONFIG_GPU4_BAR_RESERVED: reserved | |
| 52:63 | RO | RO | constant=0b000000000000 | |
| MMIO Physical Address translation register - brick 0 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010993 (SCOM) 0000000013440098 (PAU_RING) | |||
| Name: | PAU3.CS.CTL.MISC.MMIOPA0_CONFIG | |||
| Constant(s): | ||||
| Comments: | Note: should mirror the configuration in ndtx_bar for this brick | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:43 | PAU3.CS.CTL.MISC.MMIOPA0_CONFIG_Q_0_INST.LATC.L2(0:43) [00000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_MMIOPA0_RESERVED1: reserved | |
| 1:35 | RW | RW | CONFIG_MMIOPA0_ADDR: MMIO Base Physical address (addr(13:47)) | |
| 36:38 | RW | RW | CONFIG_MMIOPA0_RESERVED2: reserved | |
| 39:43 | RW | RW | CONFIG_MMIOPA0_SIZE: MMIO region size Copy of config_ndt0_bar_size | |
| 44:63 | RO | RO | constant=0b00000000000000000000 | |
| MMIO Physical Address translation register - brick 1 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010994 (SCOM) 00000000134400A0 (PAU_RING) | |||
| Name: | PAU3.CS.CTL.MISC.MMIOPA1_CONFIG | |||
| Constant(s): | ||||
| Comments: | Note: should mirror the configuration in ndtx_bar for this brick | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:43 | PAU3.CS.CTL.MISC.MMIOPA1_CONFIG_Q_0_INST.LATC.L2(0:43) [00000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_MMIOPA1_RESERVED1: reserved | |
| 1:35 | RW | RW | CONFIG_MMIOPA1_ADDR: MMIO Base Physical address (addr(13:47)) | |
| 36:38 | RW | RW | CONFIG_MMIOPA1_RESERVED2: reserved | |
| 39:43 | RW | RW | CONFIG_MMIOPA1_SIZE: MMIO region size Copy of config_ndt1_bar_size | |
| 44:63 | RO | RO | constant=0b00000000000000000000 | |
| MMIO Physical Address translation register - brick 4 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010997 (SCOM) 00000000134400B8 (PAU_RING) | |||
| Name: | PAU3.CS.CTL.MISC.MMIOPA4_CONFIG | |||
| Constant(s): | ||||
| Comments: | Note: should mirror the configuration in ndtx_bar for this brick | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:43 | PAU3.CS.CTL.MISC.MMIOPA4_CONFIG_Q_0_INST.LATC.L2(0:43) [00000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_MMIOPA4_RESERVED1: reserved | |
| 1:35 | RW | RW | CONFIG_MMIOPA4_ADDR: MMIO Base Physical address (addr(13:47)) | |
| 36:38 | RW | RW | CONFIG_MMIOPA4_RESERVED2: reserved | |
| 39:43 | RW | RW | CONFIG_MMIOPA4_SIZE: MMIO region size Copy of config_ndt4_bar_size | |
| 44:63 | RO | RO | constant=0b00000000000000000000 | |
| c_err_rpt Message-0 latches | ||||
|---|---|---|---|---|
| Addr: |
0000000011010998 (SCOM) 00000000134400C0 (PAU_RING) | |||
| Name: | PAU3.CS.CTL.MISC.CERR_MESSAGE0 | |||
| Constant(s): | ||||
| Comments: | Error message/capture register 0 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.CTL.MISC.CERR_MESSAGE0_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:63 | RWX_WCLRREG | RWX_WCLRREG | CERR_MESSAGE_BITS0: reserved | |
| c_err_rpt Message-1 latches | ||||
|---|---|---|---|---|
| Addr: |
0000000011010999 (SCOM) 00000000134400C8 (PAU_RING) | |||
| Name: | PAU3.CS.CTL.MISC.CERR_MESSAGE1 | |||
| Constant(s): | ||||
| Comments: | Error message/capture register 1 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.CTL.MISC.CERR_MESSAGE1_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:63 | RWX_WCLRREG | RWX_WCLRREG | CERR_MESSAGE_BITS1: reserved | |
| c_err_rpt Message-2 latches | ||||
|---|---|---|---|---|
| Addr: |
000000001101099A (SCOM) 00000000134400D0 (PAU_RING) | |||
| Name: | PAU3.CS.CTL.MISC.CERR_MESSAGE2 | |||
| Constant(s): | ||||
| Comments: | Error message/capture register 2 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:15 | PAU3.CS.CTL.MISC.CERR_MESSAGE2_Q_0_INST.LATC.L2(0:15) [0000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:15 | RWX_WCLRREG | RWX_WCLRREG | CERR_MESSAGE_BITS2: reserved | |
| 16:63 | RO | RO | constant=0b000000000000000000000000000000000000000000000000 | |
| c_err_rpt first-0 latches | ||||
|---|---|---|---|---|
| Addr: |
000000001101099B (SCOM) 00000000134400D8 (PAU_RING) | |||
| Name: | PAU3.CS.CTL.MISC.CERR_FIRST0 | |||
| Constant(s): | ||||
| Comments: | c_err_rpt first latches read-write-1-clear reg | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:3 | PAU3.CS.CTL.MISC.CERR_FIRST0_Q_0_INST.LATC.L2(0:3) [0000] | |||
| 4:27 | PAU3.CS.CTL.MISC.CERR_FIRST0_Q_4_INST.LATC.L2(4:27) [000000000000000000000000] | |||
| 28:39 | PAU3.CS.CTL.MISC.CERR_FIRST0_Q_28_INST.LATC.L2(28:39) [000000000000] | |||
| 40:47 | PAU3.CS.CTL.MISC.CERR_FIRST0_Q_40_INST.LATC.L2(40:47) [00000000] | |||
| 48:51 | PAU3.CS.CTL.MISC.CERR_FIRST0_Q_48_INST.LATC.L2(48:51) [0000] | |||
| 52:55 | PAU3.CS.CTL.MISC.CERR_FIRST0_Q_52_INST.LATC.L2(52:55) [0000] | |||
| 56:59 | PAU3.CS.CTL.MISC.CERR_FIRST0_Q_56_INST.LATC.L2(56:59) [0000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_NCF_0: NCF0 SM0 ncf error | |
| 1 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_NCF_1: NCF1 SM1 ncf error | |
| 2 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_NCF_2: NCF2 SM2 ncf error | |
| 3 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_NCF_3: NCF3 SM3 ncf error | |
| 4 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_NVF_0: NVF0 SM0 nvf error | |
| 5 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_NVF_1: NVF1 SM1 nvf error | |
| 6 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_NVF_2: NVF2 SM2 nvf error | |
| 7 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_NVF_3: NVF3 SM3 nvf error | |
| 8 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_NVF_4: NVF4 Malformed NVLink packet received | |
| 9 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_NVF_5: NVF5 Malformed OpenCAPI packet received | |
| 10 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_NVF_6: NVF6 OpenCAPI w/ unknown opcode received | |
| 11 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_NVF_7: NVF7 Dropped a request packet internal xTL/CTL flow control failure | |
| 12 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_NVF_8: NVF8 OpenCAPI mem_pa_flush received w/ PA that did not map to main memory via GPUx_BAR | |
| 13 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_NVF_9: NVF9 OpenCAPI .t form posted command TA did not provide write access | |
| 14 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_NVF_10: NVF10 OpenCAPI posted packet w/ bad address received | |
| 15 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_NVF_11: NVF11 BDF-to-PE lookup failed. | |
| 16 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_NVF_12: NVF12 Received a 256B FO=1 Write | |
| 17 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_NVF_13: NVF13 Received an invalid AddrType field - neither 00 or 11 | |
| 18 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_NVF_14: NVF14 Received an invalid transaction-ID in a NVLink response | |
| 19 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_NVF_15: NVF15 Received a rsp_status of target-error in an ATSD response | |
| 20 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_NVF_16: NVF16 Received a rsp_status of unsupported-request in an ATSD response | |
| 21 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_NVF_17: NVF17 Received a rsp_status of '11' - reserved value - in an ATSD response | |
| 22 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_NVF_18: NVF18 Received a response other than mem_wr_response in network mode | |
| 23 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_NVF_19: NVF19 Brick 0 NVF error occured | |
| 24 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_NVF_20: NVF20 Brick 1 NVF error occured | |
| 25 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_NVF_21: NVF21 Brick 2 NVF error occured | |
| 26 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_NVF_22: NVF22 Brick 3 NVF error occured | |
| 27 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_NVF_23: NVF23 Brick 4 NVF error occured | |
| 28 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_OCR_0: OCR0 SM0 ocr error | |
| 29 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_OCR_1: OCR1 SM1 ocr error | |
| 30 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_OCR_2: OCR2 SM2 ocr error | |
| 31 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_OCR_3: OCR3 SM3 ocr error | |
| 32 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_OCR_4: OCR4 OpenCAPI non-posted packet w/ bad address received | |
| 33 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_OCR_5: OCR5 OpenCAPI .t form non-posted command TA did not provide write access | |
| 34 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_OCR_6: OCR6 (reserved) | |
| 35 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_OCR_7: OCR7 Brick 0 OCR error occured | |
| 36 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_OCR_8: OCR8 Brick 1 OCR error occured | |
| 37 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_OCR_9: OCR9 Brick 2 OCR error occured | |
| 38 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_OCR_10: OCR10 Brick 3 OCR error occured | |
| 39 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_OCR_11: OCR11 Brick 4 OCR error occured | |
| 40 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_ASBE_0: ASBE0 SM0 asbe error | |
| 41 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_ASBE_1: ASBE1 SM1 asbe error | |
| 42 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_ASBE_2: ASBE2 SM2 asbe error | |
| 43 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_ASBE_3: ASBE3 SM3 asbe error | |
| 44 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_ASBE_4: ASBE4 PowerBus MMIO Data Ecc CE Error | |
| 45 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_ASBE_5: ASBE5 Pre-Sync Head-Tail array CE error | |
| 46 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_ASBE_6: ASBE6 Pre-Sync Next-Pointer array CE error | |
| 47 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_ASBE_7: ASBE7 Pre-Sync Previous-Pointer array CE error | |
| 48 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_PBR_0: PBR0 SM0 pbr error | |
| 49 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_PBR_1: PBR1 SM1 pbr error | |
| 50 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_PBR_2: PBR2 SM2 pbr error | |
| 51 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_PBR_3: PBR3 SM3 pbr error | |
| 52 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_REG_0: REG0 SM0 reg error | |
| 53 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_REG_1: REG1 SM1 reg error | |
| 54 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_REG_2: REG2 SM2 reg error | |
| 55 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_REG_3: REG3 SM3 reg error | |
| 56 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_DUE_0: DUE0 PowerBus MMIO Data Ecc UE Error | |
| 57 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_DUE_1: DUE1 PowerBus MMIO Data Ecc SUE Error | |
| 58 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_DUE_2: DUE2 (reserved) | |
| 59 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_DUE_3: DUE3 (reserved) | |
| 60:63 | RO | RO | constant=0b0000 | |
| c_err_rpt first-1 latches | ||||
|---|---|---|---|---|
| Addr: |
000000001101099C (SCOM) 00000000134400E0 (PAU_RING) | |||
| Name: | PAU3.CS.CTL.MISC.CERR_FIRST1 | |||
| Constant(s): | ||||
| Comments: | c_err_rpt first latches read-write-1-clear reg | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:7 | PAU3.CS.CTL.MISC.CERR_FIRST1_Q_0_INST.LATC.L2(0:7) [00000000] | |||
| 8:27 | PAU3.CS.CTL.MISC.CERR_FIRST1_Q_8_INST.LATC.L2(8:27) [00000000000000000000] | |||
| 28:31 | PAU3.CS.CTL.MISC.CERR_FIRST1_Q_28_INST.LATC.L2(28:31) [0000] | |||
| 32:39 | PAU3.CS.CTL.MISC.CERR_FIRST1_Q_32_INST.LATC.L2(32:39) [00000000] | |||
| 40:43 | PAU3.CS.CTL.MISC.CERR_FIRST1_Q_40_INST.LATC.L2(40:43) [0000] | |||
| 44:51 | PAU3.CS.CTL.MISC.CERR_FIRST1_Q_44_INST.LATC.L2(44:51) [00000000] | |||
| 52:55 | PAU3.CS.CTL.MISC.CERR_FIRST1_Q_52_INST.LATC.L2(52:55) [0000] | |||
| 56:59 | PAU3.CS.CTL.MISC.CERR_FIRST1_Q_56_INST.LATC.L2(56:59) [0000] | |||
| 60:63 | PAU3.CS.CTL.MISC.CERR_FIRST1_Q_60_INST.LATC.L2(60:63) [0000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_PEF_0: PEF0 Brick 0 received a request to a frozen bdf/pe | |
| 1 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_PEF_1: PEF1 Brick 1 received a request to a frozen bdf/pe | |
| 2 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_PEF_2: PEF2 Brick 2 received a request to a frozen bdf/pe | |
| 3 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_PEF_3: PEF3 Brick 3 received a request to a frozen bdf/pe | |
| 4 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_PEF_4: PEF4 Brick 4 received a request to a frozen bdf/pe | |
| 5 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_PEF_5: PEF5 (reserved) | |
| 6 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_PEF_6: PEF6 (reserved) | |
| 7 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_PEF_7: PEF7 (reserved) | |
| 8 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_NLG_0: NLG0 SM0 nlg error | |
| 9 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_NLG_1: NLG1 SM1 nlg error | |
| 10 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_NLG_2: NLG2 SM2 nlg error | |
| 11 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_NLG_3: NLG3 SM3 nlg error | |
| 12 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_NLG_4: NLG4 PowerBus MMIO state machine invalid state | |
| 13 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_NLG_5: NLG5 buffer used for PB response before xTL finished writing data | |
| 14 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_NLG_6: NLG6 buffer read before xTL finished writing data | |
| 15 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_NLG_7: NLG7 Invalid state in dat-read state machine | |
| 16 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_NLG_8: NLG8 Attempt to send NV/OC Req with unknown MCMD_ command type | |
| 17 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_NLG_9: NLG9 Attempt to send NV/OC Resp with unknown LRTYPE_ response type | |
| 18 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_NLG_10: NLG10 Invalid state in XA-Response state machine | |
| 19 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_NLG_11: NLG11 Invalid Master command to MMIO/etc. machine | |
| 20 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_NLG_12: NLG12 (reserved) | |
| 21 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_NLG_13: NLG13 Invalid state in ATRR internal state machine(s) | |
| 22 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_NLG_14: NLG14 More than one sync(all_stream) from OTL 0 | |
| 23 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_NLG_15: NLG15 More than one sync(all_stream) from OTL 1 | |
| 24 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_NLG_16: NLG16 More than one sync(all_stream) from OTL 2 | |
| 25 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_NLG_17: NLG17 More than one sync(all_stream) from OTL 3 | |
| 26 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_NLG_18: NLG18 More than one sync(all_stream) from OTL 4 | |
| 27 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_NLG_19: NLG19 (reserved) | |
| 28 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_FWD_0: FWD0 SM0 fwd error | |
| 29 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_FWD_1: FWD1 SM1 fwd error | |
| 30 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_FWD_2: FWD2 SM2 fwd error | |
| 31 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_FWD_3: FWD3 SM3 fwd error | |
| 32 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_AUE_0: AUE0 SM0 aue error | |
| 33 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_AUE_1: AUE1 SM1 aue error | |
| 34 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_AUE_2: AUE2 SM2 aue error | |
| 35 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_AUE_3: AUE3 SM3 aue error | |
| 36 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_AUE_4: AUE4 (reserved) | |
| 37 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_AUE_5: AUE5 Pre-Sync Head-Tail array UE error | |
| 38 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_AUE_6: AUE6 Pre-Sync Next-Pointer array UE error | |
| 39 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_AUE_7: AUE7 Pre-Sync Previous-Pointer array UE error | |
| 40 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_PBP_0: PBP0 SM0 pbp error | |
| 41 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_PBP_1: PBP1 SM1 pbp error | |
| 42 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_PBP_2: PBP2 SM2 pbp error | |
| 43 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_PBP_3: PBP3 SM3 pbp error | |
| 44 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_PBF_0: PBF0 SM0 pbf error | |
| 45 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_PBF_1: PBF1 SM1 pbf error | |
| 46 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_PBF_2: PBF2 SM2 pbf error | |
| 47 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_PBF_3: PBF3 SM3 pbf error | |
| 48 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_PBF_4: PBF4 Access to Secure Memory attempted (denied by smf_config) | |
| 49 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_PBF_5: PBR5 (reserved) | |
| 50 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_PBF_6: PBR6 (reserved) | |
| 51 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_PBF_7: PBR7 (reserved) | |
| 52 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_PBC_0: PBC0 SM0 pbc error | |
| 53 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_PBC_1: PBC1 SM1 pbc error | |
| 54 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_PBC_2: PBC2 SM2 pbc error | |
| 55 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_PBC_3: PBC3 SM3 pbc error | |
| 56 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_LDA_0: LDA0 SM0 lda error | |
| 57 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_LDA_1: LDA1 SM1 lda error | |
| 58 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_LDA_2: LDA2 SM2 lda error | |
| 59 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_LDA_3: LDA3 SM3 lda error | |
| 60 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_STA_0: STA0 SM0 sta error | |
| 61 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_STA_1: STA1 SM1 sta error | |
| 62 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_STA_2: STA2 SM2 sta error | |
| 63 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CTL_FIRST_STA_3: STA3 SM3 sta error | |
| c_err_rpt mask-0 latches | ||||
|---|---|---|---|---|
| Addr: |
000000001101099D (SCOM) 00000000134400E8 (PAU_RING) | |||
| Name: | PAU3.CS.CTL.MISC.CERR_MASK0 | |||
| Constant(s): | ||||
| Comments: | c_err_rpt mask reg Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:59 | PAU3.CS.CTL.MISC.CERR_MASK0_Q_0_INST.LATC.L2(0:59) [000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | IDIAL_CTL_MASK_NCF_0: NCF0 SM0 ncf error | |
| 1 | RW | RW | IDIAL_CTL_MASK_NCF_1: NCF1 SM1 ncf error | |
| 2 | RW | RW | IDIAL_CTL_MASK_NCF_2: NCF2 SM2 ncf error | |
| 3 | RW | RW | IDIAL_CTL_MASK_NCF_3: NCF3 SM3 ncf error | |
| 4 | RW | RW | IDIAL_CTL_MASK_NVF_0: NVF0 SM0 nvf error | |
| 5 | RW | RW | IDIAL_CTL_MASK_NVF_1: NVF1 SM1 nvf error | |
| 6 | RW | RW | IDIAL_CTL_MASK_NVF_2: NVF2 SM2 nvf error | |
| 7 | RW | RW | IDIAL_CTL_MASK_NVF_3: NVF3 SM3 nvf error | |
| 8 | RW | RW | IDIAL_CTL_MASK_NVF_4: NVF4 Malformed NVLink packet received | |
| 9 | RW | RW | IDIAL_CTL_MASK_NVF_5: NVF5 Malformed OpenCAPI packet received | |
| 10 | RW | RW | IDIAL_CTL_MASK_NVF_6: NVF6 OpenCAPI w/ unknown opcode received | |
| 11 | RW | RW | IDIAL_CTL_MASK_NVF_7: NVF7 Dropped a request packet internal xTL/CTL flow control failure | |
| 12 | RW | RW | IDIAL_CTL_MASK_NVF_8: NVF8 OpenCAPI mem_pa_flush received w/ PA that did not map to main memory via GPUx_BAR | |
| 13 | RW | RW | IDIAL_CTL_MASK_NVF_9: NVF9 OpenCAPI .t form posted command TA did not provide write access | |
| 14 | RW | RW | IDIAL_CTL_MASK_NVF_10: NVF10 OpenCAPI posted packet w/ bad address received | |
| 15 | RW | RW | IDIAL_CTL_MASK_NVF_11: NVF11 BDF-to-PE lookup failed. | |
| 16 | RW | RW | IDIAL_CTL_MASK_NVF_12: NVF12 Received a 256B FO=1 Write | |
| 17 | RW | RW | IDIAL_CTL_MASK_NVF_13: NVF13 Received an invalid AddrType field - neither 00 or 11 | |
| 18 | RW | RW | IDIAL_CTL_MASK_NVF_14: NVF14 Received an invalid transaction-ID in a NVLink response | |
| 19 | RW | RW | IDIAL_CTL_MASK_NVF_15: NVF15 Received a rsp_status of target-error in an ATSD response | |
| 20 | RW | RW | IDIAL_CTL_MASK_NVF_16: NVF16 Received a rsp_status of unsupported-request in an ATSD response | |
| 21 | RW | RW | IDIAL_CTL_MASK_NVF_17: NVF17 Received a rsp_status of '11' - reserved value - in an ATSD response | |
| 22 | RW | RW | IDIAL_CTL_MASK_NVF_18: NVF18 Received a response other than mem_wr_response in network mode | |
| 23 | RW | RW | IDIAL_CTL_MASK_NVF_19: NVF19 Brick 0 NVF error occured | |
| 24 | RW | RW | IDIAL_CTL_MASK_NVF_20: NVF20 Brick 1 NVF error occured | |
| 25 | RW | RW | IDIAL_CTL_MASK_NVF_21: NVF21 Brick 2 NVF error occured | |
| 26 | RW | RW | IDIAL_CTL_MASK_NVF_22: NVF22 Brick 3 NVF error occured | |
| 27 | RW | RW | IDIAL_CTL_MASK_NVF_23: NVF23 Brick 4 NVF error occured | |
| 28 | RW | RW | IDIAL_CTL_MASK_OCR_0: OCR0 SM0 ocr error | |
| 29 | RW | RW | IDIAL_CTL_MASK_OCR_1: OCR1 SM1 ocr error | |
| 30 | RW | RW | IDIAL_CTL_MASK_OCR_2: OCR2 SM2 ocr error | |
| 31 | RW | RW | IDIAL_CTL_MASK_OCR_3: OCR3 SM3 ocr error | |
| 32 | RW | RW | IDIAL_CTL_MASK_OCR_4: OCR4 OpenCAPI non-posted packet w/ bad address received | |
| 33 | RW | RW | IDIAL_CTL_MASK_OCR_5: OCR5 OpenCAPI .t form non-posted command TA did not provide write access | |
| 34 | RW | RW | IDIAL_CTL_MASK_OCR_6: OCR6 (reserved) | |
| 35 | RW | RW | IDIAL_CTL_MASK_OCR_7: OCR7 Brick 0 OCR error occured | |
| 36 | RW | RW | IDIAL_CTL_MASK_OCR_8: OCR8 Brick 1 OCR error occured | |
| 37 | RW | RW | IDIAL_CTL_MASK_OCR_9: OCR9 Brick 2 OCR error occured | |
| 38 | RW | RW | IDIAL_CTL_MASK_OCR_10: OCR10 Brick 3 OCR error occured | |
| 39 | RW | RW | IDIAL_CTL_MASK_OCR_11: OCR11 Brick 4 OCR error occured | |
| 40 | RW | RW | IDIAL_CTL_MASK_ASBE_0: ASBE0 SM0 asbe error | |
| 41 | RW | RW | IDIAL_CTL_MASK_ASBE_1: ASBE1 SM1 asbe error | |
| 42 | RW | RW | IDIAL_CTL_MASK_ASBE_2: ASBE2 SM2 asbe error | |
| 43 | RW | RW | IDIAL_CTL_MASK_ASBE_3: ASBE3 SM3 asbe error | |
| 44 | RW | RW | IDIAL_CTL_MASK_ASBE_4: ASBE4 PowerBus MMIO Data Ecc CE Error | |
| 45 | RW | RW | IDIAL_CTL_MASK_ASBE_5: ASBE5 Pre-Sync Head-Tail array CE error | |
| 46 | RW | RW | IDIAL_CTL_MASK_ASBE_6: ASBE6 Pre-Sync Next-Pointer array CE error | |
| 47 | RW | RW | IDIAL_CTL_MASK_ASBE_7: ASBE7 Pre-Sync Previous-Pointer array CE error | |
| 48 | RW | RW | IDIAL_CTL_MASK_PBR_0: PBR0 SM0 pbr error | |
| 49 | RW | RW | IDIAL_CTL_MASK_PBR_1: PBR1 SM1 pbr error | |
| 50 | RW | RW | IDIAL_CTL_MASK_PBR_2: PBR2 SM2 pbr error | |
| 51 | RW | RW | IDIAL_CTL_MASK_PBR_3: PBR3 SM3 pbr error | |
| 52 | RW | RW | IDIAL_CTL_MASK_REG_0: REG0 SM0 reg error | |
| 53 | RW | RW | IDIAL_CTL_MASK_REG_1: REG1 SM1 reg error | |
| 54 | RW | RW | IDIAL_CTL_MASK_REG_2: REG2 SM2 reg error | |
| 55 | RW | RW | IDIAL_CTL_MASK_REG_3: REG3 SM3 reg error | |
| 56 | RW | RW | IDIAL_CTL_MASK_DUE_0: DUE0 PowerBus MMIO Data Ecc UE Error | |
| 57 | RW | RW | IDIAL_CTL_MASK_DUE_1: DUE1 PowerBus MMIO Data Ecc SUE Error | |
| 58 | RW | RW | IDIAL_CTL_MASK_DUE_2: DUE2 (reserved) | |
| 59 | RW | RW | IDIAL_CTL_MASK_DUE_3: DUE3 (reserved) | |
| 60:63 | RO | RO | constant=0b0000 | |
| c_err_rpt mask-1 latches | ||||
|---|---|---|---|---|
| Addr: |
000000001101099E (SCOM) 00000000134400F0 (PAU_RING) | |||
| Name: | PAU3.CS.CTL.MISC.CERR_MASK1 | |||
| Constant(s): | ||||
| Comments: | c_err_rpt mask reg Note: This register should be set to the same value globally. MDials have been created at PAU_TOP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.CTL.MISC.CERR_MASK1_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | IDIAL_CTL_MASK_PEF_0: PEF0 Brick 0 received a request to a frozen bdf/pe | |
| 1 | RW | RW | IDIAL_CTL_MASK_PEF_1: PEF1 Brick 1 received a request to a frozen bdf/pe | |
| 2 | RW | RW | IDIAL_CTL_MASK_PEF_2: PEF2 Brick 2 received a request to a frozen bdf/pe | |
| 3 | RW | RW | IDIAL_CTL_MASK_PEF_3: PEF3 Brick 3 received a request to a frozen bdf/pe | |
| 4 | RW | RW | IDIAL_CTL_MASK_PEF_4: PEF4 Brick 4 received a request to a frozen bdf/pe | |
| 5 | RW | RW | IDIAL_CTL_MASK_PEF_5: PEF5 (reserved) | |
| 6 | RW | RW | IDIAL_CTL_MASK_PEF_6: PEF6 (reserved) | |
| 7 | RW | RW | IDIAL_CTL_MASK_PEF_7: PEF7 (reserved) | |
| 8 | RW | RW | IDIAL_CTL_MASK_NLG_0: NLG0 SM0 nlg error | |
| 9 | RW | RW | IDIAL_CTL_MASK_NLG_1: NLG1 SM1 nlg error | |
| 10 | RW | RW | IDIAL_CTL_MASK_NLG_2: NLG2 SM2 nlg error | |
| 11 | RW | RW | IDIAL_CTL_MASK_NLG_3: NLG3 SM3 nlg error | |
| 12 | RW | RW | IDIAL_CTL_MASK_NLG_4: NLG4 PowerBus MMIO state machine invalid state | |
| 13 | RW | RW | IDIAL_CTL_MASK_NLG_5: NLG5 buffer used for PB response before xTL finished writing data | |
| 14 | RW | RW | IDIAL_CTL_MASK_NLG_6: NLG6 buffer read before xTL finished writing data | |
| 15 | RW | RW | IDIAL_CTL_MASK_NLG_7: NLG7 Invalid state in dat-read state machine | |
| 16 | RW | RW | IDIAL_CTL_MASK_NLG_8: NLG8 Attempt to send NV/OC Req with unknown MCMD_ command type | |
| 17 | RW | RW | IDIAL_CTL_MASK_NLG_9: NLG9 Attempt to send NV/OC Resp with unknown LRTYPE_ response type | |
| 18 | RW | RW | IDIAL_CTL_MASK_NLG_10: NLG10 Invalid state in XA-Response state machine | |
| 19 | RW | RW | IDIAL_CTL_MASK_NLG_11: NLG11 Invalid Master command to MMIO/etc. machine | |
| 20 | RW | RW | IDIAL_CTL_MASK_NLG_12: NLG12 (reserved) | |
| 21 | RW | RW | IDIAL_CTL_MASK_NLG_13: NLG13 Invalid state in ATRR internal state machine(s) | |
| 22 | RW | RW | IDIAL_CTL_MASK_NLG_14: NLG14 More than one sync(all_stream) from OTL 0 | |
| 23 | RW | RW | IDIAL_CTL_MASK_NLG_15: NLG15 More than one sync(all_stream) from OTL 1 | |
| 24 | RW | RW | IDIAL_CTL_MASK_NLG_16: NLG16 More than one sync(all_stream) from OTL 2 | |
| 25 | RW | RW | IDIAL_CTL_MASK_NLG_17: NLG17 More than one sync(all_stream) from OTL 3 | |
| 26 | RW | RW | IDIAL_CTL_MASK_NLG_18: NLG18 More than one sync(all_stream) from OTL 4 | |
| 27 | RW | RW | IDIAL_CTL_MASK_NLG_19: NLG19 (reserved) | |
| 28 | RW | RW | IDIAL_CTL_MASK_FWD_0: FWD0 SM0 fwd error | |
| 29 | RW | RW | IDIAL_CTL_MASK_FWD_1: FWD1 SM1 fwd error | |
| 30 | RW | RW | IDIAL_CTL_MASK_FWD_2: FWD2 SM2 fwd error | |
| 31 | RW | RW | IDIAL_CTL_MASK_FWD_3: FWD3 SM3 fwd error | |
| 32 | RW | RW | IDIAL_CTL_MASK_AUE_0: AUE0 SM0 aue error | |
| 33 | RW | RW | IDIAL_CTL_MASK_AUE_1: AUE1 SM1 aue error | |
| 34 | RW | RW | IDIAL_CTL_MASK_AUE_2: AUE2 SM2 aue error | |
| 35 | RW | RW | IDIAL_CTL_MASK_AUE_3: AUE3 SM3 aue error | |
| 36 | RW | RW | IDIAL_CTL_MASK_AUE_4: AUE4 (reserved) | |
| 37 | RW | RW | IDIAL_CTL_MASK_AUE_5: AUE5 Pre-Sync Head-Tail array UE error | |
| 38 | RW | RW | IDIAL_CTL_MASK_AUE_6: AUE6 Pre-Sync Next-Pointer array UE error | |
| 39 | RW | RW | IDIAL_CTL_MASK_AUE_7: AUE7 Pre-Sync Previous-Pointer array UE error | |
| 40 | RW | RW | IDIAL_CTL_MASK_PBP_0: PBP0 SM0 pbp error | |
| 41 | RW | RW | IDIAL_CTL_MASK_PBP_1: PBP1 SM1 pbp error | |
| 42 | RW | RW | IDIAL_CTL_MASK_PBP_2: PBP2 SM2 pbp error | |
| 43 | RW | RW | IDIAL_CTL_MASK_PBP_3: PBP3 SM3 pbp error | |
| 44 | RW | RW | IDIAL_CTL_MASK_PBF_0: PBF0 SM0 pbf error | |
| 45 | RW | RW | IDIAL_CTL_MASK_PBF_1: PBF1 SM1 pbf error | |
| 46 | RW | RW | IDIAL_CTL_MASK_PBF_2: PBF2 SM2 pbf error | |
| 47 | RW | RW | IDIAL_CTL_MASK_PBF_3: PBF3 SM3 pbf error | |
| 48 | RW | RW | IDIAL_CTL_MASK_PBF_4: PBF4 Access to Secure Memory attempted (denied by smf_config) | |
| 49 | RW | RW | IDIAL_CTL_MASK_PBF_5: PBR5 (reserved) | |
| 50 | RW | RW | IDIAL_CTL_MASK_PBF_6: PBR6 (reserved) | |
| 51 | RW | RW | IDIAL_CTL_MASK_PBF_7: PBR7 (reserved) | |
| 52 | RW | RW | IDIAL_CTL_MASK_PBC_0: PBC0 SM0 pbc error | |
| 53 | RW | RW | IDIAL_CTL_MASK_PBC_1: PBC1 SM1 pbc error | |
| 54 | RW | RW | IDIAL_CTL_MASK_PBC_2: PBC2 SM2 pbc error | |
| 55 | RW | RW | IDIAL_CTL_MASK_PBC_3: PBC3 SM3 pbc error | |
| 56 | RW | RW | IDIAL_CTL_MASK_LDA_0: LDA0 SM0 lda error | |
| 57 | RW | RW | IDIAL_CTL_MASK_LDA_1: LDA1 SM1 lda error | |
| 58 | RW | RW | IDIAL_CTL_MASK_LDA_2: LDA2 SM2 lda error | |
| 59 | RW | RW | IDIAL_CTL_MASK_LDA_3: LDA3 SM3 lda error | |
| 60 | RW | RW | IDIAL_CTL_MASK_STA_0: STA0 SM0 sta error | |
| 61 | RW | RW | IDIAL_CTL_MASK_STA_1: STA1 SM1 sta error | |
| 62 | RW | RW | IDIAL_CTL_MASK_STA_2: STA2 SM2 sta error | |
| 63 | RW | RW | IDIAL_CTL_MASK_STA_3: STA3 SM3 sta error | |
| c_err_rpt hold-0 latches | ||||
|---|---|---|---|---|
| Addr: |
000000001101099F (SCOM) 00000000134400F8 (PAU_RING) | |||
| Name: | PAU3.CS.CTL.MISC.CERR_HOLD0 | |||
| Constant(s): | ||||
| Comments: | c_err_rpt hold latches read-write-clear reg | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:3 | PAU3.CS.CTL.MISC.CERPT_NCF.HOLD_LATCH_INST.HOLD.LATC.L2(0:3) [0000] | |||
| 4:27 | PAU3.CS.CTL.MISC.CERPT_NVF.HOLD_LATCH_INST.HOLD.LATC.L2(0:23) [000000000000000000000000] | |||
| 28:39 | PAU3.CS.CTL.MISC.CERPT_OCR.HOLD_LATCH_INST.HOLD.LATC.L2(0:11) [000000000000] | |||
| 40:47 | PAU3.CS.CTL.MISC.CERPT_ASBE.HOLD_LATCH_INST.HOLD.LATC.L2(0:7) [00000000] | |||
| 48:51 | PAU3.CS.CTL.MISC.CERPT_PBR.HOLD_LATCH_INST.HOLD.LATC.L2(0:3) [0000] | |||
| 52:55 | PAU3.CS.CTL.MISC.CERPT_REG.HOLD_LATCH_INST.HOLD.LATC.L2(0:3) [0000] | |||
| 56:59 | PAU3.CS.CTL.MISC.CERPT_DUE.HOLD_LATCH_INST.HOLD.LATC.L2(0:3) [0000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_NCF_0: NCF0 SM0 ncf error | |
| 1 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_NCF_1: NCF1 SM1 ncf error | |
| 2 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_NCF_2: NCF2 SM2 ncf error | |
| 3 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_NCF_3: NCF3 SM3 ncf error | |
| 4 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_NVF_0: NVF0 SM0 nvf error | |
| 5 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_NVF_1: NVF1 SM1 nvf error | |
| 6 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_NVF_2: NVF2 SM2 nvf error | |
| 7 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_NVF_3: NVF3 SM3 nvf error | |
| 8 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_NVF_4: NVF4 Malformed NVLink packet received | |
| 9 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_NVF_5: NVF5 Malformed OpenCAPI packet received | |
| 10 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_NVF_6: NVF6 OpenCAPI w/ unknown opcode received | |
| 11 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_NVF_7: NVF7 Dropped a request packet internal xTL/CTL flow control failure | |
| 12 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_NVF_8: NVF8 OpenCAPI mem_pa_flush received w/ PA that did not map to main memory via GPUx_BAR | |
| 13 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_NVF_9: NVF9 OpenCAPI .t form posted command TA did not provide write access | |
| 14 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_NVF_10: NVF10 OpenCAPI posted packet w/ bad address received | |
| 15 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_NVF_11: NVF11 BDF-to-PE lookup failed. | |
| 16 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_NVF_12: NVF12 Received a 256B FO=1 Write | |
| 17 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_NVF_13: NVF13 Received an invalid AddrType field - neither 00 or 11 | |
| 18 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_NVF_14: NVF14 Received an invalid transaction-ID in a NVLink response | |
| 19 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_NVF_15: NVF15 Received a rsp_status of target-error in an ATSD response | |
| 20 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_NVF_16: NVF16 Received a rsp_status of unsupported-request in an ATSD response | |
| 21 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_NVF_17: NVF17 Received a rsp_status of '11' - reserved value - in an ATSD response | |
| 22 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_NVF_18: NVF18 Received a response other than mem_wr_response in network mode | |
| 23 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_NVF_19: NVF19 Brick 0 NVF error occured | |
| 24 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_NVF_20: NVF20 Brick 1 NVF error occured | |
| 25 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_NVF_21: NVF21 Brick 2 NVF error occured | |
| 26 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_NVF_22: NVF22 Brick 3 NVF error occured | |
| 27 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_NVF_23: NVF23 Brick 4 NVF error occured | |
| 28 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_OCR_0: OCR0 SM0 ocr error | |
| 29 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_OCR_1: OCR1 SM1 ocr error | |
| 30 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_OCR_2: OCR2 SM2 ocr error | |
| 31 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_OCR_3: OCR3 SM3 ocr error | |
| 32 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_OCR_4: OCR4 OpenCAPI non-posted packet w/ bad address received | |
| 33 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_OCR_5: OCR5 OpenCAPI .t form non-posted command TA did not provide write access | |
| 34 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_OCR_6: OCR6 (reserved) | |
| 35 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_OCR_7: OCR7 Brick 0 OCR error occured | |
| 36 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_OCR_8: OCR8 Brick 1 OCR error occured | |
| 37 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_OCR_9: OCR9 Brick 2 OCR error occured | |
| 38 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_OCR_10: OCR10 Brick 3 OCR error occured | |
| 39 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_OCR_11: OCR11 Brick 4 OCR error occured | |
| 40 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_ASBE_0: ASBE0 SM0 asbe error | |
| 41 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_ASBE_1: ASBE1 SM1 asbe error | |
| 42 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_ASBE_2: ASBE2 SM2 asbe error | |
| 43 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_ASBE_3: ASBE3 SM3 asbe error | |
| 44 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_ASBE_4: ASBE4 PowerBus MMIO Data Ecc CE Error | |
| 45 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_ASBE_5: ASBE5 Pre-Sync Head-Tail array CE error | |
| 46 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_ASBE_6: ASBE6 Pre-Sync Next-Pointer array CE error | |
| 47 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_ASBE_7: ASBE7 Pre-Sync Previous-Pointer array CE error | |
| 48 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_PBR_0: PBR0 SM0 pbr error | |
| 49 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_PBR_1: PBR1 SM1 pbr error | |
| 50 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_PBR_2: PBR2 SM2 pbr error | |
| 51 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_PBR_3: PBR3 SM3 pbr error | |
| 52 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_REG_0: REG0 SM0 reg error | |
| 53 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_REG_1: REG1 SM1 reg error | |
| 54 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_REG_2: REG2 SM2 reg error | |
| 55 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_REG_3: REG3 SM3 reg error | |
| 56 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_DUE_0: DUE0 PowerBus MMIO Data Ecc UE Error | |
| 57 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_DUE_1: DUE1 PowerBus MMIO Data Ecc SUE Error | |
| 58 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_DUE_2: DUE2 (reserved) | |
| 59 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_DUE_3: DUE3 (reserved) | |
| 60:63 | RO | RO | constant=0b0000 | |
| c_err_rpt hold-1 latches | ||||
|---|---|---|---|---|
| Addr: |
00000000110109A0 (SCOM) 0000000013440100 (PAU_RING) | |||
| Name: | PAU3.CS.CTL.MISC.CERR_HOLD1 | |||
| Constant(s): | ||||
| Comments: | c_err_rpt hold latches read-write-clear reg | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:7 | PAU3.CS.CTL.MISC.CERPT_PEF.HOLD_LATCH_INST.HOLD.LATC.L2(0:7) [00000000] | |||
| 8:27 | PAU3.CS.CTL.MISC.CERPT_NLG.HOLD_LATCH_INST.HOLD.LATC.L2(0:19) [00000000000000000000] | |||
| 28:31 | PAU3.CS.CTL.MISC.CERPT_FWD.HOLD_LATCH_INST.HOLD.LATC.L2(0:3) [0000] | |||
| 32:39 | PAU3.CS.CTL.MISC.CERPT_AUE.HOLD_LATCH_INST.HOLD.LATC.L2(0:7) [00000000] | |||
| 40:43 | PAU3.CS.CTL.MISC.CERPT_PBP.HOLD_LATCH_INST.HOLD.LATC.L2(0:3) [0000] | |||
| 44:51 | PAU3.CS.CTL.MISC.CERPT_PBF.HOLD_LATCH_INST.HOLD.LATC.L2(0:7) [00000000] | |||
| 52:55 | PAU3.CS.CTL.MISC.CERPT_PBC.HOLD_LATCH_INST.HOLD.LATC.L2(0:3) [0000] | |||
| 56:59 | PAU3.CS.CTL.MISC.CERPT_LDA.HOLD_LATCH_INST.HOLD.LATC.L2(0:3) [0000] | |||
| 60:63 | PAU3.CS.CTL.MISC.CERPT_STA.HOLD_LATCH_INST.HOLD.LATC.L2(0:3) [0000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_PEF_0: PEF0 Brick 0 received a request to a frozen bdf/pe | |
| 1 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_PEF_1: PEF1 Brick 1 received a request to a frozen bdf/pe | |
| 2 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_PEF_2: PEF2 Brick 2 received a request to a frozen bdf/pe | |
| 3 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_PEF_3: PEF3 Brick 3 received a request to a frozen bdf/pe | |
| 4 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_PEF_4: PEF4 Brick 4 received a request to a frozen bdf/pe | |
| 5 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_PEF_5: PEF5 (reserved) | |
| 6 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_PEF_6: PEF6 (reserved) | |
| 7 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_PEF_7: PEF7 (reserved) | |
| 8 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_NLG_0: NLG0 SM0 nlg error | |
| 9 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_NLG_1: NLG1 SM1 nlg error | |
| 10 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_NLG_2: NLG2 SM2 nlg error | |
| 11 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_NLG_3: NLG3 SM3 nlg error | |
| 12 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_NLG_4: NLG4 PowerBus MMIO state machine invalid state | |
| 13 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_NLG_5: NLG5 buffer used for PB response before xTL finished writing data | |
| 14 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_NLG_6: NLG6 buffer read before xTL finished writing data | |
| 15 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_NLG_7: NLG7 Invalid state in dat-read state machine | |
| 16 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_NLG_8: NLG8 Attempt to send NV/OC Req with unknown MCMD_ command type | |
| 17 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_NLG_9: NLG9 Attempt to send NV/OC Resp with unknown LRTYPE_ response type | |
| 18 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_NLG_10: NLG10 Invalid state in XA-Response state machine | |
| 19 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_NLG_11: NLG11 Invalid Master command to MMIO/etc. machine | |
| 20 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_NLG_12: NLG12 (reserved) | |
| 21 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_NLG_13: NLG13 Invalid state in ATRR internal state machine(s) | |
| 22 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_NLG_14: NLG14 More than one sync(all_stream) from OTL 0 | |
| 23 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_NLG_15: NLG15 More than one sync(all_stream) from OTL 1 | |
| 24 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_NLG_16: NLG16 More than one sync(all_stream) from OTL 2 | |
| 25 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_NLG_17: NLG17 More than one sync(all_stream) from OTL 3 | |
| 26 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_NLG_18: NLG18 More than one sync(all_stream) from OTL 4 | |
| 27 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_NLG_19: NLG19 (reserved) | |
| 28 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_FWD_0: FWD0 SM0 fwd error | |
| 29 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_FWD_1: FWD1 SM1 fwd error | |
| 30 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_FWD_2: FWD2 SM2 fwd error | |
| 31 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_FWD_3: FWD3 SM3 fwd error | |
| 32 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_AUE_0: AUE0 SM0 aue error | |
| 33 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_AUE_1: AUE1 SM1 aue error | |
| 34 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_AUE_2: AUE2 SM2 aue error | |
| 35 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_AUE_3: AUE3 SM3 aue error | |
| 36 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_AUE_4: AUE4 (reserved) | |
| 37 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_AUE_5: AUE5 Pre-Sync Head-Tail array UE error | |
| 38 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_AUE_6: AUE6 Pre-Sync Next-Pointer array UE error | |
| 39 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_AUE_7: AUE7 Pre-Sync Previous-Pointer array UE error | |
| 40 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_PBP_0: PBP0 SM0 pbp error | |
| 41 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_PBP_1: PBP1 SM1 pbp error | |
| 42 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_PBP_2: PBP2 SM2 pbp error | |
| 43 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_PBP_3: PBP3 SM3 pbp error | |
| 44 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_PBF_0: PBF0 SM0 pbf error | |
| 45 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_PBF_1: PBF1 SM1 pbf error | |
| 46 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_PBF_2: PBF2 SM2 pbf error | |
| 47 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_PBF_3: PBF3 SM3 pbf error | |
| 48 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_PBF_4: PBF4 Access to Secure Memory attempted (denied by smf_config) | |
| 49 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_PBF_5: PBR5 (reserved) | |
| 50 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_PBF_6: PBR6 (reserved) | |
| 51 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_PBF_7: PBR7 (reserved) | |
| 52 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_PBC_0: PBC0 SM0 pbc error | |
| 53 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_PBC_1: PBC1 SM1 pbc error | |
| 54 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_PBC_2: PBC2 SM2 pbc error | |
| 55 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_PBC_3: PBC3 SM3 pbc error | |
| 56 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_LDA_0: LDA0 SM0 lda error | |
| 57 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_LDA_1: LDA1 SM1 lda error | |
| 58 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_LDA_2: LDA2 SM2 lda error | |
| 59 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_LDA_3: LDA3 SM3 lda error | |
| 60 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_STA_0: STA0 SM0 sta error | |
| 61 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_STA_1: STA1 SM1 sta error | |
| 62 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_STA_2: STA2 SM2 sta error | |
| 63 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_CTL_HOLD_STA_3: STA3 SM3 sta error | |
| Fence Control 0 | ||||
|---|---|---|---|---|
| Addr: |
00000000110109A1 (SCOM) 0000000013440108 (PAU_RING) | |||
| Name: | PAU3.CS.CTL.MISC.FENCE_CONTROL0 | |||
| Constant(s): | ||||
| Comments: | Controls Fence | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:3 | PAU3.CS.CTL.MISC.FENCE_CONTROL0_Q_0_INST.LATC.L2(0:3) [0000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:1 | RW | RW | FENCE0_REQUEST_FENCE: Fence state requested 00 - Reset disabled 11 - Reset (Fence) both OTL/NTL and the PowerBus for this Brick 10 - Reset (Fence) only the PowerBus for this Brick, OTL/NTL will be operational 01 - OTL/NTL disabled This field should not be changed unless bits 48:49 (dial ctl_status_brk0_am_fenced(0:1)) in the CTL_STATUS register equals the value in this field. | |
| 2:3 | RW | RW | FENCE_CONTROL0_RESERVED: Reserved | |
| 4:63 | RO | RO | constant=0b000000000000000000000000000000000000000000000000000000000000 | |
| Fence Control 1 | ||||
|---|---|---|---|---|
| Addr: |
00000000110109A2 (SCOM) 0000000013440110 (PAU_RING) | |||
| Name: | PAU3.CS.CTL.MISC.FENCE_CONTROL1 | |||
| Constant(s): | ||||
| Comments: | Controls Fence | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:3 | PAU3.CS.CTL.MISC.FENCE_CONTROL1_Q_0_INST.LATC.L2(0:3) [0000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:1 | RW | RW | FENCE1_REQUEST_FENCE: Fence state requested 00 - Reset disabled 11 - Reset (Fence) both OTL/NTL and the PowerBus for this Brick 10 - Reset (Fence) only the PowerBus for this Brick, OTL/NTL will be operational 01 - OTL/NTL disabled This field should not be changed unless bits 49:50 (dial ctl_status_brk1_am_fenced(0:1)) in the CTL_STATUS register equals the value in this field. | |
| 2:3 | RW | RW | FENCE_CONTROL1_RESERVED: Reserved | |
| 4:63 | RO | RO | constant=0b000000000000000000000000000000000000000000000000000000000000 | |
| Fence Control 2 | ||||
|---|---|---|---|---|
| Addr: |
00000000110109A3 (SCOM) 0000000013440118 (PAU_RING) | |||
| Name: | PAU3.CS.CTL.MISC.FENCE_CONTROL2 | |||
| Constant(s): | ||||
| Comments: | Controls Fence | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:3 | PAU3.CS.CTL.MISC.FENCE_CONTROL2_Q_0_INST.LATC.L2(0:3) [0000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:1 | RW | RW | FENCE2_REQUEST_FENCE: Fence state requested 00 - Reset disabled 11 - Reset (Fence) both OTL/NTL and the PowerBus for this Brick 10 - Reset (Fence) only the PowerBus for this Brick, OTL/NTL will be operational 01 - OTL/NTL disabled This field should not be changed unless bits 50:51 (dial ctl_status_brk2_am_fenced(0:1)) in the CTL_STATUS register equals the value in this field. | |
| 2:3 | RW | RW | FENCE_CONTROL2_RESERVED: Reserved | |
| 4:63 | RO | RO | constant=0b000000000000000000000000000000000000000000000000000000000000 | |
| Fence Control 3 | ||||
|---|---|---|---|---|
| Addr: |
00000000110109A4 (SCOM) 0000000013440120 (PAU_RING) | |||
| Name: | PAU3.CS.CTL.MISC.FENCE_CONTROL3 | |||
| Constant(s): | ||||
| Comments: | Controls Fence | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:3 | PAU3.CS.CTL.MISC.FENCE_CONTROL3_Q_0_INST.LATC.L2(0:3) [0000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:1 | RW | RW | FENCE3_REQUEST_FENCE: Fence state requested 00 - Reset disabled 11 - Reset (Fence) both OTL/NTL and the PowerBus for this Brick 10 - Reset (Fence) only the PowerBus for this Brick, OTL/NTL will be operational 01 - OTL/NTL disabled This field should not be changed unless bits 51:52 (dial ctl_status_brk3_am_fenced(0:1)) in the CTL_STATUS register equals the value in this field. | |
| 2:3 | RW | RW | FENCE_CONTROL3_RESERVED: Reserved | |
| 4:63 | RO | RO | constant=0b000000000000000000000000000000000000000000000000000000000000 | |
| Fence Control 4 | ||||
|---|---|---|---|---|
| Addr: |
00000000110109A5 (SCOM) 0000000013440128 (PAU_RING) | |||
| Name: | PAU3.CS.CTL.MISC.FENCE_CONTROL4 | |||
| Constant(s): | ||||
| Comments: | Controls Fence | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:3 | PAU3.CS.CTL.MISC.FENCE_CONTROL4_Q_0_INST.LATC.L2(0:3) [0000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:1 | RW | RW | FENCE4_REQUEST_FENCE: Fence state requested 00 - Reset disabled 11 - Reset (Fence) both OTL/NTL and the PowerBus for this Brick 10 - Reset (Fence) only the PowerBus for this Brick, OTL/NTL will be operational 01 - OTL/NTL disabled This field should not be changed unless bits 52:53 (dial ctl_status_brk4_am_fenced(0:1)) in the CTL_STATUS register equals the value in this field. | |
| 2:3 | RW | RW | FENCE_CONTROL4_RESERVED: Reserved | |
| 4:63 | RO | RO | constant=0b000000000000000000000000000000000000000000000000000000000000 | |
| LCO Config | ||||
|---|---|---|---|---|
| Addr: |
00000000110109A7 (SCOM) 0000000013440138 (PAU_RING) | |||
| Name: | PAU3.CS.CTL.MISC.LCO_CONFIG | |||
| Constant(s): | ||||
| Comments: | Lateral-Castout target selection configuration | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:43 | PAU3.CS.CTL.MISC.LCO_CONFIG_Q_0_INST.LATC.L2(0:43) [00000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:31 | RW | RW | CONFIG_LCO_V_TARG: LCO valid-targets vector for P10 only targets in the PAU's Sl-domain may be used (and must match the L3s that are enabled as targets) | |
| 32:34 | RW | RW | CONFIG_LCO_RESERVED1: reserved | |
| 35:39 | RW | RW | CONFIG_LCO_E_TARG_MIN: LCO minimum number of eligible targets | |
| 40:43 | RW | RW | CONFIG_LCO_RAND_EVENT: LCO Random event rate | |
| 44:63 | RO | RO | constant=0b00000000000000000000 | |
| ECC-Logger Base Address Register | ||||
|---|---|---|---|---|
| Addr: |
00000000110109A8 (SCOM) 0000000013440140 (PAU_RING) | |||
| Name: | PAU3.CS.CTL.MISC.ELOGGER_BAR | |||
| Constant(s): | ||||
| Comments: | Provides a range of memory to use for logging cache-lines w/ UE/SUE ECC errors Must only be written when the elogger is disabled in the elogger_control(0) bit and idle according to the elogger_status(0) bit | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:47 | PAU3.CS.CTL.MISC.ELOGGER_BAR_Q_0_INST.LATC.L2(0:47) [000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_ELOGGER_BAR_LOG_UNEXP: 1 = Log Unexpected ECC errors (typically due to ECC/SUE from the PowerBus, poison from NVLink, or internal array UEs) | |
| 1 | RW | RW | CONFIG_ELOGGER_BAR_LOG_BSTAT: 1 = Log Bad-STATus errors (bad response from register/MMIO logic causes buffer to be filled with SUE). | |
| 2 | RW | RW | CONFIG_ELOGGER_BAR_LOG_BQDFL: 1 = Log Bad-reQuest-Data-From-Link errors (bad data flag in OCAPI request causes buffer to be filled with SUE). | |
| 3 | RW | RW | CONFIG_ELOGGER_BAR_LOG_BSDFL: 1 = Log Bad-reSponse-Data-From-Link errors (bad data/status flag in OCAPI response causes buffer to be filled with SUE). | |
| 4 | RW | RW | CONFIG_ELOGGER_BAR_LOG_L2BF: 1 = Log L2-brick-fence errors where brick-fence cleaning of the L2 directory caused an entry to be castout with SUE data | |
| 5 | RW | RW | CONFIG_ELOGGER_BAR_LOG_BARBF: 1 = Log BAR-brick-fence errors where a fenced-brick returned SUE data to a read access hitting the BAR | |
| 6:7 | RW | RW | CONFIG_ELOGGER_BAR_RESERVED1: reserved | |
| 8:11 | RW | RW | CONFIG_ELOGGER_BAR_SIZE: Size of the elogger region 0b0000 = 64KBytes 0b0001 = 128KBytes ... 0b0011 = 512KBytes 0b0100 = 1MBytes ... 0b1101 = 512MGbytes 0b1110 = 1Gbytes 0b1111 = 2Gbytes | |
| 12:47 | RW | RW | CONFIG_ELOGGER_BAR_ADDR: Base address (64K address) of the BAR for ecc logging Must be aligned to the bar_size Corresponds to real_address(12:47) | |
| 48:63 | RO | RO | constant=0b0000000000000000 | |
| ECC-Logger Status | ||||
|---|---|---|---|---|
| Addr: |
00000000110109A9 (SCOM) 0000000013440148 (PAU_RING) | |||
| Name: | PAU3.CS.CTL.MISC.ELOGGER_STATUS | |||
| Constant(s): | ||||
| Comments: | Provides read-only status of the ECC Logger | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.CS.CTL.MISC.ELOGGER_STATUS_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | ROX | ROX | ELOGGER_STATUS_NONIDLE: 1 if the elogger state-machine is busy, 0 if idle | |
| 1:11 | ROX | ROX | ELOGGER_STATUS_RESERVED1: reserved | |
| 12:56 | ROX | ROX | ELOGGER_STATUS_ADDR: Address bits 12:56 of the next elog entry to write (the prior 128B cacheline has log entries). | |
| 57:59 | ROX | ROX | ELOGGER_STATUS_RESERVED2: reserved | |
| 60:63 | ROX | ROX | ELOGGER_STATUS_PEND_COUNT: Count of ECC log entries that have not been written to memory yet. | |
| ECC-Logger Control | ||||
|---|---|---|---|---|
| Addr: |
00000000110109AA (SCOM) 0000000013440150 (PAU_RING) | |||
| Name: | PAU3.CS.CTL.MISC.ELOGGER_CONTROL | |||
| Constant(s): | ||||
| Comments: | Provides control of the ECC Logger function | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:15 | PAU3.CS.CTL.MISC.ELOGGER_CONTROL_Q_0_INST.LATC.L2(0:15) [0000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | ELOGGER_CONTROL_ENABLE: '1' to enable the ECC logging function, '0' to disable. Do not enable the ECC logging function without first setting up the elogger_bar register. | |
| 1 | RWX | RWX | ELOGGER_CONTROL_FLUSH: Write to '1' to force the ECC logger to write any pending entries to memory. This bit will return to '0' after the write is done Note that this does not guarentee that further entries to be logged did not arrive after the flush. | |
| 2:15 | RW | RW | ELOGGER_CONTROL_RESERVED1: reserved | |
| 16:63 | RO | RO | constant=0b000000000000000000000000000000000000000000000000 | |
| Scope Predictor Control | ||||
|---|---|---|---|---|
| Addr: |
00000000110109AB (SCOM) 0000000013440158 (PAU_RING) | |||
| Name: | PAU3.CS.CTL.MISC.SCOPE_PREDICT0 | |||
| Constant(s): | ||||
| Comments: | Provides control of scope prediction | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:59 | PAU3.CS.CTL.MISC.SCOPE_PREDICT0_Q_0_INST.LATC.L2(0:59) [000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:2 | RW | RW | CONFIG_SCOPE_PREDICT_B0RD_LN_FAIL_THRESH: Brick 0 Read scope-predict for Ln failure control Threshold of # of Ln-scope fail events (forced to larger scope) before Ln scope is skipped as an initial scope | |
| 3:5 | RW | RW | CONFIG_SCOPE_PREDICT_B0RD_NN_FAIL_THRESH: Brick 0 Read scope-predict for Nn failure control Threshold of # of Nn-scope fail events (forced to larger scope) before Nn scope is skipped as an initial scope | |
| 6:8 | RW | RW | CONFIG_SCOPE_PREDICT_B0RD_RN_FAIL_THRESH: Brick 0 Read scope-predict for Rn failure control Threshold of # of Rn-scope fail events (forced to larger scope) before Rn scope is skipped as an initial scope | |
| 9:11 | RW | RW | CONFIG_SCOPE_PREDICT_B0RD_G_FAIL_THRESH: Brick 0 Read scope-predict for G failure control Threshold of # of G-scope fail events (forced to larger scope) before G scope is skipped as an initial scope | |
| 12:14 | RW | RW | CONFIG_SCOPE_PREDICT_B0RD_LN_INTV_THRESH: Brick 0 Read scope-predict for Ln intervention success Threshold of # of local intervention events (dcache=exclusive from local) before Ln scope is considered despite address group/chip match | |
| 15:17 | RW | RW | CONFIG_SCOPE_PREDICT_B0RD_G_INTV_THRESH: Brick 0 Read scope-predict for G intervention success Threshold of # of near intervention events (dcache=exclusive from local) before G scope is considered despite address group/chip match | |
| 18 | RW | RW | CONFIG_SCOPE_PREDICT_B0RD_VG_ENABLE: Brick 0 Read scope-predict enable Vg accumulation Enables 'or'-accumulating CResp scope-targets into minimum Vg scope used | |
| 19 | RW | RW | CONFIG_SCOPE_PREDICT0_RESERVED1: reserved | |
| 20:22 | RW | RW | CONFIG_SCOPE_PREDICT_B0WR_LN_FAIL_THRESH: Brick 0 Write scope-predict for Ln failure control Threshold of # of Ln-scope fail events (forced to larger scope) before Ln scope is skipped as an initial scope | |
| 23:25 | RW | RW | CONFIG_SCOPE_PREDICT_B0WR_NN_FAIL_THRESH: Brick 0 Write scope-predict for Nn failure control Threshold of # of Nn-scope fail events (forced to larger scope) before Nn scope is skipped as an initial scope | |
| 26:28 | RW | RW | CONFIG_SCOPE_PREDICT_B0WR_RN_FAIL_THRESH: Brick 0 Write scope-predict for Rn failure control Threshold of # of Rn-scope fail events (forced to larger scope) before Rn scope is skipped as an initial scope | |
| 29:31 | RW | RW | CONFIG_SCOPE_PREDICT_B0WR_G_FAIL_THRESH: Brick 0 Write scope-predict for G failure control Threshold of # of G-scope fail events (forced to larger scope) before G scope is skipped as an initial scope | |
| 32:34 | RW | RW | CONFIG_SCOPE_PREDICT_B0WR_LN_INTV_THRESH: Brick 0 Write scope-predict for Ln intervention success Threshold of # of local intervention events (dcache=exclusive from local) before Ln scope is considered despite address group/chip match | |
| 35:37 | RW | RW | CONFIG_SCOPE_PREDICT_B0WR_G_INTV_THRESH: Brick 0 Write scope-predict for G intervention success Threshold of # of near intervention events (dcache=exclusive from local) before G scope is considered despite address group/chip match | |
| 38 | RW | RW | CONFIG_SCOPE_PREDICT_B0WR_VG_ENABLE: Brick 0 Write scope-predict enable Vg accumulation Enables 'or'-accumulating CResp scope-targets into minimum Vg scope used | |
| 39 | RW | RW | CONFIG_SCOPE_PREDICT0_RESERVED2: reserved | |
| 40:42 | RW | RW | CONFIG_SCOPE_PREDICT_OTH_LN_FAIL_THRESH: Other (Non-Brick 0/1) scope-predict for Ln failure control Threshold of # of Ln-scope fail events (forced to larger scope) before Ln scope is skipped as an initial scope | |
| 43:45 | RW | RW | CONFIG_SCOPE_PREDICT_OTH_NN_FAIL_THRESH: Other (Non-Brick 0/1) scope-predict for Nn failure control Threshold of # of Nn-scope fail events (forced to larger scope) before Nn scope is skipped as an initial scope | |
| 46:48 | RW | RW | CONFIG_SCOPE_PREDICT_OTH_RN_FAIL_THRESH: Other (Non-Brick 0/1) scope-predict for Rn failure control Threshold of # of Rn-scope fail events (forced to larger scope) before Rn scope is skipped as an initial scope | |
| 49:51 | RW | RW | CONFIG_SCOPE_PREDICT_OTH_G_FAIL_THRESH: Other (Non-Brick 0/1) scope-predict for G failure control Threshold of # of G-scope fail events (forced to larger scope) before G scope is skipped as an initial scope | |
| 52:54 | RW | RW | CONFIG_SCOPE_PREDICT_OTH_LN_INTV_THRESH: Other (Non-Brick 0/1) scope-predict for Ln intervention success Threshold of # of local intervention events (dcache=exclusive from local) before Ln scope is considered despite address group/chip match | |
| 55:57 | RW | RW | CONFIG_SCOPE_PREDICT_OTH_G_INTV_THRESH: Other (Non-Brick 0/1) scope-predict for G intervention success Threshold of # of near intervention events (dcache=exclusive from local) before G scope is considered despite address group/chip match | |
| 58 | RW | RW | CONFIG_SCOPE_PREDICT_OTH_VG_ENABLE: Other (Non-Brick 0/1) scope-predict enable Vg accumulation Enables 'or'-accumulating CResp scope-targets into minimum Vg scope used | |
| 59 | RW | RW | CONFIG_SCOPE_PREDICT0_RESERVED3: reserved | |
| 60:63 | RO | RO | constant=0b0000 | |
| Scope Predictor Control | ||||
|---|---|---|---|---|
| Addr: |
00000000110109AC (SCOM) 0000000013440160 (PAU_RING) | |||
| Name: | PAU3.CS.CTL.MISC.SCOPE_PREDICT1 | |||
| Constant(s): | ||||
| Comments: | Provides control of scope prediction | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:47 | PAU3.CS.CTL.MISC.SCOPE_PREDICT1_Q_0_INST.LATC.L2(0:47) [000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:2 | RW | RW | CONFIG_SCOPE_PREDICT_B1RD_LN_FAIL_THRESH: Brick 1 Read scope-predict for Ln failure control Threshold of # of Ln-scope fail events (forced to larger scope) before Ln scope is skipped as an initial scope | |
| 3:5 | RW | RW | CONFIG_SCOPE_PREDICT_B1RD_NN_FAIL_THRESH: Brick 1 Read scope-predict for Nn failure control Threshold of # of Nn-scope fail events (forced to larger scope) before Nn scope is skipped as an initial scope | |
| 6:8 | RW | RW | CONFIG_SCOPE_PREDICT_B1RD_RN_FAIL_THRESH: Brick 1 Read scope-predict for Rn failure control Threshold of # of Rn-scope fail events (forced to larger scope) before Rn scope is skipped as an initial scope | |
| 9:11 | RW | RW | CONFIG_SCOPE_PREDICT_B1RD_G_FAIL_THRESH: Brick 1 Read scope-predict for G failure control Threshold of # of G-scope fail events (forced to larger scope) before G scope is skipped as an initial scope | |
| 12:14 | RW | RW | CONFIG_SCOPE_PREDICT_B1RD_LN_INTV_THRESH: Brick 1 Read scope-predict for Ln intervention success Threshold of # of local intervention events (dcache=exclusive from local) before Ln scope is considered despite address group/chip match | |
| 15:17 | RW | RW | CONFIG_SCOPE_PREDICT_B1RD_G_INTV_THRESH: Brick 1 Read scope-predict for G intervention success Threshold of # of near intervention events (dcache=exclusive from local) before G scope is considered despite address group/chip match | |
| 18 | RW | RW | CONFIG_SCOPE_PREDICT_B1RD_VG_ENABLE: Brick 1 Read scope-predict enable Vg accumulation Enables 'or'-accumulating CResp scope-targets into minimum Vg scope used | |
| 19 | RW | RW | CONFIG_SCOPE_PREDICT1_RESERVED1: reserved | |
| 20:22 | RW | RW | CONFIG_SCOPE_PREDICT_B1WR_LN_FAIL_THRESH: Brick 1 Write scope-predict for Ln failure control Threshold of # of Ln-scope fail events (forced to larger scope) before Ln scope is skipped as an initial scope | |
| 23:25 | RW | RW | CONFIG_SCOPE_PREDICT_B1WR_NN_FAIL_THRESH: Brick 1 Write scope-predict for Nn failure control Threshold of # of Nn-scope fail events (forced to larger scope) before Nn scope is skipped as an initial scope | |
| 26:28 | RW | RW | CONFIG_SCOPE_PREDICT_B1WR_RN_FAIL_THRESH: Brick 1 Write scope-predict for Rn failure control Threshold of # of Rn-scope fail events (forced to larger scope) before Rn scope is skipped as an initial scope | |
| 29:31 | RW | RW | CONFIG_SCOPE_PREDICT_B1WR_G_FAIL_THRESH: Brick 1 Write scope-predict for G failure control Threshold of # of G-scope fail events (forced to larger scope) before G scope is skipped as an initial scope | |
| 32:34 | RW | RW | CONFIG_SCOPE_PREDICT_B1WR_LN_INTV_THRESH: Brick 1 Write scope-predict for Ln intervention success Threshold of # of local intervention events (dcache=exclusive from local) before Ln scope is considered despite address group/chip match | |
| 35:37 | RW | RW | CONFIG_SCOPE_PREDICT_B1WR_G_INTV_THRESH: Brick 1 Write scope-predict for G intervention success Threshold of # of near intervention events (dcache=exclusive from local) before G scope is considered despite address group/chip match | |
| 38 | RW | RW | CONFIG_SCOPE_PREDICT_B1WR_VG_ENABLE: Brick 1 Write scope-predict enable Vg accumulation Enables 'or'-accumulating CResp scope-targets into minimum Vg scope used | |
| 39 | RW | RW | CONFIG_SCOPE_PREDICT1_RESERVED2: reserved | |
| 40:43 | RW | RW | CONFIG_SCOPE_PREDICT_TIMER_RAND: Scope timer randomness 0 = no bits of the base counter are random 8 = all bits of the base counter are randomized each base tick 9-15 = reserved | |
| 44:47 | RW | RW | CONFIG_SCOPE_PREDICT_TIMER_MAX: Scope timer maximum 0 = predictor timer max is 256 cycles 1 = predictor timer max is 512 cycles ... 8 = predictor timer max is 64K cycles | |
| 48:63 | RO | RO | constant=0b0000000000000000 | |
| Scope Predictor Control | ||||
|---|---|---|---|---|
| Addr: |
00000000110109AD (SCOM) 0000000013440168 (PAU_RING) | |||
| Name: | PAU3.CS.CTL.MISC.SCOPE_PREDICT2 | |||
| Constant(s): | ||||
| Comments: | Provides control of scope prediction | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:39 | PAU3.CS.CTL.MISC.SCOPE_PREDICT2_Q_0_INST.LATC.L2(0:39) [0000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:2 | RW | RW | CONFIG_SCOPE_PREDICT_B2RD_LN_FAIL_THRESH: Brick 2 Read scope-predict for Ln failure control Threshold of # of Ln-scope fail events (forced to larger scope) before Ln scope is skipped as an initial scope | |
| 3:5 | RW | RW | CONFIG_SCOPE_PREDICT_B2RD_NN_FAIL_THRESH: Brick 2 Read scope-predict for Nn failure control Threshold of # of Nn-scope fail events (forced to larger scope) before Nn scope is skipped as an initial scope | |
| 6:8 | RW | RW | CONFIG_SCOPE_PREDICT_B2RD_RN_FAIL_THRESH: Brick 2 Read scope-predict for Rn failure control Threshold of # of Rn-scope fail events (forced to larger scope) before Rn scope is skipped as an initial scope | |
| 9:11 | RW | RW | CONFIG_SCOPE_PREDICT_B2RD_G_FAIL_THRESH: Brick 2 Read scope-predict for G failure control Threshold of # of G-scope fail events (forced to larger scope) before G scope is skipped as an initial scope | |
| 12:14 | RW | RW | CONFIG_SCOPE_PREDICT_B2RD_LN_INTV_THRESH: Brick 2 Read scope-predict for Ln intervention success Threshold of # of local intervention events (dcache=exclusive from local) before Ln scope is considered despite address group/chip match | |
| 15:17 | RW | RW | CONFIG_SCOPE_PREDICT_B2RD_G_INTV_THRESH: Brick 2 Read scope-predict for G intervention success Threshold of # of near intervention events (dcache=exclusive from local) before G scope is considered despite address group/chip match | |
| 18 | RW | RW | CONFIG_SCOPE_PREDICT_B2RD_VG_ENABLE: Brick 2 Read scope-predict enable Vg accumulation Enables 'or'-accumulating CResp scope-targets into minimum Vg scope used | |
| 19 | RW | RW | CONFIG_SCOPE_PREDICT2_RESERVED1: reserved | |
| 20:22 | RW | RW | CONFIG_SCOPE_PREDICT_B2WR_LN_FAIL_THRESH: Brick 2 Write scope-predict for Ln failure control Threshold of # of Ln-scope fail events (forced to larger scope) before Ln scope is skipped as an initial scope | |
| 23:25 | RW | RW | CONFIG_SCOPE_PREDICT_B2WR_NN_FAIL_THRESH: Brick 2 Write scope-predict for Nn failure control Threshold of # of Nn-scope fail events (forced to larger scope) before Nn scope is skipped as an initial scope | |
| 26:28 | RW | RW | CONFIG_SCOPE_PREDICT_B2WR_RN_FAIL_THRESH: Brick 2 Write scope-predict for Rn failure control Threshold of # of Rn-scope fail events (forced to larger scope) before Rn scope is skipped as an initial scope | |
| 29:31 | RW | RW | CONFIG_SCOPE_PREDICT_B2WR_G_FAIL_THRESH: Brick 2 Write scope-predict for G failure control Threshold of # of G-scope fail events (forced to larger scope) before G scope is skipped as an initial scope | |
| 32:34 | RW | RW | CONFIG_SCOPE_PREDICT_B2WR_LN_INTV_THRESH: Brick 2 Write scope-predict for Ln intervention success Threshold of # of local intervention events (dcache=exclusive from local) before Ln scope is considered despite address group/chip match | |
| 35:37 | RW | RW | CONFIG_SCOPE_PREDICT_B2WR_G_INTV_THRESH: Brick 2 Write scope-predict for G intervention success Threshold of # of near intervention events (dcache=exclusive from local) before G scope is considered despite address group/chip match | |
| 38 | RW | RW | CONFIG_SCOPE_PREDICT_B2WR_VG_ENABLE: Brick 2 Write scope-predict enable Vg accumulation Enables 'or'-accumulating CResp scope-targets into minimum Vg scope used | |
| 39 | RW | RW | CONFIG_SCOPE_PREDICT2_RESERVED2: reserved | |
| 40:63 | RO | RO | constant=0b000000000000000000000000 | |
| Scope Predictor Control | ||||
|---|---|---|---|---|
| Addr: |
00000000110109AE (SCOM) 0000000013440170 (PAU_RING) | |||
| Name: | PAU3.CS.CTL.MISC.SCOPE_PREDICT3 | |||
| Constant(s): | ||||
| Comments: | Provides control of scope prediction | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:39 | PAU3.CS.CTL.MISC.SCOPE_PREDICT3_Q_0_INST.LATC.L2(0:39) [0000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:2 | RW | RW | CONFIG_SCOPE_PREDICT_B3RD_LN_FAIL_THRESH: Brick 3 Read scope-predict for Ln failure control Threshold of # of Ln-scope fail events (forced to larger scope) before Ln scope is skipped as an initial scope | |
| 3:5 | RW | RW | CONFIG_SCOPE_PREDICT_B3RD_NN_FAIL_THRESH: Brick 3 Read scope-predict for Nn failure control Threshold of # of Nn-scope fail events (forced to larger scope) before Nn scope is skipped as an initial scope | |
| 6:8 | RW | RW | CONFIG_SCOPE_PREDICT_B3RD_RN_FAIL_THRESH: Brick 3 Read scope-predict for Rn failure control Threshold of # of Rn-scope fail events (forced to larger scope) before Rn scope is skipped as an initial scope | |
| 9:11 | RW | RW | CONFIG_SCOPE_PREDICT_B3RD_G_FAIL_THRESH: Brick 3 Read scope-predict for G failure control Threshold of # of G-scope fail events (forced to larger scope) before G scope is skipped as an initial scope | |
| 12:14 | RW | RW | CONFIG_SCOPE_PREDICT_B3RD_LN_INTV_THRESH: Brick 3 Read scope-predict for Ln intervention success Threshold of # of local intervention events (dcache=exclusive from local) before Ln scope is considered despite address group/chip match | |
| 15:17 | RW | RW | CONFIG_SCOPE_PREDICT_B3RD_G_INTV_THRESH: Brick 3 Read scope-predict for G intervention success Threshold of # of near intervention events (dcache=exclusive from local) before G scope is considered despite address group/chip match | |
| 18 | RW | RW | CONFIG_SCOPE_PREDICT_B3RD_VG_ENABLE: Brick 3 Read scope-predict enable Vg accumulation Enables 'or'-accumulating CResp scope-targets into minimum Vg scope used | |
| 19 | RW | RW | CONFIG_SCOPE_PREDICT3_RESERVED1: reserved | |
| 20:22 | RW | RW | CONFIG_SCOPE_PREDICT_B3WR_LN_FAIL_THRESH: Brick 3 Write scope-predict for Ln failure control Threshold of # of Ln-scope fail events (forced to larger scope) before Ln scope is skipped as an initial scope | |
| 23:25 | RW | RW | CONFIG_SCOPE_PREDICT_B3WR_NN_FAIL_THRESH: Brick 3 Write scope-predict for Nn failure control Threshold of # of Nn-scope fail events (forced to larger scope) before Nn scope is skipped as an initial scope | |
| 26:28 | RW | RW | CONFIG_SCOPE_PREDICT_B3WR_RN_FAIL_THRESH: Brick 3 Write scope-predict for Rn failure control Threshold of # of Rn-scope fail events (forced to larger scope) before Rn scope is skipped as an initial scope | |
| 29:31 | RW | RW | CONFIG_SCOPE_PREDICT_B3WR_G_FAIL_THRESH: Brick 3 Write scope-predict for G failure control Threshold of # of G-scope fail events (forced to larger scope) before G scope is skipped as an initial scope | |
| 32:34 | RW | RW | CONFIG_SCOPE_PREDICT_B3WR_LN_INTV_THRESH: Brick 3 Write scope-predict for Ln intervention success Threshold of # of local intervention events (dcache=exclusive from local) before Ln scope is considered despite address group/chip match | |
| 35:37 | RW | RW | CONFIG_SCOPE_PREDICT_B3WR_G_INTV_THRESH: Brick 3 Write scope-predict for G intervention success Threshold of # of near intervention events (dcache=exclusive from local) before G scope is considered despite address group/chip match | |
| 38 | RW | RW | CONFIG_SCOPE_PREDICT_B3WR_VG_ENABLE: Brick 3 Write scope-predict enable Vg accumulation Enables 'or'-accumulating CResp scope-targets into minimum Vg scope used | |
| 39 | RW | RW | CONFIG_SCOPE_PREDICT3_RESERVED2: reserved | |
| 40:63 | RO | RO | constant=0b000000000000000000000000 | |
| Scope Predictor Control | ||||
|---|---|---|---|---|
| Addr: |
00000000110109AF (SCOM) 0000000013440178 (PAU_RING) | |||
| Name: | PAU3.CS.CTL.MISC.SCOPE_PREDICT4 | |||
| Constant(s): | ||||
| Comments: | Provides control of scope prediction | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:39 | PAU3.CS.CTL.MISC.SCOPE_PREDICT4_Q_0_INST.LATC.L2(0:39) [0000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:2 | RW | RW | CONFIG_SCOPE_PREDICT_B4RD_LN_FAIL_THRESH: Brick 4 Read scope-predict for Ln failure control Threshold of # of Ln-scope fail events (forced to larger scope) before Ln scope is skipped as an initial scope | |
| 3:5 | RW | RW | CONFIG_SCOPE_PREDICT_B4RD_NN_FAIL_THRESH: Brick 4 Read scope-predict for Nn failure control Threshold of # of Nn-scope fail events (forced to larger scope) before Nn scope is skipped as an initial scope | |
| 6:8 | RW | RW | CONFIG_SCOPE_PREDICT_B4RD_RN_FAIL_THRESH: Brick 4 Read scope-predict for Rn failure control Threshold of # of Rn-scope fail events (forced to larger scope) before Rn scope is skipped as an initial scope | |
| 9:11 | RW | RW | CONFIG_SCOPE_PREDICT_B4RD_G_FAIL_THRESH: Brick 4 Read scope-predict for G failure control Threshold of # of G-scope fail events (forced to larger scope) before G scope is skipped as an initial scope | |
| 12:14 | RW | RW | CONFIG_SCOPE_PREDICT_B4RD_LN_INTV_THRESH: Brick 4 Read scope-predict for Ln intervention success Threshold of # of local intervention events (dcache=exclusive from local) before Ln scope is considered despite address group/chip match | |
| 15:17 | RW | RW | CONFIG_SCOPE_PREDICT_B4RD_G_INTV_THRESH: Brick 4 Read scope-predict for G intervention success Threshold of # of near intervention events (dcache=exclusive from local) before G scope is considered despite address group/chip match | |
| 18 | RW | RW | CONFIG_SCOPE_PREDICT_B4RD_VG_ENABLE: Brick 4 Read scope-predict enable Vg accumulation Enables 'or'-accumulating CResp scope-targets into minimum Vg scope used | |
| 19 | RW | RW | CONFIG_SCOPE_PREDICT4_RESERVED1: reserved | |
| 20:22 | RW | RW | CONFIG_SCOPE_PREDICT_B4WR_LN_FAIL_THRESH: Brick 4 Write scope-predict for Ln failure control Threshold of # of Ln-scope fail events (forced to larger scope) before Ln scope is skipped as an initial scope | |
| 23:25 | RW | RW | CONFIG_SCOPE_PREDICT_B4WR_NN_FAIL_THRESH: Brick 4 Write scope-predict for Nn failure control Threshold of # of Nn-scope fail events (forced to larger scope) before Nn scope is skipped as an initial scope | |
| 26:28 | RW | RW | CONFIG_SCOPE_PREDICT_B4WR_RN_FAIL_THRESH: Brick 4 Write scope-predict for Rn failure control Threshold of # of Rn-scope fail events (forced to larger scope) before Rn scope is skipped as an initial scope | |
| 29:31 | RW | RW | CONFIG_SCOPE_PREDICT_B4WR_G_FAIL_THRESH: Brick 4 Write scope-predict for G failure control Threshold of # of G-scope fail events (forced to larger scope) before G scope is skipped as an initial scope | |
| 32:34 | RW | RW | CONFIG_SCOPE_PREDICT_B4WR_LN_INTV_THRESH: Brick 4 Write scope-predict for Ln intervention success Threshold of # of local intervention events (dcache=exclusive from local) before Ln scope is considered despite address group/chip match | |
| 35:37 | RW | RW | CONFIG_SCOPE_PREDICT_B4WR_G_INTV_THRESH: Brick 4 Write scope-predict for G intervention success Threshold of # of near intervention events (dcache=exclusive from local) before G scope is considered despite address group/chip match | |
| 38 | RW | RW | CONFIG_SCOPE_PREDICT_B4WR_VG_ENABLE: Brick 4 Write scope-predict enable Vg accumulation Enables 'or'-accumulating CResp scope-targets into minimum Vg scope used | |
| 39 | RW | RW | CONFIG_SCOPE_PREDICT4_RESERVED2: reserved | |
| 40:63 | RO | RO | constant=0b000000000000000000000000 | |
| BDF-to-PE map 0 | ||||
|---|---|---|---|---|
| Addr: |
00000000110109B0 (SCOM) 0000000013440180 (PAU_RING) | |||
| Name: | PAU3.CS.CTL.MISC.BDF2PE_0_CONFIG | |||
| Constant(s): | ||||
| Comments: | Configured BDF-to-PE mapping #0 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:23 | PAU3.CS.CTL.MISC.BDF2PE_0_CONFIG_Q_0_INST.LATC.L2(0:23) [000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_BDF2PE_0_ENABLE: 0/1 = This BDF-to-PE mapping is disabled/enabled | |
| 1 | RW | RW | CONFIG_BDF2PE_0_WILDCARD: 0/1 = This BDF-to-PE mapping matches only this BDF/matches all BDFs. (if set to 1, then all the other 2 bdf2pe entries must be disabled) | |
| 2:3 | RW | RW | CONFIG_BDF2PE_0_RESERVED: Reserved | |
| 4:7 | RW | RW | CONFIG_BDF2PE_0_PE: PE (Partitionable Endpoint) associated with this BDF | |
| 8:23 | RW | RW | CONFIG_BDF2PE_0_BDF: BDF (Bus-Device-Function) mapped to this PE | |
| 24:63 | RO | RO | constant=0b0000000000000000000000000000000000000000 | |
| BDF-to-PE map 1 | ||||
|---|---|---|---|---|
| Addr: |
00000000110109B1 (SCOM) 0000000013440188 (PAU_RING) | |||
| Name: | PAU3.CS.CTL.MISC.BDF2PE_1_CONFIG | |||
| Constant(s): | ||||
| Comments: | Configured BDF-to-PE mapping #1 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:23 | PAU3.CS.CTL.MISC.BDF2PE_1_CONFIG_Q_0_INST.LATC.L2(0:23) [000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_BDF2PE_1_ENABLE: 0/1 = This BDF-to-PE mapping is disabled/enabled | |
| 1:3 | RW | RW | CONFIG_BDF2PE_1_RESERVED: Reserved | |
| 4:7 | RW | RW | CONFIG_BDF2PE_1_PE: PE (Partitionable Endpoint) associated with this BDF | |
| 8:23 | RW | RW | CONFIG_BDF2PE_1_BDF: BDF (Bus-Device-Function) mapped to this PE | |
| 24:63 | RO | RO | constant=0b0000000000000000000000000000000000000000 | |
| BDF-to-PE map 2 | ||||
|---|---|---|---|---|
| Addr: |
00000000110109B2 (SCOM) 0000000013440190 (PAU_RING) | |||
| Name: | PAU3.CS.CTL.MISC.BDF2PE_2_CONFIG | |||
| Constant(s): | ||||
| Comments: | Configured BDF-to-PE mapping #2 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:23 | PAU3.CS.CTL.MISC.BDF2PE_2_CONFIG_Q_0_INST.LATC.L2(0:23) [000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_BDF2PE_2_ENABLE: 0/1 = This BDF-to-PE mapping is disabled/enabled | |
| 1:3 | RW | RW | CONFIG_BDF2PE_2_RESERVED: Reserved | |
| 4:7 | RW | RW | CONFIG_BDF2PE_2_PE: PE (Partitionable Endpoint) associated with this BDF | |
| 8:23 | RW | RW | CONFIG_BDF2PE_2_BDF: BDF (Bus-Device-Function) mapped to this PE | |
| 24:63 | RO | RO | constant=0b0000000000000000000000000000000000000000 | |
| BDF-to-PE map 3 | ||||
|---|---|---|---|---|
| Addr: |
00000000110109B3 (SCOM) 0000000013440198 (PAU_RING) | |||
| Name: | PAU3.CS.CTL.MISC.BDF2PE_3_CONFIG | |||
| Constant(s): | ||||
| Comments: | Configured BDF-to-PE mapping #3 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:23 | PAU3.CS.CTL.MISC.BDF2PE_3_CONFIG_Q_0_INST.LATC.L2(0:23) [000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_BDF2PE_3_ENABLE: 0/1 = This BDF-to-PE mapping is disabled/enabled | |
| 1:3 | RW | RW | CONFIG_BDF2PE_3_RESERVED: Reserved | |
| 4:7 | RW | RW | CONFIG_BDF2PE_3_PE: PE (Partitionable Endpoint) associated with this BDF | |
| 8:23 | RW | RW | CONFIG_BDF2PE_3_BDF: BDF (Bus-Device-Function) mapped to this PE | |
| 24:63 | RO | RO | constant=0b0000000000000000000000000000000000000000 | |
| BDF-to-PE map 4 | ||||
|---|---|---|---|---|
| Addr: |
00000000110109B4 (SCOM) 00000000134401A0 (PAU_RING) | |||
| Name: | PAU3.CS.CTL.MISC.BDF2PE_4_CONFIG | |||
| Constant(s): | ||||
| Comments: | Configured BDF-to-PE mapping #4 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:23 | PAU3.CS.CTL.MISC.BDF2PE_4_CONFIG_Q_0_INST.LATC.L2(0:23) [000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_BDF2PE_4_ENABLE: 0/1 = This BDF-to-PE mapping is disabled/enabled | |
| 1:3 | RW | RW | CONFIG_BDF2PE_4_RESERVED: Reserved | |
| 4:7 | RW | RW | CONFIG_BDF2PE_4_PE: PE (Partitionable Endpoint) associated with this BDF | |
| 8:23 | RW | RW | CONFIG_BDF2PE_4_BDF: BDF (Bus-Device-Function) mapped to this PE | |
| 24:63 | RO | RO | constant=0b0000000000000000000000000000000000000000 | |
| BDF-to-PE map 5 | ||||
|---|---|---|---|---|
| Addr: |
00000000110109B5 (SCOM) 00000000134401A8 (PAU_RING) | |||
| Name: | PAU3.CS.CTL.MISC.BDF2PE_5_CONFIG | |||
| Constant(s): | ||||
| Comments: | Configured BDF-to-PE mapping #5 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:23 | PAU3.CS.CTL.MISC.BDF2PE_5_CONFIG_Q_0_INST.LATC.L2(0:23) [000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_BDF2PE_5_ENABLE: 0/1 = This BDF-to-PE mapping is disabled/enabled | |
| 1:3 | RW | RW | CONFIG_BDF2PE_5_RESERVED: Reserved | |
| 4:7 | RW | RW | CONFIG_BDF2PE_5_PE: PE (Partitionable Endpoint) associated with this BDF | |
| 8:23 | RW | RW | CONFIG_BDF2PE_5_BDF: BDF (Bus-Device-Function) mapped to this PE | |
| 24:63 | RO | RO | constant=0b0000000000000000000000000000000000000000 | |
| BDF-to-PE map 6 | ||||
|---|---|---|---|---|
| Addr: |
00000000110109B6 (SCOM) 00000000134401B0 (PAU_RING) | |||
| Name: | PAU3.CS.CTL.MISC.BDF2PE_6_CONFIG | |||
| Constant(s): | ||||
| Comments: | Configured BDF-to-PE mapping #6 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:23 | PAU3.CS.CTL.MISC.BDF2PE_6_CONFIG_Q_0_INST.LATC.L2(0:23) [000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_BDF2PE_6_ENABLE: 0/1 = This BDF-to-PE mapping is disabled/enabled | |
| 1:3 | RW | RW | CONFIG_BDF2PE_6_RESERVED: Reserved | |
| 4:7 | RW | RW | CONFIG_BDF2PE_6_PE: PE (Partitionable Endpoint) associated with this BDF | |
| 8:23 | RW | RW | CONFIG_BDF2PE_6_BDF: BDF (Bus-Device-Function) mapped to this PE | |
| 24:63 | RO | RO | constant=0b0000000000000000000000000000000000000000 | |
| BDF-to-PE map 7 | ||||
|---|---|---|---|---|
| Addr: |
00000000110109B7 (SCOM) 00000000134401B8 (PAU_RING) | |||
| Name: | PAU3.CS.CTL.MISC.BDF2PE_7_CONFIG | |||
| Constant(s): | ||||
| Comments: | Configured BDF-to-PE mapping #7 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:23 | PAU3.CS.CTL.MISC.BDF2PE_7_CONFIG_Q_0_INST.LATC.L2(0:23) [000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_BDF2PE_7_ENABLE: 0/1 = This BDF-to-PE mapping is disabled/enabled | |
| 1:3 | RW | RW | CONFIG_BDF2PE_7_RESERVED: Reserved | |
| 4:7 | RW | RW | CONFIG_BDF2PE_7_PE: PE (Partitionable Endpoint) associated with this BDF | |
| 8:23 | RW | RW | CONFIG_BDF2PE_7_BDF: BDF (Bus-Device-Function) mapped to this PE | |
| 24:63 | RO | RO | constant=0b0000000000000000000000000000000000000000 | |
| BDF-to-PE map 8 | ||||
|---|---|---|---|---|
| Addr: |
00000000110109B8 (SCOM) 00000000134401C0 (PAU_RING) | |||
| Name: | PAU3.CS.CTL.MISC.BDF2PE_8_CONFIG | |||
| Constant(s): | ||||
| Comments: | Configured BDF-to-PE mapping #8 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:23 | PAU3.CS.CTL.MISC.BDF2PE_8_CONFIG_Q_0_INST.LATC.L2(0:23) [000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_BDF2PE_8_ENABLE: 0/1 = This BDF-to-PE mapping is disabled/enabled | |
| 1:3 | RW | RW | CONFIG_BDF2PE_8_RESERVED: Reserved | |
| 4:7 | RW | RW | CONFIG_BDF2PE_8_PE: PE (Partitionable Endpoint) associated with this BDF | |
| 8:23 | RW | RW | CONFIG_BDF2PE_8_BDF: BDF (Bus-Device-Function) mapped to this PE | |
| 24:63 | RO | RO | constant=0b0000000000000000000000000000000000000000 | |
| BDF-to-PE map 9 | ||||
|---|---|---|---|---|
| Addr: |
00000000110109B9 (SCOM) 00000000134401C8 (PAU_RING) | |||
| Name: | PAU3.CS.CTL.MISC.BDF2PE_9_CONFIG | |||
| Constant(s): | ||||
| Comments: | Configured BDF-to-PE mapping #9 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:23 | PAU3.CS.CTL.MISC.BDF2PE_9_CONFIG_Q_0_INST.LATC.L2(0:23) [000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_BDF2PE_9_ENABLE: 0/1 = This BDF-to-PE mapping is disabled/enabled | |
| 1:3 | RW | RW | CONFIG_BDF2PE_9_RESERVED: Reserved | |
| 4:7 | RW | RW | CONFIG_BDF2PE_9_PE: PE (Partitionable Endpoint) associated with this BDF | |
| 8:23 | RW | RW | CONFIG_BDF2PE_9_BDF: BDF (Bus-Device-Function) mapped to this PE | |
| 24:63 | RO | RO | constant=0b0000000000000000000000000000000000000000 | |
| BDF-to-PE map 10 | ||||
|---|---|---|---|---|
| Addr: |
00000000110109BA (SCOM) 00000000134401D0 (PAU_RING) | |||
| Name: | PAU3.CS.CTL.MISC.BDF2PE_10_CONFIG | |||
| Constant(s): | ||||
| Comments: | Configured BDF-to-PE mapping #10 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:23 | PAU3.CS.CTL.MISC.BDF2PE_10_CONFIG_Q_0_INST.LATC.L2(0:23) [000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_BDF2PE_10_ENABLE: 0/1 = This BDF-to-PE mapping is disabled/enabled | |
| 1:3 | RW | RW | CONFIG_BDF2PE_10_RESERVED: Reserved | |
| 4:7 | RW | RW | CONFIG_BDF2PE_10_PE: PE (Partitionable Endpoint) associated with this BDF | |
| 8:23 | RW | RW | CONFIG_BDF2PE_10_BDF: BDF (Bus-Device-Function) mapped to this PE | |
| 24:63 | RO | RO | constant=0b0000000000000000000000000000000000000000 | |
| BDF-to-PE map 11 | ||||
|---|---|---|---|---|
| Addr: |
00000000110109BB (SCOM) 00000000134401D8 (PAU_RING) | |||
| Name: | PAU3.CS.CTL.MISC.BDF2PE_11_CONFIG | |||
| Constant(s): | ||||
| Comments: | Configured BDF-to-PE mapping #11 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:23 | PAU3.CS.CTL.MISC.BDF2PE_11_CONFIG_Q_0_INST.LATC.L2(0:23) [000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_BDF2PE_11_ENABLE: 0/1 = This BDF-to-PE mapping is disabled/enabled | |
| 1:3 | RW | RW | CONFIG_BDF2PE_11_RESERVED: Reserved | |
| 4:7 | RW | RW | CONFIG_BDF2PE_11_PE: PE (Partitionable Endpoint) associated with this BDF | |
| 8:23 | RW | RW | CONFIG_BDF2PE_11_BDF: BDF (Bus-Device-Function) mapped to this PE | |
| 24:63 | RO | RO | constant=0b0000000000000000000000000000000000000000 | |
| BDF-to-PE map 12 | ||||
|---|---|---|---|---|
| Addr: |
00000000110109BC (SCOM) 00000000134401E0 (PAU_RING) | |||
| Name: | PAU3.CS.CTL.MISC.BDF2PE_12_CONFIG | |||
| Constant(s): | ||||
| Comments: | Configured BDF-to-PE mapping #12 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:23 | PAU3.CS.CTL.MISC.BDF2PE_12_CONFIG_Q_0_INST.LATC.L2(0:23) [000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_BDF2PE_12_ENABLE: 0/1 = This BDF-to-PE mapping is disabled/enabled | |
| 1:3 | RW | RW | CONFIG_BDF2PE_12_RESERVED: Reserved | |
| 4:7 | RW | RW | CONFIG_BDF2PE_12_PE: PE (Partitionable Endpoint) associated with this BDF | |
| 8:23 | RW | RW | CONFIG_BDF2PE_12_BDF: BDF (Bus-Device-Function) mapped to this PE | |
| 24:63 | RO | RO | constant=0b0000000000000000000000000000000000000000 | |
| BDF-to-PE map 13 | ||||
|---|---|---|---|---|
| Addr: |
00000000110109BD (SCOM) 00000000134401E8 (PAU_RING) | |||
| Name: | PAU3.CS.CTL.MISC.BDF2PE_13_CONFIG | |||
| Constant(s): | ||||
| Comments: | Configured BDF-to-PE mapping #13 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:23 | PAU3.CS.CTL.MISC.BDF2PE_13_CONFIG_Q_0_INST.LATC.L2(0:23) [000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_BDF2PE_13_ENABLE: 0/1 = This BDF-to-PE mapping is disabled/enabled | |
| 1:3 | RW | RW | CONFIG_BDF2PE_13_RESERVED: Reserved | |
| 4:7 | RW | RW | CONFIG_BDF2PE_13_PE: PE (Partitionable Endpoint) associated with this BDF | |
| 8:23 | RW | RW | CONFIG_BDF2PE_13_BDF: BDF (Bus-Device-Function) mapped to this PE | |
| 24:63 | RO | RO | constant=0b0000000000000000000000000000000000000000 | |
| BDF-to-PE map 14 | ||||
|---|---|---|---|---|
| Addr: |
00000000110109BE (SCOM) 00000000134401F0 (PAU_RING) | |||
| Name: | PAU3.CS.CTL.MISC.BDF2PE_14_CONFIG | |||
| Constant(s): | ||||
| Comments: | Configured BDF-to-PE mapping #14 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:23 | PAU3.CS.CTL.MISC.BDF2PE_14_CONFIG_Q_0_INST.LATC.L2(0:23) [000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_BDF2PE_14_ENABLE: 0/1 = This BDF-to-PE mapping is disabled/enabled | |
| 1:3 | RW | RW | CONFIG_BDF2PE_14_RESERVED: Reserved | |
| 4:7 | RW | RW | CONFIG_BDF2PE_14_PE: PE (Partitionable Endpoint) associated with this BDF | |
| 8:23 | RW | RW | CONFIG_BDF2PE_14_BDF: BDF (Bus-Device-Function) mapped to this PE | |
| 24:63 | RO | RO | constant=0b0000000000000000000000000000000000000000 | |
| BDF-to-PE map 15 | ||||
|---|---|---|---|---|
| Addr: |
00000000110109BF (SCOM) 00000000134401F8 (PAU_RING) | |||
| Name: | PAU3.CS.CTL.MISC.BDF2PE_15_CONFIG | |||
| Constant(s): | ||||
| Comments: | Configured BDF-to-PE mapping #15 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:23 | PAU3.CS.CTL.MISC.BDF2PE_15_CONFIG_Q_0_INST.LATC.L2(0:23) [000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_BDF2PE_15_ENABLE: 0/1 = This BDF-to-PE mapping is disabled/enabled | |
| 1:3 | RW | RW | CONFIG_BDF2PE_15_RESERVED: Reserved | |
| 4:7 | RW | RW | CONFIG_BDF2PE_15_PE: PE (Partitionable Endpoint) associated with this BDF | |
| 8:23 | RW | RW | CONFIG_BDF2PE_15_BDF: BDF (Bus-Device-Function) mapped to this PE | |
| 24:63 | RO | RO | constant=0b0000000000000000000000000000000000000000 | |
| CQ_DAT Misc config register #1 | ||||
|---|---|---|---|---|
| Addr: |
00000000110109C1 (SCOM) 0000000013450008 (PAU_RING) | |||
| Name: | PAU3.DAT.MISC.CONFIG1 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.DAT.MISC.CONFIG1Q.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:1 | RW | RW | CONFIG1_MGR_CREDIT: CTL->DAT merge request interface number of credits Dial enums: CREDIT0=>0b00 CREDIT1=>0b01 CREDIT2=>0b11 CREDIT3=>0b10 | |
| 2:4 | RW | RW | CONFIG1_MRG_PBTX_NBUF: CTL->DAT merge request Powerbus TX interface logic request buffer size Dial enums: NBUF0=>0b000 NBUF1=>0b001 NBUF2=>0b011 NBUF3=>0b111 NBUF4=>0b110 NBUF5=>0b100 | |
| 5:8 | RW | RW | CONFIG1_MRG_RDBF_NBUF: CTL->DAT merge request Powerbus TX array read logic request buffer size Dial enums: NBUF0=>0b0000 NBUF1=>0b0001 NBUF2=>0b0011 NBUF3=>0b0111 NBUF4=>0b1111 NBUF5=>0b1110 NBUF6=>0b1100 NBUF7=>0b1000 | |
| 9:12 | RW | RW | CONFIG1_MRG_IBWR_NBUF: CTL->DAT merge request BE merge/OI-loopback/AMO I-buf write logic request buffer size Dial enums: NBUF0=>0b0000 NBUF1=>0b0001 NBUF2=>0b0011 NBUF3=>0b0111 NBUF4=>0b1111 NBUF5=>0b1110 NBUF6=>0b1100 NBUF7=>0b1000 | |
| 13:15 | RW | RW | CONFIG1_MRG_IBRD_NBUF: CTL->DAT merge request BE merge/IO-loopback/AMO I-buf read logic request buffer size Dial enums: NBUF0=>0b000 NBUF1=>0b001 NBUF2=>0b011 NBUF3=>0b111 NBUF4=>0b110 NBUF5=>0b100 | |
| 16:18 | RW | RW | CONFIG1_MRG_BBRD_NBUF: CTL->DAT merge request BE merge B-buf read logic request buffer size Dial enums: NBUF0=>0b000 NBUF1=>0b001 NBUF2=>0b011 NBUF3=>0b111 NBUF4=>0b110 NBUF5=>0b100 | |
| 19:21 | RW | RW | CONFIG1_MRG_OBRD_NBUF: CTL->DAT merge request BE merge/OI-loopback/AMO O-buf read logic request buffer size Dial enums: NBUF0=>0b000 NBUF1=>0b001 NBUF2=>0b011 NBUF3=>0b111 NBUF4=>0b110 NBUF5=>0b100 | |
| 22 | RW | RW | CONFIG1_MRG_CR_DIS: Writing a 1 disables CQ_DAT to send credits to CTL for merge operations | |
| 23 | RW | RW | CONFIG1_MRG_CTLW_CR_DIS: Writing a 1 disables CQ_DAT to send credits to CTL for inbound buffer write operations | |
| 24:25 | RW | RW | CONFIG1_NTLR_PAUSE_THRESH: Specifies number of O-buf NTL port occupation cycles before raising NTL pause request(00b => 32cyc, 01b => 16cyc, 10b => 8cyc, 11b => never) | |
| 26:27 | RW | RW | CONFIG1_CTLR_HP_THRESH: Specifies number of O-buf CTL read wait cycles before giving high priority(00b => 16cyc, 01b => 8cyc, 10b => 4cyc, 11b => never) | |
| 28:29 | RW | RW | CONFIG1_NTLW_PAUSE_THRESH: Specifies number of I-buf NTL port occupation cycles before raising NTL pause request(00b => 16cyc, 01b => 8cyc, 10b => 4cyc, 11b => never) | |
| 30:31 | RW | RW | CONFIG1_CTLW_HP_THRESH: Specifies number of I-buf CTL write wait cycles before giving high priority(00b => 16cyc, 01b => 8cyc, 10b => 4cyc, 11b => never) | |
| 32 | RW | RW | CONFIG1_PBTX_REDUCE_RTAG: Writing a 1 have CQ_DAT limit number of outstanding rtags to 1 on PB transmit interface (default is 2 defined in PB spec) | |
| 33 | RW | RW | CONFIG1_PBTX_DELAY_BDONE: Writing a 1 have CQ_DAT PB transmit logic wait until all the OW is presented on the PB before raising buffdone to CTL | |
| 34 | RW | RW | CONFIG1_PBTX_FLIP_IMIN_BIG: Writing a 1 have CQ_DAT PB transmit logic send the minimum signed integer value (i.e. 100000...) in little endian format for failed armwf_inc_b, armwf_inc_e, or armwf_dec_b AMO operations with e=0 | |
| 35 | RW | RW | CONFIG1_PBTX_FLIP_IMIN_LITTLE: Writing a 1 have CQ_DAT PB transmit logic send the minimum signed integer value (i.e. 100000...) in big endian format for failed armwf_inc_b, armwf_inc_e, or armwf_dec_b AMO operations with e=1 | |
| 36 | RW | RW | CONFIG1_ALU_SAFE_LATENCY: Writing a 1 have CQ_DAT wait for 1 more cycle for ALU output in case x2 phase detection logic goes wrong | |
| 37 | RW | RW | CONFIG1_ALU_FLIP_ENDIAN_BIG: Writing a 1 have CQ_DAT flip the ALU endian when e=0 is specified | |
| 38 | RW | RW | CONFIG1_ALU_FLIP_ENDIAN_LITTLE: Writing a 1 have CQ_DAT flip the ALU endian when e=1 is specified | |
| 39 | RW | RW | CONFIG1_PBTX_EARLY_AFTAG: Writing a 1 have CQ_DAT raise buffdone to CTL earlier for armwf_* operations. CQ_DAT does not wait for fetch data to be presented on the PB. However CQ_DAT does wait for fetch data to leave the I-buf i.e. the buffer entry can still be safely reused. This bit can be randomized in verification. | |
| 40 | RW | RW | CONFIG_BRK0_OCAPI_MODE: 0/1 = Disable OpenCAPI mode / enable OpenCAPI mode for brick 0(mutually exclusive with config_brk0_nvlink_mode)Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_TOPx for this field's IDials | |
| 41 | RW | RW | CONFIG_BRK1_OCAPI_MODE: 0/1 = Disable OpenCAPI mode / enable OpenCAPI mode for brick 1(mutually exclusive with config_brk1_nvlink_mode)Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_TOPx for this field's IDials | |
| 42 | RW | RW | CONFIG_BRK2_OCAPI_MODE: 0/1 = Disable OpenCAPI mode / enable OpenCAPI mode for brick 2(mutually exclusive with config_brk2_nvlink_mode)Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_TOPx for this field's IDials | |
| 43 | RW | RW | CONFIG_BRK3_OCAPI_MODE: 0/1 = Disable OpenCAPI mode / enable OpenCAPI mode for brick 3(mutually exclusive with config_brk3_nvlink_mode)Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_TOPx for this field's IDials | |
| 44 | RW | RW | CONFIG_BRK4_OCAPI_MODE: 0/1 = Disable OpenCAPI mode / enable OpenCAPI mode for brick 4(mutually exclusive with config_brk4_nvlink_mode)Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_TOPx for this field's IDials | |
| 45 | RW | RW | CONFIG_BRK0_NVLINK_MODE: 0/1 = Disable NVLink mode / enable NVLink mode for brick 0(mutually exclusive with config_brk0_ocapi_mode)Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_TOPx for this field's IDials | |
| 46 | RW | RW | CONFIG_BRK1_NVLINK_MODE: 0/1 = Disable NVLink mode / enable NVLink mode for brick 1(mutually exclusive with config_brk1_ocapi_mode)Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_TOPx for this field's IDials | |
| 47 | RW | RW | CONFIG_BRK2_NVLINK_MODE: 0/1 = Disable NVLink mode / enable NVLink mode for brick 2(mutually exclusive with config_brk2_ocapi_mode)Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_TOPx for this field's IDials | |
| 48 | RW | RW | CONFIG_BRK3_NVLINK_MODE: 0/1 = Disable NVLink mode / enable NVLink mode for brick 3(mutually exclusive with config_brk3_ocapi_mode)Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_TOPx for this field's IDials | |
| 49 | RW | RW | CONFIG_BRK4_NVLINK_MODE: 0/1 = Disable NVLink mode / enable NVLink mode for brick 4(mutually exclusive with config_brk4_ocapi_mode)Note: This field should be set to the same value for each brick/stack. An MDial have been created at PAU_TOPx for this field's IDials | |
| 50 | RW | RW | CONFIG1_CHKNSW_HW405659: When set to 1, disables fix for HW405659. (Wrong SUE marking) | |
| 51 | RW | RW | CONFIG1_CHKNSW_HW520782: When set to 1, disables fix for HW520782. (PTE_UPD(radix) being decoded as armwf_inc/dec) | |
| 52 | RW | RW | CONFIG1_CHKNSW_HW531490: When set to 1, disables fix for hw531490. Adding iTag back into ECC calculation | |
| 53:63 | RW | RW | CONFIG1_RESERVED1: reserved | |
| CQ_DAT ECC configuration register | ||||
|---|---|---|---|---|
| Addr: |
00000000110109C2 (SCOM) 0000000013450010 (PAU_RING) | |||
| Name: | PAU3.DAT.MISC.ECC_CONFIG | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:31 | PAU3.DAT.MISC.ECC_CONFIGQ.LATC.L2(0:31) [00000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | ECC_CONFIG_PBTX_AMO_IGNORE_XUE: For armwf_inc/dec ttypes, replace PB transmit data with negative max value when comparison fails, even if the data has UE or SUE. The negative max value will be marked with SUE as long as suedis_pt = 0 | |
| 1 | RW | RW | ECC_CONFIG_SUE_DIS_BR_PERR: Writing a 1 disables marking merge result data with SUE when BE-buf read data latch has parity error | |
| 2 | RW | RW | ECC_CONFIG_SUE_DIS_IR_PERR: Writing a 1 disables marking merge result data with SUE when Inbound-buf read data latch has parity error | |
| 3 | RW | RW | ECC_CONFIG_SUE_DIS_OR_PERR: Writing a 1 disables marking merge result data with SUE when Outbound-buf read data latch has parity error | |
| 4 | RW | RW | ECC_CONFIG_CORR_DIS_PT: Writing a 1 disables ECC correction in Power Bus TX | |
| 5 | RW | RW | ECC_CONFIG_CORR_DIS_PR: Writing a 1 disables ECC correction in Power Bus RX | |
| 6 | RW | RW | ECC_CONFIG_CORR_DIS_BR: Writing a 1 disables ECC correction in Byte Enable buffer read | |
| 7 | RW | RW | ECC_CONFIG_CORR_DIS_IR: Writing a 1 disables ECC correction in Merge operation inbound buffer read | |
| 8 | RW | RW | ECC_CONFIG_CORR_DIS_OR: Writing a 1 disables ECC correction in Merge operation outbound buffer read | |
| 9 | RW | RW | ECC_CONFIG_SUE_DIS_PT: Writing a 1 disables converting ECC UE to SUE in Power Bus TX | |
| 10 | RW | RW | ECC_CONFIG_SUE_DIS_PR: Writing a 1 disables converting ECC UE to SUE in Power Bus RX | |
| 11 | RW | RW | ECC_CONFIG_SUE_DIS_BR: Writing a 1 disables converting ECC UE to SUE in Byte Enable buffer read | |
| 12 | RW | RW | ECC_CONFIG_SUE_DIS_IR: Writing a 1 disables converting ECC UE to SUE in Merge operation inbound buffer read | |
| 13 | RW | RW | ECC_CONFIG_SUE_DIS_OR: Writing a 1 disables converting ECC UE to SUE in Merge operation outbound buffer read | |
| 14:31 | RW | RW | ECC_CONFIG_RESERVED: Reserved | |
| 32:63 | RO | RO | constant=0b00000000000000000000000000000000 | |
| CQ_DAT Scratch Register 0 | ||||
|---|---|---|---|---|
| Addr: |
00000000110109C3 (SCOM) 0000000013450018 (PAU_RING) | |||
| Name: | PAU3.DAT.MISC.SCRATCH0 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.DAT.MISC.SCRATCH0Q.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:63 | RW | RW | SCRATCH0_IDIAL: Scratch register | |
| CQ_DAT ECC error c_err_rpt status and clear register | ||||
|---|---|---|---|---|
| Addr: |
00000000110109C4 (SCOM) 0000000013450020 (PAU_RING) | |||
| Name: | PAU3.DAT.MISC.CERR_ECC_HOLD | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 10:63 | PAU3.DAT.MISC.EECC.HOLD_LATCH_INST.HOLD.LATC.L2(0:53) [000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:9 | RO | RO | constant=0b0000000000 | |
| 10:13 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CERR_ECC_HOLD_PT_UE: ECC ue on Power Bus TX data path (4 ECC words) | |
| 14:17 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CERR_ECC_HOLD_PR_UE: ECC ue on Power Bus RX data path (4 ECC words) | |
| 18:19 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CERR_ECC_HOLD_BR_UE: ECC ue on Byte Enable buffer read data path (2 ECC words) | |
| 20:23 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CERR_ECC_HOLD_IR_UE: ECC ue on Merge operation inbound buffer read data path (4 ECC words) | |
| 24:27 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CERR_ECC_HOLD_OR_UE: ECC ue on Merge operation outbound buffer read data path (4 ECC words) | |
| 28:31 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CERR_ECC_HOLD_PT_SUE: ECC sue on Power Bus TX data path (4 ECC words) | |
| 32:35 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CERR_ECC_HOLD_PR_SUE: ECC sue on Power Bus RX data path (4 ECC words) | |
| 36:37 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CERR_ECC_HOLD_BR_SUE: ECC sue on Byte Enable buffer read data path (2 ECC words) | |
| 38:41 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CERR_ECC_HOLD_IR_SUE: ECC sue on Merge operation inbound buffer read data path (4 ECC words) | |
| 42:45 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CERR_ECC_HOLD_OR_SUE: ECC sue on Merge operation outbound buffer read data path (4 ECC words) | |
| 46:49 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CERR_ECC_HOLD_PT_CE: ECC ce on Power Bus TX data path (4 ECC words) | |
| 50:53 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CERR_ECC_HOLD_PR_CE: ECC ce on Power Bus RX data path (4 ECC words) | |
| 54:55 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CERR_ECC_HOLD_BR_CE: ECC ce on Byte Enable buffer read data path (2 ECC words) | |
| 56:59 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CERR_ECC_HOLD_IR_CE: ECC ce on Merge operation inbound buffer read data path (4 ECC words) | |
| 60:63 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CERR_ECC_HOLD_OR_CE: ECC ce on Merge operation outbound buffer read data path (4 ECC words) | |
| CQ_DAT ECC error c_err_rpt mask register | ||||
|---|---|---|---|---|
| Addr: |
00000000110109C5 (SCOM) 0000000013450028 (PAU_RING) | |||
| Name: | PAU3.DAT.MISC.CERR_ECC_MASK | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 10:63 | PAU3.DAT.MISC.CERR_ECC_MASKQ.LATC.L2(10:63) [000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:9 | RO | RO | constant=0b0000000000 | |
| 10:63 | RW | RW | CERR_ECC_MASK_BITS: CQ_DAT ECC error c_err_rpt mask bits | |
| CQ_DAT ECC error c_err_rpt first register | ||||
|---|---|---|---|---|
| Addr: |
00000000110109C6 (SCOM) 0000000013450030 (PAU_RING) | |||
| Name: | PAU3.DAT.MISC.CERR_ECC_FIRST | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 10:63 | PAU3.DAT.MISC.CERR_ECC_FIRSTQ.LATC.L2(10:63) [000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:9 | RO | RO | constant=0b0000000000 | |
| 10:63 | RWX_WCLEAR | RWX_WCLEAR | CERR_ECC_FIRST_BITS: CQ_DAT ECC error c_err_rpt first error bits | |
| CQ_DAT parity error c_err_rpt status and clear register | ||||
|---|---|---|---|---|
| Addr: |
00000000110109C7 (SCOM) 0000000013450038 (PAU_RING) | |||
| Name: | PAU3.DAT.MISC.CERR_PTY_HOLD | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 37:63 | PAU3.DAT.MISC.EPTY.HOLD_LATCH_INST.HOLD.LATC.L2(0:26) [000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:36 | RO | RO | constant=0b0000000000000000000000000000000000000 | |
| 37 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CERR_PTY_HOLD_INHIBIT_CONFIG: parity error on inhibit config register | |
| 38 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CERR_PTY_HOLD_MISC_STATE: parity error on critical state latches in the misc subunit | |
| 39 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CERR_PTY_HOLD_MRG_STATE: parity error on critical state latches in the merge subunit | |
| 40 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CERR_PTY_HOLD_OBUF_STATE: parity error on critical state latches in the O-buf subunit | |
| 41 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CERR_PTY_HOLD_PBTX_STATE: parity error on critical state latches in the PB transmit subunit | |
| 42 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CERR_PTY_HOLD_RQIN_STATE: parity error on critical state latches in the merge request buffer subunit | |
| 43 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CERR_PTY_HOLD_IBUF_STATE: parity error on critical state latches in the I-buf subunit | |
| 44 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CERR_PTY_HOLD_ERRINJ: parity error on ecc_errinj register | |
| 45:48 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CERR_PTY_HOLD_PBTX_AMO: parity error in PB transmit AMO inc/dec data path (4 words) | |
| 49:52 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CERR_PTY_HOLD_IBRD: parity error in Merge operation inbound buffer read data path (4 words) | |
| 53:56 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CERR_PTY_HOLD_OBRD: parity error in Merge operation outbound buffer read data path (4 words) | |
| 57:58 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CERR_PTY_HOLD_BBRD: parity error in Byte enable buffer read data path (2 words) | |
| 59 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CERR_PTY_HOLD_PBRX_RTAG: parity error on received rtag on the PB receive interface | |
| 60 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CERR_PTY_HOLD_ECC_CONFIG: parity error on ecc_config register | |
| 61 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CERR_PTY_HOLD_CONFIG1: parity error on config1 register | |
| 62 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CERR_PTY_HOLD_DEBUG0_CONFIG: parity error on debug0_config register | |
| 63 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CERR_PTY_HOLD_DEBUG1_CONFIG: parity error on debug1_config register | |
| CQ_DAT parity error c_err_rpt mask register | ||||
|---|---|---|---|---|
| Addr: |
00000000110109C8 (SCOM) 0000000013450040 (PAU_RING) | |||
| Name: | PAU3.DAT.MISC.CERR_PTY_MASK | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 37:63 | PAU3.DAT.MISC.CERR_PTY_MASKQ.LATC.L2(37:63) [000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:36 | RO | RO | constant=0b0000000000000000000000000000000000000 | |
| 37:63 | RW | RW | CERR_PTY_MASK_BITS: CQ_DAT parity error c_err_rpt mask bits | |
| CQ_DAT parity error c_err_rpt first register | ||||
|---|---|---|---|---|
| Addr: |
00000000110109C9 (SCOM) 0000000013450048 (PAU_RING) | |||
| Name: | PAU3.DAT.MISC.CERR_PTY_FIRST | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 37:63 | PAU3.DAT.MISC.CERR_PTY_FIRSTQ.LATC.L2(37:63) [000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:36 | RO | RO | constant=0b0000000000000000000000000000000000000 | |
| 37:63 | RWX_WCLEAR | RWX_WCLEAR | CERR_PTY_FIRST_BITS: CQ_DAT parity error c_err_rpt first error bits | |
| CQ_DAT logic error c_err_rpt status and clear register | ||||
|---|---|---|---|---|
| Addr: |
00000000110109CA (SCOM) 0000000013450050 (PAU_RING) | |||
| Name: | PAU3.DAT.MISC.CERR_LOG_HOLD | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 47:63 | PAU3.DAT.MISC.ELOG.HOLD_LATCH_INST.HOLD.LATC.L2(0:16) [00000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:46 | RO | RO | constant=0b00000000000000000000000000000000000000000000000 | |
| 47 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CERR_LOG_HOLD_BBUF_RDWR: Logic error: Read-write conflict on B-buf, the same buffer entry was read and written in the same cycle | |
| 48 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CERR_LOG_HOLD_IBUF_RDWR: Logic error: Read-write conflict on I-buf, the same buffer entry was read and written in the same cycle | |
| 49 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CERR_LOG_HOLD_OBUF_RDWR: Logic error: Read-write conflict on O-buf, the same buffer entry was read and written in the same cycle | |
| 50:55 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CERR_LOG_HOLD_RQIN_OVF: Logic error: Merge request buffer overflow in a merge pipeline: bit 0: Error in PB transmit request pipeline. bit 1: Error in PB transmit array read pipeline. bit 2: Error in merge I-buf write pipeline. bit 3: Error in merge I-buf read pipeline. bit 4: Error in merge B-buf read pipeline. bit 5: Error in merge O-buf read pipeline. | |
| 56 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CERR_LOG_HOLD_IBUF_CTL_PIPE: Logic error: I-buf CTL write request/data lost due to excessive incoming request. | |
| 57 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CERR_LOG_HOLD_PBTX_PIPE: Logic error: Pipeline overflow in PB transmit logic. | |
| 58 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CERR_LOG_HOLD_MRG_IR_PIPE: Logic error: Pipeline overflow in Merge I-buf read logic. | |
| 59 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CERR_LOG_HOLD_MRG_OR_PIPE: Logic error: Pipeline overflow in Merge O-buf read logic. | |
| 60 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CERR_LOG_HOLD_AMO_ADDR: Logic error: Invalid address position withn OW for armw_cas_t, armwf_inc_b, armwf_inc_e, and armwf_dec_b ttypes | |
| 61 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CERR_LOG_HOLD_PBRX_RTAG: Logic error: Invalid rtag observed on the PB receive interface | |
| 62 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CERR_LOG_HOLD_IBUF_WRITE: Logic error: NTL/ CTL wrote I-buf entry 0-3 cycles after the same entry was read for PB TX | |
| 63 | RWX_WCLEAR | RWX_WCLEAR | IDIAL_CERR_LOG_HOLD_IBUF_WARB: Logic error: More than 1 write requests granted on I-buf write port | |
| CQ_DAT logic error c_err_rpt mask register | ||||
|---|---|---|---|---|
| Addr: |
00000000110109CB (SCOM) 0000000013450058 (PAU_RING) | |||
| Name: | PAU3.DAT.MISC.CERR_LOG_MASK | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 47:63 | PAU3.DAT.MISC.CERR_LOG_MASKQ.LATC.L2(47:63) [00000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:46 | RO | RO | constant=0b00000000000000000000000000000000000000000000000 | |
| 47:63 | RW | RW | CERR_LOG_MASK_BITS: CQ_DAT logic error c_err_rpt mask bits | |
| CQ_DAT logic error c_err_rpt first register | ||||
|---|---|---|---|---|
| Addr: |
00000000110109CC (SCOM) 0000000013450060 (PAU_RING) | |||
| Name: | PAU3.DAT.MISC.CERR_LOG_FIRST | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 47:63 | PAU3.DAT.MISC.CERR_LOG_FIRSTQ.LATC.L2(47:63) [00000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:46 | RO | RO | constant=0b00000000000000000000000000000000000000000000000 | |
| 47:63 | RWX_WCLEAR | RWX_WCLEAR | CERR_LOG_FIRST_BITS: CQ_DAT logic error c_err_rpt first error bits | |
| CQ_DAT RAS Error Message 0 | ||||
|---|---|---|---|---|
| Addr: |
00000000110109CD (SCOM) 0000000013450068 (PAU_RING) | |||
| Name: | PAU3.DAT.MISC.REM0 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 17:63 | PAU3.DAT.MISC.REM0RQ.LATC.L2(17:63) [00000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:16 | RO | RO | constant=0b00000000000000000 | |
| 17:21 | ROX | ROX | REM0_IBUF_WSRC: Indicates the I-buf write requestor that caused read-write conflict. bit 0 : NTL0 datin immediate write. bit 1 : NTL1 datin immediate write. bit 2 : NTL1 datin delayed write. bit 3 : CTL write. bit 4 : Merge logic. | |
| 22:23 | ROX | ROX | REM0_IBUF_RSRC: Indicates the I-buf read requestor that caused read-write conflict. bit 0 : PBTX transmit. bit 1 : Merge logic. | |
| 24:31 | ROX | ROX | REM0_IBUF_AIDX: The I-buf entry (0-255) on which read-write conflict occurred. | |
| 32:33 | ROX | ROX | REM0_IBUF_ABANK: The I-buf array bank (0-3) on which read-write conflict occurred. | |
| 34:35 | ROX | ROX | REM0_OBUF_WSRC: Indicates the O-buf write requestor that caused read-write conflict. bit 0 : PBTX receive. bit 1 : Merge logic I-O loopback. | |
| 36:41 | ROX | ROX | REM0_OBUF_RSRC: Indicates the O-buf read requestor that caused read-write conflict. bit 0 : NTL0 datout immedate read. bit 1 : NTL1 datout immedate read. bit 2 : NTL0 datout regular read. bit 3 : NTL1 datout regular read. bit 4 : Merge logic. bit 5 : CTL read. | |
| 42:49 | ROX | ROX | REM0_OBUF_AIDX: The O-buf entry (0-255) on which read-write conflict occurred. | |
| 50:51 | ROX | ROX | REM0_OBUF_ABANK: The O-buf array bank (0-3) on which read-write conflict occurred. | |
| 52:53 | ROX | ROX | REM0_BBUF_WSRC: Indicates the B-buf write requestor that caused read-write conflict. bit 0 : NTL datin. bit 1 : Dispalt logic in MISC. | |
| 54:55 | ROX | ROX | REM0_BBUF_RSRC: Indicates the B-buf read requestor that caused read-write conflict. bit 0 : Merge logic. bit 1 : Dispalt logic in MISC. | |
| 56:63 | ROX | ROX | REM0_BBUF_AIDX: The B-buf entry (0-255) on which read-write conflict occurred. | |
| CQ_DAT RAS Error Message 1 | ||||
|---|---|---|---|---|
| Addr: |
00000000110109CE (SCOM) 0000000013450070 (PAU_RING) | |||
| Name: | PAU3.DAT.MISC.REM1 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 34:63 | PAU3.DAT.MISC.REM1RQ.LATC.L2(34:63) [000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:33 | RO | RO | constant=0b0000000000000000000000000000000000 | |
| 34:55 | ROX | ROX | REM1_PBRX_RTAG: The invalid rtag observed on PB receive interface. | |
| 56:58 | ROX | ROX | REM1_ALU_ADR: The invalid ALU address in the OW that caused address error (in unit of 4B, 0 to 7). | |
| 59:62 | ROX | ROX | REM1_ALU_TYPE: The ALU optype with which an address error was detected. | |
| 63 | ROX | ROX | REM1_ALU_SZ: The ALU operand size (0:4B, 1:8B) when an address error was detected. | |
| CQ_DAT Debug0 config register | ||||
|---|---|---|---|---|
| Addr: |
00000000110109D0 (SCOM) 0000000013450080 (PAU_RING) | |||
| Name: | PAU3.DAT.MISC.DEBUG0_CONFIG | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.DAT.MISC.DEBUG0_CONFIGQ.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:4 | RW | RW | DEBUG0_CONFIG_POD0: Mux control for byte 0 of trace-0 | |
| 5:9 | RW | RW | DEBUG0_CONFIG_POD1: Mux control for byte 1 of trace-0 | |
| 10:14 | RW | RW | DEBUG0_CONFIG_POD2: Mux control for byte 2 of trace-0 | |
| 15:19 | RW | RW | DEBUG0_CONFIG_POD3: Mux control for byte 3 of trace-0 | |
| 20:24 | RW | RW | DEBUG0_CONFIG_POD4: Mux control for byte 4 of trace-0 | |
| 25:29 | RW | RW | DEBUG0_CONFIG_POD5: Mux control for byte 5 of trace-0 | |
| 30:34 | RW | RW | DEBUG0_CONFIG_POD6: Mux control for byte 6 of trace-0 | |
| 35:39 | RW | RW | DEBUG0_CONFIG_POD7: Mux control for byte 7 of trace-0 | |
| 40:44 | RW | RW | DEBUG0_CONFIG_POD8: Mux control for byte 8 of trace-0 | |
| 45:49 | RW | RW | DEBUG0_CONFIG_POD9: Mux control for byte 9 of trace-0 | |
| 50:54 | RW | RW | DEBUG0_CONFIG_POD10: Mux control for byte 10 of trace-0 | |
| 55:62 | RW | RW | DEBUG0_CONFIG_RESERVED1: reserved | |
| 63 | RW | RW | DEBUG0_CONFIG_ACT: Enable clock-gates for debug trace latches | |
| CQ_DAT Debug1 config register | ||||
|---|---|---|---|---|
| Addr: |
00000000110109D1 (SCOM) 0000000013450088 (PAU_RING) | |||
| Name: | PAU3.DAT.MISC.DEBUG1_CONFIG | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.DAT.MISC.DEBUG1_CONFIGQ.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:4 | RW | RW | DEBUG1_CONFIG_POD0: Mux control for byte 0 of trace-0 | |
| 5:9 | RW | RW | DEBUG1_CONFIG_POD1: Mux control for byte 1 of trace-0 | |
| 10:14 | RW | RW | DEBUG1_CONFIG_POD2: Mux control for byte 2 of trace-0 | |
| 15:19 | RW | RW | DEBUG1_CONFIG_POD3: Mux control for byte 3 of trace-0 | |
| 20:24 | RW | RW | DEBUG1_CONFIG_POD4: Mux control for byte 4 of trace-0 | |
| 25:29 | RW | RW | DEBUG1_CONFIG_POD5: Mux control for byte 5 of trace-0 | |
| 30:34 | RW | RW | DEBUG1_CONFIG_POD6: Mux control for byte 6 of trace-0 | |
| 35:39 | RW | RW | DEBUG1_CONFIG_POD7: Mux control for byte 7 of trace-0 | |
| 40:44 | RW | RW | DEBUG1_CONFIG_POD8: Mux control for byte 8 of trace-0 | |
| 45:49 | RW | RW | DEBUG1_CONFIG_POD9: Mux control for byte 9 of trace-0 | |
| 50:54 | RW | RW | DEBUG1_CONFIG_POD10: Mux control for byte 10 of trace-0 | |
| 55:62 | RW | RW | DEBUG1_CONFIG_RESERVED1: reserved | |
| 63 | RW | RW | DEBUG1_CONFIG_ACT: Enable clock-gates for debug trace latches | |
| CQ_DAT scratch register 1 | ||||
|---|---|---|---|---|
| Addr: |
00000000110109DC (SCOM) 00000000134500E0 (PAU_RING) | |||
| Name: | PAU3.DAT.MISC.SCRATCH1 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.DAT.MISC.SCRATCH1Q.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:63 | RW | RW | SCRATCH1_IDIAL: Scratch register | |
| OTL Configuration 0 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A20 (SCOM) 00000000134C0000 (PAU_RING) | |||
| Name: | PAU3.OTL0.MISC.CONFIG0 | |||
| Constant(s): | ||||
| Comments: | OTL Configuration 0 Register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.OTL0.MISC.CONFIG0_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_OTL_EN: OTL enable - turn on the transaction layer for this brick | |
| 1 | RW | RW | CONFIG_OTL_BLOCK_PE_HANDLE: OTL config - block the pe_handle from affecting the ERAT index | |
| 2:3 | RW | RW | CONFIG_OTL_BRICKID: OTL Brick ID | |
| 4:7 | RW | RW | CONFIG_OTL_PE_MASK: OTL PE_Mask - used to control the BDF+PASID => pe_handle conversion | |
| 8:10 | RW | RW | CONFIG_OTL_RXO_RR2: OTL RXO RR config bits - gives another arb slot to vc1,vc2,vc3 respectively. | |
| 11:31 | RW | RW | CONFIG_OTL_SPARE21: OTL spare config bits | |
| 32 | RW | RW | CONFIG_OTL_CFIFO0_LO_ENABLE1: OTL RXI Command FIFO 0 array error inject lo enable 1 | |
| 33 | RW | RW | CONFIG_OTL_CFIFO0_LO_ENABLE2: OTL RXI Command FIFO 0 array error inject lo enable 2 | |
| 34 | RW | RW | CONFIG_OTL_CFIFO0_HI_ENABLE1: OTL RXI Command FIFO 0 array error inject hi enable 1 | |
| 35 | RW | RW | CONFIG_OTL_CFIFO0_HI_ENABLE2: OTL RXI Command FIFO 0 array error inject hi enable 2 | |
| 36 | RW | RW | CONFIG_OTL_CFIFO1_ENABLE1: OTL RXI Command FIFO 1 array error inject enable 1 | |
| 37 | RW | RW | CONFIG_OTL_CFIFO1_ENABLE2: OTL RXI Command FIFO 1 array error inject enable 2 | |
| 38 | RW | RW | CONFIG_OTL_RFIFO_ENABLE1: OTL RXI Response FIFO array error inject enable 1 | |
| 39 | RW | RW | CONFIG_OTL_RFIFO_ENABLE2: OTL RXI Response FIFO array error inject enable 2 | |
| 40 | RW | RW | CONFIG_OTL_ACTAG_ENABLE1: OTL RXI acTag array error inject enable 1 | |
| 41 | RW | RW | CONFIG_OTL_ACTAG_ENABLE2: OTL RXI acTag array error inject enable 2 | |
| 42 | RW | RW | CONFIG_OTL_CDFIFO_LO_ENABLE1: OTL RXI Command Data FIFO array error inject lo enable 1 | |
| 43 | RW | RW | CONFIG_OTL_CDFIFO_LO_ENABLE2: OTL RXI Command Data FIFO array error inject lo enable 2 | |
| 44 | RW | RW | CONFIG_OTL_CDFIFO_HI_ENABLE1: OTL RXI Command Data FIFO array error inject hi enable 1 | |
| 45 | RW | RW | CONFIG_OTL_CDFIFO_HI_ENABLE2: OTL RXI Command Data FIFO array error inject hi enable 2 | |
| 46 | RW | RW | CONFIG_OTL_RDFIFO_LO_ENABLE1: OTL RXI Response Data FIFO array error inject lo enable 1 | |
| 47 | RW | RW | CONFIG_OTL_RDFIFO_LO_ENABLE2: OTL RXI Response Data FIFO array error inject lo enable 2 | |
| 48 | RW | RW | CONFIG_OTL_RDFIFO_HI_ENABLE1: OTL RXI Response Data FIFO array error inject hi enable 1 | |
| 49 | RW | RW | CONFIG_OTL_RDFIFO_HI_ENABLE2: OTL RXI Response Data FIFO array error inject hi enable 2 | |
| 50 | RW | RW | CONFIG_OTL_BLOCK_TID_OVERRIDE: OTL TID control - blocks the ability for the AFU to speecify the TID in a wake_host_thread command, and lets the XSL determine the TID as usual. | |
| 51 | RW | RW | CONFIG_OTL_ENABLE_4_0: OTL enable version 4 functions - when 1, enables the new 4.0-level functions listed in the OpenCAPI 4.0 specification. | |
| 52 | RW | RW | CONFIG_OTL_VC1FIFO_LO_ENABLE1: OTL RXI vc1 Command FIFO array error inject lo enable 1 | |
| 53 | RW | RW | CONFIG_OTL_VC1FIFO_LO_ENABLE2: OTL RXI vc1 Command FIFO array error inject lo enable 2 | |
| 54 | RW | RW | CONFIG_OTL_VC1FIFO_HI_ENABLE1: OTL RXI vc1 Command FIFO array error inject hi enable 1 | |
| 55 | RW | RW | CONFIG_OTL_VC1FIFO_HI_ENABLE2: OTL RXI vc1 Command FIFO array error inject hi enable 2 | |
| 56 | RW | RW | CONFIG_OTL_VC2FIFO_LO_ENABLE1: OTL RXI vc2 Command FIFO array error inject lo enable 1 | |
| 57 | RW | RW | CONFIG_OTL_VC2FIFO_LO_ENABLE2: OTL RXI vc2 Command FIFO array error inject lo enable 2 | |
| 58 | RW | RW | CONFIG_OTL_DCP2FIFO_LO_ENABLE1: OTL RXI dcp2 Data FIFO array error inject lo enable 1 | |
| 59 | RW | RW | CONFIG_OTL_DCP2FIFO_LO_ENABLE2: OTL RXI dcp2 Data FIFO array error inject lo enable 2 | |
| 60 | RW | RW | CONFIG_OTL_DCP2FIFO_HI_ENABLE1: OTL RXI dcp2 Data FIFO array error inject hi enable 1 | |
| 61 | RW | RW | CONFIG_OTL_DCP2FIFO_HI_ENABLE2: OTL RXI dcp2 Data FIFO array error inject hi enable 2 | |
| 62 | RW | RW | CONFIG_OTL_XLATE_RELEASE_HAS_NO_ITAG: OTL RXO. When 1, RXO is NOT expecting XSL to return an itag for an xlate_release request. Setting this bit contrary to the setting of xsl_gp_bits_dial(40) will cause unpredictable RXO misbehavior. | |
| 63 | RW | RW | CONFIG_OTL_ENABLE_5_0: OTL enable version 5 functions - when 1, enables the new 5.0-level functions listed in the OpenCAPI 5.0 specification. | |
| OTL Chicken Switch 0 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A21 (SCOM) 00000000134C0008 (PAU_RING) | |||
| Name: | PAU3.OTL0.MISC.CHKSW0 | |||
| Constant(s): | ||||
| Comments: | OTL Chicken Switch 0 Register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.OTL0.MISC.CHKSW0_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_INHIBIT_EN: OTL inhibit enable for clock gating | |
| 1:3 | RW | RW | CONFIG_INHIBIT_PACE_ENABLE_CMD: OTL RXI inhibit command pacing enable duration 0b000 disabled 0b001 8k+1 cycles 0b010 2k+1 cycles 0b011 512+1 cycles 0b100 128+1 cycles 0b101 32+1 cycles 0b110 8+1 cycles 0b111 2+1 cycles | |
| 4:6 | RW | RW | CONFIG_INHIBIT_PACE_DISABLE_CMD: OTL RXI inhibit command pacing disable duration 0b000 disabled 0b001 8k+1 cycles 0b010 2k+1 cycles 0b011 512+1 cycles 0b100 128+1 cycles 0b101 32+1 cycles 0b110 8+1 cycles 0b111 2+1 cycles | |
| 7:9 | RW | RW | CONFIG_INHIBIT_PACE_ENABLE_RESP: OTL RXI inhibit response pacing enable duration 0b000 disabled 0b001 8k+1 cycles 0b010 2k+1 cycles 0b011 512+1 cycles 0b100 128+1 cycles 0b101 32+1 cycles 0b110 8+1 cycles 0b111 2+1 cycles | |
| 10:12 | RW | RW | CONFIG_INHIBIT_PACE_DISABLE_RESP: OTL RXI inhibit response pacing disable duration 0b000 disabled 0b001 8k+1 cycles 0b010 2k+1 cycles 0b011 512+1 cycles 0b100 128+1 cycles 0b101 32+1 cycles 0b110 8+1 cycles 0b111 2+1 cycles | |
| 13 | RW | RW | CONFIG_OTL_RXO_SNGLTHRD_XSL_OPS: OTL RXO enable single-threaded ops to XSL | |
| 14 | RW | RW | CONFIG_OTL_RXO_DIS_EARLY_READ: OTL RXO disable early read after write to CTL | |
| 15 | RW | RW | CONFIG_OTL_RXO_HW407209_DISABLE: OTL RXO disable fence cleanup in rxo->rxi credit logic | |
| 16 | RW | RW | CONFIG_OTL_RXO_HW407443_DISABLE: OTL RXO disable fence cleanup in stages 3 and 4 of rxo pipe | |
| 17 | RW | RW | CONFIG_OTL_RXO_CONVERT_DOTN_TO_NORMAL: OTL RXO convert .n commands to normal commands at the RXO->XSL interface | |
| 18 | RW | RW | CONFIG_OTL_RXO_HW530141_DISABLE: OTL RXO disable earlier suspend_done during fence | |
| 19 | RW | RW | CONFIG_OTL_RXO_HW531488_DISABLE: OTL RXO disable fix for proper reset of sync ops during fence | |
| 20 | RW | RW | CONFIG_OTL_RXO_HW538558_DISABLE: OTL RXO disable fix for proper command ordering during suspend | |
| 21:31 | RW | RW | CONFIG_OTL_CHKSW00: OTL chicken switch spares | |
| 32:63 | RW | RW | CONFIG_OTL_CHKSW01: OTL chicken switch spares | |
| OTL PMU Control Register 0 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A22 (SCOM) 00000000134C0010 (PAU_RING) | |||
| Name: | PAU3.OTL0.MISC.PMU_CONTROL0 | |||
| Constant(s): | ||||
| Comments: | OTL Performance Monitor Control Register 0 For each of the 4 pmulet counters (counter0-3), select input event pair using 8 bit field config_pmu_events_c0-3. -- OTL RXI -- x00 array full vc3 fifo, 0 x01 array full vc0 fifo, 0 x02 array full vc1 fifo, 0 x03 array full vc2 fifo, 0 x04 array full dcp3 data fifo, 0 x05 array full dcp0 data fifo, 0 x06 array full dcp2 data fifo, 0 x07 waiting for otl rxo vc3 credit (does not include repeats for 256B ops), 0 x08 waiting for cq ctl vc0 credit, 0 x09 waiting for otl rxo vc1 credit (does not include repeats for 256B ops), 0 x0a waiting for otl rxo vc2 credit (does not include repeats for 256B ops), 0 x0b received control flit, any, 0 x0c received control flit, template x00, 0 x0d received control flit, template x01, 0 x0e received control flit, template x02, 0 x0f received control flit, template x03, 0 x10 received control flit, null, 0 x11 received control flit, not null (=ctlflit_commit_s4), 0 x12 received data flit (validated w/ ctlflit crc), 0 x13 received data flit (validated w/ ctlflit crc) w/ bdfi, 0 x14 received tl credit, any, 0 x15 received tl credit via null control flit, 0 x16 received tl credit via not null control flit, 0 x17 parsed any vc3 opcode, 0 x18 parsed any vc0 opcode, 0 x19 parsed any vc1 opcode, 0 x1a parsed any vc2 opcode, 0 x1b received DL CRC error, 0 x1c waiting for dcp3 data to arrive (does not include rxo cdfiford_pipeline_avail), 0 x1d waiting for dcp0 data to arrive (does not include rxo rdfiford_pipeline_avail), 0 x1e waiting for dcp2 data to arrive (does not include rxo dcp2fiford_pipeline_avail), 0 x1f latency, asserted 1 cycle per configured opcode, 0 x20 latency, asserted every cycle configured opcode is outstanding, 0 x21 received opcode specified by OTL PMU Control Register 1 config_pmu_c01_opcodeA/dlA and OTL PMU Control Register 2 config_pmu_c01_dcmaskA/dlA, 0 x22 received opcode specified by OTL PMU Control Register 1 config_pmu_c01_opcodeB/dlB and OTL PMU Control Register 2 config_pmu_c01_dcmaskB/dlB, 0 x23 received opcode specified by OTL PMU Control Register 1 config_pmu_c23_opcodeA/dlA and OTL PMU Control Register 2 config_pmu_c23_dcmaskA/dlA, 0 x24 received opcode specified by OTL PMU Control Register 1 config_pmu_c23_opcodeB/dlB and OTL PMU Control Register 2 config_pmu_c23_dcmaskB/dlB, 0 x25 HAPPI BAR0 match, 0 x26 HAPPI BAR1 match, 0 x27 HAPPI BAR2 match, 0 x28 HAPPI BAR3 match, 0 -- OTL RXO -- x60 filtered rxi->rxo opcodeA count, filtered rxi->rxo opcodeB count x61 filtered rxi->rxo ordered opcodeA count, filtered rxi->rxo ordered opcodeB count x62 filtered rxi->rxo opcodeA duration event, filtered rxi->rxo opcodeB duration event x63 filtered rxi->rxo opcodeA duration, filtered rxi->rxo opcodeB duration x64 filtered xsl->rxo response (c01 A filter), filtered xsl->rxo response (c01 B filter) x65 filtered rxo->txi op+resp using c01_opcodea+b, filtered rxo->txi op+resp using c23_opcodea+b NOTE: encode 65, event A: pmu_c01_opcode/mask A used for rxo->txi opcode+mask filter, and left half of pmu_c01_opcode/mask B used for response+mask filter NOTE: encode 65, event B: pmu_c23_opcode/mask A used for rxo->txi opcode+mask filter, and left half of pmu_c23_opcode/mask B used for response+mask filter x66 interrupt event, ops to xsl x67 interrupt duration, ops to xsl - credit wait duration x68 interrupt not posted - busy, ops to ctl x69 hashcam is full, ops to ctl - credit wait duration x6A cmd array >= 25% full, ops to ctl - stalled for any reason duration x6B cmd array >= 50% fulll, responses to xsl x6C cmd array >= 75% full, responses to xsl - credit wait duration x6D cmd array is full, responses to txi x6E pmu0/2=16B+byte_en moving to CQDAT // pmu1/3=byte_en to CQDat, responses to xsl - credit wait duration --> OTL PMU Control Register 0 event list continued under OTL PMU Control Register 1 (workaround for 5000 character figmunge limit) | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.OTL0.MISC.PMU_CONTROL0_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_PMU_ENABLE: OTL pmu enable - 1=clock gate enable | |
| 1 | RW | RW | CONFIG_PMU_RESETMODE: OTL pmu resetmode - 0=reset counters on pmu_control0 register read, 1=reset counters on counter register write | |
| 2 | RW | RW | CONFIG_PMU_FREEZEMODE: OTL pmu freezemode - 1=freeze counters on pmulet freeze out asserted | |
| 3 | RW | RW | CONFIG_PMU_DISABLE_PMISC: OTL pmu disable_pmisc - 0=reset counters on powerbus pmu_enable rising edge, freeze counters if pmu_enable not asserted | |
| 4 | RW | RW | CONFIG_PMU_PMISC_MODE: OTL pmu pmisc_mode - 1=reset counters on powerbus pmu_enable rising edge | |
| 5:7 | RW | RW | CONFIG_PMU_CASCADE: OTL pmu cascade - 001=c0_to_c1, 011=c1_to_c2, 011=c2_to_c3, 101=c1_to_c0, 110=c2_to_c1, 111=c3_to_c2 | |
| 8:9 | RW | RW | CONFIG_PMU_PRESCALE_C0: OTL pmu prescale_c0 - 00=20-bit, 01=16-bit, 10=8-bit, 11=4-bit | |
| 10:11 | RW | RW | CONFIG_PMU_PRESCALE_C1: OTL pmu prescale_c1 - 00=20-bit, 01=16-bit, 10=8-bit, 11=4-bit | |
| 12:13 | RW | RW | CONFIG_PMU_PRESCALE_C2: OTL pmu prescale_c2 - 00=20-bit, 01=16-bit, 10=8-bit, 11=4-bit | |
| 14:15 | RW | RW | CONFIG_PMU_PRESCALE_C3: OTL pmu prescale_c3 - 00=20-bit, 01=16-bit, 10=8-bit, 11=4-bit | |
| 16:17 | RW | RW | CONFIG_PMU_OPERATION_C0: OTL pmu operation_c0 - 00=count c0_events0, 01=count c0_events1, 10=count c0_events0+c0_events1, 11=count cycles | |
| 18:19 | RW | RW | CONFIG_PMU_OPERATION_C1: OTL pmu operation_c1 - 00=count c1_events0, 01=count c1_events1, 10=count c1_events0+c1_events1, 11=count cycles | |
| 20:21 | RW | RW | CONFIG_PMU_OPERATION_C2: OTL pmu operation_c2 - 00=count c2_events0, 01=count c2_events1, 10=count c2_events0+c2_events1, 11=count cycles | |
| 22:23 | RW | RW | CONFIG_PMU_OPERATION_C3: OTL pmu operation_c3 - 00=count c3_events0, 01=count c3_events1, 10=count c3_events0+c3_events1, 11=count cycles | |
| 24:31 | RW | RW | CONFIG_PMU_EVENTS_C0: OTL pmu events c0 - selects 2 bit events to input to pmulet counter 0 | |
| 32:39 | RW | RW | CONFIG_PMU_EVENTS_C1: OTL pmu events c1 - selects 2 bit events to input to pmulet counter 1 | |
| 40:47 | RW | RW | CONFIG_PMU_EVENTS_C2: OTL pmu events c2 - selects 2 bit events to input to pmulet counter 2 | |
| 48:55 | RW | RW | CONFIG_PMU_EVENTS_C3: OTL pmu events c3 - selects 2 bit events to input to pmulet counter 3 | |
| 56:63 | RW | RW | CONFIG_PMU_RESERVED0: Reserved | |
| OTL PMU Control Register 1 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A23 (SCOM) 00000000134C0018 (PAU_RING) | |||
| Name: | PAU3.OTL0.MISC.PMU_CONTROL1 | |||
| Constant(s): | ||||
| Comments: | OTL Performance Monitor Control Register 1 - opcode/dLength match filter hit = signal_valid and and_reduce((signal_of_interest xnor match_opcode) or match_dc_mask) --> OTL PMU Control Register 0 event list continued For each of the 4 pmulet counters (counter0-3), select input event pair using 8 bit field config_pmu_events_c0-3. -- OTL TXO -- x80 tied to 0, tied to 1 -- tied to 1 might not be necessary. Can put operation_cX=11 instead. x81 control flit sent, data flit sent x82 data flit for opcodeA sent, data flit for opcodeB sent x83 rate limit nop flit sent, other nop flit sent x84 temp0 flit sent, temp1 flit sent x85 temp2 flit sent, temp3 flit sent x86 nop flit with return_tlx_credits sent, non-nop flit with return_tlx_credits sent x87: reserved x88 temp0 requests sent, temp0 responses sent x89 temp0 opcodeA sent, temp0 opcodeB sent x8a temp1 requests sent, temp1 responses sent x8b temp1 opcodeA sent, temp1 opcodeB sent x8c tied to 0, temp2 responses sent x8d temp2 opcodeA sent, temp2 opcodeB sent x8e temp3 requests sent, temp3 responses sent x8f temp3 opcodeA sent, temp3 opcodeB sent x90 requests with dL=64B sent, responses with dL=64B sent x91 requests with dL=128B sent, responses with dL=128B sent x92 requests sent, responses sent x93: reserved x94 opcode A with dL=64B sent, opcode B with dL=64B sent x95 opcode A with dL=128B sent, opcode B with dL=128B sent x96 opcode A sent, opcode B sent x97: reserved x98 At least one response had to wait for VC0 credits, At least one response had to wait for DCP0 credits x99 VC0 totally exhausted and blocked responses, DCP0 totally exhausted and blocked responses x9A At least one resquest had to wait for VC1 credits, At least one request had to wait for DCP1 credits x9B VC1 totally exhausted and blocked requests, DCP1 totally exhausted and blocked requests x9C contol flit stalled due to insufficient DL credits, data flit stalled due to insufficient DL credits x9D control flit ignored by build, data flit stalled due to insufficient DL credits x9E At least one rquest had to wait for VC2 credits, At least one request had to wait for DCP1 credits (VC2 uses no data) x9F VC2 totally exhausted and blocked requests, DCP1 totally exhausted and blocked VC1 requests (VC2 uses no data) Others: reserved NOTE: opcodeA and opcodeB are specified in the pmu_control1 register. opcodeA/B cannot be used for mathing return_tlx_credits. Use dedicated counter events instead. | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.OTL0.MISC.PMU_CONTROL1_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:7 | RW | RW | CONFIG_PMU_C01_OPCODEA: OTL pmu match opcode A : optional opcode for counter 0/1 to filter out OCAPI requests/responses to count. | |
| 8:15 | RW | RW | CONFIG_PMU_C01_OPCODEB: OTL pmu match opcode B : optional opcode for counter 0/1 to filter out OCAPI requests/responses to count. | |
| 16:23 | RW | RW | CONFIG_PMU_C23_OPCODEA: OTL pmu match opcode A : optional opcode for counter 2/3 to filter out OCAPI requests/responses to count. | |
| 24:31 | RW | RW | CONFIG_PMU_C23_OPCODEB: OTL pmu match opcode B : optional opcode for counter 2/3 to filter out OCAPI requests/responses to count. | |
| 32:33 | RW | RW | CONFIG_PMU_C01_DLA: OTL pmu match opcode A dLength : optional opcode dLength for counter 0/1 to filter out OCAPI requests/responses to count. | |
| 34:35 | RW | RW | CONFIG_PMU_C01_DLB: OTL pmu match opcode B dLength : optional opcode dLength for counter 0/1 to filter out OCAPI requests/responses to count. | |
| 36:37 | RW | RW | CONFIG_PMU_C23_DLA: OTL pmu match opcode A dLength : optional opcode dLength for counter 2/3 to filter out OCAPI requests/responses to count. | |
| 38:39 | RW | RW | CONFIG_PMU_C23_DLB: OTL pmu match opcode B dLength : optional opcode dLength for counter 2/3 to filter out OCAPI requests/responses to count. | |
| 40:47 | RW | RW | CONFIG_PMU_OPCODE_LATENCY: OTL pmu match opcode latency : opcode to filter out AP commands to count PAU latency. | |
| 48:63 | RW | RW | CONFIG_PMU_RESERVED1: Reserved | |
| OTL PMU Control Register 2 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A24 (SCOM) 00000000134C0020 (PAU_RING) | |||
| Name: | PAU3.OTL0.MISC.PMU_CONTROL2 | |||
| Constant(s): | ||||
| Comments: | OTL Performance Monitor Control Register 2 - opcode/dLength dc mask | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.OTL0.MISC.PMU_CONTROL2_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:7 | RW | RW | CONFIG_PMU_C01_DCMASKA: OTL pmu DC mask A : optional don't care mask for counter 0/1 to filter out OCAPI requests/responses to count. | |
| 8:15 | RW | RW | CONFIG_PMU_C01_DCMASKB: OTL pmu DC mask B : optional don't care mask for counter 0/1 to filter out OCAPI requests/responses to count. | |
| 16:23 | RW | RW | CONFIG_PMU_C23_DCMASKA: OTL pmu DC mask A : optional don't care mask for counter 2/3 to filter out OCAPI requests/responses to count. | |
| 24:31 | RW | RW | CONFIG_PMU_C23_DCMASKB: OTL pmu DC mask B : optional don't care mask for counter 2/3 to filter out OCAPI requests/responses to count. | |
| 32:33 | RW | RW | CONFIG_PMU_C01_DCMASKDLA: OTL pmu DC mask dLength A : optional don't care mask for counter 0/1 to filter out OCAPI requests/responses to count. | |
| 34:35 | RW | RW | CONFIG_PMU_C01_DCMASKDLB: OTL pmu DC mask dLength B : optional don't care mask for counter 0/1 to filter out OCAPI requests/responses to count. | |
| 36:37 | RW | RW | CONFIG_PMU_C23_DCMASKDLA: OTL pmu DC mask dLength A : optional don't care mask for counter 2/3 to filter out OCAPI requests/responses to count. | |
| 38:39 | RW | RW | CONFIG_PMU_C23_DCMASKDLB: OTL pmu DC mask dLength B : optional don't care mask for counter 2/3 to filter out OCAPI requests/responses to count. | |
| 40:47 | RW | RW | CONFIG_PMU_DCMASK_LATENCY: unused - spare config bits. | |
| 48:63 | RW | RW | CONFIG_PMU_RESERVED2: Reserved | |
| OTL PMU Count Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A25 (SCOM) 00000000134C0028 (PAU_RING) | |||
| Name: | PAU3.OTL0.MISC.PMU_COUNT | |||
| Constant(s): | ||||
| Comments: | OTL Performance Monitor Count Register (4x16b) | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:15 | PAU3.OTL0.MISC.PMLET.COUNTER0_CNT_Q_0_INST.LATC.L2(0:15) [0000000000000000] | |||
| 16:31 | PAU3.OTL0.MISC.PMLET.COUNTER1_CNT_Q_0_INST.LATC.L2(0:15) [0000000000000000] | |||
| 32:47 | PAU3.OTL0.MISC.PMLET.COUNTER2_CNT_Q_0_INST.LATC.L2(0:15) [0000000000000000] | |||
| 48:63 | PAU3.OTL0.MISC.PMLET.COUNTER3_CNT_Q_0_INST.LATC.L2(0:15) [0000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:15 | ROX | ROX | CONFIG_PMU_COUNT0: OTL pmu count 0 | |
| 16:31 | ROX | ROX | CONFIG_PMU_COUNT1: OTL pmu count 1 | |
| 32:47 | ROX | ROX | CONFIG_PMU_COUNT2: OTL pmu count 2 | |
| 48:63 | ROX | ROX | CONFIG_PMU_COUNT3: OTL pmu count 3 | |
| OTL Error Report Register 0 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A26 (SCOM) 00000000134C0030 (PAU_RING) | |||
| Name: | PAU3.OTL0.MISC.C_ERR_RPT_HOLD0 | |||
| Constant(s): | ||||
| Comments: | OTL Error Report Register 0 (c_err_rpt 0 hold) | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.OTL0.MISC.ERR_RPT0.HOLD_LATCH_INST.HOLD.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_TL_CRD_OVF: OTL TL credit counter overflow caused by return_tl_credits. | |
| 1 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_ACTAG_IDX: OTL RXI acTag specified in a command is outside the configured specification set. | |
| 2 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_ACTAG_INV: OTL RXI acTag specified in the command points to an invalid entry. | |
| 3 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_OPC_RSVD: OTL RXI reserved opcode used. | |
| 4 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_RTC_POS: OTL RXI return_tl_credit command found outside slot0 | |
| 5 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_TMPL: OTL RXI bad opcode and template combination. | |
| 6 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_TMPL_UNS: OTL RXI unsupported template format. | |
| 7 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_TMPL_X00: OTL RXI bad template x00 format. | |
| 8 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_CTLFLIT_OVERRUN: OTL RXI control flit overrun. | |
| 9 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_UNEXPECTED_DATA_FLIT: OTL RXI unexpected data flit. | |
| 10 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_LINK_DOWN: OTL RXI DL link down. | |
| 11 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_BAD_DATA_RECEIVED_CMD: OTL RXI bad data received on command. | |
| 12 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_BAD_DATA_RECEIVED_RESP: OTL RXI bad data received on response. | |
| 13 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_RESPONSE_NOT_ALLOWED: OTL RXI AP response not allowed (CAPPTag not recognized). | |
| 14 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_MISC_PERR: OTL MISC state bit parity error. | |
| 15 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_TXO_PERR: OTL TXO state bit parity error. | |
| 16 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_PERR_FRMD: OTL RXI parity error on frame data. | |
| 17 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_PERR_FRMC: OTL RXI parity error on frame control signals. | |
| 18 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_TXO_CBUF_CE: OTL TX command buffer ECC CE. | |
| 19 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_TXO_CBUF_UE: OTL TX command buffer ECC UE. | |
| 20 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_TXI_DBUF_CE: OTL TX ECC CE on CQ buffer read data. | |
| 21 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_TXI_DBUF_UE: OTL TX ECC UE on CQ buffer read data. | |
| 22 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_CDFIFO_LO_CE: OTL RXI command data fifo ECC CE, lo bits 0:63. | |
| 23 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_CDFIFO_LO_UE: OTL RXI command data fifo ECC UE, lo bits 0:63. | |
| 24 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_CDFIFO_HI_CE: OTL RXI command data fifo ECC CE, hi bits 64:127. | |
| 25 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_CDFIFO_HI_UE: OTL RXI command data fifo ECC UE, hi bits 64:127. | |
| 26 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_RDFIFO_LO_CE: OTL RXI response data fifo ECC CE, lo bits 0:63. | |
| 27 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_RDFIFO_LO_UE: OTL RXI response data fifo ECC UE, lo bits 0:63. | |
| 28 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_RDFIFO_HI_CE: OTL RXI response data fifo ECC CE, hi bits 64:127. | |
| 29 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_RDFIFO_HI_UE: OTL RXI response data fifo ECC UE, hi bits 64:127. | |
| 30 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_CFIFO0_LO_CE: OTL RXI command fifo0 ECC CE, lo bits 0:63. | |
| 31 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_CFIFO0_LO_UE: OTL RXI command fifo0 ECC UE, lo bits 0:63. | |
| 32 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_CFIFO0_HI_CE: OTL RXI command fifo0 ECC CE, hi bits 64:127. | |
| 33 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_CFIFO0_HI_UE: OTL RXI command fifo0 ECC UE, hi bits 64:127. | |
| 34 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_CFIFO1_CE: OTL RXI command fifo1 ECC CE. | |
| 35 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_CFIFO1_UE: OTL RXI command fifo1 ECC UE. | |
| 36 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_RFIFO_CE: OTL RXI response fifo ECC CE. | |
| 37 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_RFIFO_UE: OTL RXI response fifo ECC UE. | |
| 38 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_ACTAG_CE: OTL RXI acTag ECC CE. | |
| 39 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_ACTAG_UE: OTL RXI acTag ECC UE. | |
| 40 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXO_SBE11: OTL RXO Cmd1 Array lo bits SBE. | |
| 41 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXO_UE11: OTL RXO Cmd1 Array lo bits UE. | |
| 42 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXO_SBE12: OTL RXO Cmd1 Array hi bits SBE (byte enable field). | |
| 43 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXO_UE12: OTL RXO Cmd1 Array hi bits UE (byte enable field). | |
| 44 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXO_SBE2: OTL RXO Cmd2 Array SBE. | |
| 45 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXO_UE2: OTL RXO Cmd2 Array UE. | |
| 46 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXO_ILLEGAL_BDF_PASID_ERROR: OTL RXO illegal BDF or PASID error. | |
| 47 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXO_BAD_PE_HANDLE_ERROR: OTL RXO bad pe_handle error. | |
| 48 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXO_OPCODE_VIOLATION_ERROR: OTL RXO opcode violation. | |
| 49 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXO_0B_WR_VIOLATION_ERROR: OTL RXO 0B write detected. | |
| 50 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXO_PL_VIOLATION_INTRP_REQ_D: OTL RXO intrp_req.d pLength violation. | |
| 51 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXO_HASHCAM_DECR_ERROR: OTL RXO hashcam decrement error - response missed the cam. | |
| 52 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXO_HASHCAM_OVERFLOW_ERROR: OTL RXO hashcam overflow error - too many ops received from RXI. | |
| 53 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXO_HASHCAM_UNDERFLOW_ERROR: OTL RXO hashcam underflow error - logic fault. | |
| 54 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXO_CMD_ARRAY_OVERFLOW: OTL RXO command array overflow - too many ops received from RXI. | |
| 55 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXO_ARB_S2_POSTED_WRT_FAIL: OTL RXO arb s2 posted wrt fail - attempted posted write without having write permissions. | |
| 56 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXO_DAT_ARY_CE: OTL RXO data array correctable error. | |
| 57 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXO_DAT_ARY_UE: OTL RXO data array uncorrectable error. | |
| 58 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_CFIFO_OVERRUN: OTL RX command fifo overrun. | |
| 59 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_RFIFO_OVERRUN: OTL RX response fifo overrun. | |
| 60 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_CDFIFO_OVERRUN: OTL RX command data fifo overrun. | |
| 61 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_RDFIFO_OVERRUN: OTL RX response data fifo overrun. | |
| 62 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_DRL_RANGE: OTL RXI control flit data run length invalid. | |
| 63 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_PKTFIELDRSVDVAL_DLEQ0: OTL RXI opcode utilizing dLength specifies dL=0b00 or other invalid dL (hw539630). | |
| OTL Error Report Mask Register 0 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A27 (SCOM) 00000000134C0038 (PAU_RING) | |||
| Name: | PAU3.OTL0.MISC.C_ERR_RPT_MASK0 | |||
| Constant(s): | ||||
| Comments: | OTL Error Report Mask Register 0 (c_err_rpt 0 mask) | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.OTL0.MISC.ERR_RPT0_MASK.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RO | RO | OTL_ERR_MASK000: OTL error mask 0 00 | |
| 1 | RO | RO | OTL_ERR_MASK001: OTL error mask 0 01 | |
| 2 | RO | RO | OTL_ERR_MASK002: OTL error mask 0 02 | |
| 3 | RO | RO | OTL_ERR_MASK003: OTL error mask 0 03 | |
| 4 | RO | RO | OTL_ERR_MASK004: OTL error mask 0 04 | |
| 5 | RO | RO | OTL_ERR_MASK005: OTL error mask 0 05 | |
| 6 | RO | RO | OTL_ERR_MASK006: OTL error mask 0 06 | |
| 7 | RO | RO | OTL_ERR_MASK007: OTL error mask 0 07 | |
| 8 | RO | RO | OTL_ERR_MASK008: OTL error mask 0 08 | |
| 9 | RO | RO | OTL_ERR_MASK009: OTL error mask 0 09 | |
| 10 | RO | RO | OTL_ERR_MASK010: OTL error mask 0 10 | |
| 11 | RO | RO | OTL_ERR_MASK011: OTL error mask 0 11 | |
| 12 | RO | RO | OTL_ERR_MASK012: OTL error mask 0 12 | |
| 13 | RO | RO | OTL_ERR_MASK013: OTL error mask 0 13 | |
| 14 | RO | RO | OTL_ERR_MASK014: OTL error mask 0 14 | |
| 15 | RO | RO | OTL_ERR_MASK015: OTL error mask 0 15 | |
| 16 | RO | RO | OTL_ERR_MASK016: OTL error mask 0 16 | |
| 17 | RO | RO | OTL_ERR_MASK017: OTL error mask 0 17 | |
| 18 | RO | RO | OTL_ERR_MASK018: OTL error mask 0 18 | |
| 19 | RO | RO | OTL_ERR_MASK019: OTL error mask 0 19 | |
| 20 | RO | RO | OTL_ERR_MASK020: OTL error mask 0 20 | |
| 21 | RO | RO | OTL_ERR_MASK021: OTL error mask 0 21 | |
| 22 | RO | RO | OTL_ERR_MASK022: OTL error mask 0 22 | |
| 23 | RO | RO | OTL_ERR_MASK023: OTL error mask 0 23 | |
| 24 | RO | RO | OTL_ERR_MASK024: OTL error mask 0 24 | |
| 25 | RO | RO | OTL_ERR_MASK025: OTL error mask 0 25 | |
| 26 | RO | RO | OTL_ERR_MASK026: OTL error mask 0 26 | |
| 27 | RO | RO | OTL_ERR_MASK027: OTL error mask 0 27 | |
| 28 | RO | RO | OTL_ERR_MASK028: OTL error mask 0 28 | |
| 29 | RO | RO | OTL_ERR_MASK029: OTL error mask 0 29 | |
| 30 | RO | RO | OTL_ERR_MASK030: OTL error mask 0 30 | |
| 31 | RO | RO | OTL_ERR_MASK031: OTL error mask 0 31 | |
| 32 | RO | RO | OTL_ERR_MASK032: OTL error mask 0 32 | |
| 33 | RO | RO | OTL_ERR_MASK033: OTL error mask 0 33 | |
| 34 | RO | RO | OTL_ERR_MASK034: OTL error mask 0 34 | |
| 35 | RO | RO | OTL_ERR_MASK035: OTL error mask 0 35 | |
| 36 | RO | RO | OTL_ERR_MASK036: OTL error mask 0 36 | |
| 37 | RO | RO | OTL_ERR_MASK037: OTL error mask 0 37 | |
| 38 | RO | RO | OTL_ERR_MASK038: OTL error mask 0 38 | |
| 39 | RO | RO | OTL_ERR_MASK039: OTL error mask 0 39 | |
| 40 | RO | RO | OTL_ERR_MASK040: OTL error mask 0 40 | |
| 41 | RO | RO | OTL_ERR_MASK041: OTL error mask 0 41 | |
| 42 | RO | RO | OTL_ERR_MASK042: OTL error mask 0 42 | |
| 43 | RO | RO | OTL_ERR_MASK043: OTL error mask 0 43 | |
| 44 | RO | RO | OTL_ERR_MASK044: OTL error mask 0 44 | |
| 45 | RO | RO | OTL_ERR_MASK045: OTL error mask 0 45 | |
| 46 | RO | RO | OTL_ERR_MASK046: OTL error mask 0 46 | |
| 47 | RO | RO | OTL_ERR_MASK047: OTL error mask 0 47 | |
| 48 | RO | RO | OTL_ERR_MASK048: OTL error mask 0 48 | |
| 49 | RO | RO | OTL_ERR_MASK049: OTL error mask 0 49 | |
| 50 | RO | RO | OTL_ERR_MASK050: OTL error mask 0 50 | |
| 51 | RO | RO | OTL_ERR_MASK051: OTL error mask 0 51 | |
| 52 | RO | RO | OTL_ERR_MASK052: OTL error mask 0 52 | |
| 53 | RO | RO | OTL_ERR_MASK053: OTL error mask 0 53 | |
| 54 | RO | RO | OTL_ERR_MASK054: OTL error mask 0 54 | |
| 55 | RO | RO | OTL_ERR_MASK055: OTL error mask 0 55 | |
| 56 | RO | RO | OTL_ERR_MASK056: OTL error mask 0 56 | |
| 57 | RO | RO | OTL_ERR_MASK057: OTL error mask 0 57 | |
| 58 | RO | RO | OTL_ERR_MASK058: OTL error mask 0 58 | |
| 59 | RO | RO | OTL_ERR_MASK059: OTL error mask 0 59 | |
| 60 | RO | RO | OTL_ERR_MASK060: OTL error mask 0 60 | |
| 61 | RO | RO | OTL_ERR_MASK061: OTL error mask 0 61 | |
| 62 | RO | RO | OTL_ERR_MASK062: OTL error mask 0 62 | |
| 63 | RO | RO | OTL_ERR_MASK063: OTL error mask 0 63 | |
| Debug Config 0 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A28 (SCOM) 00000000134C0040 (PAU_RING) | |||
| Name: | PAU3.OTL0.MISC.CONFIG_DEBUG0 | |||
| Constant(s): | ||||
| Comments: | Debug Config register 0 Selects which bits to route to the debug 0 bus output. There are total 11 of 5 bit field to control what to output each byte pos on the debug 0 bus. The 5 bit field selects one of the following 20 inputs: 00000b: pass_d0: debug bus 0 input passthrough 00001b: pass_d1: debug bus 1 input passthrough 00010b: local0: local trace input group 0 00011b: local1: local trace input group 1 00100b: local2: local trace input group 2 00101b: local3: local trace input group 3 00110b: local4: local trace input group 4 00111b: local5: local trace input group 5 01000b: local6: local trace input group 6 01001b: local7: local trace input group 7 10000b: pass_d0_rot: debug bus 0 input passthrough, rotated by 8 bits 10001b: pass_d1_rot: debug bus 1 input passthrough, rotated by 16 bits 10010b: local0_rot: local trace input group 0, rotated by 24 bits 10011b: local1_rot: local trace input group 1, rotated by 32 bits 10100b: local2_rot: local trace input group 2, rotated by 40 bits 10101b: local3_rot: local trace input group 3, rotated by 48 bits 10110b: local4_rot: local trace input group 4, rotated by 56 bits 10111b: local5_rot: local trace input group 5, rotated by 64 bits 11000b: local6_rot: local trace input group 6, rotated by 72 bits 11001b: local7_rot: local trace input group 7, rotated by 80 bits others: reserved. | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.OTL0.MISC.CONFIG_DEBUG0_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:4 | RW | RW | CONFIG_DEBUG0_BYTE0: 5b select for byte 0 of output bus 0 | |
| 5:9 | RW | RW | CONFIG_DEBUG0_BYTE1: 5b select for byte 1 of output bus 0 | |
| 10:14 | RW | RW | CONFIG_DEBUG0_BYTE2: 5b select for byte 2 of output bus 0 | |
| 15:19 | RW | RW | CONFIG_DEBUG0_BYTE3: 5b select for byte 3 of output bus 0 | |
| 20:24 | RW | RW | CONFIG_DEBUG0_BYTE4: 5b select for byte 4 of output bus 0 | |
| 25:29 | RW | RW | CONFIG_DEBUG0_BYTE5: 5b select for byte 5 of output bus 0 | |
| 30:34 | RW | RW | CONFIG_DEBUG0_BYTE6: 5b select for byte 6 of output bus 0 | |
| 35:39 | RW | RW | CONFIG_DEBUG0_BYTE7: 5b select for byte 7 of output bus 0 | |
| 40:44 | RW | RW | CONFIG_DEBUG0_BYTE8: 5b select for byte 8 of output bus 0 | |
| 45:49 | RW | RW | CONFIG_DEBUG0_BYTE9: 5b select for byte 9 of output bus 0 | |
| 50:54 | RW | RW | CONFIG_DEBUG0_BYTE10: 5b select for byte 10 of output bus 0 | |
| 55:62 | RW | RW | CONFIG_DEBUG0_RESERVED: Reserved | |
| 63 | RW | RW | CONFIG_DEBUG_ACT: Clock activate OTL macro debug logic | |
| Debug Config 1 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A29 (SCOM) 00000000134C0048 (PAU_RING) | |||
| Name: | PAU3.OTL0.MISC.CONFIG_DEBUG1 | |||
| Constant(s): | ||||
| Comments: | Debug Config register 1 Selects which bits to route to the debug 1 bus output. There are total 11 of 5 bit field to control what to output each byte pos on the debug 1 bus. The 5 bit field selects one of the following 20 inputs: 00000b: pass_d0: debug bus 0 input passthrough 00001b: pass_d1: debug bus 1 input passthrough 00010b: local0: local trace input group 0 00011b: local1: local trace input group 1 00100b: local2: local trace input group 2 00101b: local3: local trace input group 3 00110b: local4: local trace input group 4 00111b: local5: local trace input group 5 01000b: local6: local trace input group 6 01001b: local7: local trace input group 7 10000b: pass_d0_rot: debug bus 0 input passthrough, rotated by 8 bits 10001b: pass_d1_rot: debug bus 1 input passthrough, rotated by 16 bits 10010b: local0_rot: local trace input group 0, rotated by 24 bits 10011b: local1_rot: local trace input group 1, rotated by 32 bits 10100b: local2_rot: local trace input group 2, rotated by 40 bits 10101b: local3_rot: local trace input group 3, rotated by 48 bits 10110b: local4_rot: local trace input group 4, rotated by 56 bits 10111b: local5_rot: local trace input group 5, rotated by 64 bits 11000b: local6_rot: local trace input group 6, rotated by 72 bits 11001b: local7_rot: local trace input group 7, rotated by 80 bits others: reserved. | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.OTL0.MISC.CONFIG_DEBUG1_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:4 | RW | RW | CONFIG_DEBUG1_BYTE0: 5b select for byte 0 of output bus 1 | |
| 5:9 | RW | RW | CONFIG_DEBUG1_BYTE1: 5b select for byte 1 of output bus 1 | |
| 10:14 | RW | RW | CONFIG_DEBUG1_BYTE2: 5b select for byte 2 of output bus 1 | |
| 15:19 | RW | RW | CONFIG_DEBUG1_BYTE3: 5b select for byte 3 of output bus 1 | |
| 20:24 | RW | RW | CONFIG_DEBUG1_BYTE4: 5b select for byte 4 of output bus 1 | |
| 25:29 | RW | RW | CONFIG_DEBUG1_BYTE5: 5b select for byte 5 of output bus 1 | |
| 30:34 | RW | RW | CONFIG_DEBUG1_BYTE6: 5b select for byte 6 of output bus 1 | |
| 35:39 | RW | RW | CONFIG_DEBUG1_BYTE7: 5b select for byte 7 of output bus 1 | |
| 40:44 | RW | RW | CONFIG_DEBUG1_BYTE8: 5b select for byte 8 of output bus 1 | |
| 45:49 | RW | RW | CONFIG_DEBUG1_BYTE9: 5b select for byte 9 of output bus 1 | |
| 50:54 | RW | RW | CONFIG_DEBUG1_BYTE10: 5b select for byte 10 of output bus 1 | |
| 55:63 | RW | RW | CONFIG_DEBUG1_RESERVED: Reserved | |
| TLX Credit Configuration | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A2A (SCOM) 00000000134C0050 (PAU_RING) | |||
| Name: | PAU3.OTL0.MISC.CONFIG_TLX_CREDITS | |||
| Constant(s): | ||||
| Comments: | OTL TLX Credit Configuration Register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.OTL0.MISC.CONFIG_TLX_CREDITS_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:7 | RW | RW | CONFIG_TLX_VC0_CREDITS: OTL TLX VC0 Credits - Specifies how many vc0 credits to advertise to AFU (0-64). OTL RX physically has 64 buffer entries for VC0. Thus this field must not exceed 64. Can be changed while OTL is active. | |
| 8:15 | RW | RW | CONFIG_TLX_VC1_CREDITS: OTL TLX VC1 Credits - Specifies how many vc1 credits to advertise to AFU. OTL RX physically has 64 buffer entries for VC1. Thus this field must not exceed 64. Can be changed while OTL is active. | |
| 16:23 | RW | RW | CONFIG_TLX_VC2_CREDITS: OTL TLX VC2 Credits - Specifies how many vc2 credits to advertise to AFU. OTL RX physically has 64 buffer entries for VC2. Thus this field must not exceed 64. Can be changed while OTL is active. | |
| 24:31 | RW | RW | CONFIG_TLX_VC3_CREDITS: OTL TLX VC3 Credits - Specifies how many vc3 credits to advertise to AFU (0-64). OTL RX physically has 64 buffer entries for VC3. Thus this field must not exceed 64. Can be changed while OTL is active. | |
| 32:39 | RW | RW | CONFIG_TLX_DCP0_CREDITS: OTL TLX DCP0 Initial Credits - Specifies how many dcp0 credits to advertise to AFU (0-128). OTL RX physically has 128 buffer entries for DCP0. Thus this field must not exceed 128. Can be changed while OTL is active. | |
| 40:47 | RW | RW | CONFIG_TLX_SPARE: OTL TLX config spare bits | |
| 48:55 | RW | RW | CONFIG_TLX_DCP2_CREDITS: OTL TLX DCP2 Initial Credits - Specifies how many dcp2 credits to advertise to AFU. OTL RX physically has 128 buffer entries for DCP2. Thus this field must not exceed 128. Can be changed while OTL is active. | |
| 56:63 | RW | RW | CONFIG_TLX_DCP3_CREDITS: OTL TLX DCP3 Initial Credits - Specifies how many dcp3 credits to advertise to AFU (0-128). OTL RX physically has 128 buffer entries for DCP3. Thus this field must not exceed 128. Can be changed while OTL is active. | |
| OTL Configuration 1 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A2B (SCOM) 00000000134C0058 (PAU_RING) | |||
| Name: | PAU3.OTL0.MISC.CONFIG_TX | |||
| Constant(s): | ||||
| Comments: | OTL Configuration 1 Register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.OTL0.MISC.CONFIG_TX_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_TX_SPARE0: Spare config bit. | |
| 1 | RW | RW | CONFIG_TX_TEMP1_EN: OTL TX Template 1 Enable - Enables OTL TX to send a template 1 control flit. Can be changed while OTL is active. | |
| 2 | RW | RW | CONFIG_TX_TEMP2_EN: OTL TX Template 2 Enable - Enables OTL TX to send a template 2 control flit. Can be changed while OTL is active. | |
| 3 | RW | RW | CONFIG_TX_TEMP3_EN: OTL TX Template 3 Enable - Enables OTL TX to send a template 3 control flit. Can be changed while OTL is active. | |
| 4 | RW | RW | CONFIG_TX_SPARE1: Spare bit. | |
| 5:7 | RW | RW | CONFIG_TX_DRDY_WAIT: Extra wait cycles (0 to 7) to insert for data ready signal from TXI to TXO pack. If the default wait cycle is too short a TXI C8T read-write conflict will occur. | |
| 8:11 | RW | RW | CONFIG_TX_TEMP0_RATE: Template 0 Flit Rate - Secifies minimum number of data or nop control flits (0-15) to follow a template 0 control flit. This value should be set according to the command flit rate capability of the AFU RX. Can be changed while OTL is active. | |
| 12:15 | RW | RW | CONFIG_TX_TEMP1_RATE: Template 1 Flit Rate - Secifies minimum number of data or nop control flits (0-15) to follow a template 1 control flit. This value should be set according to the command flit rate capability of the AFU RX. Can be changed while OTL is active. | |
| 16:19 | RW | RW | CONFIG_TX_TEMP2_RATE: Template 2 Flit Rate - Secifies minimum number of data or nop control flits (0-15) to follow a template 2 control flit. This value should be set according to the command flit rate capability of the AFU RX. Can be changed while OTL is active. | |
| 20:23 | RW | RW | CONFIG_TX_TEMP3_RATE: Template 3 Flit Rate - Secifies minimum number of data or nop control flits (0-15) to follow a template 3 control flit. This value should be set according to the command flit rate capability of the AFU RX. Can be changed while OTL is active. | |
| 24:31 | RW | RW | CONFIG_TX_SPARE2: Spare bits. | |
| 32:34 | RW | RW | CONFIG_TX_CRET_FREQ: Specifies minimum frequency to return TLX credits to AFU provided that there is a nonzero vc/dcp. 000 : At least once every 512 nest cycles (256ns). 001 : At least once every 256 nest cycles (128ns). 010 : At least once every 128 nest cycles (64ns). 011 : At least once every 64 nest cycles (32ns). 1** : Reserved. Can be changed while OTL is active. | |
| 35:39 | RW | RW | CONFIG_TX_AGE_FREQ: Deprecated / not used starting with Axone design. OTL TX Command Age Update Frequency - Specifies frequency to add age to pending requests/responses. When this register has value N, a pending command ages every time N new requests/responses are input to TX. A command has age 0 (youngest), 1, and 2(oldest). Oldness is considered for scheduling but will not force absolute priority. Can be changed while OTL is active. | |
| 40:45 | RW | RW | CONFIG_TX_RS2_HPWAIT: Deprecated / not used starting with Axone design. OTL TX Response High Priority Threshold - Specifies how long to wait before giving high priority to responses. When this register has value N(1-54), and TX logic sees no response is scheduled while sending N flits (ctrl + data), it will prioritize responses when packing the next control flit. Can be changed while OTL is active. | |
| 46:51 | RW | RW | CONFIG_TX_RQ4_HPWAIT: Deprecated / not used starting with Axone design. OTL TX 4-slot Request High Priority Threshold - Specifies how long to wait before giving high priority to 4-slot requests. When this register has value N(1-54), and TX logic sees no 4-slot request is scheduled while sending N flits (ctrl + data), it will prioritize 4-slot requests when packing the next control flit. Can be changed while OTL is active. | |
| 52:57 | RW | RW | CONFIG_TX_RQ6_HPWAIT: Deprecated / not used starting with Axone design. OTL TX 6-slot Request High Priority Threshold - Specifies how long to wait before giving high priority to 6-slot requests. When this register has value N(1-54), and TX logic sees no 6-slot request is scheduled while sending N flits (ctrl + data), it will prioritize 6-slot requests when packing the next control flit. Can be changed while OTL is active. | |
| 58 | RW | RW | CONFIG_TX_CBUF_ECC_DIS: OTL TX Command Buffer ECC Correction Disable - Setting this bit to 1 disables correcting ECC on TX command buffer read data. | |
| 59 | RW | RW | CONFIG_TX_EVENT: OTL TX tl_event Signal - Setting this bit to 1, TX drives the tl_event signal to ODL, which will notify AFU that appropriate action should be taken. (stop a trace, capture state, etc.). | |
| 60 | RW | RW | CONFIG_TX_STOP_ON_UE: OTL TX Stop Link on UE - Setting this bit to 1 allows TX to assert the tl_error signal to ODL when it detects UEs on command buffer C8T. | |
| 61 | RW | RW | CONFIG_TX_T0_MASK_CRTN0: OTL TX Mask All-zero return_tlx_credits for Template0 - Setting this bit to 1 have TX logic zero out return_tlx_credit packets when all VC/DCP counts are 0s when sending out a template 0 control flit. The slot 0 and 1 will be all 0s (i.e. NOP). | |
| 62 | RW | RW | CONFIG_TX_T123_MASK_CRTN0: OTL TX Mask All-zero return_tlx_credits for Template1,2,3 - Setting this bit to 1 have TX logic zero out return_tlx_credit packets when all VC/DCP counts are 0s when sending out a template 1,2, or 3 control flit. The slot 0 and 1 will be all 0s (i.e. NOP). | |
| 63 | RW | RW | CONFIG_TX_SPARE3: OTL TX spare cfg bits. | |
| OTL TX DL Credit Configuration | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A2C (SCOM) 00000000134C0060 (PAU_RING) | |||
| Name: | PAU3.OTL0.MISC.CONFIG_TX_DLC | |||
| Constant(s): | ||||
| Comments: | OTL TX DL Credit Configuration Register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:9 | PAU3.OTL0.MISC.CONFIG_TX_DLC_Q_0_INST.LATC.L2(0:9) [0000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:9 | RW | RW | CONFIG_TX_DL_CREDITS: OTL TX DL Credits - Specifies how many DL TX credits OTL initially has. (0-64) ODL buffer size is 64 entries (16B entries) and hence this field should be set to 64. Can be changed while OTL is active. | |
| 10:63 | RO | RO | constant=0b000000000000000000000000000000000000000000000000000000 | |
| OTL RAS Error Message 0 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A2D (SCOM) 00000000134C0068 (PAU_RING) | |||
| Name: | PAU3.OTL0.MISC.OTL_REM0 | |||
| Constant(s): | ||||
| Comments: | OTL RAS Error Message 0 Register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:7 | PAU3.OTL0.MISC.OTL_REM0Q.LATC.L2(0:7) [00000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | ROX | ROX | REM0_CRD_TL_OVF_VC0: TL vc0 credit counter overflow condition has encountered as a result of a received return_tl_credit. The HW logic saturated the counter at 2^16-1. | |
| 1 | ROX | ROX | REM0_CRD_TL_OVF_VC1: TL vc1 credit counter overflow condition has encountered as a result of a received return_tl_credit. The HW logic saturated the counter at 2^16-1. | |
| 2 | ROX | ROX | REM0_CRD_TL_OVF_VC2: TL vc2 credit counter overflow condition has encountered as a result of a received return_tl_credit. The HW logic saturated the counter at 2^16-1. | |
| 3 | ROX | ROX | REM0_CRD_TL_OVF_RSVD3: Reserved. | |
| 4 | ROX | ROX | REM0_CRD_TL_OVF_DCP0: TL dcp0 credit counter overflow condition has encountered as a result of a received return_tl_credit. The HW logic saturated the counter at 2^16-1. | |
| 5 | ROX | ROX | REM0_CRD_TL_OVF_DCP1: TL dcp1 credit counter overflow condition has encountered as a result of a received return_tl_credit. The HW logic saturated the counter at 2^16-1. | |
| 6 | ROX | ROX | REM0_CRD_TL_OVF_RSVD6: Reserved. | |
| 7 | ROX | ROX | REM0_CRD_TL_OVF_RSVD7: Reserved. | |
| 8:63 | RO | RO | constant=0b00000000000000000000000000000000000000000000000000000000 | |
| OTL RXI Error Signature | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A2E (SCOM) 00000000134C0070 (PAU_RING) | |||
| Name: | PAU3.OTL0.MISC.ERROR_SIG_RXI | |||
| Constant(s): | ||||
| Comments: | OTL RXI Error Signature Register Captures on first error not masked by c_err_rpt | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.OTL0.MISC.ERROR_SIG_RXIQ.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | ERRSIGRXI_CAPTURED: 0b1 = error signature valid | |
| 1:7 | RW | RW | ERRSIGRXI_ENCODE: error encode matches c_err_rpt 0 | |
| 8:63 | RW | RW | ERRSIGRXI_SIGNATURE: error signature varies by encode | |
| OTL RXO Error Signature Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A2F (SCOM) 00000000134C0078 (PAU_RING) | |||
| Name: | PAU3.OTL0.MISC.ERROR_SIG_RXO | |||
| Constant(s): | ||||
| Comments: | OTL RXO Error Signature Register Captures on first error not masked by c_err_rpt | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.OTL0.MISC.ERROR_SIG_RXOQ.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:2 | RWX | RWX | ERRSIGRXO_TYPE: 0b100 = bdf/pasid error 0b010 = opcode error 0b001 = arb_s2_posted_wrt_fail/pe_handle error | |
| 3 | RWX | RWX | ERRSIGRXO_XSL_RSP0: xsl response bit 0 - only valid when errsigrxo_type=001. See errsigrxo_xsl_rsp12. | |
| 4:19 | RWX | RWX | ERRSIGRXO_AFUTAG: afutag of the offending op | |
| 20:27 | RWX | RWX | ERRSIGRXO_OPCODE: opcode of the offending op | |
| 28:39 | RWX | RWX | ERRSIGRXO_ACTAG: actag of the offending op - valid only if a bdf or pasid error. If pe_handle error, or another type, then actag must be derived by finding the actag entry that yields the pe_handle in the queue entry | |
| 40:45 | RWX | RWX | ERRSIGRXO_QINDEX: index of the rxo queue entry used by the offending op | |
| 46:61 | RWX | RWX | ERRSIGRXO_PE_HANDLE: pe_handle of the bad op - only valid when errsigrxo_type=001 | |
| 62:63 | RWX | RWX | ERRSIGRXO_XSL_RSP12: xsl response bits 1:2 - only valid when errsigrxo_type=001. Encodes(0:2): 1=TA permission mismatch, 2=TA Process Index mismatch, 3=Invalid TA, 4=Brick fence in progress. | |
| Alter OTL Credit Counters | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A30 (SCOM) 00000000134C0080 (PAU_RING) | |||
| Name: | PAU3.OTL0.MISC.ALTER_CREDIT_COUNTERS | |||
| Constant(s): | ||||
| Comments: | Alter OTL Credit Counters | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:23 | PAU3.OTL0.MISC.ALTER_CREDIT_COUNTERS_Q_0_INST.LATC.L2(0:23) [000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | ALTER_CRD_ENABLE: Enables altering credit counters. | |
| 1:3 | RW | RW | ALTER_CRD_RESERVED: Reserved. | |
| 4:7 | RW | RW | ALTER_CRD_TARGET: When a nonzero value is to this register, a credit counter will be updated with the value field. This update occurs only once on writing this register. 0 : Will not update any credit counter. 1 : Update the TLX vc0 credit counter. Only 8 LSBs of the value field will be used. 2 : Update the TLX vc1 credit counter. Only 8 LSBs of the value field will be used. 3 : Update the TLX vc2 credit counter. Only 8 LSBs of the value field will be used. 4 : Update the TLX vc3 credit counter. Only 8 LSBs of the value field will be used. 5 : Update the TLX dcp0 credit counter. Only 8 LSBs of the value field will be used. 6 : Update the TLX dcp2 credit counter. Only 8 LSBs of the value field will be used. 7 : Update the TLX dcp3 credit counter. Only 8 LSBs of the value field will be used. 8 : Update the TL vc0 credit counter. 9 : Update the TL vc1 credit counter. 10 : Update the TL vc2 credit counter. 11 : Update the TL dcp0 credit counter. 12 : Update the TL dcp1 credit counter. 13 : Update the TX DL credit counter. | |
| 8:23 | RW | RW | ALTER_CRD_VALUE: The value to be written to the target credit counter. | |
| 24:63 | RO | RO | constant=0b0000000000000000000000000000000000000000 | |
| TLX Credit Counter Status | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A31 (SCOM) 00000000134C0088 (PAU_RING) | |||
| Name: | PAU3.OTL0.MISC.TLX_CREDIT_STATUS | |||
| Constant(s): | ||||
| Comments: | OTL TLX Credit Counter Status Register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:7 | PAU3.OTL0.MISC.CRD_TLX_VC0Q.LATC.L2(0:7) [00000000] | |||
| 8:15 | PAU3.OTL0.MISC.CRD_TLX_VC1Q.LATC.L2(0:7) [00000000] | |||
| 16:23 | PAU3.OTL0.MISC.CRD_TLX_VC2Q.LATC.L2(0:7) [00000000] | |||
| 24:31 | PAU3.OTL0.MISC.CRD_TLX_VC3Q.LATC.L2(0:7) [00000000] | |||
| 32:39 | PAU3.OTL0.MISC.CRD_TLX_DCP0Q.LATC.L2(0:7) [00000000] | |||
| 40:47 | PAU3.OTL0.MISC.CRD_TLX_DCP2Q.LATC.L2(0:7) [00000000] | |||
| 48:55 | PAU3.OTL0.MISC.CRD_TLX_DCP3Q.LATC.L2(0:7) [00000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:7 | ROX | ROX | STATUS_TLX_VC0_COUNT: Current value of the TLX vc0 credit counter. Indicates (number of credits OTL has advertised) minus (number of consumed credits by the received TLX packets). When idle, this counter should match the config_tlx_vc0_credits value. | |
| 8:15 | ROX | ROX | STATUS_TLX_VC1_COUNT: Current value of the TLX vc1 credit counter. Indicates (number of credits OTL has advertised) minus (number of consumed credits by the received TLX packets). When idle, this counter should match the config_tlx_vc1_credits value. | |
| 16:23 | ROX | ROX | STATUS_TLX_VC2_COUNT: Current value of the TLX vc2 credit counter. Indicates (number of credits OTL has advertised) minus (number of consumed credits by the received TLX packets). When idle, this counter should match the config_tlx_vc2_credits value. | |
| 24:31 | ROX | ROX | STATUS_TLX_VC3_COUNT: Current value of the TLX vc3 credit counter. Indicates (number of credits OTL has advertised) minus (number of consumed credits by the received TLX packets). When idle, this counter should match the config_tlx_vc3_credits value. | |
| 32:39 | ROX | ROX | STATUS_TLX_DCP0_COUNT: Current value of the TLX dcp0 credit counter. Indicates (number of credits OTL has advertised) minus (number of consumed credits by the received TLX packets). When idle, this counter should match the config_tlx_dcp0_credits value. | |
| 40:47 | ROX | ROX | STATUS_TLX_DCP2_COUNT: Current value of the TLX dcp2 credit counter. Indicates (number of credits OTL has advertised) minus (number of consumed credits by the received TLX packets). When idle, this counter should match the config_tlx_dcp2_credits value. | |
| 48:55 | ROX | ROX | STATUS_TLX_DCP3_COUNT: Current value of the TLX dcp3 credit counter. Indicates (number of credits OTL has advertised) minus (number of consumed credits by the received TLX packets). When idle, this counter should match the config_tlx_dcp3_credits value. | |
| 56:63 | RO | RO | constant=0b00000000 | |
| TL VC Credit Counter Status | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A32 (SCOM) 00000000134C0090 (PAU_RING) | |||
| Name: | PAU3.OTL0.MISC.TL_VC_CREDIT_STATUS | |||
| Constant(s): | ||||
| Comments: | OTL TL VC Credit Counter Status Register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:15 | PAU3.OTL0.MISC.CRD_TL_VC0Q.LATC.L2(0:15) [0000000000000000] | |||
| 16:31 | PAU3.OTL0.MISC.CRD_TL_VC1Q.LATC.L2(0:15) [0000000000000000] | |||
| 32:47 | PAU3.OTL0.MISC.CRD_TL_VC2Q.LATC.L2(0:15) [0000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:15 | ROX | ROX | STATUS_TL_VC0_COUNT: Current value of the TL vc0 credit counter. Indicates number of vc0 packets in contol flits OTL is allowed to send to AFU. When idle, this counter should hit the MAX value AFU can advertise. | |
| 16:31 | ROX | ROX | STATUS_TL_VC1_COUNT: Current value of the TL vc1 credit counter. Indicates number of vc1 packets in contol flits OTL is allowed to send to AFU. When idle, this counter should hit the MAX value AFU can advertise. | |
| 32:47 | ROX | ROX | STATUS_TL_VC2_COUNT: Current value of the TL vc2 credit counter. Indicates number of vc2 packets in contol flits OTL is allowed to send to AFU. When idle, this counter should hit the MAX value AFU can advertise. | |
| 48:63 | RO | RO | constant=0b0000000000000000 | |
| TL DCP Credit Counter Status | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A33 (SCOM) 00000000134C0098 (PAU_RING) | |||
| Name: | PAU3.OTL0.MISC.TL_DCP_CREDIT_STATUS | |||
| Constant(s): | ||||
| Comments: | OTL TL DCP Credit Counter Status Register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:15 | PAU3.OTL0.MISC.CRD_TL_DCP0Q.LATC.L2(0:15) [0000000000000000] | |||
| 16:31 | PAU3.OTL0.MISC.CRD_TL_DCP1Q.LATC.L2(0:15) [0000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:15 | ROX | ROX | STATUS_TL_DCP0_COUNT: Current value of the TL dcp0 credit counter. Indicates number of data flits in dcp0 that OTL is allowed to send to AFU. When idle, this counter should hit the MAX value AFU can advertise. | |
| 16:31 | ROX | ROX | STATUS_TL_DCP1_COUNT: Current value of the TL dcp1 credit counter. Indicates number of data flits in dcp1 that OTL is allowed to send to AFU. When idle, this counter should hit the MAX value AFU can advertise. | |
| 32:63 | RO | RO | constant=0b00000000000000000000000000000000 | |
| TX DL Credit Counter Status | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A34 (SCOM) 00000000134C00A0 (PAU_RING) | |||
| Name: | PAU3.OTL0.MISC.TX_DL_CREDIT_STATUS | |||
| Constant(s): | ||||
| Comments: | OTL TX DL Credit Counter Status Register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:11 | PAU3.OTL0.MISC.CRD_DL_TXQ.LATC.L2(0:11) [000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:11 | ROX | ROX | STATUS_DL_CREDIT_COUNT: Current value of the TX DL credit counter. Indicates number of 16B chunks of command or data flits that OTL TX can send to ODL TX. When idle, this counter should hit the MAX value ODL can advertise. | |
| 12:63 | RO | RO | constant=0b0000000000000000000000000000000000000000000000000000 | |
| TXI Error Injection | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A35 (SCOM) 00000000134C00A8 (PAU_RING) | |||
| Name: | PAU3.OTL0.MISC.TXI_ERR_INJ | |||
| Constant(s): | ||||
| Comments: | OTL TXI Array Error Injection Control and Status Register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:5 | PAU3.OTL0.MISC.TXI_ERR_INJQ.LATC.L2(0:5) [000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX | RWX | TXI_CTRL_ERR_INJ_CE: CE error injection control for TXI CTRL array. On register write withg this bit set to 1, the next SRAM write will contain a CE. | |
| 1 | RWX | RWX | TXI_CTRL_ERR_INJ_UE: UE error injection control for TXI CTRL array. On register write withg this bit set to 1, the next SRAM write will contain a UE. | |
| 2 | RWX | RWX | TXI_DATA_ERR_INJ_CE: CE error injection control for TXI DATA array. On register write withg this bit set to 1, the next SRAM write will contain a CE. | |
| 3 | RWX | RWX | TXI_DATA_ERR_INJ_UE: UE error injection control for TXI DATA array. On register write withg this bit set to 1, the next SRAM write will contain a UE. | |
| 4 | ROX | ROX | TXI_CTRL_ERR_INJ_PEND: Error injection status for TXI CTRL array. This register will read 1 until the requested error has been injected. | |
| 5 | ROX | ROX | TXI_DATA_ERR_INJ_PEND: Error injection status for TXI DATA array. This register will read 1 until the requested error has been injected. | |
| 6:63 | RO | RO | constant=0b0000000000000000000000000000000000000000000000000000000000 | |
| OTL Error Report Register 1 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A36 (SCOM) 00000000134C00B0 (PAU_RING) | |||
| Name: | PAU3.OTL0.MISC.C_ERR_RPT_HOLD1 | |||
| Constant(s): | ||||
| Comments: | OTL Error Report Register 1 (c_err_rpt 1 hold) | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:31 | PAU3.OTL0.MISC.ERR_RPT1.HOLD_LATCH_INST.HOLD.LATC.L2(0:31) [00000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_VC1FIFO_LO_CE: OTL RXI vc1 fifo ECC CE, lo bits 0:63. | |
| 1 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_VC1FIFO_LO_UE: OTL RXI vc1 fifo ECC CE, lo bits 0:63. | |
| 2 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_VC1FIFO_HI_CE: OTL RXI vc1 fifo ECC CE, hi bits 64:111. | |
| 3 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_VC1FIFO_HI_UE: OTL RXI vc1 fifo ECC CE, hi bits 64:111. | |
| 4 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_VC2FIFO_LO_CE: OTL RXI vc2 fifo ECC CE, lo bits 0:55. | |
| 5 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_VC2FIFO_LO_UE: OTL RXI vc2 fifo ECC CE, lo bits 0:55. | |
| 6 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_BAD_DATA_RECIEVED_VC2: OTL RXI bad data received vc2. | |
| 7 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_DCP2FIFO_LO_CE: OTL RXI dcp2 data fifo ECC CE, lo bits 0:63. | |
| 8 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_DCP2FIFO_LO_UE: OTL RXI dcp2 data fifo ECC CE, lo bits 0:63. | |
| 9 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_DCP2FIFO_HI_CE: OTL RXI dcp2 data fifo ECC CE, lo bits 64:127. | |
| 10 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_DCP2FIFO_HI_UE: OTL RXI dcp2 data fifo ECC CE, lo bits 64:127. | |
| 11 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_DCP2FIFO_OVERRUN: OTL RXI dcp2fifo overrun. | |
| 12 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_VC1FIFO_OVERRUN: OTL RXI vc1fifo overrun. | |
| 13 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_VC2FIFO_OVERRUN: OTL RXI vc2fifo overrun. | |
| 14 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_DL_VC0: OTL RXI dL not supported vc0. | |
| 15 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_DL_VC2: OTL RXI dL not supported vc2. | |
| 16 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_DL_VC3: OTL RXI dL not supported vc3. | |
| 17 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_TXI_CTL_OPCODE_ERR: OTL TXI CTL issued 4.0 opcode while in 3.0 mode. See error_sig_txi. | |
| 18 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_TXI_XSL_OPCODE_ERR: OTL TXI XSL issued 4.0 opcode while in 3.0 mode. See error_sig_txi. | |
| 19 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_FIELDRSVDNE0_TLVC2: OTL RXI malformed packet error type 4, reserved field not transmitted as 0, TL.vc.2 in ocapi 3.0 mode. | |
| 20 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_IMP_NOBARMATCH: OTL RXI Incepted Memory no address BAR match. | |
| 21 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD1_SPARE21: OTL error spare 21 | |
| 22 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD1_SPARE22: OTL error spare 22 | |
| 23 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD1_SPARE23: OTL error spare 23 | |
| 24 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD1_SPARE24: OTL error spare 24 | |
| 25 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD1_SPARE25: OTL error spare 25 | |
| 26 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD1_SPARE26: OTL error spare 26 | |
| 27 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD1_SPARE27: OTL error spare 27 | |
| 28 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD1_SPARE28: OTL error spare 28 | |
| 29 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD1_SPARE29: OTL error spare 29 | |
| 30 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD1_SPARE30: OTL error spare 30 | |
| 31 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD1_SPARE31: OTL error spare 31 | |
| 32:63 | RO | RO | constant=0b00000000000000000000000000000000 | |
| OTL Error Report Mask Register 1 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A37 (SCOM) 00000000134C00B8 (PAU_RING) | |||
| Name: | PAU3.OTL0.MISC.C_ERR_RPT_MASK1 | |||
| Constant(s): | ||||
| Comments: | OTL Error Report Mask Register 1 (c_err_rpt 1 mask) | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:31 | PAU3.OTL0.MISC.ERR_RPT1_MASK.LATC.L2(0:31) [00000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RO | RO | OTL_ERR_MASK100: OTL error mask 00 | |
| 1 | RO | RO | OTL_ERR_MASK101: OTL error mask 01 | |
| 2 | RO | RO | OTL_ERR_MASK102: OTL error mask 02 | |
| 3 | RO | RO | OTL_ERR_MASK103: OTL error mask 03 | |
| 4 | RO | RO | OTL_ERR_MASK104: OTL error mask 04 | |
| 5 | RO | RO | OTL_ERR_MASK105: OTL error mask 05 | |
| 6 | RO | RO | OTL_ERR_MASK106: OTL error mask 06 | |
| 7 | RO | RO | OTL_ERR_MASK107: OTL error mask 07 | |
| 8 | RO | RO | OTL_ERR_MASK108: OTL error mask 08 | |
| 9 | RO | RO | OTL_ERR_MASK109: OTL error mask 09 | |
| 10 | RO | RO | OTL_ERR_MASK110: OTL error mask 10 | |
| 11 | RO | RO | OTL_ERR_MASK111: OTL error mask 11 | |
| 12 | RO | RO | OTL_ERR_MASK112: OTL error mask 12 | |
| 13 | RO | RO | OTL_ERR_MASK113: OTL error mask 13 | |
| 14 | RO | RO | OTL_ERR_MASK114: OTL error mask 14 | |
| 15 | RO | RO | OTL_ERR_MASK115: OTL error mask 15 | |
| 16 | RO | RO | OTL_ERR_MASK116: OTL error mask 16 | |
| 17 | RO | RO | OTL_ERR_MASK117: OTL error mask 17 | |
| 18 | RO | RO | OTL_ERR_MASK118: OTL error mask 18 | |
| 19 | RO | RO | OTL_ERR_MASK119: OTL error mask 19 | |
| 20 | RO | RO | OTL_ERR_MASK120: OTL error mask 20 | |
| 21 | RO | RO | OTL_ERR_MASK121: OTL error mask 21 | |
| 22 | RO | RO | OTL_ERR_MASK122: OTL error mask 22 | |
| 23 | RO | RO | OTL_ERR_MASK123: OTL error mask 23 | |
| 24 | RO | RO | OTL_ERR_MASK124: OTL error mask 24 | |
| 25 | RO | RO | OTL_ERR_MASK125: OTL error mask 25 | |
| 26 | RO | RO | OTL_ERR_MASK126: OTL error mask 26 | |
| 27 | RO | RO | OTL_ERR_MASK127: OTL error mask 27 | |
| 28 | RO | RO | OTL_ERR_MASK128: OTL error mask 28 | |
| 29 | RO | RO | OTL_ERR_MASK129: OTL error mask 29 | |
| 30 | RO | RO | OTL_ERR_MASK130: OTL error mask 30 | |
| 31 | RO | RO | OTL_ERR_MASK131: OTL error mask 31 | |
| 32:63 | RO | RO | constant=0b00000000000000000000000000000000 | |
| OTL Configuration 2 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A38 (SCOM) 00000000134C00C0 (PAU_RING) | |||
| Name: | PAU3.OTL0.MISC.CONFIG_TX2 | |||
| Constant(s): | ||||
| Comments: | OTL Configuration 2 Register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:27 | PAU3.OTL0.MISC.CONFIG_TX2Q.LATC.L2(0:27) [0000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX | RWX | CONFIG_TX_SEND_EN: OTL TX Send Enable - Allows OTL TX to send out packets to AFU. When this bit is 0, OTL TX still accepts requests and responses from CQ and RXI as long as the buffer is not full. But these commands and responses will be held in TX until this bit becomes 1. HW will clear this send_en bit automatically when this OTL enters fence mode (i.e. when ctl_otl_fence_dx=1). | |
| 1:3 | RWX | RWX | CONFIG_TX_SPARE4: Spare config bits. | |
| 4:7 | RWX | RWX | CONFIG_VC1_THRESH1: VC1 threshold 1 = bit value, i.e., 0-15. CTL SM allocation behavior changes if VC1 queue exceeds this value. Flush value is 3. (VC1 threshold1=3) | |
| 8:11 | RWX | RWX | CONFIG_VC2_THRESH1: VC2 threshold 1 = bit value, i.e., 0-15. CTL SM allocation behavior changes if VC2 queue exceeds this value. Flush value is 3. (VC2 threshold1=3) | |
| 12:15 | RWX | RWX | CONFIG_VC3_THRESH1: VC3 threshold 1 = bit value, i.e., 0-15. CTL SM allocation behavior changes if VC3 queue exceeds this value. Flush value is 3. (VC3 threshold1=3) | |
| 16:19 | RWX | RWX | CONFIG_VC1_THRESH2: VC1 threshold 2 = (bit value x 4) + 3, i.e., 3,7,..,63. CTL SM allocation behavior changes if VC1 queue exceeds this value. Flush value is 7. (VC1 threshold2=31) | |
| 20:23 | RWX | RWX | CONFIG_VC2_THRESH2: VC2 threshold 2 = (bit value x 4) + 3, i.e., 3,7,..,63. CTL SM allocation behavior changes if VC2 queue exceeds this value. Flush value is 7. (VC2 threshold2=31) | |
| 24:27 | RWX | RWX | CONFIG_VC3_THRESH2: VC3 threshold 2 = (bit value x 4) + 3, i.e., 3,7,..,63. CTL SM allocation behavior changes if VC3 queue exceeds this value. Flush value is 7. (VC3 threshold2=31) | |
| 28:63 | RO | RO | constant=0b000000000000000000000000000000000000 | |
| OTL ERAT Hash Configuration Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A39 (SCOM) 00000000134C00C8 (PAU_RING) | |||
| Name: | PAU3.OTL0.MISC.CONFIG_ERAT_HASH | |||
| Constant(s): | ||||
| Comments: | OTL ERAT Hash Configuration Register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:59 | PAU3.OTL0.MISC.CONFIG_ERAT_HASH_Q_0_INST.LATC.L2(0:59) [000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:5 | RW | RW | CONFIG_OTL_ERAT_HASH_0: OTL ERAT HASH0 - hashed against actag(5:0) and pe_handle( 6) to generate xsl erat_index(0) (MSB) (flushes to 0x37) | |
| 6:11 | RW | RW | CONFIG_OTL_ERAT_HASH_1: OTL ERAT HASH1 - hashed against actag(5:0) and pe_handle( 7) to generate xsl erat_index(1) (flushes to 0x16) | |
| 12:17 | RW | RW | CONFIG_OTL_ERAT_HASH_2: OTL ERAT HASH2 - hashed against actag(5:0) and pe_handle( 8) to generate xsl erat_index(2) (flushes to 0x08) | |
| 18:23 | RW | RW | CONFIG_OTL_ERAT_HASH_3: OTL ERAT HASH3 - hashed against actag(5:0) and pe_handle( 9) to generate xsl erat_index(3) (flushes to 0x0d) | |
| 24:29 | RW | RW | CONFIG_OTL_ERAT_HASH_4: OTL ERAT HASH4 - hashed against actag(5:0) and pe_handle(10) to generate xsl erat_index(4) (flushes to 0x38) | |
| 30:35 | RW | RW | CONFIG_OTL_ERAT_HASH_5: OTL ERAT HASH5 - hashed against actag(5:0) and pe_handle(11) to generate xsl erat_index(5) (flushes to 0x0e) | |
| 36:41 | RW | RW | CONFIG_OTL_ERAT_HASH_6: OTL ERAT HASH6 - hashed against actag(5:0) and pe_handle(12) to generate xsl erat_index(6) (flushes to 0x0d) | |
| 42:47 | RW | RW | CONFIG_OTL_ERAT_HASH_7: OTL ERAT HASH7 - hashed against actag(5:0) and pe_handle(13) to generate xsl erat_index(7) (flushes to 0x1a) | |
| 48:53 | RW | RW | CONFIG_OTL_ERAT_HASH_8: OTL ERAT HASH8 - hashed against actag(5:0) and pe_handle(14) to generate xsl erat_index(8) (flushes to 0x21) | |
| 54:59 | RW | RW | CONFIG_OTL_ERAT_HASH_9: OTL ERAT HASH9 - hashed against actag(5:0) and pe_handle(15) to generate xsl erat_index(9) (LSB) (flushes to 0x36) | |
| 60:63 | RO | RO | constant=0b0000 | |
| OTL TXI Error Signature Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A3A (SCOM) 00000000134C00D0 (PAU_RING) | |||
| Name: | PAU3.OTL0.MISC.ERROR_SIG_TXI | |||
| Constant(s): | ||||
| Comments: | OTL TXI Error Signature Register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:7 | PAU3.OTL0.MISC.ERROR_SIG_TXIQ.LATC.L2(0:7) [00000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:7 | ROX | ROX | ERRSIGTXI_BAD_OPCODE: OTL TXI - bad opcode detected per c_err_rpt_hold1(16:17) | |
| 8:63 | RO | RO | constant=0b00000000000000000000000000000000000000000000000000000000 | |
| OTL HAPPI BAR0 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A3B (SCOM) 00000000134C00D8 (PAU_RING) | |||
| Name: | PAU3.OTL0.MISC.HAPPI_BAR0 | |||
| Constant(s): | ||||
| Comments: | OTL HAPPI BAR0 Register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.OTL0.MISC.HAPPI_BAR0_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_HAPPI_BAR0_ENABLE: Enable for this BAR (0=disabled, 1=enabled) (but only when config_otl_enable_happi=1, in networking mode, the enable is config_otl_enable_min | |
| 1:21 | RW | RW | CONFIG_HAPPI_BAR0_ADDR: BAR address HAPPI mode: Reg bits 1:21 used for masked compare of receive PA(50 downto 30) = Powerbus(13 to 33) = 1G address. Network mode: Reg bits 8:21 used for masked compare of received MEA(20:33) = Powerbus(20:33). | |
| 22:42 | RW | RW | CONFIG_HAPPI_BAR0_MASK: BAR mask - both modes | |
| 43:63 | RW | RW | CONFIG_HAPPI_BAR0_SUB: BAR substitute address / compare/mask extension Happi mode: Replaces unmasked compare bits 13:33 Network mode: reg bits 44:53 compare against MEA(34:43), reg bits 54:63 are mask for MEA(34:43) compare. | |
| OTL HAPPI BAR1 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A3C (SCOM) 00000000134C00E0 (PAU_RING) | |||
| Name: | PAU3.OTL0.MISC.HAPPI_BAR1 | |||
| Constant(s): | ||||
| Comments: | OTL HAPPI BAR1 Register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.OTL0.MISC.HAPPI_BAR1_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_HAPPI_BAR1_ENABLE: Enable for this BAR (0=disabled, 1=enabled) | |
| 1:21 | RW | RW | CONFIG_HAPPI_BAR1_ADDR: BAR address Happi mode: Used for masked compare of receive PA(50 downto 30) = Powerbus(13 to 33) = 1G address Network mode: reg bits 1:20 are used for MEA(0:19) when presenting the address to the XSL, replacing MEA(12:19) which came in off the OC link. | |
| 22:42 | RW | RW | CONFIG_HAPPI_BAR1_MASK: BAR mask (not used in Network Mode) | |
| 43:63 | RW | RW | CONFIG_HAPPI_BAR1_SUB: BAR substitute address (not used in Network Mode) Replaces unmasked compare bits. | |
| OTL HAPPI BAR2 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A3D (SCOM) 00000000134C00E8 (PAU_RING) | |||
| Name: | PAU3.OTL0.MISC.HAPPI_BAR2 | |||
| Constant(s): | ||||
| Comments: | OTL HAPPI BAR2 Register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.OTL0.MISC.HAPPI_BAR2_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_HAPPI_BAR2_ENABLE: Enable for this BAR (0=disabled, 1=enabled) | |
| 1:21 | RW | RW | CONFIG_HAPPI_BAR2_ADDR: BAR address Used for masked compare of receive PA(50 downto 30) = Powerbus(13 to 33) = 1G address | |
| 22:42 | RW | RW | CONFIG_HAPPI_BAR2_MASK: BAR mask | |
| 43:63 | RW | RW | CONFIG_HAPPI_BAR2_SUB: BAR substitute address Replaces unmasked compare bits | |
| OTL HAPPI BAR3 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A3E (SCOM) 00000000134C00F0 (PAU_RING) | |||
| Name: | PAU3.OTL0.MISC.HAPPI_BAR3 | |||
| Constant(s): | ||||
| Comments: | OTL HAPPI BAR3 Register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.OTL0.MISC.HAPPI_BAR3_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_HAPPI_BAR3_ENABLE: Enable for this BAR (0=disabled, 1=enabled) | |
| 1:21 | RW | RW | CONFIG_HAPPI_BAR3_ADDR: BAR address Used for masked compare of receive PA(50 downto 30) = Powerbus(13 to 33) = 1G address | |
| 22:42 | RW | RW | CONFIG_HAPPI_BAR3_MASK: BAR mask | |
| 43:63 | RW | RW | CONFIG_HAPPI_BAR3_SUB: BAR substitute address Replaces unmasked compare bits | |
| OTL Configuration 3 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A3F (SCOM) 00000000134C00F8 (PAU_RING) | |||
| Name: | PAU3.OTL0.MISC.CONFIG3 | |||
| Constant(s): | ||||
| Comments: | OTL Configuration 3 Register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:31 | PAU3.OTL0.MISC.CONFIG3_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_OTL_ENABLE_HAPPI: OTL enable HAPPI (0=disabled, 1=enabled) | |
| 1 | RW | RW | CONFIG_OTL_ENABLE_MIN: OTL enable Memory Inception Networking mode (0=disabled, 1=enabled). Received TL packets are converted to TLX packets per the Memory Incepted Networking protocol. This mode is requires the following modes to be disabled: config_otl_enable_4_0, config_otl_enable_5_0, and config_otl_enable_happi. | |
| 2 | RW | RW | CONFIG_OTL_ENABLE_HAPPI_ASYM: OTL enable HAPPI Async mode (0=disabled, 1=enabled). Outbound opcodes will be converted from TL form to TLX form. Intended for connecting to a P9 chip. | |
| 3 | RW | RW | CONFIG_OTL_DISABLE_STREAM_ORDERING: OTL disable stream ordering in HAPPI and MIN modes. Only affects ordering when config_otl_enable_happi or config_otl_enable_min are active. | |
| 4:31 | RW | RW | CONFIG_OTL_CONFIG3_SPARE: spare | |
| 32:63 | RO | RO | constant=0b00000000000000000000000000000000 | |
| OSL_DSISR | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A48 (SCOM) 00000000130C0000 (PAU_RING) | |||
| Name: | PAU3.OTL0.MISC.PSL_DSISR_AN | |||
| Constant(s): | ||||
| Comments: | OSL Data Storage Interrupt Status Register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 3 | PAU3.OTL0.MISC.PSL_DSISR_AN3Q.LATC.L2(0) [0] | |||
| 38 | PAU3.OTL0.MISC.PSL_DSISR_AN38Q.LATC.L2(0) [0] | |||
| 56:63 | PAU3.OTL0.MISC.PSL_DSISR_AN56Q.LATC.L2(56:63) [00000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:2 | RO | RO | constant=0b000 | |
| 3 | RO | RO | TF: Translation Fault - Set to 1 if the PSL has detected a translation fault. The cause of the translation fault is contained in OSL_DSISR[CO_RSP]. This bit is reset to 0 when the corresponding OSL_TFC Register is written. | |
| 4:37 | RO | RO | constant=0b0000000000000000000000000000000000 | |
| 38 | RO | RO | S: Translation fail for a write operation. Set to 1 if the access type was a write operation. | |
| 39:55 | RO | RO | constant=0b00000000000000000 | |
| 56:63 | RO | RO | CO_RSP: Checkout Response Status This field will contain the status byte returned by nMMU for an unsuccessful Checkout request. | |
| OSL_DAR | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A49 (SCOM) 00000000130C0008 (PAU_RING) | |||
| Name: | PAU3.OTL0.MISC.PSL_DAR_AN | |||
| Constant(s): | ||||
| Comments: | PS Checkout Effective Address Register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:51 | PAU3.OTL0.MISC.PSL_DAR_ANQ.LATC.L2(0:51) [0000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:51 | RO | RO | CO_EA: Effective Address 0:51 associated with the data segment or data storage interrupt | |
| 52:63 | RO | RO | constant=0b000000000000 | |
| OSL_TFC | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A4A (SCOM) 00000000130C0010 (PAU_RING) | |||
| Name: | PAU3.OTL0.MISC.PSL_TFC_AN | |||
| Constant(s): | ||||
| Comments: | OS Translation Fault Control Register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 28:31 | PAU3.OTL0.MISC.PSL_TFC_ANQ.LATC.L2(28:31) [0000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:27 | RO | RO | constant=0b0000000000000000000000000000 | |
| 28 | WO_1P | WO_1P | TFC_ACK: Does nothing. Resets to 0 if written to 1. | |
| 29 | RWX | RWX | C: Continue. Current translation fault is not resolved and must be retried at a later time. Note: This bit must be set to 1 to cause a xlate_done to be sent to the AFU with RespCode = 0010 (Retry Request) Note: bits 29:31 can only be written with a 1-hot value, or the results will be undefined. | |
| 30 | RWX | RWX | AE: Address error on the transaction caused the translation fault. Note: This bit must be set to 1 to cause a xlate_done to be sent to the AFU with RespCode = 1111 (Address Translation Error) | |
| 31 | RWX | RWX | R: Restarts the AFU transaction that caused the translation fault. Note: This bit must be set to 1 to cause a xlate_done to be sent to the AFU with RespCode = 0000 (Complete) | |
| 32:63 | RO | RO | constant=0b00000000000000000000000000000000 | |
| OSL_PEHandle | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A4B (SCOM) 00000000130C0018 (PAU_RING) | |||
| Name: | PAU3.OTL0.MISC.PSL_PEHANDLE_AN | |||
| Constant(s): | ||||
| Comments: | PE_Handle Process Element Handle | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 16:31 | PAU3.OTL0.MISC.PSL_PEHANDLE16_ANQ.LATC.L2(16:31) [0000000000000000] | |||
| 48:63 | PAU3.OTL0.MISC.PSL_PEHANDLE48_ANQ.LATC.L2(48:63) [0000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:15 | RO | RO | constant=0b0000000000000000 | |
| 16:31 | RO | RO | AFUTAG: Command tag. The command tag is a 16-bit AFU tag corresponding to the AFU command that caused the interrupt. | |
| 32:47 | RO | RO | constant=0b0000000000000000 | |
| 48:63 | RO | RO | PE_HANDLE: Process Element Handle. The process element handle is the 16-bit pointer to the corresponding process element. The leftmost bit indicates the brickid within the pair of bricks serviced by this OTL. | |
| OTL Configuration 0 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A50 (SCOM) 00000000134D0000 (PAU_RING) | |||
| Name: | PAU3.OTL1.MISC.CONFIG0 | |||
| Constant(s): | ||||
| Comments: | OTL Configuration 0 Register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.OTL1.MISC.CONFIG0_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_OTL_EN: OTL enable - turn on the transaction layer for this brick | |
| 1 | RW | RW | CONFIG_OTL_BLOCK_PE_HANDLE: OTL config - block the pe_handle from affecting the ERAT index | |
| 2:3 | RW | RW | CONFIG_OTL_BRICKID: OTL Brick ID | |
| 4:7 | RW | RW | CONFIG_OTL_PE_MASK: OTL PE_Mask - used to control the BDF+PASID => pe_handle conversion | |
| 8:10 | RW | RW | CONFIG_OTL_RXO_RR2: OTL RXO RR config bits - gives another arb slot to vc1,vc2,vc3 respectively. | |
| 11:31 | RW | RW | CONFIG_OTL_SPARE21: OTL spare config bits | |
| 32 | RW | RW | CONFIG_OTL_CFIFO0_LO_ENABLE1: OTL RXI Command FIFO 0 array error inject lo enable 1 | |
| 33 | RW | RW | CONFIG_OTL_CFIFO0_LO_ENABLE2: OTL RXI Command FIFO 0 array error inject lo enable 2 | |
| 34 | RW | RW | CONFIG_OTL_CFIFO0_HI_ENABLE1: OTL RXI Command FIFO 0 array error inject hi enable 1 | |
| 35 | RW | RW | CONFIG_OTL_CFIFO0_HI_ENABLE2: OTL RXI Command FIFO 0 array error inject hi enable 2 | |
| 36 | RW | RW | CONFIG_OTL_CFIFO1_ENABLE1: OTL RXI Command FIFO 1 array error inject enable 1 | |
| 37 | RW | RW | CONFIG_OTL_CFIFO1_ENABLE2: OTL RXI Command FIFO 1 array error inject enable 2 | |
| 38 | RW | RW | CONFIG_OTL_RFIFO_ENABLE1: OTL RXI Response FIFO array error inject enable 1 | |
| 39 | RW | RW | CONFIG_OTL_RFIFO_ENABLE2: OTL RXI Response FIFO array error inject enable 2 | |
| 40 | RW | RW | CONFIG_OTL_ACTAG_ENABLE1: OTL RXI acTag array error inject enable 1 | |
| 41 | RW | RW | CONFIG_OTL_ACTAG_ENABLE2: OTL RXI acTag array error inject enable 2 | |
| 42 | RW | RW | CONFIG_OTL_CDFIFO_LO_ENABLE1: OTL RXI Command Data FIFO array error inject lo enable 1 | |
| 43 | RW | RW | CONFIG_OTL_CDFIFO_LO_ENABLE2: OTL RXI Command Data FIFO array error inject lo enable 2 | |
| 44 | RW | RW | CONFIG_OTL_CDFIFO_HI_ENABLE1: OTL RXI Command Data FIFO array error inject hi enable 1 | |
| 45 | RW | RW | CONFIG_OTL_CDFIFO_HI_ENABLE2: OTL RXI Command Data FIFO array error inject hi enable 2 | |
| 46 | RW | RW | CONFIG_OTL_RDFIFO_LO_ENABLE1: OTL RXI Response Data FIFO array error inject lo enable 1 | |
| 47 | RW | RW | CONFIG_OTL_RDFIFO_LO_ENABLE2: OTL RXI Response Data FIFO array error inject lo enable 2 | |
| 48 | RW | RW | CONFIG_OTL_RDFIFO_HI_ENABLE1: OTL RXI Response Data FIFO array error inject hi enable 1 | |
| 49 | RW | RW | CONFIG_OTL_RDFIFO_HI_ENABLE2: OTL RXI Response Data FIFO array error inject hi enable 2 | |
| 50 | RW | RW | CONFIG_OTL_BLOCK_TID_OVERRIDE: OTL TID control - blocks the ability for the AFU to speecify the TID in a wake_host_thread command, and lets the XSL determine the TID as usual. | |
| 51 | RW | RW | CONFIG_OTL_ENABLE_4_0: OTL enable version 4 functions - when 1, enables the new 4.0-level functions listed in the OpenCAPI 4.0 specification. | |
| 52 | RW | RW | CONFIG_OTL_VC1FIFO_LO_ENABLE1: OTL RXI vc1 Command FIFO array error inject lo enable 1 | |
| 53 | RW | RW | CONFIG_OTL_VC1FIFO_LO_ENABLE2: OTL RXI vc1 Command FIFO array error inject lo enable 2 | |
| 54 | RW | RW | CONFIG_OTL_VC1FIFO_HI_ENABLE1: OTL RXI vc1 Command FIFO array error inject hi enable 1 | |
| 55 | RW | RW | CONFIG_OTL_VC1FIFO_HI_ENABLE2: OTL RXI vc1 Command FIFO array error inject hi enable 2 | |
| 56 | RW | RW | CONFIG_OTL_VC2FIFO_LO_ENABLE1: OTL RXI vc2 Command FIFO array error inject lo enable 1 | |
| 57 | RW | RW | CONFIG_OTL_VC2FIFO_LO_ENABLE2: OTL RXI vc2 Command FIFO array error inject lo enable 2 | |
| 58 | RW | RW | CONFIG_OTL_DCP2FIFO_LO_ENABLE1: OTL RXI dcp2 Data FIFO array error inject lo enable 1 | |
| 59 | RW | RW | CONFIG_OTL_DCP2FIFO_LO_ENABLE2: OTL RXI dcp2 Data FIFO array error inject lo enable 2 | |
| 60 | RW | RW | CONFIG_OTL_DCP2FIFO_HI_ENABLE1: OTL RXI dcp2 Data FIFO array error inject hi enable 1 | |
| 61 | RW | RW | CONFIG_OTL_DCP2FIFO_HI_ENABLE2: OTL RXI dcp2 Data FIFO array error inject hi enable 2 | |
| 62 | RW | RW | CONFIG_OTL_XLATE_RELEASE_HAS_NO_ITAG: OTL RXO. When 1, RXO is NOT expecting XSL to return an itag for an xlate_release request. Setting this bit contrary to the setting of xsl_gp_bits_dial(40) will cause unpredictable RXO misbehavior. | |
| 63 | RW | RW | CONFIG_OTL_ENABLE_5_0: OTL enable version 5 functions - when 1, enables the new 5.0-level functions listed in the OpenCAPI 5.0 specification. | |
| OTL Chicken Switch 0 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A51 (SCOM) 00000000134D0008 (PAU_RING) | |||
| Name: | PAU3.OTL1.MISC.CHKSW0 | |||
| Constant(s): | ||||
| Comments: | OTL Chicken Switch 0 Register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.OTL1.MISC.CHKSW0_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_INHIBIT_EN: OTL inhibit enable for clock gating | |
| 1:3 | RW | RW | CONFIG_INHIBIT_PACE_ENABLE_CMD: OTL RXI inhibit command pacing enable duration 0b000 disabled 0b001 8k+1 cycles 0b010 2k+1 cycles 0b011 512+1 cycles 0b100 128+1 cycles 0b101 32+1 cycles 0b110 8+1 cycles 0b111 2+1 cycles | |
| 4:6 | RW | RW | CONFIG_INHIBIT_PACE_DISABLE_CMD: OTL RXI inhibit command pacing disable duration 0b000 disabled 0b001 8k+1 cycles 0b010 2k+1 cycles 0b011 512+1 cycles 0b100 128+1 cycles 0b101 32+1 cycles 0b110 8+1 cycles 0b111 2+1 cycles | |
| 7:9 | RW | RW | CONFIG_INHIBIT_PACE_ENABLE_RESP: OTL RXI inhibit response pacing enable duration 0b000 disabled 0b001 8k+1 cycles 0b010 2k+1 cycles 0b011 512+1 cycles 0b100 128+1 cycles 0b101 32+1 cycles 0b110 8+1 cycles 0b111 2+1 cycles | |
| 10:12 | RW | RW | CONFIG_INHIBIT_PACE_DISABLE_RESP: OTL RXI inhibit response pacing disable duration 0b000 disabled 0b001 8k+1 cycles 0b010 2k+1 cycles 0b011 512+1 cycles 0b100 128+1 cycles 0b101 32+1 cycles 0b110 8+1 cycles 0b111 2+1 cycles | |
| 13 | RW | RW | CONFIG_OTL_RXO_SNGLTHRD_XSL_OPS: OTL RXO enable single-threaded ops to XSL | |
| 14 | RW | RW | CONFIG_OTL_RXO_DIS_EARLY_READ: OTL RXO disable early read after write to CTL | |
| 15 | RW | RW | CONFIG_OTL_RXO_HW407209_DISABLE: OTL RXO disable fence cleanup in rxo->rxi credit logic | |
| 16 | RW | RW | CONFIG_OTL_RXO_HW407443_DISABLE: OTL RXO disable fence cleanup in stages 3 and 4 of rxo pipe | |
| 17 | RW | RW | CONFIG_OTL_RXO_CONVERT_DOTN_TO_NORMAL: OTL RXO convert .n commands to normal commands at the RXO->XSL interface | |
| 18 | RW | RW | CONFIG_OTL_RXO_HW530141_DISABLE: OTL RXO disable earlier suspend_done during fence | |
| 19 | RW | RW | CONFIG_OTL_RXO_HW531488_DISABLE: OTL RXO disable fix for proper reset of sync ops during fence | |
| 20 | RW | RW | CONFIG_OTL_RXO_HW538558_DISABLE: OTL RXO disable fix for proper command ordering during suspend | |
| 21:31 | RW | RW | CONFIG_OTL_CHKSW00: OTL chicken switch spares | |
| 32:63 | RW | RW | CONFIG_OTL_CHKSW01: OTL chicken switch spares | |
| OTL PMU Control Register 0 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A52 (SCOM) 00000000134D0010 (PAU_RING) | |||
| Name: | PAU3.OTL1.MISC.PMU_CONTROL0 | |||
| Constant(s): | ||||
| Comments: | OTL Performance Monitor Control Register 0 For each of the 4 pmulet counters (counter0-3), select input event pair using 8 bit field config_pmu_events_c0-3. -- OTL RXI -- x00 array full vc3 fifo, 0 x01 array full vc0 fifo, 0 x02 array full vc1 fifo, 0 x03 array full vc2 fifo, 0 x04 array full dcp3 data fifo, 0 x05 array full dcp0 data fifo, 0 x06 array full dcp2 data fifo, 0 x07 waiting for otl rxo vc3 credit (does not include repeats for 256B ops), 0 x08 waiting for cq ctl vc0 credit, 0 x09 waiting for otl rxo vc1 credit (does not include repeats for 256B ops), 0 x0a waiting for otl rxo vc2 credit (does not include repeats for 256B ops), 0 x0b received control flit, any, 0 x0c received control flit, template x00, 0 x0d received control flit, template x01, 0 x0e received control flit, template x02, 0 x0f received control flit, template x03, 0 x10 received control flit, null, 0 x11 received control flit, not null (=ctlflit_commit_s4), 0 x12 received data flit (validated w/ ctlflit crc), 0 x13 received data flit (validated w/ ctlflit crc) w/ bdfi, 0 x14 received tl credit, any, 0 x15 received tl credit via null control flit, 0 x16 received tl credit via not null control flit, 0 x17 parsed any vc3 opcode, 0 x18 parsed any vc0 opcode, 0 x19 parsed any vc1 opcode, 0 x1a parsed any vc2 opcode, 0 x1b received DL CRC error, 0 x1c waiting for dcp3 data to arrive (does not include rxo cdfiford_pipeline_avail), 0 x1d waiting for dcp0 data to arrive (does not include rxo rdfiford_pipeline_avail), 0 x1e waiting for dcp2 data to arrive (does not include rxo dcp2fiford_pipeline_avail), 0 x1f latency, asserted 1 cycle per configured opcode, 0 x20 latency, asserted every cycle configured opcode is outstanding, 0 x21 received opcode specified by OTL PMU Control Register 1 config_pmu_c01_opcodeA/dlA and OTL PMU Control Register 2 config_pmu_c01_dcmaskA/dlA, 0 x22 received opcode specified by OTL PMU Control Register 1 config_pmu_c01_opcodeB/dlB and OTL PMU Control Register 2 config_pmu_c01_dcmaskB/dlB, 0 x23 received opcode specified by OTL PMU Control Register 1 config_pmu_c23_opcodeA/dlA and OTL PMU Control Register 2 config_pmu_c23_dcmaskA/dlA, 0 x24 received opcode specified by OTL PMU Control Register 1 config_pmu_c23_opcodeB/dlB and OTL PMU Control Register 2 config_pmu_c23_dcmaskB/dlB, 0 x25 HAPPI BAR0 match, 0 x26 HAPPI BAR1 match, 0 x27 HAPPI BAR2 match, 0 x28 HAPPI BAR3 match, 0 -- OTL RXO -- x60 filtered rxi->rxo opcodeA count, filtered rxi->rxo opcodeB count x61 filtered rxi->rxo ordered opcodeA count, filtered rxi->rxo ordered opcodeB count x62 filtered rxi->rxo opcodeA duration event, filtered rxi->rxo opcodeB duration event x63 filtered rxi->rxo opcodeA duration, filtered rxi->rxo opcodeB duration x64 filtered xsl->rxo response (c01 A filter), filtered xsl->rxo response (c01 B filter) x65 filtered rxo->txi op+resp using c01_opcodea+b, filtered rxo->txi op+resp using c23_opcodea+b NOTE: encode 65, event A: pmu_c01_opcode/mask A used for rxo->txi opcode+mask filter, and left half of pmu_c01_opcode/mask B used for response+mask filter NOTE: encode 65, event B: pmu_c23_opcode/mask A used for rxo->txi opcode+mask filter, and left half of pmu_c23_opcode/mask B used for response+mask filter x66 interrupt event, ops to xsl x67 interrupt duration, ops to xsl - credit wait duration x68 interrupt not posted - busy, ops to ctl x69 hashcam is full, ops to ctl - credit wait duration x6A cmd array >= 25% full, ops to ctl - stalled for any reason duration x6B cmd array >= 50% fulll, responses to xsl x6C cmd array >= 75% full, responses to xsl - credit wait duration x6D cmd array is full, responses to txi x6E pmu0/2=16B+byte_en moving to CQDAT // pmu1/3=byte_en to CQDat, responses to xsl - credit wait duration --> OTL PMU Control Register 0 event list continued under OTL PMU Control Register 1 (workaround for 5000 character figmunge limit) | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.OTL1.MISC.PMU_CONTROL0_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_PMU_ENABLE: OTL pmu enable - 1=clock gate enable | |
| 1 | RW | RW | CONFIG_PMU_RESETMODE: OTL pmu resetmode - 0=reset counters on pmu_control0 register read, 1=reset counters on counter register write | |
| 2 | RW | RW | CONFIG_PMU_FREEZEMODE: OTL pmu freezemode - 1=freeze counters on pmulet freeze out asserted | |
| 3 | RW | RW | CONFIG_PMU_DISABLE_PMISC: OTL pmu disable_pmisc - 0=reset counters on powerbus pmu_enable rising edge, freeze counters if pmu_enable not asserted | |
| 4 | RW | RW | CONFIG_PMU_PMISC_MODE: OTL pmu pmisc_mode - 1=reset counters on powerbus pmu_enable rising edge | |
| 5:7 | RW | RW | CONFIG_PMU_CASCADE: OTL pmu cascade - 001=c0_to_c1, 011=c1_to_c2, 011=c2_to_c3, 101=c1_to_c0, 110=c2_to_c1, 111=c3_to_c2 | |
| 8:9 | RW | RW | CONFIG_PMU_PRESCALE_C0: OTL pmu prescale_c0 - 00=20-bit, 01=16-bit, 10=8-bit, 11=4-bit | |
| 10:11 | RW | RW | CONFIG_PMU_PRESCALE_C1: OTL pmu prescale_c1 - 00=20-bit, 01=16-bit, 10=8-bit, 11=4-bit | |
| 12:13 | RW | RW | CONFIG_PMU_PRESCALE_C2: OTL pmu prescale_c2 - 00=20-bit, 01=16-bit, 10=8-bit, 11=4-bit | |
| 14:15 | RW | RW | CONFIG_PMU_PRESCALE_C3: OTL pmu prescale_c3 - 00=20-bit, 01=16-bit, 10=8-bit, 11=4-bit | |
| 16:17 | RW | RW | CONFIG_PMU_OPERATION_C0: OTL pmu operation_c0 - 00=count c0_events0, 01=count c0_events1, 10=count c0_events0+c0_events1, 11=count cycles | |
| 18:19 | RW | RW | CONFIG_PMU_OPERATION_C1: OTL pmu operation_c1 - 00=count c1_events0, 01=count c1_events1, 10=count c1_events0+c1_events1, 11=count cycles | |
| 20:21 | RW | RW | CONFIG_PMU_OPERATION_C2: OTL pmu operation_c2 - 00=count c2_events0, 01=count c2_events1, 10=count c2_events0+c2_events1, 11=count cycles | |
| 22:23 | RW | RW | CONFIG_PMU_OPERATION_C3: OTL pmu operation_c3 - 00=count c3_events0, 01=count c3_events1, 10=count c3_events0+c3_events1, 11=count cycles | |
| 24:31 | RW | RW | CONFIG_PMU_EVENTS_C0: OTL pmu events c0 - selects 2 bit events to input to pmulet counter 0 | |
| 32:39 | RW | RW | CONFIG_PMU_EVENTS_C1: OTL pmu events c1 - selects 2 bit events to input to pmulet counter 1 | |
| 40:47 | RW | RW | CONFIG_PMU_EVENTS_C2: OTL pmu events c2 - selects 2 bit events to input to pmulet counter 2 | |
| 48:55 | RW | RW | CONFIG_PMU_EVENTS_C3: OTL pmu events c3 - selects 2 bit events to input to pmulet counter 3 | |
| 56:63 | RW | RW | CONFIG_PMU_RESERVED0: Reserved | |
| OTL PMU Control Register 1 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A53 (SCOM) 00000000134D0018 (PAU_RING) | |||
| Name: | PAU3.OTL1.MISC.PMU_CONTROL1 | |||
| Constant(s): | ||||
| Comments: | OTL Performance Monitor Control Register 1 - opcode/dLength match filter hit = signal_valid and and_reduce((signal_of_interest xnor match_opcode) or match_dc_mask) --> OTL PMU Control Register 0 event list continued For each of the 4 pmulet counters (counter0-3), select input event pair using 8 bit field config_pmu_events_c0-3. -- OTL TXO -- x80 tied to 0, tied to 1 -- tied to 1 might not be necessary. Can put operation_cX=11 instead. x81 control flit sent, data flit sent x82 data flit for opcodeA sent, data flit for opcodeB sent x83 rate limit nop flit sent, other nop flit sent x84 temp0 flit sent, temp1 flit sent x85 temp2 flit sent, temp3 flit sent x86 nop flit with return_tlx_credits sent, non-nop flit with return_tlx_credits sent x87: reserved x88 temp0 requests sent, temp0 responses sent x89 temp0 opcodeA sent, temp0 opcodeB sent x8a temp1 requests sent, temp1 responses sent x8b temp1 opcodeA sent, temp1 opcodeB sent x8c tied to 0, temp2 responses sent x8d temp2 opcodeA sent, temp2 opcodeB sent x8e temp3 requests sent, temp3 responses sent x8f temp3 opcodeA sent, temp3 opcodeB sent x90 requests with dL=64B sent, responses with dL=64B sent x91 requests with dL=128B sent, responses with dL=128B sent x92 requests sent, responses sent x93: reserved x94 opcode A with dL=64B sent, opcode B with dL=64B sent x95 opcode A with dL=128B sent, opcode B with dL=128B sent x96 opcode A sent, opcode B sent x97: reserved x98 At least one response had to wait for VC0 credits, At least one response had to wait for DCP0 credits x99 VC0 totally exhausted and blocked responses, DCP0 totally exhausted and blocked responses x9A At least one resquest had to wait for VC1 credits, At least one request had to wait for DCP1 credits x9B VC1 totally exhausted and blocked requests, DCP1 totally exhausted and blocked requests x9C contol flit stalled due to insufficient DL credits, data flit stalled due to insufficient DL credits x9D control flit ignored by build, data flit stalled due to insufficient DL credits x9E At least one rquest had to wait for VC2 credits, At least one request had to wait for DCP1 credits (VC2 uses no data) x9F VC2 totally exhausted and blocked requests, DCP1 totally exhausted and blocked VC1 requests (VC2 uses no data) Others: reserved NOTE: opcodeA and opcodeB are specified in the pmu_control1 register. opcodeA/B cannot be used for mathing return_tlx_credits. Use dedicated counter events instead. | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.OTL1.MISC.PMU_CONTROL1_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:7 | RW | RW | CONFIG_PMU_C01_OPCODEA: OTL pmu match opcode A : optional opcode for counter 0/1 to filter out OCAPI requests/responses to count. | |
| 8:15 | RW | RW | CONFIG_PMU_C01_OPCODEB: OTL pmu match opcode B : optional opcode for counter 0/1 to filter out OCAPI requests/responses to count. | |
| 16:23 | RW | RW | CONFIG_PMU_C23_OPCODEA: OTL pmu match opcode A : optional opcode for counter 2/3 to filter out OCAPI requests/responses to count. | |
| 24:31 | RW | RW | CONFIG_PMU_C23_OPCODEB: OTL pmu match opcode B : optional opcode for counter 2/3 to filter out OCAPI requests/responses to count. | |
| 32:33 | RW | RW | CONFIG_PMU_C01_DLA: OTL pmu match opcode A dLength : optional opcode dLength for counter 0/1 to filter out OCAPI requests/responses to count. | |
| 34:35 | RW | RW | CONFIG_PMU_C01_DLB: OTL pmu match opcode B dLength : optional opcode dLength for counter 0/1 to filter out OCAPI requests/responses to count. | |
| 36:37 | RW | RW | CONFIG_PMU_C23_DLA: OTL pmu match opcode A dLength : optional opcode dLength for counter 2/3 to filter out OCAPI requests/responses to count. | |
| 38:39 | RW | RW | CONFIG_PMU_C23_DLB: OTL pmu match opcode B dLength : optional opcode dLength for counter 2/3 to filter out OCAPI requests/responses to count. | |
| 40:47 | RW | RW | CONFIG_PMU_OPCODE_LATENCY: OTL pmu match opcode latency : opcode to filter out AP commands to count PAU latency. | |
| 48:63 | RW | RW | CONFIG_PMU_RESERVED1: Reserved | |
| OTL PMU Control Register 2 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A54 (SCOM) 00000000134D0020 (PAU_RING) | |||
| Name: | PAU3.OTL1.MISC.PMU_CONTROL2 | |||
| Constant(s): | ||||
| Comments: | OTL Performance Monitor Control Register 2 - opcode/dLength dc mask | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.OTL1.MISC.PMU_CONTROL2_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:7 | RW | RW | CONFIG_PMU_C01_DCMASKA: OTL pmu DC mask A : optional don't care mask for counter 0/1 to filter out OCAPI requests/responses to count. | |
| 8:15 | RW | RW | CONFIG_PMU_C01_DCMASKB: OTL pmu DC mask B : optional don't care mask for counter 0/1 to filter out OCAPI requests/responses to count. | |
| 16:23 | RW | RW | CONFIG_PMU_C23_DCMASKA: OTL pmu DC mask A : optional don't care mask for counter 2/3 to filter out OCAPI requests/responses to count. | |
| 24:31 | RW | RW | CONFIG_PMU_C23_DCMASKB: OTL pmu DC mask B : optional don't care mask for counter 2/3 to filter out OCAPI requests/responses to count. | |
| 32:33 | RW | RW | CONFIG_PMU_C01_DCMASKDLA: OTL pmu DC mask dLength A : optional don't care mask for counter 0/1 to filter out OCAPI requests/responses to count. | |
| 34:35 | RW | RW | CONFIG_PMU_C01_DCMASKDLB: OTL pmu DC mask dLength B : optional don't care mask for counter 0/1 to filter out OCAPI requests/responses to count. | |
| 36:37 | RW | RW | CONFIG_PMU_C23_DCMASKDLA: OTL pmu DC mask dLength A : optional don't care mask for counter 2/3 to filter out OCAPI requests/responses to count. | |
| 38:39 | RW | RW | CONFIG_PMU_C23_DCMASKDLB: OTL pmu DC mask dLength B : optional don't care mask for counter 2/3 to filter out OCAPI requests/responses to count. | |
| 40:47 | RW | RW | CONFIG_PMU_DCMASK_LATENCY: unused - spare config bits. | |
| 48:63 | RW | RW | CONFIG_PMU_RESERVED2: Reserved | |
| OTL PMU Count Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A55 (SCOM) 00000000134D0028 (PAU_RING) | |||
| Name: | PAU3.OTL1.MISC.PMU_COUNT | |||
| Constant(s): | ||||
| Comments: | OTL Performance Monitor Count Register (4x16b) | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:15 | PAU3.OTL1.MISC.PMLET.COUNTER0_CNT_Q_0_INST.LATC.L2(0:15) [0000000000000000] | |||
| 16:31 | PAU3.OTL1.MISC.PMLET.COUNTER1_CNT_Q_0_INST.LATC.L2(0:15) [0000000000000000] | |||
| 32:47 | PAU3.OTL1.MISC.PMLET.COUNTER2_CNT_Q_0_INST.LATC.L2(0:15) [0000000000000000] | |||
| 48:63 | PAU3.OTL1.MISC.PMLET.COUNTER3_CNT_Q_0_INST.LATC.L2(0:15) [0000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:15 | ROX | ROX | CONFIG_PMU_COUNT0: OTL pmu count 0 | |
| 16:31 | ROX | ROX | CONFIG_PMU_COUNT1: OTL pmu count 1 | |
| 32:47 | ROX | ROX | CONFIG_PMU_COUNT2: OTL pmu count 2 | |
| 48:63 | ROX | ROX | CONFIG_PMU_COUNT3: OTL pmu count 3 | |
| OTL Error Report Register 0 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A56 (SCOM) 00000000134D0030 (PAU_RING) | |||
| Name: | PAU3.OTL1.MISC.C_ERR_RPT_HOLD0 | |||
| Constant(s): | ||||
| Comments: | OTL Error Report Register 0 (c_err_rpt 0 hold) | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.OTL1.MISC.ERR_RPT0.HOLD_LATCH_INST.HOLD.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_TL_CRD_OVF: OTL TL credit counter overflow caused by return_tl_credits. | |
| 1 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_ACTAG_IDX: OTL RXI acTag specified in a command is outside the configured specification set. | |
| 2 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_ACTAG_INV: OTL RXI acTag specified in the command points to an invalid entry. | |
| 3 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_OPC_RSVD: OTL RXI reserved opcode used. | |
| 4 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_RTC_POS: OTL RXI return_tl_credit command found outside slot0 | |
| 5 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_TMPL: OTL RXI bad opcode and template combination. | |
| 6 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_TMPL_UNS: OTL RXI unsupported template format. | |
| 7 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_TMPL_X00: OTL RXI bad template x00 format. | |
| 8 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_CTLFLIT_OVERRUN: OTL RXI control flit overrun. | |
| 9 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_UNEXPECTED_DATA_FLIT: OTL RXI unexpected data flit. | |
| 10 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_LINK_DOWN: OTL RXI DL link down. | |
| 11 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_BAD_DATA_RECEIVED_CMD: OTL RXI bad data received on command. | |
| 12 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_BAD_DATA_RECEIVED_RESP: OTL RXI bad data received on response. | |
| 13 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_RESPONSE_NOT_ALLOWED: OTL RXI AP response not allowed (CAPPTag not recognized). | |
| 14 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_MISC_PERR: OTL MISC state bit parity error. | |
| 15 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_TXO_PERR: OTL TXO state bit parity error. | |
| 16 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_PERR_FRMD: OTL RXI parity error on frame data. | |
| 17 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_PERR_FRMC: OTL RXI parity error on frame control signals. | |
| 18 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_TXO_CBUF_CE: OTL TX command buffer ECC CE. | |
| 19 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_TXO_CBUF_UE: OTL TX command buffer ECC UE. | |
| 20 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_TXI_DBUF_CE: OTL TX ECC CE on CQ buffer read data. | |
| 21 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_TXI_DBUF_UE: OTL TX ECC UE on CQ buffer read data. | |
| 22 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_CDFIFO_LO_CE: OTL RXI command data fifo ECC CE, lo bits 0:63. | |
| 23 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_CDFIFO_LO_UE: OTL RXI command data fifo ECC UE, lo bits 0:63. | |
| 24 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_CDFIFO_HI_CE: OTL RXI command data fifo ECC CE, hi bits 64:127. | |
| 25 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_CDFIFO_HI_UE: OTL RXI command data fifo ECC UE, hi bits 64:127. | |
| 26 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_RDFIFO_LO_CE: OTL RXI response data fifo ECC CE, lo bits 0:63. | |
| 27 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_RDFIFO_LO_UE: OTL RXI response data fifo ECC UE, lo bits 0:63. | |
| 28 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_RDFIFO_HI_CE: OTL RXI response data fifo ECC CE, hi bits 64:127. | |
| 29 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_RDFIFO_HI_UE: OTL RXI response data fifo ECC UE, hi bits 64:127. | |
| 30 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_CFIFO0_LO_CE: OTL RXI command fifo0 ECC CE, lo bits 0:63. | |
| 31 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_CFIFO0_LO_UE: OTL RXI command fifo0 ECC UE, lo bits 0:63. | |
| 32 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_CFIFO0_HI_CE: OTL RXI command fifo0 ECC CE, hi bits 64:127. | |
| 33 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_CFIFO0_HI_UE: OTL RXI command fifo0 ECC UE, hi bits 64:127. | |
| 34 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_CFIFO1_CE: OTL RXI command fifo1 ECC CE. | |
| 35 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_CFIFO1_UE: OTL RXI command fifo1 ECC UE. | |
| 36 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_RFIFO_CE: OTL RXI response fifo ECC CE. | |
| 37 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_RFIFO_UE: OTL RXI response fifo ECC UE. | |
| 38 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_ACTAG_CE: OTL RXI acTag ECC CE. | |
| 39 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_ACTAG_UE: OTL RXI acTag ECC UE. | |
| 40 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXO_SBE11: OTL RXO Cmd1 Array lo bits SBE. | |
| 41 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXO_UE11: OTL RXO Cmd1 Array lo bits UE. | |
| 42 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXO_SBE12: OTL RXO Cmd1 Array hi bits SBE (byte enable field). | |
| 43 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXO_UE12: OTL RXO Cmd1 Array hi bits UE (byte enable field). | |
| 44 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXO_SBE2: OTL RXO Cmd2 Array SBE. | |
| 45 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXO_UE2: OTL RXO Cmd2 Array UE. | |
| 46 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXO_ILLEGAL_BDF_PASID_ERROR: OTL RXO illegal BDF or PASID error. | |
| 47 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXO_BAD_PE_HANDLE_ERROR: OTL RXO bad pe_handle error. | |
| 48 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXO_OPCODE_VIOLATION_ERROR: OTL RXO opcode violation. | |
| 49 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXO_0B_WR_VIOLATION_ERROR: OTL RXO 0B write detected. | |
| 50 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXO_PL_VIOLATION_INTRP_REQ_D: OTL RXO intrp_req.d pLength violation. | |
| 51 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXO_HASHCAM_DECR_ERROR: OTL RXO hashcam decrement error - response missed the cam. | |
| 52 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXO_HASHCAM_OVERFLOW_ERROR: OTL RXO hashcam overflow error - too many ops received from RXI. | |
| 53 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXO_HASHCAM_UNDERFLOW_ERROR: OTL RXO hashcam underflow error - logic fault. | |
| 54 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXO_CMD_ARRAY_OVERFLOW: OTL RXO command array overflow - too many ops received from RXI. | |
| 55 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXO_ARB_S2_POSTED_WRT_FAIL: OTL RXO arb s2 posted wrt fail - attempted posted write without having write permissions. | |
| 56 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXO_DAT_ARY_CE: OTL RXO data array correctable error. | |
| 57 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXO_DAT_ARY_UE: OTL RXO data array uncorrectable error. | |
| 58 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_CFIFO_OVERRUN: OTL RX command fifo overrun. | |
| 59 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_RFIFO_OVERRUN: OTL RX response fifo overrun. | |
| 60 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_CDFIFO_OVERRUN: OTL RX command data fifo overrun. | |
| 61 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_RDFIFO_OVERRUN: OTL RX response data fifo overrun. | |
| 62 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_DRL_RANGE: OTL RXI control flit data run length invalid. | |
| 63 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_PKTFIELDRSVDVAL_DLEQ0: OTL RXI opcode utilizing dLength specifies dL=0b00 or other invalid dL (hw539630). | |
| OTL Error Report Mask Register 0 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A57 (SCOM) 00000000134D0038 (PAU_RING) | |||
| Name: | PAU3.OTL1.MISC.C_ERR_RPT_MASK0 | |||
| Constant(s): | ||||
| Comments: | OTL Error Report Mask Register 0 (c_err_rpt 0 mask) | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.OTL1.MISC.ERR_RPT0_MASK.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RO | RO | OTL_ERR_MASK000: OTL error mask 0 00 | |
| 1 | RO | RO | OTL_ERR_MASK001: OTL error mask 0 01 | |
| 2 | RO | RO | OTL_ERR_MASK002: OTL error mask 0 02 | |
| 3 | RO | RO | OTL_ERR_MASK003: OTL error mask 0 03 | |
| 4 | RO | RO | OTL_ERR_MASK004: OTL error mask 0 04 | |
| 5 | RO | RO | OTL_ERR_MASK005: OTL error mask 0 05 | |
| 6 | RO | RO | OTL_ERR_MASK006: OTL error mask 0 06 | |
| 7 | RO | RO | OTL_ERR_MASK007: OTL error mask 0 07 | |
| 8 | RO | RO | OTL_ERR_MASK008: OTL error mask 0 08 | |
| 9 | RO | RO | OTL_ERR_MASK009: OTL error mask 0 09 | |
| 10 | RO | RO | OTL_ERR_MASK010: OTL error mask 0 10 | |
| 11 | RO | RO | OTL_ERR_MASK011: OTL error mask 0 11 | |
| 12 | RO | RO | OTL_ERR_MASK012: OTL error mask 0 12 | |
| 13 | RO | RO | OTL_ERR_MASK013: OTL error mask 0 13 | |
| 14 | RO | RO | OTL_ERR_MASK014: OTL error mask 0 14 | |
| 15 | RO | RO | OTL_ERR_MASK015: OTL error mask 0 15 | |
| 16 | RO | RO | OTL_ERR_MASK016: OTL error mask 0 16 | |
| 17 | RO | RO | OTL_ERR_MASK017: OTL error mask 0 17 | |
| 18 | RO | RO | OTL_ERR_MASK018: OTL error mask 0 18 | |
| 19 | RO | RO | OTL_ERR_MASK019: OTL error mask 0 19 | |
| 20 | RO | RO | OTL_ERR_MASK020: OTL error mask 0 20 | |
| 21 | RO | RO | OTL_ERR_MASK021: OTL error mask 0 21 | |
| 22 | RO | RO | OTL_ERR_MASK022: OTL error mask 0 22 | |
| 23 | RO | RO | OTL_ERR_MASK023: OTL error mask 0 23 | |
| 24 | RO | RO | OTL_ERR_MASK024: OTL error mask 0 24 | |
| 25 | RO | RO | OTL_ERR_MASK025: OTL error mask 0 25 | |
| 26 | RO | RO | OTL_ERR_MASK026: OTL error mask 0 26 | |
| 27 | RO | RO | OTL_ERR_MASK027: OTL error mask 0 27 | |
| 28 | RO | RO | OTL_ERR_MASK028: OTL error mask 0 28 | |
| 29 | RO | RO | OTL_ERR_MASK029: OTL error mask 0 29 | |
| 30 | RO | RO | OTL_ERR_MASK030: OTL error mask 0 30 | |
| 31 | RO | RO | OTL_ERR_MASK031: OTL error mask 0 31 | |
| 32 | RO | RO | OTL_ERR_MASK032: OTL error mask 0 32 | |
| 33 | RO | RO | OTL_ERR_MASK033: OTL error mask 0 33 | |
| 34 | RO | RO | OTL_ERR_MASK034: OTL error mask 0 34 | |
| 35 | RO | RO | OTL_ERR_MASK035: OTL error mask 0 35 | |
| 36 | RO | RO | OTL_ERR_MASK036: OTL error mask 0 36 | |
| 37 | RO | RO | OTL_ERR_MASK037: OTL error mask 0 37 | |
| 38 | RO | RO | OTL_ERR_MASK038: OTL error mask 0 38 | |
| 39 | RO | RO | OTL_ERR_MASK039: OTL error mask 0 39 | |
| 40 | RO | RO | OTL_ERR_MASK040: OTL error mask 0 40 | |
| 41 | RO | RO | OTL_ERR_MASK041: OTL error mask 0 41 | |
| 42 | RO | RO | OTL_ERR_MASK042: OTL error mask 0 42 | |
| 43 | RO | RO | OTL_ERR_MASK043: OTL error mask 0 43 | |
| 44 | RO | RO | OTL_ERR_MASK044: OTL error mask 0 44 | |
| 45 | RO | RO | OTL_ERR_MASK045: OTL error mask 0 45 | |
| 46 | RO | RO | OTL_ERR_MASK046: OTL error mask 0 46 | |
| 47 | RO | RO | OTL_ERR_MASK047: OTL error mask 0 47 | |
| 48 | RO | RO | OTL_ERR_MASK048: OTL error mask 0 48 | |
| 49 | RO | RO | OTL_ERR_MASK049: OTL error mask 0 49 | |
| 50 | RO | RO | OTL_ERR_MASK050: OTL error mask 0 50 | |
| 51 | RO | RO | OTL_ERR_MASK051: OTL error mask 0 51 | |
| 52 | RO | RO | OTL_ERR_MASK052: OTL error mask 0 52 | |
| 53 | RO | RO | OTL_ERR_MASK053: OTL error mask 0 53 | |
| 54 | RO | RO | OTL_ERR_MASK054: OTL error mask 0 54 | |
| 55 | RO | RO | OTL_ERR_MASK055: OTL error mask 0 55 | |
| 56 | RO | RO | OTL_ERR_MASK056: OTL error mask 0 56 | |
| 57 | RO | RO | OTL_ERR_MASK057: OTL error mask 0 57 | |
| 58 | RO | RO | OTL_ERR_MASK058: OTL error mask 0 58 | |
| 59 | RO | RO | OTL_ERR_MASK059: OTL error mask 0 59 | |
| 60 | RO | RO | OTL_ERR_MASK060: OTL error mask 0 60 | |
| 61 | RO | RO | OTL_ERR_MASK061: OTL error mask 0 61 | |
| 62 | RO | RO | OTL_ERR_MASK062: OTL error mask 0 62 | |
| 63 | RO | RO | OTL_ERR_MASK063: OTL error mask 0 63 | |
| Debug Config 0 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A58 (SCOM) 00000000134D0040 (PAU_RING) | |||
| Name: | PAU3.OTL1.MISC.CONFIG_DEBUG0 | |||
| Constant(s): | ||||
| Comments: | Debug Config register 0 Selects which bits to route to the debug 0 bus output. There are total 11 of 5 bit field to control what to output each byte pos on the debug 0 bus. The 5 bit field selects one of the following 20 inputs: 00000b: pass_d0: debug bus 0 input passthrough 00001b: pass_d1: debug bus 1 input passthrough 00010b: local0: local trace input group 0 00011b: local1: local trace input group 1 00100b: local2: local trace input group 2 00101b: local3: local trace input group 3 00110b: local4: local trace input group 4 00111b: local5: local trace input group 5 01000b: local6: local trace input group 6 01001b: local7: local trace input group 7 10000b: pass_d0_rot: debug bus 0 input passthrough, rotated by 8 bits 10001b: pass_d1_rot: debug bus 1 input passthrough, rotated by 16 bits 10010b: local0_rot: local trace input group 0, rotated by 24 bits 10011b: local1_rot: local trace input group 1, rotated by 32 bits 10100b: local2_rot: local trace input group 2, rotated by 40 bits 10101b: local3_rot: local trace input group 3, rotated by 48 bits 10110b: local4_rot: local trace input group 4, rotated by 56 bits 10111b: local5_rot: local trace input group 5, rotated by 64 bits 11000b: local6_rot: local trace input group 6, rotated by 72 bits 11001b: local7_rot: local trace input group 7, rotated by 80 bits others: reserved. | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.OTL1.MISC.CONFIG_DEBUG0_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:4 | RW | RW | CONFIG_DEBUG0_BYTE0: 5b select for byte 0 of output bus 0 | |
| 5:9 | RW | RW | CONFIG_DEBUG0_BYTE1: 5b select for byte 1 of output bus 0 | |
| 10:14 | RW | RW | CONFIG_DEBUG0_BYTE2: 5b select for byte 2 of output bus 0 | |
| 15:19 | RW | RW | CONFIG_DEBUG0_BYTE3: 5b select for byte 3 of output bus 0 | |
| 20:24 | RW | RW | CONFIG_DEBUG0_BYTE4: 5b select for byte 4 of output bus 0 | |
| 25:29 | RW | RW | CONFIG_DEBUG0_BYTE5: 5b select for byte 5 of output bus 0 | |
| 30:34 | RW | RW | CONFIG_DEBUG0_BYTE6: 5b select for byte 6 of output bus 0 | |
| 35:39 | RW | RW | CONFIG_DEBUG0_BYTE7: 5b select for byte 7 of output bus 0 | |
| 40:44 | RW | RW | CONFIG_DEBUG0_BYTE8: 5b select for byte 8 of output bus 0 | |
| 45:49 | RW | RW | CONFIG_DEBUG0_BYTE9: 5b select for byte 9 of output bus 0 | |
| 50:54 | RW | RW | CONFIG_DEBUG0_BYTE10: 5b select for byte 10 of output bus 0 | |
| 55:62 | RW | RW | CONFIG_DEBUG0_RESERVED: Reserved | |
| 63 | RW | RW | CONFIG_DEBUG_ACT: Clock activate OTL macro debug logic | |
| Debug Config 1 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A59 (SCOM) 00000000134D0048 (PAU_RING) | |||
| Name: | PAU3.OTL1.MISC.CONFIG_DEBUG1 | |||
| Constant(s): | ||||
| Comments: | Debug Config register 1 Selects which bits to route to the debug 1 bus output. There are total 11 of 5 bit field to control what to output each byte pos on the debug 1 bus. The 5 bit field selects one of the following 20 inputs: 00000b: pass_d0: debug bus 0 input passthrough 00001b: pass_d1: debug bus 1 input passthrough 00010b: local0: local trace input group 0 00011b: local1: local trace input group 1 00100b: local2: local trace input group 2 00101b: local3: local trace input group 3 00110b: local4: local trace input group 4 00111b: local5: local trace input group 5 01000b: local6: local trace input group 6 01001b: local7: local trace input group 7 10000b: pass_d0_rot: debug bus 0 input passthrough, rotated by 8 bits 10001b: pass_d1_rot: debug bus 1 input passthrough, rotated by 16 bits 10010b: local0_rot: local trace input group 0, rotated by 24 bits 10011b: local1_rot: local trace input group 1, rotated by 32 bits 10100b: local2_rot: local trace input group 2, rotated by 40 bits 10101b: local3_rot: local trace input group 3, rotated by 48 bits 10110b: local4_rot: local trace input group 4, rotated by 56 bits 10111b: local5_rot: local trace input group 5, rotated by 64 bits 11000b: local6_rot: local trace input group 6, rotated by 72 bits 11001b: local7_rot: local trace input group 7, rotated by 80 bits others: reserved. | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.OTL1.MISC.CONFIG_DEBUG1_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:4 | RW | RW | CONFIG_DEBUG1_BYTE0: 5b select for byte 0 of output bus 1 | |
| 5:9 | RW | RW | CONFIG_DEBUG1_BYTE1: 5b select for byte 1 of output bus 1 | |
| 10:14 | RW | RW | CONFIG_DEBUG1_BYTE2: 5b select for byte 2 of output bus 1 | |
| 15:19 | RW | RW | CONFIG_DEBUG1_BYTE3: 5b select for byte 3 of output bus 1 | |
| 20:24 | RW | RW | CONFIG_DEBUG1_BYTE4: 5b select for byte 4 of output bus 1 | |
| 25:29 | RW | RW | CONFIG_DEBUG1_BYTE5: 5b select for byte 5 of output bus 1 | |
| 30:34 | RW | RW | CONFIG_DEBUG1_BYTE6: 5b select for byte 6 of output bus 1 | |
| 35:39 | RW | RW | CONFIG_DEBUG1_BYTE7: 5b select for byte 7 of output bus 1 | |
| 40:44 | RW | RW | CONFIG_DEBUG1_BYTE8: 5b select for byte 8 of output bus 1 | |
| 45:49 | RW | RW | CONFIG_DEBUG1_BYTE9: 5b select for byte 9 of output bus 1 | |
| 50:54 | RW | RW | CONFIG_DEBUG1_BYTE10: 5b select for byte 10 of output bus 1 | |
| 55:63 | RW | RW | CONFIG_DEBUG1_RESERVED: Reserved | |
| TLX Credit Configuration | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A5A (SCOM) 00000000134D0050 (PAU_RING) | |||
| Name: | PAU3.OTL1.MISC.CONFIG_TLX_CREDITS | |||
| Constant(s): | ||||
| Comments: | OTL TLX Credit Configuration Register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.OTL1.MISC.CONFIG_TLX_CREDITS_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:7 | RW | RW | CONFIG_TLX_VC0_CREDITS: OTL TLX VC0 Credits - Specifies how many vc0 credits to advertise to AFU (0-64). OTL RX physically has 64 buffer entries for VC0. Thus this field must not exceed 64. Can be changed while OTL is active. | |
| 8:15 | RW | RW | CONFIG_TLX_VC1_CREDITS: OTL TLX VC1 Credits - Specifies how many vc1 credits to advertise to AFU. OTL RX physically has 64 buffer entries for VC1. Thus this field must not exceed 64. Can be changed while OTL is active. | |
| 16:23 | RW | RW | CONFIG_TLX_VC2_CREDITS: OTL TLX VC2 Credits - Specifies how many vc2 credits to advertise to AFU. OTL RX physically has 64 buffer entries for VC2. Thus this field must not exceed 64. Can be changed while OTL is active. | |
| 24:31 | RW | RW | CONFIG_TLX_VC3_CREDITS: OTL TLX VC3 Credits - Specifies how many vc3 credits to advertise to AFU (0-64). OTL RX physically has 64 buffer entries for VC3. Thus this field must not exceed 64. Can be changed while OTL is active. | |
| 32:39 | RW | RW | CONFIG_TLX_DCP0_CREDITS: OTL TLX DCP0 Initial Credits - Specifies how many dcp0 credits to advertise to AFU (0-128). OTL RX physically has 128 buffer entries for DCP0. Thus this field must not exceed 128. Can be changed while OTL is active. | |
| 40:47 | RW | RW | CONFIG_TLX_SPARE: OTL TLX config spare bits | |
| 48:55 | RW | RW | CONFIG_TLX_DCP2_CREDITS: OTL TLX DCP2 Initial Credits - Specifies how many dcp2 credits to advertise to AFU. OTL RX physically has 128 buffer entries for DCP2. Thus this field must not exceed 128. Can be changed while OTL is active. | |
| 56:63 | RW | RW | CONFIG_TLX_DCP3_CREDITS: OTL TLX DCP3 Initial Credits - Specifies how many dcp3 credits to advertise to AFU (0-128). OTL RX physically has 128 buffer entries for DCP3. Thus this field must not exceed 128. Can be changed while OTL is active. | |
| OTL Configuration 1 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A5B (SCOM) 00000000134D0058 (PAU_RING) | |||
| Name: | PAU3.OTL1.MISC.CONFIG_TX | |||
| Constant(s): | ||||
| Comments: | OTL Configuration 1 Register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.OTL1.MISC.CONFIG_TX_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_TX_SPARE0: Spare config bit. | |
| 1 | RW | RW | CONFIG_TX_TEMP1_EN: OTL TX Template 1 Enable - Enables OTL TX to send a template 1 control flit. Can be changed while OTL is active. | |
| 2 | RW | RW | CONFIG_TX_TEMP2_EN: OTL TX Template 2 Enable - Enables OTL TX to send a template 2 control flit. Can be changed while OTL is active. | |
| 3 | RW | RW | CONFIG_TX_TEMP3_EN: OTL TX Template 3 Enable - Enables OTL TX to send a template 3 control flit. Can be changed while OTL is active. | |
| 4 | RW | RW | CONFIG_TX_SPARE1: Spare bit. | |
| 5:7 | RW | RW | CONFIG_TX_DRDY_WAIT: Extra wait cycles (0 to 7) to insert for data ready signal from TXI to TXO pack. If the default wait cycle is too short a TXI C8T read-write conflict will occur. | |
| 8:11 | RW | RW | CONFIG_TX_TEMP0_RATE: Template 0 Flit Rate - Secifies minimum number of data or nop control flits (0-15) to follow a template 0 control flit. This value should be set according to the command flit rate capability of the AFU RX. Can be changed while OTL is active. | |
| 12:15 | RW | RW | CONFIG_TX_TEMP1_RATE: Template 1 Flit Rate - Secifies minimum number of data or nop control flits (0-15) to follow a template 1 control flit. This value should be set according to the command flit rate capability of the AFU RX. Can be changed while OTL is active. | |
| 16:19 | RW | RW | CONFIG_TX_TEMP2_RATE: Template 2 Flit Rate - Secifies minimum number of data or nop control flits (0-15) to follow a template 2 control flit. This value should be set according to the command flit rate capability of the AFU RX. Can be changed while OTL is active. | |
| 20:23 | RW | RW | CONFIG_TX_TEMP3_RATE: Template 3 Flit Rate - Secifies minimum number of data or nop control flits (0-15) to follow a template 3 control flit. This value should be set according to the command flit rate capability of the AFU RX. Can be changed while OTL is active. | |
| 24:31 | RW | RW | CONFIG_TX_SPARE2: Spare bits. | |
| 32:34 | RW | RW | CONFIG_TX_CRET_FREQ: Specifies minimum frequency to return TLX credits to AFU provided that there is a nonzero vc/dcp. 000 : At least once every 512 nest cycles (256ns). 001 : At least once every 256 nest cycles (128ns). 010 : At least once every 128 nest cycles (64ns). 011 : At least once every 64 nest cycles (32ns). 1** : Reserved. Can be changed while OTL is active. | |
| 35:39 | RW | RW | CONFIG_TX_AGE_FREQ: Deprecated / not used starting with Axone design. OTL TX Command Age Update Frequency - Specifies frequency to add age to pending requests/responses. When this register has value N, a pending command ages every time N new requests/responses are input to TX. A command has age 0 (youngest), 1, and 2(oldest). Oldness is considered for scheduling but will not force absolute priority. Can be changed while OTL is active. | |
| 40:45 | RW | RW | CONFIG_TX_RS2_HPWAIT: Deprecated / not used starting with Axone design. OTL TX Response High Priority Threshold - Specifies how long to wait before giving high priority to responses. When this register has value N(1-54), and TX logic sees no response is scheduled while sending N flits (ctrl + data), it will prioritize responses when packing the next control flit. Can be changed while OTL is active. | |
| 46:51 | RW | RW | CONFIG_TX_RQ4_HPWAIT: Deprecated / not used starting with Axone design. OTL TX 4-slot Request High Priority Threshold - Specifies how long to wait before giving high priority to 4-slot requests. When this register has value N(1-54), and TX logic sees no 4-slot request is scheduled while sending N flits (ctrl + data), it will prioritize 4-slot requests when packing the next control flit. Can be changed while OTL is active. | |
| 52:57 | RW | RW | CONFIG_TX_RQ6_HPWAIT: Deprecated / not used starting with Axone design. OTL TX 6-slot Request High Priority Threshold - Specifies how long to wait before giving high priority to 6-slot requests. When this register has value N(1-54), and TX logic sees no 6-slot request is scheduled while sending N flits (ctrl + data), it will prioritize 6-slot requests when packing the next control flit. Can be changed while OTL is active. | |
| 58 | RW | RW | CONFIG_TX_CBUF_ECC_DIS: OTL TX Command Buffer ECC Correction Disable - Setting this bit to 1 disables correcting ECC on TX command buffer read data. | |
| 59 | RW | RW | CONFIG_TX_EVENT: OTL TX tl_event Signal - Setting this bit to 1, TX drives the tl_event signal to ODL, which will notify AFU that appropriate action should be taken. (stop a trace, capture state, etc.). | |
| 60 | RW | RW | CONFIG_TX_STOP_ON_UE: OTL TX Stop Link on UE - Setting this bit to 1 allows TX to assert the tl_error signal to ODL when it detects UEs on command buffer C8T. | |
| 61 | RW | RW | CONFIG_TX_T0_MASK_CRTN0: OTL TX Mask All-zero return_tlx_credits for Template0 - Setting this bit to 1 have TX logic zero out return_tlx_credit packets when all VC/DCP counts are 0s when sending out a template 0 control flit. The slot 0 and 1 will be all 0s (i.e. NOP). | |
| 62 | RW | RW | CONFIG_TX_T123_MASK_CRTN0: OTL TX Mask All-zero return_tlx_credits for Template1,2,3 - Setting this bit to 1 have TX logic zero out return_tlx_credit packets when all VC/DCP counts are 0s when sending out a template 1,2, or 3 control flit. The slot 0 and 1 will be all 0s (i.e. NOP). | |
| 63 | RW | RW | CONFIG_TX_SPARE3: OTL TX spare cfg bits. | |
| OTL TX DL Credit Configuration | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A5C (SCOM) 00000000134D0060 (PAU_RING) | |||
| Name: | PAU3.OTL1.MISC.CONFIG_TX_DLC | |||
| Constant(s): | ||||
| Comments: | OTL TX DL Credit Configuration Register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:9 | PAU3.OTL1.MISC.CONFIG_TX_DLC_Q_0_INST.LATC.L2(0:9) [0000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:9 | RW | RW | CONFIG_TX_DL_CREDITS: OTL TX DL Credits - Specifies how many DL TX credits OTL initially has. (0-64) ODL buffer size is 64 entries (16B entries) and hence this field should be set to 64. Can be changed while OTL is active. | |
| 10:63 | RO | RO | constant=0b000000000000000000000000000000000000000000000000000000 | |
| OTL RAS Error Message 0 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A5D (SCOM) 00000000134D0068 (PAU_RING) | |||
| Name: | PAU3.OTL1.MISC.OTL_REM0 | |||
| Constant(s): | ||||
| Comments: | OTL RAS Error Message 0 Register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:7 | PAU3.OTL1.MISC.OTL_REM0Q.LATC.L2(0:7) [00000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | ROX | ROX | REM0_CRD_TL_OVF_VC0: TL vc0 credit counter overflow condition has encountered as a result of a received return_tl_credit. The HW logic saturated the counter at 2^16-1. | |
| 1 | ROX | ROX | REM0_CRD_TL_OVF_VC1: TL vc1 credit counter overflow condition has encountered as a result of a received return_tl_credit. The HW logic saturated the counter at 2^16-1. | |
| 2 | ROX | ROX | REM0_CRD_TL_OVF_VC2: TL vc2 credit counter overflow condition has encountered as a result of a received return_tl_credit. The HW logic saturated the counter at 2^16-1. | |
| 3 | ROX | ROX | REM0_CRD_TL_OVF_RSVD3: Reserved. | |
| 4 | ROX | ROX | REM0_CRD_TL_OVF_DCP0: TL dcp0 credit counter overflow condition has encountered as a result of a received return_tl_credit. The HW logic saturated the counter at 2^16-1. | |
| 5 | ROX | ROX | REM0_CRD_TL_OVF_DCP1: TL dcp1 credit counter overflow condition has encountered as a result of a received return_tl_credit. The HW logic saturated the counter at 2^16-1. | |
| 6 | ROX | ROX | REM0_CRD_TL_OVF_RSVD6: Reserved. | |
| 7 | ROX | ROX | REM0_CRD_TL_OVF_RSVD7: Reserved. | |
| 8:63 | RO | RO | constant=0b00000000000000000000000000000000000000000000000000000000 | |
| OTL RXI Error Signature | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A5E (SCOM) 00000000134D0070 (PAU_RING) | |||
| Name: | PAU3.OTL1.MISC.ERROR_SIG_RXI | |||
| Constant(s): | ||||
| Comments: | OTL RXI Error Signature Register Captures on first error not masked by c_err_rpt | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.OTL1.MISC.ERROR_SIG_RXIQ.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | ERRSIGRXI_CAPTURED: 0b1 = error signature valid | |
| 1:7 | RW | RW | ERRSIGRXI_ENCODE: error encode matches c_err_rpt 0 | |
| 8:63 | RW | RW | ERRSIGRXI_SIGNATURE: error signature varies by encode | |
| OTL RXO Error Signature Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A5F (SCOM) 00000000134D0078 (PAU_RING) | |||
| Name: | PAU3.OTL1.MISC.ERROR_SIG_RXO | |||
| Constant(s): | ||||
| Comments: | OTL RXO Error Signature Register Captures on first error not masked by c_err_rpt | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.OTL1.MISC.ERROR_SIG_RXOQ.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:2 | RWX | RWX | ERRSIGRXO_TYPE: 0b100 = bdf/pasid error 0b010 = opcode error 0b001 = arb_s2_posted_wrt_fail/pe_handle error | |
| 3 | RWX | RWX | ERRSIGRXO_XSL_RSP0: xsl response bit 0 - only valid when errsigrxo_type=001. See errsigrxo_xsl_rsp12. | |
| 4:19 | RWX | RWX | ERRSIGRXO_AFUTAG: afutag of the offending op | |
| 20:27 | RWX | RWX | ERRSIGRXO_OPCODE: opcode of the offending op | |
| 28:39 | RWX | RWX | ERRSIGRXO_ACTAG: actag of the offending op - valid only if a bdf or pasid error. If pe_handle error, or another type, then actag must be derived by finding the actag entry that yields the pe_handle in the queue entry | |
| 40:45 | RWX | RWX | ERRSIGRXO_QINDEX: index of the rxo queue entry used by the offending op | |
| 46:61 | RWX | RWX | ERRSIGRXO_PE_HANDLE: pe_handle of the bad op - only valid when errsigrxo_type=001 | |
| 62:63 | RWX | RWX | ERRSIGRXO_XSL_RSP12: xsl response bits 1:2 - only valid when errsigrxo_type=001. Encodes(0:2): 1=TA permission mismatch, 2=TA Process Index mismatch, 3=Invalid TA, 4=Brick fence in progress. | |
| Alter OTL Credit Counters | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A60 (SCOM) 00000000134D0080 (PAU_RING) | |||
| Name: | PAU3.OTL1.MISC.ALTER_CREDIT_COUNTERS | |||
| Constant(s): | ||||
| Comments: | Alter OTL Credit Counters | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:23 | PAU3.OTL1.MISC.ALTER_CREDIT_COUNTERS_Q_0_INST.LATC.L2(0:23) [000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | ALTER_CRD_ENABLE: Enables altering credit counters. | |
| 1:3 | RW | RW | ALTER_CRD_RESERVED: Reserved. | |
| 4:7 | RW | RW | ALTER_CRD_TARGET: When a nonzero value is to this register, a credit counter will be updated with the value field. This update occurs only once on writing this register. 0 : Will not update any credit counter. 1 : Update the TLX vc0 credit counter. Only 8 LSBs of the value field will be used. 2 : Update the TLX vc1 credit counter. Only 8 LSBs of the value field will be used. 3 : Update the TLX vc2 credit counter. Only 8 LSBs of the value field will be used. 4 : Update the TLX vc3 credit counter. Only 8 LSBs of the value field will be used. 5 : Update the TLX dcp0 credit counter. Only 8 LSBs of the value field will be used. 6 : Update the TLX dcp2 credit counter. Only 8 LSBs of the value field will be used. 7 : Update the TLX dcp3 credit counter. Only 8 LSBs of the value field will be used. 8 : Update the TL vc0 credit counter. 9 : Update the TL vc1 credit counter. 10 : Update the TL vc2 credit counter. 11 : Update the TL dcp0 credit counter. 12 : Update the TL dcp1 credit counter. 13 : Update the TX DL credit counter. | |
| 8:23 | RW | RW | ALTER_CRD_VALUE: The value to be written to the target credit counter. | |
| 24:63 | RO | RO | constant=0b0000000000000000000000000000000000000000 | |
| TLX Credit Counter Status | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A61 (SCOM) 00000000134D0088 (PAU_RING) | |||
| Name: | PAU3.OTL1.MISC.TLX_CREDIT_STATUS | |||
| Constant(s): | ||||
| Comments: | OTL TLX Credit Counter Status Register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:7 | PAU3.OTL1.MISC.CRD_TLX_VC0Q.LATC.L2(0:7) [00000000] | |||
| 8:15 | PAU3.OTL1.MISC.CRD_TLX_VC1Q.LATC.L2(0:7) [00000000] | |||
| 16:23 | PAU3.OTL1.MISC.CRD_TLX_VC2Q.LATC.L2(0:7) [00000000] | |||
| 24:31 | PAU3.OTL1.MISC.CRD_TLX_VC3Q.LATC.L2(0:7) [00000000] | |||
| 32:39 | PAU3.OTL1.MISC.CRD_TLX_DCP0Q.LATC.L2(0:7) [00000000] | |||
| 40:47 | PAU3.OTL1.MISC.CRD_TLX_DCP2Q.LATC.L2(0:7) [00000000] | |||
| 48:55 | PAU3.OTL1.MISC.CRD_TLX_DCP3Q.LATC.L2(0:7) [00000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:7 | ROX | ROX | STATUS_TLX_VC0_COUNT: Current value of the TLX vc0 credit counter. Indicates (number of credits OTL has advertised) minus (number of consumed credits by the received TLX packets). When idle, this counter should match the config_tlx_vc0_credits value. | |
| 8:15 | ROX | ROX | STATUS_TLX_VC1_COUNT: Current value of the TLX vc1 credit counter. Indicates (number of credits OTL has advertised) minus (number of consumed credits by the received TLX packets). When idle, this counter should match the config_tlx_vc1_credits value. | |
| 16:23 | ROX | ROX | STATUS_TLX_VC2_COUNT: Current value of the TLX vc2 credit counter. Indicates (number of credits OTL has advertised) minus (number of consumed credits by the received TLX packets). When idle, this counter should match the config_tlx_vc2_credits value. | |
| 24:31 | ROX | ROX | STATUS_TLX_VC3_COUNT: Current value of the TLX vc3 credit counter. Indicates (number of credits OTL has advertised) minus (number of consumed credits by the received TLX packets). When idle, this counter should match the config_tlx_vc3_credits value. | |
| 32:39 | ROX | ROX | STATUS_TLX_DCP0_COUNT: Current value of the TLX dcp0 credit counter. Indicates (number of credits OTL has advertised) minus (number of consumed credits by the received TLX packets). When idle, this counter should match the config_tlx_dcp0_credits value. | |
| 40:47 | ROX | ROX | STATUS_TLX_DCP2_COUNT: Current value of the TLX dcp2 credit counter. Indicates (number of credits OTL has advertised) minus (number of consumed credits by the received TLX packets). When idle, this counter should match the config_tlx_dcp2_credits value. | |
| 48:55 | ROX | ROX | STATUS_TLX_DCP3_COUNT: Current value of the TLX dcp3 credit counter. Indicates (number of credits OTL has advertised) minus (number of consumed credits by the received TLX packets). When idle, this counter should match the config_tlx_dcp3_credits value. | |
| 56:63 | RO | RO | constant=0b00000000 | |
| TL VC Credit Counter Status | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A62 (SCOM) 00000000134D0090 (PAU_RING) | |||
| Name: | PAU3.OTL1.MISC.TL_VC_CREDIT_STATUS | |||
| Constant(s): | ||||
| Comments: | OTL TL VC Credit Counter Status Register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:15 | PAU3.OTL1.MISC.CRD_TL_VC0Q.LATC.L2(0:15) [0000000000000000] | |||
| 16:31 | PAU3.OTL1.MISC.CRD_TL_VC1Q.LATC.L2(0:15) [0000000000000000] | |||
| 32:47 | PAU3.OTL1.MISC.CRD_TL_VC2Q.LATC.L2(0:15) [0000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:15 | ROX | ROX | STATUS_TL_VC0_COUNT: Current value of the TL vc0 credit counter. Indicates number of vc0 packets in contol flits OTL is allowed to send to AFU. When idle, this counter should hit the MAX value AFU can advertise. | |
| 16:31 | ROX | ROX | STATUS_TL_VC1_COUNT: Current value of the TL vc1 credit counter. Indicates number of vc1 packets in contol flits OTL is allowed to send to AFU. When idle, this counter should hit the MAX value AFU can advertise. | |
| 32:47 | ROX | ROX | STATUS_TL_VC2_COUNT: Current value of the TL vc2 credit counter. Indicates number of vc2 packets in contol flits OTL is allowed to send to AFU. When idle, this counter should hit the MAX value AFU can advertise. | |
| 48:63 | RO | RO | constant=0b0000000000000000 | |
| TL DCP Credit Counter Status | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A63 (SCOM) 00000000134D0098 (PAU_RING) | |||
| Name: | PAU3.OTL1.MISC.TL_DCP_CREDIT_STATUS | |||
| Constant(s): | ||||
| Comments: | OTL TL DCP Credit Counter Status Register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:15 | PAU3.OTL1.MISC.CRD_TL_DCP0Q.LATC.L2(0:15) [0000000000000000] | |||
| 16:31 | PAU3.OTL1.MISC.CRD_TL_DCP1Q.LATC.L2(0:15) [0000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:15 | ROX | ROX | STATUS_TL_DCP0_COUNT: Current value of the TL dcp0 credit counter. Indicates number of data flits in dcp0 that OTL is allowed to send to AFU. When idle, this counter should hit the MAX value AFU can advertise. | |
| 16:31 | ROX | ROX | STATUS_TL_DCP1_COUNT: Current value of the TL dcp1 credit counter. Indicates number of data flits in dcp1 that OTL is allowed to send to AFU. When idle, this counter should hit the MAX value AFU can advertise. | |
| 32:63 | RO | RO | constant=0b00000000000000000000000000000000 | |
| TX DL Credit Counter Status | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A64 (SCOM) 00000000134D00A0 (PAU_RING) | |||
| Name: | PAU3.OTL1.MISC.TX_DL_CREDIT_STATUS | |||
| Constant(s): | ||||
| Comments: | OTL TX DL Credit Counter Status Register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:11 | PAU3.OTL1.MISC.CRD_DL_TXQ.LATC.L2(0:11) [000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:11 | ROX | ROX | STATUS_DL_CREDIT_COUNT: Current value of the TX DL credit counter. Indicates number of 16B chunks of command or data flits that OTL TX can send to ODL TX. When idle, this counter should hit the MAX value ODL can advertise. | |
| 12:63 | RO | RO | constant=0b0000000000000000000000000000000000000000000000000000 | |
| TXI Error Injection | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A65 (SCOM) 00000000134D00A8 (PAU_RING) | |||
| Name: | PAU3.OTL1.MISC.TXI_ERR_INJ | |||
| Constant(s): | ||||
| Comments: | OTL TXI Array Error Injection Control and Status Register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:5 | PAU3.OTL1.MISC.TXI_ERR_INJQ.LATC.L2(0:5) [000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX | RWX | TXI_CTRL_ERR_INJ_CE: CE error injection control for TXI CTRL array. On register write withg this bit set to 1, the next SRAM write will contain a CE. | |
| 1 | RWX | RWX | TXI_CTRL_ERR_INJ_UE: UE error injection control for TXI CTRL array. On register write withg this bit set to 1, the next SRAM write will contain a UE. | |
| 2 | RWX | RWX | TXI_DATA_ERR_INJ_CE: CE error injection control for TXI DATA array. On register write withg this bit set to 1, the next SRAM write will contain a CE. | |
| 3 | RWX | RWX | TXI_DATA_ERR_INJ_UE: UE error injection control for TXI DATA array. On register write withg this bit set to 1, the next SRAM write will contain a UE. | |
| 4 | ROX | ROX | TXI_CTRL_ERR_INJ_PEND: Error injection status for TXI CTRL array. This register will read 1 until the requested error has been injected. | |
| 5 | ROX | ROX | TXI_DATA_ERR_INJ_PEND: Error injection status for TXI DATA array. This register will read 1 until the requested error has been injected. | |
| 6:63 | RO | RO | constant=0b0000000000000000000000000000000000000000000000000000000000 | |
| OTL Error Report Register 1 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A66 (SCOM) 00000000134D00B0 (PAU_RING) | |||
| Name: | PAU3.OTL1.MISC.C_ERR_RPT_HOLD1 | |||
| Constant(s): | ||||
| Comments: | OTL Error Report Register 1 (c_err_rpt 1 hold) | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:31 | PAU3.OTL1.MISC.ERR_RPT1.HOLD_LATCH_INST.HOLD.LATC.L2(0:31) [00000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_VC1FIFO_LO_CE: OTL RXI vc1 fifo ECC CE, lo bits 0:63. | |
| 1 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_VC1FIFO_LO_UE: OTL RXI vc1 fifo ECC CE, lo bits 0:63. | |
| 2 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_VC1FIFO_HI_CE: OTL RXI vc1 fifo ECC CE, hi bits 64:111. | |
| 3 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_VC1FIFO_HI_UE: OTL RXI vc1 fifo ECC CE, hi bits 64:111. | |
| 4 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_VC2FIFO_LO_CE: OTL RXI vc2 fifo ECC CE, lo bits 0:55. | |
| 5 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_VC2FIFO_LO_UE: OTL RXI vc2 fifo ECC CE, lo bits 0:55. | |
| 6 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_BAD_DATA_RECIEVED_VC2: OTL RXI bad data received vc2. | |
| 7 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_DCP2FIFO_LO_CE: OTL RXI dcp2 data fifo ECC CE, lo bits 0:63. | |
| 8 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_DCP2FIFO_LO_UE: OTL RXI dcp2 data fifo ECC CE, lo bits 0:63. | |
| 9 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_DCP2FIFO_HI_CE: OTL RXI dcp2 data fifo ECC CE, lo bits 64:127. | |
| 10 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_DCP2FIFO_HI_UE: OTL RXI dcp2 data fifo ECC CE, lo bits 64:127. | |
| 11 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_DCP2FIFO_OVERRUN: OTL RXI dcp2fifo overrun. | |
| 12 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_VC1FIFO_OVERRUN: OTL RXI vc1fifo overrun. | |
| 13 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_VC2FIFO_OVERRUN: OTL RXI vc2fifo overrun. | |
| 14 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_DL_VC0: OTL RXI dL not supported vc0. | |
| 15 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_DL_VC2: OTL RXI dL not supported vc2. | |
| 16 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_DL_VC3: OTL RXI dL not supported vc3. | |
| 17 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_TXI_CTL_OPCODE_ERR: OTL TXI CTL issued 4.0 opcode while in 3.0 mode. See error_sig_txi. | |
| 18 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_TXI_XSL_OPCODE_ERR: OTL TXI XSL issued 4.0 opcode while in 3.0 mode. See error_sig_txi. | |
| 19 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_FIELDRSVDNE0_TLVC2: OTL RXI malformed packet error type 4, reserved field not transmitted as 0, TL.vc.2 in ocapi 3.0 mode. | |
| 20 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD_RXI_IMP_NOBARMATCH: OTL RXI Incepted Memory no address BAR match. | |
| 21 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD1_SPARE21: OTL error spare 21 | |
| 22 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD1_SPARE22: OTL error spare 22 | |
| 23 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD1_SPARE23: OTL error spare 23 | |
| 24 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD1_SPARE24: OTL error spare 24 | |
| 25 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD1_SPARE25: OTL error spare 25 | |
| 26 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD1_SPARE26: OTL error spare 26 | |
| 27 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD1_SPARE27: OTL error spare 27 | |
| 28 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD1_SPARE28: OTL error spare 28 | |
| 29 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD1_SPARE29: OTL error spare 29 | |
| 30 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD1_SPARE30: OTL error spare 30 | |
| 31 | RWX_WCLRREG | RWX_WCLRREG | OTL_ERR_HOLD1_SPARE31: OTL error spare 31 | |
| 32:63 | RO | RO | constant=0b00000000000000000000000000000000 | |
| OTL Error Report Mask Register 1 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A67 (SCOM) 00000000134D00B8 (PAU_RING) | |||
| Name: | PAU3.OTL1.MISC.C_ERR_RPT_MASK1 | |||
| Constant(s): | ||||
| Comments: | OTL Error Report Mask Register 1 (c_err_rpt 1 mask) | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:31 | PAU3.OTL1.MISC.ERR_RPT1_MASK.LATC.L2(0:31) [00000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RO | RO | OTL_ERR_MASK100: OTL error mask 00 | |
| 1 | RO | RO | OTL_ERR_MASK101: OTL error mask 01 | |
| 2 | RO | RO | OTL_ERR_MASK102: OTL error mask 02 | |
| 3 | RO | RO | OTL_ERR_MASK103: OTL error mask 03 | |
| 4 | RO | RO | OTL_ERR_MASK104: OTL error mask 04 | |
| 5 | RO | RO | OTL_ERR_MASK105: OTL error mask 05 | |
| 6 | RO | RO | OTL_ERR_MASK106: OTL error mask 06 | |
| 7 | RO | RO | OTL_ERR_MASK107: OTL error mask 07 | |
| 8 | RO | RO | OTL_ERR_MASK108: OTL error mask 08 | |
| 9 | RO | RO | OTL_ERR_MASK109: OTL error mask 09 | |
| 10 | RO | RO | OTL_ERR_MASK110: OTL error mask 10 | |
| 11 | RO | RO | OTL_ERR_MASK111: OTL error mask 11 | |
| 12 | RO | RO | OTL_ERR_MASK112: OTL error mask 12 | |
| 13 | RO | RO | OTL_ERR_MASK113: OTL error mask 13 | |
| 14 | RO | RO | OTL_ERR_MASK114: OTL error mask 14 | |
| 15 | RO | RO | OTL_ERR_MASK115: OTL error mask 15 | |
| 16 | RO | RO | OTL_ERR_MASK116: OTL error mask 16 | |
| 17 | RO | RO | OTL_ERR_MASK117: OTL error mask 17 | |
| 18 | RO | RO | OTL_ERR_MASK118: OTL error mask 18 | |
| 19 | RO | RO | OTL_ERR_MASK119: OTL error mask 19 | |
| 20 | RO | RO | OTL_ERR_MASK120: OTL error mask 20 | |
| 21 | RO | RO | OTL_ERR_MASK121: OTL error mask 21 | |
| 22 | RO | RO | OTL_ERR_MASK122: OTL error mask 22 | |
| 23 | RO | RO | OTL_ERR_MASK123: OTL error mask 23 | |
| 24 | RO | RO | OTL_ERR_MASK124: OTL error mask 24 | |
| 25 | RO | RO | OTL_ERR_MASK125: OTL error mask 25 | |
| 26 | RO | RO | OTL_ERR_MASK126: OTL error mask 26 | |
| 27 | RO | RO | OTL_ERR_MASK127: OTL error mask 27 | |
| 28 | RO | RO | OTL_ERR_MASK128: OTL error mask 28 | |
| 29 | RO | RO | OTL_ERR_MASK129: OTL error mask 29 | |
| 30 | RO | RO | OTL_ERR_MASK130: OTL error mask 30 | |
| 31 | RO | RO | OTL_ERR_MASK131: OTL error mask 31 | |
| 32:63 | RO | RO | constant=0b00000000000000000000000000000000 | |
| OTL Configuration 2 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A68 (SCOM) 00000000134D00C0 (PAU_RING) | |||
| Name: | PAU3.OTL1.MISC.CONFIG_TX2 | |||
| Constant(s): | ||||
| Comments: | OTL Configuration 2 Register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:27 | PAU3.OTL1.MISC.CONFIG_TX2Q.LATC.L2(0:27) [0000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX | RWX | CONFIG_TX_SEND_EN: OTL TX Send Enable - Allows OTL TX to send out packets to AFU. When this bit is 0, OTL TX still accepts requests and responses from CQ and RXI as long as the buffer is not full. But these commands and responses will be held in TX until this bit becomes 1. HW will clear this send_en bit automatically when this OTL enters fence mode (i.e. when ctl_otl_fence_dx=1). | |
| 1:3 | RWX | RWX | CONFIG_TX_SPARE4: Spare config bits. | |
| 4:7 | RWX | RWX | CONFIG_VC1_THRESH1: VC1 threshold 1 = bit value, i.e., 0-15. CTL SM allocation behavior changes if VC1 queue exceeds this value. Flush value is 3. (VC1 threshold1=3) | |
| 8:11 | RWX | RWX | CONFIG_VC2_THRESH1: VC2 threshold 1 = bit value, i.e., 0-15. CTL SM allocation behavior changes if VC2 queue exceeds this value. Flush value is 3. (VC2 threshold1=3) | |
| 12:15 | RWX | RWX | CONFIG_VC3_THRESH1: VC3 threshold 1 = bit value, i.e., 0-15. CTL SM allocation behavior changes if VC3 queue exceeds this value. Flush value is 3. (VC3 threshold1=3) | |
| 16:19 | RWX | RWX | CONFIG_VC1_THRESH2: VC1 threshold 2 = (bit value x 4) + 3, i.e., 3,7,..,63. CTL SM allocation behavior changes if VC1 queue exceeds this value. Flush value is 7. (VC1 threshold2=31) | |
| 20:23 | RWX | RWX | CONFIG_VC2_THRESH2: VC2 threshold 2 = (bit value x 4) + 3, i.e., 3,7,..,63. CTL SM allocation behavior changes if VC2 queue exceeds this value. Flush value is 7. (VC2 threshold2=31) | |
| 24:27 | RWX | RWX | CONFIG_VC3_THRESH2: VC3 threshold 2 = (bit value x 4) + 3, i.e., 3,7,..,63. CTL SM allocation behavior changes if VC3 queue exceeds this value. Flush value is 7. (VC3 threshold2=31) | |
| 28:63 | RO | RO | constant=0b000000000000000000000000000000000000 | |
| OTL ERAT Hash Configuration Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A69 (SCOM) 00000000134D00C8 (PAU_RING) | |||
| Name: | PAU3.OTL1.MISC.CONFIG_ERAT_HASH | |||
| Constant(s): | ||||
| Comments: | OTL ERAT Hash Configuration Register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:59 | PAU3.OTL1.MISC.CONFIG_ERAT_HASH_Q_0_INST.LATC.L2(0:59) [000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:5 | RW | RW | CONFIG_OTL_ERAT_HASH_0: OTL ERAT HASH0 - hashed against actag(5:0) and pe_handle( 6) to generate xsl erat_index(0) (MSB) (flushes to 0x37) | |
| 6:11 | RW | RW | CONFIG_OTL_ERAT_HASH_1: OTL ERAT HASH1 - hashed against actag(5:0) and pe_handle( 7) to generate xsl erat_index(1) (flushes to 0x16) | |
| 12:17 | RW | RW | CONFIG_OTL_ERAT_HASH_2: OTL ERAT HASH2 - hashed against actag(5:0) and pe_handle( 8) to generate xsl erat_index(2) (flushes to 0x08) | |
| 18:23 | RW | RW | CONFIG_OTL_ERAT_HASH_3: OTL ERAT HASH3 - hashed against actag(5:0) and pe_handle( 9) to generate xsl erat_index(3) (flushes to 0x0d) | |
| 24:29 | RW | RW | CONFIG_OTL_ERAT_HASH_4: OTL ERAT HASH4 - hashed against actag(5:0) and pe_handle(10) to generate xsl erat_index(4) (flushes to 0x38) | |
| 30:35 | RW | RW | CONFIG_OTL_ERAT_HASH_5: OTL ERAT HASH5 - hashed against actag(5:0) and pe_handle(11) to generate xsl erat_index(5) (flushes to 0x0e) | |
| 36:41 | RW | RW | CONFIG_OTL_ERAT_HASH_6: OTL ERAT HASH6 - hashed against actag(5:0) and pe_handle(12) to generate xsl erat_index(6) (flushes to 0x0d) | |
| 42:47 | RW | RW | CONFIG_OTL_ERAT_HASH_7: OTL ERAT HASH7 - hashed against actag(5:0) and pe_handle(13) to generate xsl erat_index(7) (flushes to 0x1a) | |
| 48:53 | RW | RW | CONFIG_OTL_ERAT_HASH_8: OTL ERAT HASH8 - hashed against actag(5:0) and pe_handle(14) to generate xsl erat_index(8) (flushes to 0x21) | |
| 54:59 | RW | RW | CONFIG_OTL_ERAT_HASH_9: OTL ERAT HASH9 - hashed against actag(5:0) and pe_handle(15) to generate xsl erat_index(9) (LSB) (flushes to 0x36) | |
| 60:63 | RO | RO | constant=0b0000 | |
| OTL TXI Error Signature Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A6A (SCOM) 00000000134D00D0 (PAU_RING) | |||
| Name: | PAU3.OTL1.MISC.ERROR_SIG_TXI | |||
| Constant(s): | ||||
| Comments: | OTL TXI Error Signature Register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:7 | PAU3.OTL1.MISC.ERROR_SIG_TXIQ.LATC.L2(0:7) [00000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:7 | ROX | ROX | ERRSIGTXI_BAD_OPCODE: OTL TXI - bad opcode detected per c_err_rpt_hold1(16:17) | |
| 8:63 | RO | RO | constant=0b00000000000000000000000000000000000000000000000000000000 | |
| OTL HAPPI BAR0 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A6B (SCOM) 00000000134D00D8 (PAU_RING) | |||
| Name: | PAU3.OTL1.MISC.HAPPI_BAR0 | |||
| Constant(s): | ||||
| Comments: | OTL HAPPI BAR0 Register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.OTL1.MISC.HAPPI_BAR0_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_HAPPI_BAR0_ENABLE: Enable for this BAR (0=disabled, 1=enabled) (but only when config_otl_enable_happi=1, in networking mode, the enable is config_otl_enable_min | |
| 1:21 | RW | RW | CONFIG_HAPPI_BAR0_ADDR: BAR address HAPPI mode: Reg bits 1:21 used for masked compare of receive PA(50 downto 30) = Powerbus(13 to 33) = 1G address. Network mode: Reg bits 8:21 used for masked compare of received MEA(20:33) = Powerbus(20:33). | |
| 22:42 | RW | RW | CONFIG_HAPPI_BAR0_MASK: BAR mask - both modes | |
| 43:63 | RW | RW | CONFIG_HAPPI_BAR0_SUB: BAR substitute address / compare/mask extension Happi mode: Replaces unmasked compare bits 13:33 Network mode: reg bits 44:53 compare against MEA(34:43), reg bits 54:63 are mask for MEA(34:43) compare. | |
| OTL HAPPI BAR1 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A6C (SCOM) 00000000134D00E0 (PAU_RING) | |||
| Name: | PAU3.OTL1.MISC.HAPPI_BAR1 | |||
| Constant(s): | ||||
| Comments: | OTL HAPPI BAR1 Register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.OTL1.MISC.HAPPI_BAR1_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_HAPPI_BAR1_ENABLE: Enable for this BAR (0=disabled, 1=enabled) | |
| 1:21 | RW | RW | CONFIG_HAPPI_BAR1_ADDR: BAR address Happi mode: Used for masked compare of receive PA(50 downto 30) = Powerbus(13 to 33) = 1G address Network mode: reg bits 1:20 are used for MEA(0:19) when presenting the address to the XSL, replacing MEA(12:19) which came in off the OC link. | |
| 22:42 | RW | RW | CONFIG_HAPPI_BAR1_MASK: BAR mask (not used in Network Mode) | |
| 43:63 | RW | RW | CONFIG_HAPPI_BAR1_SUB: BAR substitute address (not used in Network Mode) Replaces unmasked compare bits. | |
| OTL HAPPI BAR2 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A6D (SCOM) 00000000134D00E8 (PAU_RING) | |||
| Name: | PAU3.OTL1.MISC.HAPPI_BAR2 | |||
| Constant(s): | ||||
| Comments: | OTL HAPPI BAR2 Register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.OTL1.MISC.HAPPI_BAR2_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_HAPPI_BAR2_ENABLE: Enable for this BAR (0=disabled, 1=enabled) | |
| 1:21 | RW | RW | CONFIG_HAPPI_BAR2_ADDR: BAR address Used for masked compare of receive PA(50 downto 30) = Powerbus(13 to 33) = 1G address | |
| 22:42 | RW | RW | CONFIG_HAPPI_BAR2_MASK: BAR mask | |
| 43:63 | RW | RW | CONFIG_HAPPI_BAR2_SUB: BAR substitute address Replaces unmasked compare bits | |
| OTL HAPPI BAR3 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A6E (SCOM) 00000000134D00F0 (PAU_RING) | |||
| Name: | PAU3.OTL1.MISC.HAPPI_BAR3 | |||
| Constant(s): | ||||
| Comments: | OTL HAPPI BAR3 Register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.OTL1.MISC.HAPPI_BAR3_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_HAPPI_BAR3_ENABLE: Enable for this BAR (0=disabled, 1=enabled) | |
| 1:21 | RW | RW | CONFIG_HAPPI_BAR3_ADDR: BAR address Used for masked compare of receive PA(50 downto 30) = Powerbus(13 to 33) = 1G address | |
| 22:42 | RW | RW | CONFIG_HAPPI_BAR3_MASK: BAR mask | |
| 43:63 | RW | RW | CONFIG_HAPPI_BAR3_SUB: BAR substitute address Replaces unmasked compare bits | |
| OTL Configuration 3 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A6F (SCOM) 00000000134D00F8 (PAU_RING) | |||
| Name: | PAU3.OTL1.MISC.CONFIG3 | |||
| Constant(s): | ||||
| Comments: | OTL Configuration 3 Register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:31 | PAU3.OTL1.MISC.CONFIG3_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_OTL_ENABLE_HAPPI: OTL enable HAPPI (0=disabled, 1=enabled) | |
| 1 | RW | RW | CONFIG_OTL_ENABLE_MIN: OTL enable Memory Inception Networking mode (0=disabled, 1=enabled). Received TL packets are converted to TLX packets per the Memory Incepted Networking protocol. This mode is requires the following modes to be disabled: config_otl_enable_4_0, config_otl_enable_5_0, and config_otl_enable_happi. | |
| 2 | RW | RW | CONFIG_OTL_ENABLE_HAPPI_ASYM: OTL enable HAPPI Async mode (0=disabled, 1=enabled). Outbound opcodes will be converted from TL form to TLX form. Intended for connecting to a P9 chip. | |
| 3 | RW | RW | CONFIG_OTL_DISABLE_STREAM_ORDERING: OTL disable stream ordering in HAPPI and MIN modes. Only affects ordering when config_otl_enable_happi or config_otl_enable_min are active. | |
| 4:31 | RW | RW | CONFIG_OTL_CONFIG3_SPARE: spare | |
| 32:63 | RO | RO | constant=0b00000000000000000000000000000000 | |
| OSL_DSISR | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A78 (SCOM) 00000000130D0000 (PAU_RING) | |||
| Name: | PAU3.OTL1.MISC.PSL_DSISR_AN | |||
| Constant(s): | ||||
| Comments: | OSL Data Storage Interrupt Status Register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 3 | PAU3.OTL1.MISC.PSL_DSISR_AN3Q.LATC.L2(0) [0] | |||
| 38 | PAU3.OTL1.MISC.PSL_DSISR_AN38Q.LATC.L2(0) [0] | |||
| 56:63 | PAU3.OTL1.MISC.PSL_DSISR_AN56Q.LATC.L2(56:63) [00000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:2 | RO | RO | constant=0b000 | |
| 3 | RO | RO | TF: Translation Fault - Set to 1 if the PSL has detected a translation fault. The cause of the translation fault is contained in OSL_DSISR[CO_RSP]. This bit is reset to 0 when the corresponding OSL_TFC Register is written. | |
| 4:37 | RO | RO | constant=0b0000000000000000000000000000000000 | |
| 38 | RO | RO | S: Translation fail for a write operation. Set to 1 if the access type was a write operation. | |
| 39:55 | RO | RO | constant=0b00000000000000000 | |
| 56:63 | RO | RO | CO_RSP: Checkout Response Status This field will contain the status byte returned by nMMU for an unsuccessful Checkout request. | |
| OSL_DAR | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A79 (SCOM) 00000000130D0008 (PAU_RING) | |||
| Name: | PAU3.OTL1.MISC.PSL_DAR_AN | |||
| Constant(s): | ||||
| Comments: | PS Checkout Effective Address Register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:51 | PAU3.OTL1.MISC.PSL_DAR_ANQ.LATC.L2(0:51) [0000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:51 | RO | RO | CO_EA: Effective Address 0:51 associated with the data segment or data storage interrupt | |
| 52:63 | RO | RO | constant=0b000000000000 | |
| OSL_TFC | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A7A (SCOM) 00000000130D0010 (PAU_RING) | |||
| Name: | PAU3.OTL1.MISC.PSL_TFC_AN | |||
| Constant(s): | ||||
| Comments: | OS Translation Fault Control Register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 28:31 | PAU3.OTL1.MISC.PSL_TFC_ANQ.LATC.L2(28:31) [0000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:27 | RO | RO | constant=0b0000000000000000000000000000 | |
| 28 | WO_1P | WO_1P | TFC_ACK: Does nothing. Resets to 0 if written to 1. | |
| 29 | RWX | RWX | C: Continue. Current translation fault is not resolved and must be retried at a later time. Note: This bit must be set to 1 to cause a xlate_done to be sent to the AFU with RespCode = 0010 (Retry Request) Note: bits 29:31 can only be written with a 1-hot value, or the results will be undefined. | |
| 30 | RWX | RWX | AE: Address error on the transaction caused the translation fault. Note: This bit must be set to 1 to cause a xlate_done to be sent to the AFU with RespCode = 1111 (Address Translation Error) | |
| 31 | RWX | RWX | R: Restarts the AFU transaction that caused the translation fault. Note: This bit must be set to 1 to cause a xlate_done to be sent to the AFU with RespCode = 0000 (Complete) | |
| 32:63 | RO | RO | constant=0b00000000000000000000000000000000 | |
| OSL_PEHandle | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A7B (SCOM) 00000000130D0018 (PAU_RING) | |||
| Name: | PAU3.OTL1.MISC.PSL_PEHANDLE_AN | |||
| Constant(s): | ||||
| Comments: | PE_Handle Process Element Handle | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 16:31 | PAU3.OTL1.MISC.PSL_PEHANDLE16_ANQ.LATC.L2(16:31) [0000000000000000] | |||
| 48:63 | PAU3.OTL1.MISC.PSL_PEHANDLE48_ANQ.LATC.L2(48:63) [0000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:15 | RO | RO | constant=0b0000000000000000 | |
| 16:31 | RO | RO | AFUTAG: Command tag. The command tag is a 16-bit AFU tag corresponding to the AFU command that caused the interrupt. | |
| 32:47 | RO | RO | constant=0b0000000000000000 | |
| 48:63 | RO | RO | PE_HANDLE: Process Element Handle. The process element handle is the 16-bit pointer to the corresponding process element. The leftmost bit indicates the brickid within the pair of bricks serviced by this OTL. | |
| OSL_SPAP_A0 Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A80 (SCOM) 00000000134E0000 (PAU_RING) | |||
| Name: | PAU3.XSL.XSL_MAIN.XSLOP_VLOG.RGS.OSL_SPAP_A0 | |||
| Constant(s): | ||||
| Comments: | OSL_SPAP_A0 Register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 4:51 | PAU3.XSL.XSL_MAIN.XSLOP_VLOG.RGS.XSL_PARAM_CG_PARREG_RGS_1.morph_dff_st_gr_data_ff.LATC.L2(0:47) [000000000000000000000000000000000000000000000000] | |||
| 63 | PAU3.XSL.XSL_MAIN.XSLOP_VLOG.RGS.XSL_PARAM_CG_PARREG_RGS_1.morph_dff_st_gr_data_ff.LATC.L2(48) [0] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:3 | RO | RO | constant=0b0000 | |
| 4:51 | RW | RW | OSL_SPAP_A0_ADDR_DIAL: OSL_SPAP_A0 Address Dial, bits 42:51 must be set to 0b0000000000 | |
| 52:62 | RO | RO | constant=0b00000000000 | |
| 63 | RW | RW | OSL_SPAP_A0_VALID_DIAL: OSL_SPAP_A0 valid Dial | |
| OSL_SPAP_A1 Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A81 (SCOM) 00000000134E0008 (PAU_RING) | |||
| Name: | PAU3.XSL.XSL_MAIN.XSLOP_VLOG.RGS.OSL_SPAP_A1 | |||
| Constant(s): | ||||
| Comments: | OSL_SPAP_A1 Register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 4:51 | PAU3.XSL.XSL_MAIN.XSLOP_VLOG.RGS.XSL_PARAM_CG_PARREG_RGS_4.morph_dff_st_gr_data_ff.LATC.L2(0:47) [000000000000000000000000000000000000000000000000] | |||
| 63 | PAU3.XSL.XSL_MAIN.XSLOP_VLOG.RGS.XSL_PARAM_CG_PARREG_RGS_4.morph_dff_st_gr_data_ff.LATC.L2(48) [0] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:3 | RO | RO | constant=0b0000 | |
| 4:51 | RW | RW | OSL_SPAP_A1_ADDR_DIAL: OSL_SPAP_A1 Address Dial, bits 42:51 must be set to 0b0000000000 | |
| 52:62 | RO | RO | constant=0b00000000000 | |
| 63 | RW | RW | OSL_SPAP_A1_VALID_DIAL: OSL_SPAP_A1 valid Dial | |
| OSL_SPAP_A2 Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A82 (SCOM) 00000000134E0010 (PAU_RING) | |||
| Name: | PAU3.XSL.XSL_MAIN.XSLOP_VLOG.RGS.OSL_SPAP_A2 | |||
| Constant(s): | ||||
| Comments: | OSL_SPAP_A2 Register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 4:51 | PAU3.XSL.XSL_MAIN.XSLOP_VLOG.RGS.XSL_PARAM_CG_PARREG_RGS_15.morph_dff_st_gr_data_ff.LATC.L2(0:47) [000000000000000000000000000000000000000000000000] | |||
| 63 | PAU3.XSL.XSL_MAIN.XSLOP_VLOG.RGS.XSL_PARAM_CG_PARREG_RGS_15.morph_dff_st_gr_data_ff.LATC.L2(48) [0] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:3 | RO | RO | constant=0b0000 | |
| 4:51 | RW | RW | OSL_SPAP_A2_ADDR_DIAL: OSL_SPAP_A2 Address Dial, bits 42:51 must be set to 0b0000000000 | |
| 52:62 | RO | RO | constant=0b00000000000 | |
| 63 | RW | RW | OSL_SPAP_A2_VALID_DIAL: OSL_SPAP_A2 valid Dial | |
| OSL_XLATE_CNTL0 Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A84 (SCOM) 00000000134E0020 (PAU_RING) | |||
| Name: | PAU3.XSL.XSL_MAIN.XSLOP_VLOG.RGS.OSL_XLATE_CNTL0 | |||
| Constant(s): | ||||
| Comments: | OSL_XLATE_CNTL0 Register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 3 | PAU3.XSL.XSL_MAIN.XSLOP_VLOG.RGS.XSL_PARAM_CG_PARREG_RGS_14.morph_dff_st_gr_data_ff.LATC.L2(0) [0] | |||
| 6:7 | PAU3.XSL.XSL_MAIN.XSLOP_VLOG.RGS.morph_dff_st_rg_atcc0_fsm_cur_state.LATC.L2(0:1) [00] | |||
| 9:11 | PAU3.XSL.XSL_MAIN.XSLOP_VLOG.RGS.XSL_PARAM_CG_PARREG_RGS_14.morph_dff_st_gr_data_ff.LATC.L2(1:3) [000] | |||
| 14:15 | PAU3.XSL.XSL_MAIN.XSLOP_VLOG.RGS.morph_dff_st_rg_cacc0_fsm_cur_state.LATC.L2(0:1) [00] | |||
| 16:51 | PAU3.XSL.XSL_MAIN.XSLOP_VLOG.RGS.XSL_PARAM_CG_PARREG_RGS_14.morph_dff_st_gr_data_ff.LATC.L2(4:39) [000000000000000000000000000000000000] | |||
| 54:55 | PAU3.XSL.XSL_MAIN.XSLOP_VLOG.RGS.morph_dff_st_rg_osl_xlate_cntl0_ss_l.LATC.L2(0:1) [00] | |||
| 63 | PAU3.XSL.XSL_MAIN.XSLOP_VLOG.RGS.XSL_PARAM_CG_PARREG_RGS_14.morph_dff_st_gr_data_ff.LATC.L2(40) [0] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:2 | RO | RO | constant=0b000 | |
| 3 | RW | RW | OSL_XLATE_CNTL0_CC_DIAL: OSL_XLATE_CNTL0 cc Dial | |
| 4:5 | RO | RO | constant=0b00 | |
| 6:7 | ROX | ROX | OSL_XLATE_CNTL0_CS_DIAL: OSL_XLATE_CNTL0 cs Dial | |
| 8 | RO | RO | constant=0b0 | |
| 9:10 | RW | RW | OSL_XLATE_CNTL0_DAT_DIAL: OSL_XLATE_CNTL0 dat Dial | |
| 11 | RW | RW | OSL_XLATE_CNTL0_AC_DIAL: OSL_XLATE_CNTL0 ac Dial | |
| 12:13 | RO | RO | constant=0b00 | |
| 14:15 | ROX | ROX | OSL_XLATE_CNTL0_AS_DIAL: OSL_XLATE_CNTL0 as Dial | |
| 16:31 | RW | RW | OSL_XLATE_CNTL0_DABDF_DIAL: OSL_XLATE_CNTL0 dabdf Dial | |
| 32:51 | RW | RW | OSL_XLATE_CNTL0_DAPASID_DIAL: OSL_XLATE_CNTL0 dapasid Dial | |
| 52:53 | RO | RO | constant=0b00 | |
| 54:55 | ROX | ROX | OSL_XLATE_CNTL0_SS_DIAL: OSL_XLATE_CNTL0 SS Dial | |
| 56:62 | RO | RO | constant=0b0000000 | |
| 63 | RW | RW | OSL_XLATE_CNTL0_SC_DIAL: OSL_XLATE_CNTL0 SC Dial | |
| OSL_XLATE_CNTL1 Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A85 (SCOM) 00000000134E0028 (PAU_RING) | |||
| Name: | PAU3.XSL.XSL_MAIN.XSLOP_VLOG.RGS.OSL_XLATE_CNTL1 | |||
| Constant(s): | ||||
| Comments: | OSL_XLATE_CNTL1 Register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 3 | PAU3.XSL.XSL_MAIN.XSLOP_VLOG.RGS.XSL_PARAM_CG_PARREG_RGS_11.morph_dff_st_gr_data_ff.LATC.L2(0) [0] | |||
| 6:7 | PAU3.XSL.XSL_MAIN.XSLOP_VLOG.RGS.morph_dff_st_rg_atcc1_fsm_cur_state.LATC.L2(0:1) [00] | |||
| 9:11 | PAU3.XSL.XSL_MAIN.XSLOP_VLOG.RGS.XSL_PARAM_CG_PARREG_RGS_11.morph_dff_st_gr_data_ff.LATC.L2(1:3) [000] | |||
| 14:15 | PAU3.XSL.XSL_MAIN.XSLOP_VLOG.RGS.morph_dff_st_rg_cacc1_fsm_cur_state.LATC.L2(0:1) [00] | |||
| 16:51 | PAU3.XSL.XSL_MAIN.XSLOP_VLOG.RGS.XSL_PARAM_CG_PARREG_RGS_11.morph_dff_st_gr_data_ff.LATC.L2(4:39) [000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:2 | RO | RO | constant=0b000 | |
| 3 | RW | RW | OSL_XLATE_CNTL1_CC_DIAL: OSL_XLATE_CNTL1 cc Dial | |
| 4:5 | RO | RO | constant=0b00 | |
| 6:7 | ROX | ROX | OSL_XLATE_CNTL1_CS_DIAL: OSL_XLATE_CNTL1 cs Dial | |
| 8 | RO | RO | constant=0b0 | |
| 9:10 | RW | RW | OSL_XLATE_CNTL1_DAT_DIAL: OSL_XLATE_CNTL1 dat Dial | |
| 11 | RW | RW | OSL_XLATE_CNTL1_AC_DIAL: OSL_XLATE_CNTL1 ac Dial | |
| 12:13 | RO | RO | constant=0b00 | |
| 14:15 | ROX | ROX | OSL_XLATE_CNTL1_AS_DIAL: OSL_XLATE_CNTL1 as Dial | |
| 16:31 | RW | RW | OSL_XLATE_CNTL1_DABDF_DIAL: OSL_XLATE_CNTL1 dabdf Dial | |
| 32:51 | RW | RW | OSL_XLATE_CNTL1_DAPASID_DIAL: OSL_XLATE_CNTL1 dapasid Dial | |
| 52:63 | RO | RO | constant=0b000000000000 | |
| osl_xlate_cfg0 Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A88 (SCOM) 00000000134E0040 (PAU_RING) | |||
| Name: | PAU3.XSL.XSL_MAIN.XSLOP_VLOG.RGS.OSL_XLATE_CFG0 | |||
| Constant(s): | ||||
| Comments: | osl_xlate_cfg0 Register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 33:34 | PAU3.XSL.XSL_MAIN.XSLOP_VLOG.RGS.morph_dff_st_rg_osl_xlate_cfg0_kill_xlate_type_l.LATC.L2(0:1) [00] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | OSL_XLATE_CFG0_MULTI_AFU_DIAL: osl_xlate_cfg0 multi_afu Dial | |
| 1 | RO | RO | constant=0b0 | |
| 2 | RW | RW | OSL_XLATE_CFG0_64K_PG_DISABLE_DIAL: osl_xlate_cfg0 Disable 64K page size Support Dial | |
| 3 | RW | RW | OSL_XLATE_CFG0_2M_PG_DISABLE_DIAL: osl_xlate_cfg0 Disable 2m page sizeSupport Dial | |
| 4:31 | RO | RO | constant=0b0000000000000000000000000000 | |
| 32 | RW | RW | OSL_XLATE_CFG0_OPENCAPI3_DIAL: osl_xlate_cfg0 XSLOP works in OPENCAPI 3 mode Dial | |
| 33:34 | RW | RW | OSL_XLATE_CFG0_KILL_XLATE_TYPE_DIAL: osl_xlate_cfg0 Kill Xlate Type. OC4.0 Dial | |
| 35:63 | RO | RO | constant=0b00000000000000000000000000000 | |
| osl_xlate_cfg1 Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A89 (SCOM) 00000000134E0048 (PAU_RING) | |||
| Name: | PAU3.XSL.XSL_MAIN.XSLOP_VLOG.RGS.OSL_XLATE_CFG1 | |||
| Constant(s): | ||||
| Comments: | osl_xlate_cfg1 Register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 33:34 | PAU3.XSL.XSL_MAIN.XSLOP_VLOG.RGS.morph_dff_st_rg_osl_xlate_cfg1_kill_xlate_type_l.LATC.L2(0:1) [00] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | OSL_XLATE_CFG1_MULTI_AFU_DIAL: osl_xlate_cfg1 multi_afu Dial | |
| 1 | RO | RO | constant=0b0 | |
| 2 | RW | RW | OSL_XLATE_CFG1_64K_PG_DISABLE_DIAL: osl_xlate_cfg1 Disable 64K page size Support Dial | |
| 3 | RW | RW | OSL_XLATE_CFG1_2M_PG_DISABLE_DIAL: osl_xlate_cfg1 Disable 2m page sizeSupport Dial | |
| 4:31 | RO | RO | constant=0b0000000000000000000000000000 | |
| 32 | RW | RW | OSL_XLATE_CFG1_OPENCAPI3_DIAL: osl_xlate_cfg1 XSLOP works in OPENCAPI 3 mode Dial | |
| 33:34 | RW | RW | OSL_XLATE_CFG1_KILL_XLATE_TYPE_DIAL: osl_xlate_cfg1 Kill Xlate Type. OC4.0 Dial | |
| 35:63 | RO | RO | constant=0b00000000000000000000000000000 | |
| osl_xlate_cfg2 Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A8A (SCOM) 00000000134E0050 (PAU_RING) | |||
| Name: | PAU3.XSL.XSL_MAIN.XSLOP_VLOG.RGS.OSL_XLATE_CFG2 | |||
| Constant(s): | ||||
| Comments: | osl_xlate_cfg2 Register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 33:34 | PAU3.XSL.XSL_MAIN.XSLOP_VLOG.RGS.morph_dff_st_rg_osl_xlate_cfg2_kill_xlate_type_l.LATC.L2(0:1) [00] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:1 | RO | RO | constant=0b00 | |
| 2 | RW | RW | OSL_XLATE_CFG2_64K_PG_DISABLE_DIAL: osl_xlate_cfg2 Disable 64K page size Support Dial | |
| 3 | RW | RW | OSL_XLATE_CFG2_2M_PG_DISABLE_DIAL: osl_xlate_cfg2 Disable 2m page sizeSupport Dial | |
| 4 | RW | RW | OSL_XLATE_CFG2_AME_DISABLE_DIAL: osl_xlate_cfg2 Disable AME function Dial | |
| 5:32 | RO | RO | constant=0b0000000000000000000000000000 | |
| 33:34 | RW | RW | OSL_XLATE_CFG2_KILL_XLATE_TYPE_DIAL: osl_xlate_cfg2 Kill Xlate Type. OC4.0 Dial | |
| 35:63 | RO | RO | constant=0b00000000000000000000000000000 | |
| INV_ERAT Write Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A8C (SCOM) 00000000134E0060 (PAU_RING) | |||
| Name: | PAU3.XSL.XSL_MAIN.XSLOP_VLOG.RGS.INV_ERAT_WR | |||
| Constant(s): | ||||
| Comments: | INV_ERAT Write Register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:8 | PAU3.XSL.XSL_MAIN.XSLOP_VLOG.RGS.XSL_PARAM_CG_PARREG_RGS_5.morph_dff_st_gr_data_ff.LATC.L2(0:8) [000000000] | |||
| 10:63 | PAU3.XSL.XSL_MAIN.XSLOP_VLOG.RGS.XSL_PARAM_CG_PARREG_RGS_5.morph_dff_st_gr_data_ff.LATC.L2(9:62) [000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | WOX | WOX | INV_ERAT_MLPID_DIAL: INV_ERAT_WR mlpid Dial | |
| 1 | WOX | WOX | INV_ERAT_MPID_DIAL: INV_ERAT_WR mpid Dial | |
| 2 | WOX | WOX | INV_ERAT_MADDR_DIAL: INV_ERAT_WR maddr Dial | |
| 3 | WOX | WOX | INV_ERAT_INVR_DIAL: INV_ERAT_WR invr Dial | |
| 4 | WOX | WOX | INV_ERAT_PRS_DIAL: INV_ERAT_WR prs Dial | |
| 5:7 | WOX | WOX | INV_ERAT_PAGESIZE_DIAL: INV_ERAT_WR pagesize Dial | |
| 8 | WOX | WOX | INV_ERAT_INVALL_DIAL: INV_ERAT_WR invall Dial | |
| 9 | RO | RO | constant=0b0 | |
| 10 | WOX | WOX | INV_ERAT_SEGSIZE_DIAL: INV_ERAT_WR segsize Dial | |
| 11 | WOX | WOX | INV_ERAT_INVEA_DIAL: INV_ERAT_WR invea Dial | |
| 12:63 | WOX | WOX | INV_ERAT_INVADDR_DIAL: INV_ERAT_WR invaddr Dial | |
| INV_LPP Read Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A8D (SCOM) 00000000134E0068 (PAU_RING) | |||
| Name: | PAU3.XSL.XSL_MAIN.XSLOP_VLOG.RGS.INV_LPP | |||
| Constant(s): | ||||
| Comments: | INV_LPP Read Register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 12:31 | PAU3.XSL.XSL_MAIN.XSLOP_VLOG.RGS.XSL_PARAM_CG_PARREG_RGS_9.morph_dff_st_gr_data_ff.LATC.L2(0:19) [00000000000000000000] | |||
| 52:63 | PAU3.XSL.XSL_MAIN.XSLOP_VLOG.RGS.XSL_PARAM_CG_PARREG_RGS_9.morph_dff_st_gr_data_ff.LATC.L2(20:31) [000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:11 | RO | RO | constant=0b000000000000 | |
| 12:31 | RW | RW | INV_LPP_PID_DIAL: INV_LPP PID Dial | |
| 32:51 | RO | RO | constant=0b00000000000000000000 | |
| 52:63 | RW | RW | INV_LPP_LPID_DIAL: INV_LPP LPID Dial | |
| OSL_CCINV Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A8E (SCOM) 00000000134E0070 (PAU_RING) | |||
| Name: | PAU3.XSL.XSL_MAIN.XSLOP_VLOG.RGS.OSL_CCINV | |||
| Constant(s): | ||||
| Comments: | OSL_CCINV Register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 47:63 | PAU3.XSL.XSL_MAIN.XSLOP_VLOG.RGS.XSL_PARAM_CG_PARREG_RGS_13.morph_dff_st_gr_data_ff.LATC.L2(1:17) [00000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:14 | RO | RO | constant=0b000000000000000 | |
| 15 | WOX_1P | WOX_1P | PSL_CCINV_REMOVE_DIAL: OSL_CCINV remove Dial | |
| 16 | ROX | ROX | PSL_CCINV_PENDING_DIAL: OSL_CCINV pending Dial | |
| 17:46 | RO | RO | constant=0b000000000000000000000000000000 | |
| 47:63 | RW | RW | PSL_CCINV_LINK_DIAL: OSL_CCINV link Dial | |
| XSL_GP Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A90 (SCOM) 00000000134E0080 (PAU_RING) | |||
| Name: | PAU3.XSL.XSL_MAIN.XSLOP_VLOG.RGS.XSL_GP | |||
| Constant(s): | ||||
| Comments: | XSL_GP Register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.XSL.XSL_MAIN.XSLOP_VLOG.RGS.XSL_PARAM_CG_PARREG_RGS_7.morph_dff_st_gr_data_ff.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:63 | RW | RW | XSL_GP_BITS_DIAL: XSL_GP bits Dial | |
| XSL_DEF Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A91 (SCOM) 00000000134E0088 (PAU_RING) | |||
| Name: | PAU3.XSL.XSL_MAIN.XSLOP_VLOG.RGS.XSL_DEF | |||
| Constant(s): | ||||
| Comments: | XSL_DEF Register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:3 | PAU3.XSL.XSL_MAIN.XSLOP_VLOG.RGS.XSL_PARAM_CG_PARREG_RGS_10.morph_dff_st_gr_data_ff.LATC.L2(0:3) [0000] | |||
| 5:26 | PAU3.XSL.XSL_MAIN.XSLOP_VLOG.RGS.XSL_PARAM_CG_PARREG_RGS_10.morph_dff_st_gr_data_ff.LATC.L2(4:25) [0000000000000000000000] | |||
| 28:36 | PAU3.XSL.XSL_MAIN.XSLOP_VLOG.RGS.XSL_PARAM_CG_PARREG_RGS_10.morph_dff_st_gr_data_ff.LATC.L2(26:34) [000000000] | |||
| 61:63 | PAU3.XSL.XSL_MAIN.XSLOP_VLOG.RGS.XSL_PARAM_CG_PARREG_RGS_10.morph_dff_st_gr_data_ff.LATC.L2(35:37) [000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:3 | RW | RW | XSL_DEF_MEE_DIAL: XSL_DEF mee Dial | |
| 4 | RO | RO | constant=0b0 | |
| 5:7 | RW | RW | XSL_DEF_ITL_DIAL: XSL_DEF itl Dial | |
| 8:12 | RW | RW | XSL_DEF_ITE_DIAL: XSL_DEF ite Dial | |
| 13:16 | RW | RW | XSL_DEF_ERT_SIZE_DIAL: XSL_DEF ert_size Dial | |
| 17:20 | RW | RW | XSL_DEF_CTX_SIZE_DIAL: XSL_DEF ctx_size Dial | |
| 21:24 | RW | RW | XSL_DEF_TAD_SIZE_DIAL: XSL_DEF tad_size Dial | |
| 25 | RW | RW | XSL_DEF_CTXM_DIAL: XSL_DEF ctxm Dial | |
| 26 | RW | RW | XSL_DEF_ECOE_ASSIGN_METHOD_DIAL: XSL_DEF ecoe_assign_method Dial | |
| 27 | RO | RO | constant=0b0 | |
| 28:31 | RW | RW | XSL_DEF_ECOEE_DIAL: XSL_DEF ecoee Dial | |
| 32:35 | RW | RW | XSL_DEF_TCOEE_DIAL: XSL_DEF tcoee Dial | |
| 36 | RW | RW | XSL_DEF_DIS_ECOE_BLOCKER_DIAL: XSL_DEF dis_ecoe_blocker Dial | |
| 37:60 | RO | RO | constant=0b000000000000000000000000 | |
| 61:62 | RW | RW | XSL_DEF_CO_RTRY_LIM_DIAL: XSL_DEF co_rtry_lim Dial | |
| 63 | RW | RW | XSL_DEF_DEFE_DIAL: XSL_DEF defe Dial | |
| XSL_FEC Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A92 (SCOM) 00000000134E0090 (PAU_RING) | |||
| Name: | PAU3.XSL.XSL_MAIN.XSLOP_VLOG.RGS.XSL_FEC | |||
| Constant(s): | ||||
| Comments: | XSL_FEC Register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.XSL.XSL_MAIN.XSLOP_VLOG.RGS.XSL_PARAM_CG_PARREG_RGS_12.morph_dff_st_gr_data_ff.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX_WCLEAR | RWX_WCLEAR | XSL_FEC_EVT: XSL_FEC evt - FEC Reg Valid Bit | |
| 1:7 | ROX | ROX | XSL_FEC_ET: XSL_FEC et - 7 Bit Error Encode Encode Error 01 xlbi_reg_overrun 02 unexpected_itag0 03 unexpected_itag1 04 bad_pee_cmpl 05 bad_cor_cmpl 06 spap_invalid 07 pee_sws_reset 08 blmf_prot_err 09 non_val_ta 0a xlate_rel_err 0b epoch_timeout 0c insecure 0d xlate_in_suspend 0e unsup_page_size 0f xlat_rel_fail_pi 10 kxd_fail | |
| 8:63 | ROX | ROX | XSL_FEC_EI: XSL_FEC ei - 56 Bits Error Capture Information | |
| OSL_EPOCH_CTL Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A93 (SCOM) 00000000134E0098 (PAU_RING) | |||
| Name: | PAU3.XSL.XSL_MAIN.XSLOP_VLOG.RGS.OSL_EPOCH_CTL | |||
| Constant(s): | ||||
| Comments: | OSL_EPOCH_CTL Register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:31 | PAU3.XSL.XSL_MAIN.XSLOP_VLOG.RGS.XSL_PARAM_CG_PARREG_RGS_8.morph_dff_st_gr_data_ff.LATC.L2(0:31) [00000000000000000000000000000000] | |||
| 33:35 | PAU3.XSL.XSL_MAIN.XSLOP_VLOG.RGS.XSL_PARAM_CG_PARREG_RGS_8.morph_dff_st_gr_data_ff.LATC.L2(32:34) [000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:31 | RW | RW | OSL_EPOCH_CTL_EPCHCNT_DIAL: OSL_EPOCH_CTL epchcnt Dial | |
| 32 | RO | RO | constant=0b0 | |
| 33:35 | RW | RW | OSL_EPOCH_CTL_EPCHTO_DIAL: OSL_EPOCH_CTL epchto Dial | |
| 36:63 | RO | RO | constant=0b0000000000000000000000000000 | |
| XSL_DBG_WR Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A94 (SCOM) 00000000134E00A0 (PAU_RING) | |||
| Name: | PAU3.XSL.XSL_MAIN.XSLOP_VLOG.RGS.XSL_DBG_WR | |||
| Constant(s): | ||||
| Comments: | XSL_DBG_WR Register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:2 | PAU3.XSL.XSL_MAIN.XSLOP_VLOG.RGS.XSL_PARAM_CG_PARREG_RGS_2.morph_dff_st_gr_data_ff.LATC.L2(0:2) [000] | |||
| 8:32 | PAU3.XSL.XSL_MAIN.XSLOP_VLOG.RGS.XSL_PARAM_CG_PARREG_RGS_2.morph_dff_st_gr_data_ff.LATC.L2(3:27) [0000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | WO | WO | XSL_DBG_TO_DIAL: XSL_DBG_WR trcovrd Dial | |
| 1 | WO | WO | XSL_DBG_TRNSO_DIAL: XSL_DBG_WR trnso Dial | |
| 2 | WO | WO | XSL_DBG_ERTO_DIAL: XSL_DBG_WR erto Dial | |
| 3:7 | RO | RO | constant=0b00000 | |
| 8:23 | WO | WO | XSL_DBG_DVS_DIAL: XSL_DBG_WR dvs Dial | |
| 24:32 | WO | WO | XSL_DBG_ITAG_INIT_DIAL: XSL_DBG_WR itag_init Dial | |
| 33:63 | RO | RO | constant=0b0000000000000000000000000000000 | |
| XSL_EEI Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A95 (SCOM) 00000000134E00A8 (PAU_RING) | |||
| Name: | PAU3.XSL.XSL_MAIN.XSLOP_VLOG.RGS.XSL_EEI | |||
| Constant(s): | ||||
| Comments: | XSL_EEI Register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0 | PAU3.XSL.XSL_MAIN.XSLOP_VLOG.RGS.XSL_PARAM_CG_PARREG_RGS_3.morph_dff_st_gr_data_ff.LATC.L2(0) [0] | |||
| 2:15 | PAU3.XSL.XSL_MAIN.XSLOP_VLOG.RGS.XSL_PARAM_CG_PARREG_RGS_3.morph_dff_st_gr_data_ff.LATC.L2(1:14) [00000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX | RWX | XSL_EEI_ECMD_DIAL: XSL_EEI ecmd Dial | |
| 1 | RO | RO | constant=0b0 | |
| 2:7 | RW | RW | XSL_EEI_ETYPE_DIAL: XSL_EEI etype Dial | |
| 8:15 | RW | RW | XSL_EEI_RSPCODE_DIAL: XSL_EEI rspcode Dial | |
| 16:63 | RO | RO | constant=0b000000000000000000000000000000000000000000000000 | |
| XSL_ATD Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A96 (SCOM) 00000000134E00B0 (PAU_RING) | |||
| Name: | PAU3.XSL.XSL_MAIN.XSLOP_VLOG.RGS.XSL_ATD | |||
| Constant(s): | ||||
| Comments: | XSL_ATD Register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.XSL.XSL_MAIN.XSLOP_VLOG.RGS.XSL_PARAM_CG_PARREG_RGS_0.morph_dff_st_gr_data_ff.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:51 | RWX | RWX | XSL_ATD_DIAL: XSL_ATD Dial | |
| 52 | WOX | WOX | XSL_ATD_DIAL: XSL_ATD Dial | |
| 53:63 | RWX | RWX | XSL_ATD_DIAL: XSL_ATD Dial | |
| XSL_PMON Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A97 (SCOM) 00000000134E00B8 (PAU_RING) | |||
| Name: | PAU3.XSL.XSL_MAIN.XSLOP_VLOG.RGS.XSL_PMON | |||
| Constant(s): | ||||
| Comments: | Each Dial selects one of 36 PMON signals to send to XSL PMULet. Decimal Encodes: 00 OTL translation interface - Good translation response 01 OTL translation interface - Bad translation response 02 ERAT miss - Brick 0 03 ERAT hit - Brick 0 04 CTX miss - Brick 0 05 � CTX hit - Brick 0 06 ERAT miss - Brick 1 07 ERAT hit - Brick 1 08 CTX miss - Brick 1 09 � CTX hit - Brick 1 10 Checkout Response 4k Page 11 Chcekout Response 64k Page 12 Checkout Response >64k Page 13 CTX invalidate cache hit (LLMCD) 14 ERAT invalidate cache hit 15 Invalidate checks ERAT but finds nothing 16 Invalidate checks ERAT and IDB and finds nothing 17 Invalidate hits IDB 18 Invalidate hits the TRKR 19 Checkout is retried more than once due to TRKR hit 20 PEE read sent 21 Checkout Request Sent 22 Checkout Request sent from MSE0 23 MSE0 waiting for Checkout response 24 No Checkout credit available - Brick 0 25 No Checkout credit available - Brick 1 26 TRANSLATE_Valid is high, TRANSLATE_RDY is low 27 KILL XLATE Response is slow 28 Xlate Touch Request 29 Xlate Touch Request, but no TA TAG available. 30 Xlate Release 31 ERAT Castout Generated 32 ERAT miss - Brick 2 33 ERAT hit - Brick 2 34 CTX miss - Brick 2 35 � CTX hit - Brick 2 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 2:7 | PAU3.XSL.XSL_MAIN.XSLOP_VLOG.RGS.XSL_PARAM_CG_PARREG_RGS_6.morph_dff_st_gr_data_ff.LATC.L2(0:5) [000000] | |||
| 10:15 | PAU3.XSL.XSL_MAIN.XSLOP_VLOG.RGS.XSL_PARAM_CG_PARREG_RGS_6.morph_dff_st_gr_data_ff.LATC.L2(6:11) [000000] | |||
| 18:23 | PAU3.XSL.XSL_MAIN.XSLOP_VLOG.RGS.XSL_PARAM_CG_PARREG_RGS_6.morph_dff_st_gr_data_ff.LATC.L2(12:17) [000000] | |||
| 26:31 | PAU3.XSL.XSL_MAIN.XSLOP_VLOG.RGS.XSL_PARAM_CG_PARREG_RGS_6.morph_dff_st_gr_data_ff.LATC.L2(18:23) [000000] | |||
| 34:39 | PAU3.XSL.XSL_MAIN.XSLOP_VLOG.RGS.XSL_PARAM_CG_PARREG_RGS_6.morph_dff_st_gr_data_ff.LATC.L2(24:29) [000000] | |||
| 42:47 | PAU3.XSL.XSL_MAIN.XSLOP_VLOG.RGS.XSL_PARAM_CG_PARREG_RGS_6.morph_dff_st_gr_data_ff.LATC.L2(30:35) [000000] | |||
| 50:55 | PAU3.XSL.XSL_MAIN.XSLOP_VLOG.RGS.XSL_PARAM_CG_PARREG_RGS_6.morph_dff_st_gr_data_ff.LATC.L2(36:41) [000000] | |||
| 58:63 | PAU3.XSL.XSL_MAIN.XSLOP_VLOG.RGS.XSL_PARAM_CG_PARREG_RGS_6.morph_dff_st_gr_data_ff.LATC.L2(42:47) [000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:1 | RO | RO | constant=0b00 | |
| 2:7 | RW | RW | XSL_PMON_PMONSEL0_DIAL: XSL_PMON pmonsel0 Dial | |
| 8:9 | RO | RO | constant=0b00 | |
| 10:15 | RW | RW | XSL_PMON_PMONSEL1_DIAL: XSL_PMON pmonsel1 Dial | |
| 16:17 | RO | RO | constant=0b00 | |
| 18:23 | RW | RW | XSL_PMON_PMONSEL2_DIAL: XSL_PMON pmonsel2 Dial | |
| 24:25 | RO | RO | constant=0b00 | |
| 26:31 | RW | RW | XSL_PMON_PMONSEL3_DIAL: XSL_PMON pmonsel3 Dial | |
| 32:33 | RO | RO | constant=0b00 | |
| 34:39 | RW | RW | XSL_PMON_PMONSEL4_DIAL: XSL_PMON pmonsel4 Dial | |
| 40:41 | RO | RO | constant=0b00 | |
| 42:47 | RW | RW | XSL_PMON_PMONSEL5_DIAL: XSL_PMON pmonsel5 Dial | |
| 48:49 | RO | RO | constant=0b00 | |
| 50:55 | RW | RW | XSL_PMON_PMONSEL6_DIAL: XSL_PMON pmonsel6 Dial | |
| 56:57 | RO | RO | constant=0b00 | |
| 58:63 | RW | RW | XSL_PMON_PMONSEL7_DIAL: XSL_PMON pmonsel7 Dial | |
| GPU0-Memory BAR | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A9A (SCOM) 00000000134E00D0 (PAU_RING) | |||
| Name: | PAU3.XSL.XSL_MAIN.GPU0_BAR | |||
| Constant(s): | ||||
| Comments: | BAR register defining GPU Mem addresses serviced by brick 0 connected to this stack. Note: This register should be set to the same value for each brick/stack. MDials have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:51 | PAU3.XSL.XSL_MAIN.GPU0_BAR_Q_0_INST.LATC.L2(0:51) [0000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_GPU0_BAR_ENABLE: Enable for this BAR (0=disabled, 1=enabled) for brick 0 | |
| 1:35 | RW | RW | CONFIG_GPU0_BAR_ADDR_MASK: BAR Address/Mask bits 1:35 for brick 0 In Small-BAR mode (see bit 36): 1:7 = Base_Addr(13:19) = 16T slice 8:21 = Base_Addr(20:33) = 1G address in slice 22:35 = Base_Mask(20:33) = 1G...16T BAR size. (Note: Mask limited to 1G...4T in Axone and P10 w/ GPU systems) In Large-BAR mode (see bit 36): 1 = '1' to match MemSel = addr(13:14) = 0b00 2 = '1' to match MemSel = addr(13:14) = 0b01 3 = '1' to match MemSel = addr(13:14) = 0b10 4:35 = Topology_Id_Mask(0:31) when chip_eq_group=0, TIM(0:31) bit 'i' corresponds to addr(15:19) = 'i' when chip_eq_group=1, TIM(0:31) bit 'i' corresponds to (addr(15:16) & addr(19:21)) = 'i' | |
| 36 | RW | RW | CONFIG_GPU0_BAR_SL_MODE: 0/1 = Small-BAR/Large-BAR Mode selector | |
| 37 | RW | RW | CONFIG_GPU0_BAR_4T_LIMIT: 0 = no limit, 16T slices can be used. 1 = limit slices to 4T. -> when chip_eq_group=0, addr(20:21) must match bar_4t_select -> when chip_eq_group=1, addr(17:18) must match bar_4t_select limit=1 is used in P10 systems w/ a GPU or in Axone systems | |
| 38:39 | RW | RW | CONFIG_GPU0_BAR_4T_SELECT: when bar_4t_limit=1 this field selects the value in addr(20:21) or addr(17:18) to match | |
| 40:43 | RW | RW | CONFIG_GPU0_BAR_MODE: Hash mode of the BAR for brick 0: if bar_extended_mode == 0: 0 = (single) match on all address in addr/size 1 = (dual.0) match if hashbits(7)=0 2 = (dual.1) match if hashbits(7)=1 3 = (triple.0) match if hashbits%3=0 4 = (triple.1) match if hashbits%3=1 5 = (triple.2) match if hashbits%3=2 6 = (quad.0) match if hashbits(6:7)=0 7 = (quad.1) match if hashbits(6:7)=1 8 = (quad.2) match if hashbits(6:7)=2 9 = (quad.3) match if hashbits(6:7)=3 10 = (six.0) match if hashbits%3=0 and hashbits(7)=0 11 = (six.1) match if hashbits%3=0 and hashbits(7)=1 12 = (six.2) match if hashbits%3=1 and hashbits(7)=0 13 = (six.3) match if hashbits%3=1 and hashbits(7)=1 14 = (six.4) match if hashbits%3=2 and hashbits(7)=0 15 = (six.5) match if hashbits%3=2 and hashbits(7)=1 if bar_extended_mode == 1: 0 = (oct.0) match if hashbits(5:7)=0 1 = (oct.1) match if hashbits(5:7)=1 2 = (oct.2) match if hashbits(5:7)=2 3 = (oct.3) match if hashbits(5:7)=3 4 = (oct.4) match if hashbits(5:7)=4 5 = (oct.5) match if hashbits(5:7)=5 6 = (oct.6) match if hashbits(5:7)=6 7 = (oct.7) match if hashbits(5:7)=7 others = reserved | |
| 44 | RW | RW | CONFIG_GPU0_BAR_GRANULE: Hash boundary for brick 0: 0 = hash on 512B boundary (hashbits(0:7)=addr(47:54)) 1 = hash on 1024B boundary (hashbits(0:7)=addr(46:53)) | |
| 45 | RW | RW | CONFIG_GPU0_BAR_POISON: on failed access return all ones 0/1 = with good ECC / with SUE ECC. | |
| 46 | RW | RW | CONFIG_GPU0_BAR_M2MODE: 0 = OpenCAPI AFU M1 mode / 1 = OpenCAPI AFU M2 mode Has no effect when in NVLink mode | |
| 47 | RW | RW | CONFIG_GPU0_BAR_PA_IGNORE_MODE: Set to '1' for RA-to-PA conversion to ignore the mode field | |
| 48 | RW | RW | CONFIG_GPU0_BAR_SECURE_A12: P10 Only: this specifies the addr(12) value to match for this BAR. Can only be set to one in P10 and only when SMF_CONFIG=0b11. | |
| 49 | RW | RW | CONFIG_GPU0_BAR_CHIP_EQ_GROUP: Axone Only: this specifies that the system is in chip=group mode. This bit should only be set when sl_mode=1 and 4t_limit=1. 0/1 = TIM(0:31) applies to addr(15:19) / TIM(0:31) applies to (addr(15:16) & addr(19:21)). | |
| 50 | RW | RW | CONFIG_GPU0_BAR_EXTENDED_MODE: 0/1 = bar_mode selects 1,2,3,4,6 way hashing / bar_mode selects 8-way hashing | |
| 51 | RW | RW | CONFIG_GPU0_BAR_RESERVED: reserved | |
| 52:63 | RO | RO | constant=0b000000000000 | |
| GPU1-Memory BAR | ||||
|---|---|---|---|---|
| Addr: |
0000000011010A9B (SCOM) 00000000134E00D8 (PAU_RING) | |||
| Name: | PAU3.XSL.XSL_MAIN.GPU1_BAR | |||
| Constant(s): | ||||
| Comments: | BAR register defining GPU Mem addresses serviced by brick 1 connected to this stack. Note: This register should be set to the same value for each brick/stack. MDials have been created at PAU_STACK_WRAP/PAU_STACKO_WRAP for this register's IDials | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:51 | PAU3.XSL.XSL_MAIN.GPU1_BAR_Q_0_INST.LATC.L2(0:51) [0000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_GPU1_BAR_ENABLE: Enable for this BAR (0=disabled, 1=enabled) for brick 1 | |
| 1:35 | RW | RW | CONFIG_GPU1_BAR_ADDR_MASK: BAR Address/Mask bits 1:35 for brick 1 In Small-BAR mode (see bit 36): 1:7 = Base_Addr(13:19) = 16T slice 8:21 = Base_Addr(20:33) = 1G address in slice 22:35 = Base_Mask(20:33) = 1G...16T BAR size. (Note: Mask limited to 1G...4T in Axone and P10 w/ GPU systems) In Large-BAR mode (see bit 36): 1 = '1' to match MemSel = addr(13:14) = 0b00 2 = '1' to match MemSel = addr(13:14) = 0b01 3 = '1' to match MemSel = addr(13:14) = 0b10 4:35 = Topology_Id_Mask(0:31) when chip_eq_group=0, TIM(0:31) bit 'i' corresponds to addr(15:19) = 'i' when chip_eq_group=1, TIM(0:31) bit 'i' corresponds to (addr(15:16) & addr(19:21)) = 'i' | |
| 36 | RW | RW | CONFIG_GPU1_BAR_SL_MODE: 0/1 = Small-BAR/Large-BAR Mode selector | |
| 37 | RW | RW | CONFIG_GPU1_BAR_4T_LIMIT: 0 = no limit, 16T slices can be used. 1 = limit slices to 4T. -> when chip_eq_group=0, addr(20:21) must match bar_4t_select -> when chip_eq_group=1, addr(17:18) must match bar_4t_select limit=1 is used in P10 systems w/ a GPU or in Axone systems | |
| 38:39 | RW | RW | CONFIG_GPU1_BAR_4T_SELECT: when bar_4t_limit=1 this field selects the value in addr(20:21) or addr(17:18) to match | |
| 40:43 | RW | RW | CONFIG_GPU1_BAR_MODE: Hash mode of the BAR for brick 1: if bar_extended_mode == 0: 0 = (single) match on all address in addr/size 1 = (dual.0) match if hashbits(7)=0 2 = (dual.1) match if hashbits(7)=1 3 = (triple.0) match if hashbits%3=0 4 = (triple.1) match if hashbits%3=1 5 = (triple.2) match if hashbits%3=2 6 = (quad.0) match if hashbits(6:7)=0 7 = (quad.1) match if hashbits(6:7)=1 8 = (quad.2) match if hashbits(6:7)=2 9 = (quad.3) match if hashbits(6:7)=3 10 = (six.0) match if hashbits%3=0 and hashbits(7)=0 11 = (six.1) match if hashbits%3=0 and hashbits(7)=1 12 = (six.2) match if hashbits%3=1 and hashbits(7)=0 13 = (six.3) match if hashbits%3=1 and hashbits(7)=1 14 = (six.4) match if hashbits%3=2 and hashbits(7)=0 15 = (six.5) match if hashbits%3=2 and hashbits(7)=1 if bar_extended_mode == 1: 0 = (oct.0) match if hashbits(5:7)=0 1 = (oct.1) match if hashbits(5:7)=1 2 = (oct.2) match if hashbits(5:7)=2 3 = (oct.3) match if hashbits(5:7)=3 4 = (oct.4) match if hashbits(5:7)=4 5 = (oct.5) match if hashbits(5:7)=5 6 = (oct.6) match if hashbits(5:7)=6 7 = (oct.7) match if hashbits(5:7)=7 others = reserved | |
| 44 | RW | RW | CONFIG_GPU1_BAR_GRANULE: Hash boundary for brick 1: 0 = hash on 512B boundary (hashbits(0:7)=addr(47:54)) 1 = hash on 1024B boundary (hashbits(0:7)=addr(46:53)) | |
| 45 | RW | RW | CONFIG_GPU1_BAR_POISON: on failed access return all ones 0/1 = with good ECC / with SUE ECC. | |
| 46 | RW | RW | CONFIG_GPU1_BAR_M2MODE: 0 = OpenCAPI AFU M1 mode / 1 = OpenCAPI AFU M2 mode Has no effect when in NVLink mode | |
| 47 | RW | RW | CONFIG_GPU1_BAR_PA_IGNORE_MODE: Set to '1' for RA-to-PA conversion to ignore the mode field | |
| 48 | RW | RW | CONFIG_GPU1_BAR_SECURE_A12: P10 Only: this specifies the addr(12) value to match for this BAR. Can only be set to one in P10 and only when SMF_CONFIG=0b11. | |
| 49 | RW | RW | CONFIG_GPU1_BAR_CHIP_EQ_GROUP: Axone Only: this specifies that the system is in chip=group mode. This bit should only be set when sl_mode=1 and 4t_limit=1. 0/1 = TIM(0:31) applies to addr(15:19) / TIM(0:31) applies to (addr(15:16) & addr(19:21)). | |
| 50 | RW | RW | CONFIG_GPU1_BAR_EXTENDED_MODE: 0/1 = bar_mode selects 1,2,3,4,6 way hashing / bar_mode selects 8-way hashing | |
| 51 | RW | RW | CONFIG_GPU1_BAR_RESERVED: reserved | |
| 52:63 | RO | RO | constant=0b000000000000 | |
| xsl_wrap_cfg Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010AA0 (SCOM) 00000000134E0100 (PAU_RING) | |||
| Name: | PAU3.XSL.XSL_MAIN.XSL_WRAP_CFG | |||
| Constant(s): | ||||
| Comments: | xsl_wrap_cfg Register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:7 | PAU3.XSL.XSL_MAIN.XSL_WRAP_CFG_Q_0_INST.LATC.L2(0:7) [00000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | XSLO_CLOCK_ENABLE: XSLO_clock_enable | |
| 1 | RW | RW | XSLO_BLOCK_MEMHIT: XSLO_block_memhit | |
| 2:3 | RW | RW | RESERVED: reserved | |
| 4:7 | RW | RW | XSLO_OTL_REQ_LIMIT: XSLO_OTL_Req_Limit Dial enums: 2=>0b0010 3=>0b0011 4=>0b0100 5=>0b0101 6=>0b0110 7=>0b0111 8=>0b1000 9=>0b1001 10=>0b1010 11=>0b1011 12=>0b1100 13=>0b1101 14=>0b1110 15=>0b1111 | |
| 8:63 | RO | RO | constant=0b00000000000000000000000000000000000000000000000000000000 Dial enums: 2=>0b0010 3=>0b0011 4=>0b0100 5=>0b0101 6=>0b0110 7=>0b0111 8=>0b1000 9=>0b1001 10=>0b1010 11=>0b1011 12=>0b1100 13=>0b1101 14=>0b1110 15=>0b1111 | |
| XSL Array Read Address Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010AA1 (SCOM) 00000000134E0108 (PAU_RING) | |||
| Name: | PAU3.XSL.XSL_MAIN.XSL_ARY_RD_ADDR_REG | |||
| Constant(s): | ||||
| Comments: | XSL array read address register bits(0:2)= 000 - select ERAT0 bits(0:2)= 001 - select ERAT1 bits(0:2)= 010 - select ERAT2 bits(0:2)= 011 - select ERAT3 bits(0:2)= 100 - select TADB bits(0:2)= 101 - select TADBX bits(3:12) - array entry address bits(13:14)= 00 - select entry data(0:63) bits(13:14)= 01 - select entry data(64:127) bits(13:14)= 10 - select entry data(128:191) bits(13:14)= 11 - select entry data(192:197) & ecc(0:23) | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:14 | PAU3.XSL.XSL_MAIN.XSL_ARY_RD_ADDR_REG_Q_0_INST.LATC.L2(0:14) [000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:2 | RW | RW | XSL_ARRAY_SELECT: XSL_array_select | |
| 3:12 | RW | RW | XSL_ARRAY_ENTRY_ADDRESS: XSL_array_entry_address | |
| 13:14 | RW | RW | XSL_ARRAY_DATA_SELECT: XSL_array_data_select | |
| 15:63 | RO | RO | constant=0b0000000000000000000000000000000000000000000000000 | |
| XSL Array Read Function | ||||
|---|---|---|---|---|
| Addr: |
0000000011010AA2 (SCOM) 00000000134E0110 (PAU_RING) | |||
| Name: | PAU3.XSL.XSL_MAIN.XSL_ARY_RD_FUNC | |||
| Constant(s): | ||||
| Comments: | Read data from the selected array and entry as specified in xsl_ary_rd_addr_reg The logic will automatically increment xsl_ary_rd_addr_reg after the read so that repeated reading from this facility would walk through all the data from all of the arrays | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.XSL.XSL_MAIN.SCOM_ARY_RD_DATA64_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:63 | ROX | ROX | XSL_ARY_DATA: xsl_ary_data | |
| xsl_debug0_config Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010AA3 (SCOM) 00000000134E0118 (PAU_RING) | |||
| Name: | PAU3.XSL.XSL_MAIN.XSL_DEBUG0_CONFIG | |||
| Constant(s): | ||||
| Comments: | xsl_debug0_config Register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.XSL.XSL_MAIN.DEBUG0_CONFIG_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:63 | RW | RW | XSL_DEBUG0_CONFIG_DIAL: xsl_debug0_config Register Dial | |
| xsl_debug1_config Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010AA4 (SCOM) 00000000134E0120 (PAU_RING) | |||
| Name: | PAU3.XSL.XSL_MAIN.XSL_DEBUG1_CONFIG | |||
| Constant(s): | ||||
| Comments: | xsl_debug1_config Register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.XSL.XSL_MAIN.DEBUG1_CONFIG_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:63 | RW | RW | XSL_DEBUG1_CONFIG_DIAL: xsl_debug1_config Register Dial | |
| xsl_wrap_error_0 Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010AA6 (SCOM) 00000000134E0130 (PAU_RING) | |||
| Name: | PAU3.XSL.XSL_MAIN.XSL_WRAP_ERROR_0 | |||
| Constant(s): | ||||
| Comments: | xsl_wrap_error_0 Register (c_err_rpt hold(0 to 53)) | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:53 | PAU3.XSL.XSL_MAIN.ERR_RPT0.HOLD_LATCH_INST.HOLD.LATC.L2(0:53) [000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | ROX | ROX | MMIO_INVALIDATE_REQ_WHILE_1_INPROG: mmio_invalidate_req_while_1_inprog | |
| 1 | ROX | ROX | UNEXPECTED_ITAG_PORT_0: unexpected_itag_port_0 | |
| 2 | ROX | ROX | UNEXPECTED_ITAG_PORT_1: unexpected_itag_port_1 | |
| 3 | ROX | ROX | UNEXPECTED_RD_PEE_COMPLETION: unexpected_rd_pee_completion | |
| 4 | ROX | ROX | UNEXPECTED_CO_RESP: unexpected_co_resp | |
| 5 | ROX | ROX | XLAT_REQ_WHILE_SPAP_INVALID: xlat_req_while_spap_invalid | |
| 6 | ROX | ROX | INVALID_PEE: invalid_pee | |
| 7 | ROX | ROX | BLOOM_FILTER_ARY_ERROR: bloom_filter_ary_error | |
| 8 | ROX | ROX | TRANSLATION_REQ_TO_INVALID_TA: translation_req_to_invalid_ta | |
| 9 | ROX | ROX | TA_XLATE_RELEASE_TO_INVALID_TA: ta_xlate_release_to_invalid_ta | |
| 10 | ROX | ROX | TRKR0_SBE_ERROR: trkr0_sbe_error | |
| 11 | ROX | ROX | TRKR1_SBE_ERROR: trkr1_sbe_error | |
| 12 | ROX | ROX | IDBA0_SBE_ERROR: idba0_sbe_error | |
| 13 | ROX | ROX | IDBA1_SBE_ERROR: idba1_sbe_error | |
| 14 | ROX | ROX | FITA_SBE_ERROR: fita_sbe_error | |
| 15 | ROX | ROX | CTX0A_SBE_ERROR: ctx0a_sbe_error | |
| 16 | ROX | ROX | CTX0B_SBE_ERROR: ctx0b_sbe_error | |
| 17 | ROX | ROX | CTX1A_SBE_ERROR: ctx1a_sbe_error | |
| 18 | ROX | ROX | CTX1B_SBE_ERROR: ctx1b_sbe_error | |
| 19 | ROX | ROX | CTX2A_SBE_ERROR: ctx2a_sbe_error | |
| 20 | ROX | ROX | CTX2B_SBE_ERROR: ctx2b_sbe_error | |
| 21 | ROX | ROX | CTX3A_SBE_ERROR: ctx3a_sbe_error | |
| 22 | ROX | ROX | CTX3B_SBE_ERROR: ctx3b_sbe_error | |
| 23 | ROX | ROX | ERT0_LO_SBE_ERROR: ert0_lo_sbe_error | |
| 24 | ROX | ROX | ERT0_MID_SBE_ERROR: ert0_mid_sbe_error | |
| 25 | ROX | ROX | ERT0_HI_SBE_ERROR: ert0_hi_sbe_error | |
| 26 | ROX | ROX | ERT1_LO_SBE_ERROR: ert1_lo_sbe_error | |
| 27 | ROX | ROX | ERT1_MID_SBE_ERROR: ert1_mid_sbe_error | |
| 28 | ROX | ROX | ERT1_HI_SBE_ERROR: ert1_hi_sbe_error | |
| 29 | ROX | ROX | ERT2_LO_SBE_ERROR: ert2_lo_sbe_error | |
| 30 | ROX | ROX | ERT2_MID_SBE_ERROR: ert2_mid_sbe_error | |
| 31 | ROX | ROX | ERT2_HI_SBE_ERROR: ert2_hi_sbe_error | |
| 32 | ROX | ROX | ERT3_LO_SBE_ERROR: ert3_lo_sbe_error | |
| 33 | ROX | ROX | ERT3_MID_SBE_ERROR: ert3_mid_sbe_error | |
| 34 | ROX | ROX | ERT3_HI_SBE_ERROR: ert3_hi_sbe_error | |
| 35 | ROX | ROX | TADB_LO_SBE_ERROR: tadb_lo_sbe_error | |
| 36 | ROX | ROX | TADB_MID_SBE_ERROR: tadb_mid_sbe_error | |
| 37 | ROX | ROX | TADB_HI_SBE_ERROR: tadb_hi_sbe_error | |
| 38 | ROX | ROX | COSB_LO_SBE_ERROR: cosb_lo_sbe_error | |
| 39 | ROX | ROX | COSB_MID_SBE_ERROR: cosb_mid_sbe_error | |
| 40 | ROX | ROX | COSB_HI_SBE_ERROR: cosb_hi_sbe_error | |
| 41 | ROX | ROX | TRKR0_UE_ERROR: trkr0_ue_error | |
| 42 | ROX | ROX | TRKR1_UE_ERROR: trkr1_ue_error | |
| 43 | ROX | ROX | IDBA0_UE_ERROR: idba0_ue_error | |
| 44 | ROX | ROX | IDBA1_UE_ERROR: idba1_ue_error | |
| 45 | ROX | ROX | FITA_UE_ERROR: fita_ue_error | |
| 46 | ROX | ROX | CTX0A_UE_ERROR: ctx0a_ue_error | |
| 47 | ROX | ROX | CTX0B_UE_ERROR: ctx0b_ue_error | |
| 48 | ROX | ROX | CTX1A_UE_ERROR: ctx1a_ue_error | |
| 49 | ROX | ROX | CTX1B_UE_ERROR: ctx1b_ue_error | |
| 50 | ROX | ROX | CTX2A_UE_ERROR: ctx2a_ue_error | |
| 51 | ROX | ROX | CTX2B_UE_ERROR: ctx2b_ue_error | |
| 52 | ROX | ROX | CTX3A_UE_ERROR: ctx3a_ue_error | |
| 53 | ROX | ROX | CTX3B_UE_ERROR: ctx3b_ue_error | |
| 54:63 | RO | RO | constant=0b0000000000 | |
| xsl_wrap_error_1 Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010AA7 (SCOM) 00000000134E0138 (PAU_RING) | |||
| Name: | PAU3.XSL.XSL_MAIN.XSL_WRAP_ERROR_1 | |||
| Constant(s): | ||||
| Comments: | xsl_wrap_error_1 Register (c_err_rpt hold(54:84)) | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:30 | PAU3.XSL.XSL_MAIN.ERR_RPT1.HOLD_LATCH_INST.HOLD.LATC.L2(0:30) [0000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | ROX | ROX | ERT0_LO_UE_ERROR: ert0_lo_ue_error | |
| 1 | ROX | ROX | ERT0_MID_UE_ERROR: ert0_mid_ue_error | |
| 2 | ROX | ROX | ERT0_HI_UE_ERROR: ert0_hi_ue_error | |
| 3 | ROX | ROX | ERT1_LO_UE_ERROR: ert1_lo_ue_error | |
| 4 | ROX | ROX | ERT1_MID_UE_ERROR: ert1_mid_ue_error | |
| 5 | ROX | ROX | ERT1_HI_UE_ERROR: ert1_hi_ue_error | |
| 6 | ROX | ROX | ERT2_LO_UE_ERROR: ert2_lo_ue_error | |
| 7 | ROX | ROX | ERT2_MID_UE_ERROR: ert2_mid_ue_error | |
| 8 | ROX | ROX | ERT2_HI_UE_ERROR: ert2_hi_ue_error | |
| 9 | ROX | ROX | ERT3_LO_UE_ERROR: ert3_lo_ue_error | |
| 10 | ROX | ROX | ERT3_MID_UE_ERROR: ert3_mid_ue_error | |
| 11 | ROX | ROX | ERT3_HI_UE_ERROR: ert3_hi_ue_error | |
| 12 | ROX | ROX | TADB_LO_UE_ERROR: tadb_lo_ue_error | |
| 13 | ROX | ROX | TADB_MID_UE_ERROR: tadb_mid_ue_error | |
| 14 | ROX | ROX | TADB_HI_UE_ERROR: tadb_hi_ue_error | |
| 15 | ROX | ROX | COSB_LO_UE_ERROR: cosb_lo_ue_error | |
| 16 | ROX | ROX | COSB_MID_UE_ERROR: cosb_mid_ue_error | |
| 17 | ROX | ROX | COSB_HI_UE_ERROR: cosb_hi_ue_error | |
| 18 | ROX | ROX | RQDB_PE: rqdb_pe | |
| 19 | ROX | ROX | RSDB_PE: rsdb_pe | |
| 20 | ROX | ROX | MDB0_PE: mdb0_pe | |
| 21 | ROX | ROX | MDB1_PE: mdb1_pe | |
| 22 | ROX | ROX | STLBI_PE: stlbi_pe | |
| 23 | ROX | ROX | STLBI_OVERFLOW_ERR: stlbi_overflow_err | |
| 24 | ROX | ROX | CORESP_DATA_CE: coresp_data_ce | |
| 25 | ROX | ROX | CORESP_DATA_UE: coresp_data_ue | |
| 26 | ROX | ROX | CORESP_DATA_SUE: coresp_data_sue | |
| 27 | ROX | ROX | PEE_DATA_CE: pee_data_ce | |
| 28 | ROX | ROX | PEE_DATA_UE: pee_data_ue | |
| 29 | ROX | ROX | PEE_DATA_SUE: pee_data_sue | |
| 30 | ROX | ROX | MEMHIT_W_BAR_MODE_NONZERO_ERROR: memhit_w_bar_mode_nonzero_error | |
| 31:63 | RO | RO | constant=0b000000000000000000000000000000000 | |
| xsl_wrap_error_2 Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010AA8 (SCOM) 00000000134E0140 (PAU_RING) | |||
| Name: | PAU3.XSL.XSL_MAIN.XSL_WRAP_ERROR_2 | |||
| Constant(s): | ||||
| Comments: | xsl_wrap_error_2 Register (c_err_rpt hold(85 to 94)) | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:11 | PAU3.XSL.XSL_MAIN.ERR_RPT2.HOLD_LATCH_INST.HOLD.LATC.L2(0:11) [000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | ROX | ROX | KILL_XLATE_EPOCH_TIMEOUT: kill_xlate_epoch_timeout | |
| 1 | ROX | ROX | BAR_SECURE_SMF_INSECURE: bar_secure_smf_insecure | |
| 2 | ROX | ROX | XLATE_IN_SUSPEND: xlate_in_suspend | |
| 3 | ROX | ROX | UNSUPPORTED_PAGE_SIZE: unsupported_page_size | |
| 4 | ROX | ROX | XLAT_REL_FAIL_PI: xlat_rel_fail_PI | |
| 5 | ROX | ROX | KILL_XLATE_DONE_FAIL: kill_xlate_done_fail | |
| 6 | ROX | ROX | XSL_INT_PAR_ERR: xsl_int_par_err | |
| 7:9 | ROX | ROX | RESERVED_XSLO_2: reserved_xslo_2 | |
| 10 | ROX | ROX | XSL_WRAP_PAR_ERR: xsl_wrap_par_err | |
| 11 | ROX | ROX | INVLD_PEHANDLE_ATL: invld_pehandle_atl | |
| 12:63 | RO | RO | constant=0b0000000000000000000000000000000000000000000000000000 | |
| xsl_wrap_err_mask_0 Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010AAA (SCOM) 00000000134E0150 (PAU_RING) | |||
| Name: | PAU3.XSL.XSL_MAIN.XSL_WRAP_ERR_MASK_0 | |||
| Constant(s): | ||||
| Comments: | xsl_wrap_err_mask_0 Register (c_err_rpt mask(0:53)) | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:53 | PAU3.XSL.XSL_MAIN.C_ERR_RPT_MASK_Q_0_INST.LATC.L2(0:53) [000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:53 | RO | RO | XSL_WRAP_ERR_MASK_0_DIAL: xsl_wrap_err_mask_0 Register Dial | |
| 54:63 | RO | RO | constant=0b0000000000 | |
| xsl_wrap_err_mask_1 Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010AAB (SCOM) 00000000134E0158 (PAU_RING) | |||
| Name: | PAU3.XSL.XSL_MAIN.XSL_WRAP_ERR_MASK_1 | |||
| Constant(s): | ||||
| Comments: | xsl_wrap_err_mask_1 Register (c_err_rpt mask(54:84)) | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:30 | PAU3.XSL.XSL_MAIN.C_ERR_RPT_MASK_Q_0_INST.LATC.L2(54:84) [0000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:30 | RO | RO | XSL_WRAP_ERR_MASK_1_DIAL: xsl_wrap_err_mask_1 Register Dial | |
| 31:63 | RO | RO | constant=0b000000000000000000000000000000000 | |
| xsl_wrap_err_mask_2 Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010AAC (SCOM) 00000000134E0160 (PAU_RING) | |||
| Name: | PAU3.XSL.XSL_MAIN.XSL_WRAP_ERR_MASK_2 | |||
| Constant(s): | ||||
| Comments: | xsl_wrap_err_mask_2 Register (c_err_rpt mask(85:96)) | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:11 | PAU3.XSL.XSL_MAIN.C_ERR_RPT_MASK_Q_0_INST.LATC.L2(85:96) [000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:11 | RO | RO | XSL_WRAP_ERR_MASK_2_DIAL: xsl_wrap_err_mask_2 Register Dial | |
| 12:63 | RO | RO | constant=0b0000000000000000000000000000000000000000000000000000 | |
| XSL PMU Control Register 0 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010AAE (SCOM) 00000000134E0170 (PAU_RING) | |||
| Name: | PAU3.XSL.XSL_MAIN.PMU_CONTROL0 | |||
| Constant(s): | ||||
| Comments: | XSL Performance Monitor Control Register 0 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.XSL.XSL_MAIN.PMU_CONTROL0_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_PMU_ENABLE: XSL pmu enable | |
| 1 | RW | RW | CONFIG_PMU_RESETMODE: XSL pmu resetmode | |
| 2 | RW | RW | CONFIG_PMU_FREEZEMODE: XSL pmu freezemode | |
| 3 | RW | RW | CONFIG_PMU_DISABLE_PMISC: XSL pmu disable_pmis | |
| 4 | RW | RW | CONFIG_PMU_PMISC_MODE: XSL pmu pmisc_mode | |
| 5:7 | RW | RW | CONFIG_PMU_CASCADE: XSL pmu cascade | |
| 8:9 | RW | RW | CONFIG_PMU_PRESCALE_C0: XSL pmu prescale_c0 | |
| 10:11 | RW | RW | CONFIG_PMU_PRESCALE_C1: XSL pmu prescale_c1 | |
| 12:13 | RW | RW | CONFIG_PMU_PRESCALE_C2: XSL pmu prescale_c2 | |
| 14:15 | RW | RW | CONFIG_PMU_PRESCALE_C3: XSL pmu prescale_c3 | |
| 16:17 | RW | RW | CONFIG_PMU_OPERATION_C0: XSL pmu operation_c0 | |
| 18:19 | RW | RW | CONFIG_PMU_OPERATION_C1: XSL pmu operation_c1 | |
| 20:21 | RW | RW | CONFIG_PMU_OPERATION_C2: XSL pmu operation_c2 | |
| 22:23 | RW | RW | CONFIG_PMU_OPERATION_C3: XSL pmu operation_c3 | |
| 24:31 | RW | RW | CONFIG_PMU_EVENTS_C0: XSL pmu events c0 : Selects 2 bit events to input to pmulet counter 0 | |
| 32:39 | RW | RW | CONFIG_PMU_EVENTS_C1: XSL pmu events c1 : Selects 2 bit events to input to pmulet counter 1 | |
| 40:47 | RW | RW | CONFIG_PMU_EVENTS_C2: XSL pmu events c2 : Selects 2 bit events to input to pmulet counter 2 | |
| 48:55 | RW | RW | CONFIG_PMU_EVENTS_C3: XSL pmu events c3 : Selects 2 bit events to input to pmulet counter 3 | |
| 56:63 | RW | RW | CONFIG_PMU_RESERVED0: Reserved | |
| XSL PMU Count Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010AAF (SCOM) 00000000134E0178 (PAU_RING) | |||
| Name: | PAU3.XSL.XSL_MAIN.PMU_COUNT | |||
| Constant(s): | ||||
| Comments: | XSL Performance Monitor Count Register (4x16b) | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:15 | PAU3.XSL.XSL_MAIN.PMLET.COUNTER0_CNT_Q_0_INST.LATC.L2(0:15) [0000000000000000] | |||
| 16:31 | PAU3.XSL.XSL_MAIN.PMLET.COUNTER1_CNT_Q_0_INST.LATC.L2(0:15) [0000000000000000] | |||
| 32:47 | PAU3.XSL.XSL_MAIN.PMLET.COUNTER2_CNT_Q_0_INST.LATC.L2(0:15) [0000000000000000] | |||
| 48:63 | PAU3.XSL.XSL_MAIN.PMLET.COUNTER3_CNT_Q_0_INST.LATC.L2(0:15) [0000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:15 | ROX | ROX | CONFIG_PMU_COUNT0: XSL pmu count 0 | |
| 16:31 | ROX | ROX | CONFIG_PMU_COUNT1: XSL pmu count 1 | |
| 32:47 | ROX | ROX | CONFIG_PMU_COUNT2: XSL pmu count 2 | |
| 48:63 | ROX | ROX | CONFIG_PMU_COUNT3: XSL pmu count 3 | |
| XTS error c_err_rpt status and clear register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010AF0 (SCOM) 0000000013710000 (PAU_RING) | |||
| Name: | PAU3.XTS.REG.ERR_HOLD | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.XTS.REG.ERR.HOLD_LATCH_INST.HOLD.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX_WCLEAR | RWX_WCLEAR | DEBUG0_CONFIG_P_ERR: debug0 config register parity error | |
| 1 | RWX_WCLEAR | RWX_WCLEAR | DEBUG1_CONFIG_P_ERR: debug1 config register parity error | |
| 2 | RWX_WCLEAR | RWX_WCLEAR | XTS_CONFIG_P_ERR: xts config register parity error | |
| 3 | RWX_WCLEAR | RWX_WCLEAR | XTS_CONFIG2_P_ERR: xts config2 register parity error | |
| 4 | RWX_WCLEAR | RWX_WCLEAR | XTS_CONFIG3_P_ERR: xts config3 register parity error | |
| 5 | RWX_WCLEAR | RWX_WCLEAR | SNP_REG_ERR9: Informational fir that is set when the snooper retries a rpt_hang.check or rpt_hang.poll command. | |
| 6 | RWX_WCLEAR | RWX_WCLEAR | SNP_REG_ERR7: PBus Snoop, any of the snoopers main state machines latches takes a parity error | |
| 7 | RWX_WCLEAR | RWX_WCLEAR | SNP_REG_ERR8: PBus Snoop, protocol checker to see if a snptlbcmp or not_my_lpar arrives when the snooper doesn't expect one | |
| 8 | RWX_WCLEAR | RWX_WCLEAR | SNP_REG_ERR0: PBus Snoop 0 address parity error | |
| 9 | RWX_WCLEAR | RWX_WCLEAR | SNP_REG_ERR1: PBus Snoop 0 ttag parity error | |
| 10 | RWX_WCLEAR | RWX_WCLEAR | SNP_REG_ERR2: PBus Snoop 1 address parity error | |
| 11 | RWX_WCLEAR | RWX_WCLEAR | SNP_REG_ERR3: PBus Snoop 1 ttag parity error | |
| 12 | RWX_WCLEAR | RWX_WCLEAR | SNP_REG_ERR4: PBus Snoop bad op error | |
| 13 | RWX_WCLEAR | RWX_WCLEAR | SNP_REG_ERR5: PBus Snoop sequence parity error | |
| 14 | RWX_WCLEAR | RWX_WCLEAR | SNP_REG_ERR6: PBus Snoop time out | |
| 15 | RWX_WCLEAR | RWX_WCLEAR | ATR_ERR_SM_STATE: ATR state machine parity error | |
| 16 | RWX_WCLEAR | RWX_WCLEAR | ATSD_ERR_SM_STATE: ATSD state machine parity error | |
| 17 | RWX_WCLEAR | RWX_WCLEAR | ATR_ERR_TIMEOUT: ATR state machine time out | |
| 18 | RWX_WCLEAR | RWX_WCLEAR | ATSD_ERR_TIMEOUT: ATSD state machine time out | |
| 19 | RWX_WCLEAR | RWX_WCLEAR | ATSD_ERR_BAD_TAG: unexpected ATSD response tag | |
| 20 | RWX_WCLEAR | RWX_WCLEAR | MAP_REG_ERR2: ATR BDF table lookup parity error | |
| 21 | RWX_WCLEAR | RWX_WCLEAR | MAP_REG_ERR3: ATR PID table lookup parity error | |
| 22 | RWX_WCLEAR | RWX_WCLEAR | MAP_REG_ERR4: ATSD BDF table lookup parity error | |
| 23 | RWX_WCLEAR | RWX_WCLEAR | ATR_ERR_ARBSTATE: ATR arbiter state not on-hot during selection phase | |
| 24 | RWX_WCLEAR | RWX_WCLEAR | ATR_ERR_RADDR_BND: check-out response is beyond GPU addressable range | |
| 25 | RWX_WCLEAR | RWX_WCLEAR | BDF_MAP_REG_PARITY_ERR: BDF Map registers parity error | |
| 26 | RWX_WCLEAR | RWX_WCLEAR | PID_MAP_REG_PARITY_ERR: PID Map registers parity error | |
| 27:31 | RWX_WCLEAR | RWX_WCLEAR | ERR_UNUSED2: unused | |
| 32 | RWX_WCLEAR | RWX_WCLEAR | IFC_REG_CERR0: MMU response correctable ECC error | |
| 33 | RWX_WCLEAR | RWX_WCLEAR | IFC_REG_CERR1: Reserved, tied to 0 | |
| 34 | RWX_WCLEAR | RWX_WCLEAR | IFC_REG_CERR2: Reserved, tied to 0 | |
| 35 | RWX_WCLEAR | RWX_WCLEAR | MAP_REG_CERR0: AMR SRAM correctable ECC error | |
| 36 | RWX_WCLEAR | RWX_WCLEAR | MAP_REG_CERR1: Reserved, tied to 0 | |
| 37:47 | RWX_WCLEAR | RWX_WCLEAR | ERR_UNUSED3: unused | |
| 48 | RWX_WCLEAR | RWX_WCLEAR | IFC_REG_ERR0: MMU response uncorrectable ECC error | |
| 49 | RWX_WCLEAR | RWX_WCLEAR | IFC_REG_ERR1: MMU response special uncorrectable ECC error | |
| 50 | RWX_WCLEAR | RWX_WCLEAR | IFC_REG_ERR2: MMU response bad tag | |
| 51 | RWX_WCLEAR | RWX_WCLEAR | IFC_REG_ERR3: Reserved, tied to 0 | |
| 52 | RWX_WCLEAR | RWX_WCLEAR | IFC_REG_ERR4: Reserved, tied to 0 | |
| 53 | RWX_WCLEAR | RWX_WCLEAR | IFC_REG_ERR5: Reserved, tied to 0 | |
| 54 | RWX_WCLEAR | RWX_WCLEAR | IFC_REG_ERR6: Reserved, tied to 0 | |
| 55 | RWX_WCLEAR | RWX_WCLEAR | IFC_REG_ERR7: Reserved, tied to 0 | |
| 56 | RWX_WCLEAR | RWX_WCLEAR | IFC_REG_ERR8: Reserved, tied to 0 | |
| 57 | RWX_WCLEAR | RWX_WCLEAR | MAP_REG_ERR0: AMR SRAM uncorrectable ECC error | |
| 58 | RWX_WCLEAR | RWX_WCLEAR | MAP_REG_ERR1: Reserved, tied to 0 | |
| 59:62 | RWX_WCLEAR | RWX_WCLEAR | ERR_UNUSED4: unused | |
| 63 | RWX_WCLEAR | RWX_WCLEAR | ATR_MISS_IRQ: atr miss interrupt | |
| XTS c_err_rpt error injection test register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010AF1 (SCOM) 0000000013710008 (PAU_RING) | |||
| Name: | PAU3.XTS.REG.TEST_CERR | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0 | PAU3.XTS.REG.ATR_ERR_INJ_PENDQ.LATC.L2(0) [0] | |||
| 1 | PAU3.XTS.REG.MAP_ERR_INJ_PENDQ.LATC.L2(0) [0] | |||
| 56:63 | PAU3.XTS.REG.TEST_CERRWQ.LATC.L2(56:63) [00000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | ROX | ROX | ATR_ERR_INJ_PEND: Indicates that an ATR SRAM error injection has been started, but the error has not been injected yet. The error will be injected when the next ATR response is assembled by the XTS | |
| 1 | ROX | ROX | MAP_ERR_INJ_PEND: Indicates that an MAP SRAM error injection has been started, but the error has not been injected yet. The error will be injected the next time the SEIDR or AMR SRAM is written via MMIO or SCOM | |
| 2:55 | RO | RO | constant=0b000000000000000000000000000000000000000000000000000000 | |
| 56:57 | WO | WO | TEST_CERR_REGSEL: Selects c_err_rpt to inject an error (00b: none, 01b: fir, 10b: ATR SRAM, 11b: SEIDR/AMR SRAM) | |
| 58:63 | WO | WO | TEST_CERR_BITSEL: Selects the FIR bit to inject the error (0: The MSB, 1: The second MSB, ...., 63: The LSB); select CE (0) or UE (1) for SRAM injection | |
| XTS error c_err_rpt mask register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010AF2 (SCOM) 0000000013710010 (PAU_RING) | |||
| Name: | PAU3.XTS.REG.ERR_MASK | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.XTS.REG.ERR_MASK.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:63 | ROX | ROX | ERR_MASK_BITS: XTS error c_err_rpt mask bits | |
| XTS error first register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010AF3 (SCOM) 0000000013710018 (PAU_RING) | |||
| Name: | PAU3.XTS.REG.ERR_FIRST | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.XTS.REG.ERR_FIRSTQ.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:63 | RWX_WCLEAR | RWX_WCLEAR | ERR_FIRST_BITS: XTS error first bits | |
| XTS Config Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010AF4 (SCOM) 0000000013710020 (PAU_RING) | |||
| Name: | PAU3.XTS.REG.XTS_CONFIG | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.XTS.REG.XTS_CONFIGQ.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | XTS_CONFIG_UNUSED0: unused | |
| 1 | RW | RW | XTS_CONFIG_MMIOSD: enables NVLink MMIO controlled translation shoot downs | |
| 2 | RW | RW | XTS_CONFIG_BIG_RSP: enables ATR response sizes matching exactly the request | |
| 3 | RW | RW | XTS_CONFIG_CHOP1G: split 1G page into 16 2M pages | |
| 4 | RW | RW | XTS_CONFIG_DIS_NCNP: disable NCNP flag on inhibited/guarded pages | |
| 5 | RW | RW | XTS_CONFIG_OVR_PM: override PM bit in ATR with PR bit in PID table | |
| 6 | RW | RW | XTS_CONFIG_TRY_ATR_RO: retry RW checkouts as RO on protection fault | |
| 7 | RW | RW | XTS_CONFIG_SPLURGE: use all 8 NMMU channels for prefetches if available | |
| 8 | RW | RW | XTS_CONFIG_LIM_PS: limit valid page sizes to 64K/2M/1G; if 1G splitting is enabled, only 64K/2MB ATR responses will be sent | |
| 9 | RW | RW | XTS_CONFIG_PREF2DMD: convert NMMU prefetch requests to demand types, forcing table walk on NMMU cache miss | |
| 10 | RW | RW | XTS_CONFIG_PREFEVOD: walks even addresses, then odd addresses for prefetches, or vice versa | |
| 11 | RW | RW | XTS_CONFIG_EAINJ: when set to 1, injects 3 random bits into EA[12:14] for CO requests | |
| 12 | RW | RW | XTS_CONFIG_SPL_ONLY: if set and splurge active, preferred slot no longer wins for prefetches | |
| 13 | RW | RW | XTS_CONFIG_BYPASS_CO: if set, reduces checkout latency by bypassing the arbitration pipeline | |
| 14 | RW | RW | XTS_CONFIG_UNUSED: unused | |
| 15 | RW | RW | XTS_CONFIG_OPENCAPI: if set, activates interfaces to OpenCAPI and AME XSLs | |
| 16:23 | RW | RW | XTS_CONFIG_TLBIE_DEC_RATE: TLBI temperature dec pulse every n+1 cycles | |
| 24:31 | RW | RW | XTS_CONFIG_TLBIE_INC_RATE: TLBI temperature inc pulse every n+1 cycles | |
| 32:39 | RW | RW | XTS_CONFIG_TLBIE_CNT_THRESH: throttle if global TLBI temperature counter exceeds this threshold | |
| 40 | RW | RW | XTS_CONFIG_WAIT_MISS: when set, ATSD SMs will wait for all responses on BDF table miss | |
| 41:43 | RW | RW | XTS_CONFIG_PREF_TIMEOUT: delay after which an ATR state machine no longer issues prefetches Dial enums: OFF=>0b000 64NS=>0b001 128NS=>0b010 256NS=>0b011 512NS=>0b100 1US=>0b101 2US=>0b110 4US=>0b111 | |
| 44:47 | RW | RW | XTS_CONFIG_PREF_DEPTH: maximum number of prefetches returned in addition to demand for single ATR request | |
| 48:51 | RW | RW | XTS_CONFIG_PREF_THRSH0: number of concurrent ATR prefetches when no request is queued in front of ATR state machines | |
| 52:55 | RW | RW | XTS_CONFIG_PREF_THRSH1: number of concurrent ATR prefetches when one request is queued in front of ATR state machines | |
| 56:59 | RW | RW | XTS_CONFIG_PREF_THRSH2: number of concurrent ATR prefetches when two requests are queued in front of ATR state machines | |
| 60:63 | RW | RW | XTS_CONFIG_PREF_THRSH3: number of concurrent ATR prefetches when three requests are queued in front of ATR state machines | |
| XTS Config2 Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010AF5 (SCOM) 0000000013710028 (PAU_RING) | |||
| Name: | PAU3.XTS.REG.XTS_CONFIG2 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.XTS.REG.XTS_CONFIG2Q.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | XTS_CONFIG2_PERF_ENABLE: PMULet Enable (clocks enable) | |
| 1 | RW | RW | XTS_CONFIG2_PERF_RESETMODE: 0/1 = reset-on-read/reset-on-write | |
| 2 | RW | RW | XTS_CONFIG2_PERF_FREEZEMODE: 0/1 = freeze-on-any-max/freerun-mode | |
| 3 | RW | RW | XTS_CONFIG2_PERF_DISABLE_PMISC: 0/1 = enable-pmisc/disable-pmisc control of counters | |
| 4 | RW | RW | XTS_CONFIG2_PERF_PMISC_MODE: 0/1 = global pmu pmisc no reset/global pmu misc reset-on-enable | |
| 5:7 | RW | RW | XTS_CONFIG2_PERF_CASCADE: pmulet cascade config | |
| 8:9 | RW | RW | XTS_CONFIG2_PERF_PRESCALE_C0: prescale config for counter 0 | |
| 10:11 | RW | RW | XTS_CONFIG2_PERF_PRESCALE_C1: prescale config for counter 1 | |
| 12:13 | RW | RW | XTS_CONFIG2_PERF_PRESCALE_C2: prescale config for counter 2 | |
| 14:15 | RW | RW | XTS_CONFIG2_PERF_PRESCALE_C3: prescale config for counter 3 | |
| 16:23 | RW | RW | XTS_CONFIG2_PERF_EVENT0: Event 0 select | |
| 24:31 | RW | RW | XTS_CONFIG2_PERF_EVENT1: Event 1 select | |
| 32:39 | RW | RW | XTS_CONFIG2_PERF_EVENT2: Event 2 select | |
| 40:47 | RW | RW | XTS_CONFIG2_PERF_EVENT3: Event 3 select | |
| 48 | RW | RW | XTS_CONFIG2_RADDR_BND: if enabled, causes fault if check-out response is beyond GPU addressable range | |
| 49 | RW | RW | XTS_CONFIG2_NO_FLUSH_ENA: if enabled, allows MMIO ATSDs to suppress the flush | |
| 50 | RW | RW | XTS_CONFIG2_MAP_ILOCK: if enabled, activates write interlock for AMR and SEIDR SRAMs | |
| 51 | RW | RW | XTS_CONFIG2_ADJUST_PLS_RATE: if enabled, increases TLBI pulse rate for GPU to match XSL | |
| 52 | RW | RW | XTS_CONFIG2_TLBIE_HV_EN: enable is=11 to broadcast to all BDFs if HV bit set | |
| 53 | RW | RW | XTS_CONFIG2_TLBIE_PACING_CNT_EN: Enables pacing counters for XSL TLBI back pressure | |
| 54 | RW | RW | XTS_CONFIG2_UNUSED: XTS config2 unused/reserved bit for future use | |
| 55 | RW | RW | XTS_CONFIG2_XSL2_ENA: Enables interface for XSL2 | |
| 56:59 | RW | RW | XTS_CONFIG2_ATSD_TIMEOUT: Time out select for ATSD | |
| 60:63 | RW | RW | XTS_CONFIG2_ATR_TIMEOUT: Time out select for ATR (NMMU response time-out) | |
| XTS Debug0 config register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010AF6 (SCOM) 0000000013710030 (PAU_RING) | |||
| Name: | PAU3.XTS.REG.DEBUG0_CONFIG | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.XTS.REG.DEBUG0_CONFIGQ.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:4 | RW | RW | DEBUG0_CONFIG_POD0: Mux control for byte 0 of trace-0 Dial enums: POD_INP0=>0b00000 POD_INP1=>0b00001 POD_INP2=>0b00010 POD_INP3=>0b00011 POD_INP4=>0b00100 POD_INP5=>0b00101 POD_INP6=>0b00110 POD_INP7=>0b00111 POD_INP8=>0b01000 POD_INP9=>0b01001 POD_INP10=>0b01010 SNP_DEBUG0_ROT0=>0b01011 SNP_DEBUG0_ROT16=>0b01100 SNP_DEBUG0_ROT32=>0b01101 SNP_DEBUG1_ROT0=>0b01110 SNP_DEBUG1_ROT16=>0b01111 SNP_DEBUG1_ROT32=>0b10000 ATR_DEBUG0_ROT0=>0b10001 ATR_DEBUG0_ROT16=>0b10010 ATR_DEBUG0_ROT32=>0b10011 ATSD_DEBUG0_ROT0=>0b10100 ATSD_DEBUG0_ROT16=>0b10101 ATSD_DEBUG0_ROT32=>0b10110 ATSD_DEBUG1_ROT0=>0b10111 ATSD_DEBUG1_ROT16=>0b11000 ATSD_DEBUG1_ROT32=>0b11001 ATSD_DEBUG2_ROT0=>0b11010 ATSD_DEBUG2_ROT16=>0b11011 ATSD_DEBUG2_ROT32=>0b11100 ATSD_DEBUG4_ROT0=>0b11101 ATSD_DEBUG4_ROT16=>0b11110 ATSD_DEBUG4_ROT32=>0b11111 | |
| 5:9 | RW | RW | DEBUG0_CONFIG_POD1: Mux control for byte 1 of trace-0 Dial enums: POD_INP1=>0b00000 POD_INP2=>0b00001 POD_INP3=>0b00010 POD_INP4=>0b00011 POD_INP5=>0b00100 POD_INP6=>0b00101 POD_INP7=>0b00110 POD_INP8=>0b00111 POD_INP9=>0b01000 POD_INP10=>0b01001 POD_INP0=>0b01010 SNP_DEBUG0_ROT0=>0b01011 SNP_DEBUG0_ROT16=>0b01100 SNP_DEBUG0_ROT32=>0b01101 SNP_DEBUG1_ROT0=>0b01110 SNP_DEBUG1_ROT16=>0b01111 SNP_DEBUG1_ROT32=>0b10000 ATR_DEBUG0_ROT0=>0b10001 ATR_DEBUG0_ROT16=>0b10010 ATR_DEBUG0_ROT32=>0b10011 ATSD_DEBUG0_ROT0=>0b10100 ATSD_DEBUG0_ROT16=>0b10101 ATSD_DEBUG0_ROT32=>0b10110 ATSD_DEBUG1_ROT0=>0b10111 ATSD_DEBUG1_ROT16=>0b11000 ATSD_DEBUG1_ROT32=>0b11001 ATSD_DEBUG2_ROT0=>0b11010 ATSD_DEBUG2_ROT16=>0b11011 ATSD_DEBUG2_ROT32=>0b11100 ATSD_DEBUG4_ROT0=>0b11101 ATSD_DEBUG4_ROT16=>0b11110 ATSD_DEBUG4_ROT32=>0b11111 | |
| 10:14 | RW | RW | DEBUG0_CONFIG_POD2: Mux control for byte 2 of trace-0 Dial enums: POD_INP2=>0b00000 POD_INP3=>0b00001 POD_INP4=>0b00010 POD_INP5=>0b00011 POD_INP6=>0b00100 POD_INP7=>0b00101 POD_INP8=>0b00110 POD_INP9=>0b00111 POD_INP10=>0b01000 POD_INP0=>0b01001 POD_INP1=>0b01010 SNP_DEBUG0_ROT0=>0b01011 SNP_DEBUG0_ROT16=>0b01100 SNP_DEBUG0_ROT32=>0b01101 SNP_DEBUG1_ROT0=>0b01110 SNP_DEBUG1_ROT16=>0b01111 SNP_DEBUG1_ROT32=>0b10000 ATR_DEBUG0_ROT0=>0b10001 ATR_DEBUG0_ROT16=>0b10010 ATR_DEBUG0_ROT32=>0b10011 ATSD_DEBUG0_ROT0=>0b10100 ATSD_DEBUG0_ROT16=>0b10101 ATSD_DEBUG0_ROT32=>0b10110 ATSD_DEBUG1_ROT0=>0b10111 ATSD_DEBUG1_ROT16=>0b11000 ATSD_DEBUG1_ROT32=>0b11001 ATSD_DEBUG2_ROT0=>0b11010 ATSD_DEBUG2_ROT16=>0b11011 ATSD_DEBUG2_ROT32=>0b11100 ATSD_DEBUG4_ROT0=>0b11101 ATSD_DEBUG4_ROT16=>0b11110 ATSD_DEBUG4_ROT32=>0b11111 | |
| 15:19 | RW | RW | DEBUG0_CONFIG_POD3: Mux control for byte 3 of trace-0 Dial enums: POD_INP3=>0b00000 POD_INP4=>0b00001 POD_INP5=>0b00010 POD_INP6=>0b00011 POD_INP7=>0b00100 POD_INP8=>0b00101 POD_INP9=>0b00110 POD_INP10=>0b00111 POD_INP0=>0b01000 POD_INP1=>0b01001 POD_INP2=>0b01010 SNP_DEBUG0_ROT0=>0b01011 SNP_DEBUG0_ROT16=>0b01100 SNP_DEBUG0_ROT32=>0b01101 SNP_DEBUG1_ROT0=>0b01110 SNP_DEBUG1_ROT16=>0b01111 SNP_DEBUG1_ROT32=>0b10000 ATR_DEBUG0_ROT0=>0b10001 ATR_DEBUG0_ROT16=>0b10010 ATR_DEBUG0_ROT32=>0b10011 ATSD_DEBUG0_ROT0=>0b10100 ATSD_DEBUG0_ROT16=>0b10101 ATSD_DEBUG0_ROT32=>0b10110 ATSD_DEBUG1_ROT0=>0b10111 ATSD_DEBUG1_ROT16=>0b11000 ATSD_DEBUG1_ROT32=>0b11001 ATSD_DEBUG2_ROT0=>0b11010 ATSD_DEBUG2_ROT16=>0b11011 ATSD_DEBUG2_ROT32=>0b11100 ATSD_DEBUG4_ROT0=>0b11101 ATSD_DEBUG4_ROT16=>0b11110 ATSD_DEBUG4_ROT32=>0b11111 | |
| 20:24 | RW | RW | DEBUG0_CONFIG_POD4: Mux control for byte 4 of trace-0 Dial enums: POD_INP4=>0b00000 POD_INP5=>0b00001 POD_INP6=>0b00010 POD_INP7=>0b00011 POD_INP8=>0b00100 POD_INP9=>0b00101 POD_INP10=>0b00110 POD_INP0=>0b00111 POD_INP1=>0b01000 POD_INP2=>0b01001 POD_INP3=>0b01010 SNP_DEBUG0_ROT0=>0b01011 SNP_DEBUG0_ROT16=>0b01100 SNP_DEBUG0_ROT32=>0b01101 SNP_DEBUG1_ROT0=>0b01110 SNP_DEBUG1_ROT16=>0b01111 SNP_DEBUG1_ROT32=>0b10000 ATR_DEBUG0_ROT0=>0b10001 ATR_DEBUG0_ROT16=>0b10010 ATR_DEBUG0_ROT32=>0b10011 ATSD_DEBUG0_ROT0=>0b10100 ATSD_DEBUG0_ROT16=>0b10101 ATSD_DEBUG0_ROT32=>0b10110 ATSD_DEBUG1_ROT0=>0b10111 ATSD_DEBUG1_ROT16=>0b11000 ATSD_DEBUG1_ROT32=>0b11001 ATSD_DEBUG2_ROT0=>0b11010 ATSD_DEBUG2_ROT16=>0b11011 ATSD_DEBUG2_ROT32=>0b11100 ATSD_DEBUG4_ROT0=>0b11101 ATSD_DEBUG4_ROT16=>0b11110 ATSD_DEBUG4_ROT32=>0b11111 | |
| 25:29 | RW | RW | DEBUG0_CONFIG_POD5: Mux control for byte 5 of trace-0 Dial enums: POD_INP5=>0b00000 POD_INP6=>0b00001 POD_INP7=>0b00010 POD_INP8=>0b00011 POD_INP9=>0b00100 POD_INP10=>0b00101 POD_INP0=>0b00110 POD_INP1=>0b00111 POD_INP2=>0b01000 POD_INP3=>0b01001 POD_INP4=>0b01010 SNP_DEBUG0_ROT0=>0b01011 SNP_DEBUG0_ROT16=>0b01100 SNP_DEBUG0_ROT32=>0b01101 SNP_DEBUG1_ROT0=>0b01110 SNP_DEBUG1_ROT16=>0b01111 SNP_DEBUG1_ROT32=>0b10000 ATR_DEBUG0_ROT0=>0b10001 ATR_DEBUG0_ROT16=>0b10010 ATR_DEBUG0_ROT32=>0b10011 ATSD_DEBUG0_ROT0=>0b10100 ATSD_DEBUG0_ROT16=>0b10101 ATSD_DEBUG0_ROT32=>0b10110 ATSD_DEBUG1_ROT0=>0b10111 ATSD_DEBUG1_ROT16=>0b11000 ATSD_DEBUG1_ROT32=>0b11001 ATSD_DEBUG2_ROT0=>0b11010 ATSD_DEBUG2_ROT16=>0b11011 ATSD_DEBUG2_ROT32=>0b11100 ATSD_DEBUG4_ROT0=>0b11101 ATSD_DEBUG4_ROT16=>0b11110 ATSD_DEBUG4_ROT32=>0b11111 | |
| 30:34 | RW | RW | DEBUG0_CONFIG_POD6: Mux control for byte 6 of trace-0 Dial enums: POD_INP6=>0b00000 POD_INP7=>0b00001 POD_INP8=>0b00010 POD_INP9=>0b00011 POD_INP10=>0b00100 POD_INP0=>0b00101 POD_INP1=>0b00110 POD_INP2=>0b00111 POD_INP3=>0b01000 POD_INP4=>0b01001 POD_INP5=>0b01010 SNP_DEBUG0_ROT0=>0b01011 SNP_DEBUG0_ROT16=>0b01100 SNP_DEBUG0_ROT32=>0b01101 SNP_DEBUG1_ROT0=>0b01110 SNP_DEBUG1_ROT16=>0b01111 SNP_DEBUG1_ROT32=>0b10000 ATR_DEBUG0_ROT0=>0b10001 ATR_DEBUG0_ROT16=>0b10010 ATR_DEBUG0_ROT32=>0b10011 ATSD_DEBUG0_ROT0=>0b10100 ATSD_DEBUG0_ROT16=>0b10101 ATSD_DEBUG0_ROT32=>0b10110 ATSD_DEBUG1_ROT0=>0b10111 ATSD_DEBUG1_ROT16=>0b11000 ATSD_DEBUG1_ROT32=>0b11001 ATSD_DEBUG2_ROT0=>0b11010 ATSD_DEBUG2_ROT16=>0b11011 ATSD_DEBUG2_ROT32=>0b11100 ATSD_DEBUG4_ROT0=>0b11101 ATSD_DEBUG4_ROT16=>0b11110 ATSD_DEBUG4_ROT32=>0b11111 | |
| 35:39 | RW | RW | DEBUG0_CONFIG_POD7: Mux control for byte 7 of trace-0 Dial enums: POD_INP7=>0b00000 POD_INP8=>0b00001 POD_INP9=>0b00010 POD_INP10=>0b00011 POD_INP0=>0b00100 POD_INP1=>0b00101 POD_INP2=>0b00110 POD_INP3=>0b00111 POD_INP4=>0b01000 POD_INP5=>0b01001 POD_INP6=>0b01010 SNP_DEBUG0_ROT0=>0b01011 SNP_DEBUG0_ROT16=>0b01100 SNP_DEBUG0_ROT32=>0b01101 SNP_DEBUG1_ROT0=>0b01110 SNP_DEBUG1_ROT16=>0b01111 SNP_DEBUG1_ROT32=>0b10000 ATR_DEBUG0_ROT0=>0b10001 ATR_DEBUG0_ROT16=>0b10010 ATR_DEBUG0_ROT32=>0b10011 ATSD_DEBUG0_ROT0=>0b10100 ATSD_DEBUG0_ROT16=>0b10101 ATSD_DEBUG0_ROT32=>0b10110 ATSD_DEBUG1_ROT0=>0b10111 ATSD_DEBUG1_ROT16=>0b11000 ATSD_DEBUG1_ROT32=>0b11001 ATSD_DEBUG2_ROT0=>0b11010 ATSD_DEBUG2_ROT16=>0b11011 ATSD_DEBUG2_ROT32=>0b11100 ATSD_DEBUG4_ROT0=>0b11101 ATSD_DEBUG4_ROT16=>0b11110 ATSD_DEBUG4_ROT32=>0b11111 | |
| 40:44 | RW | RW | DEBUG0_CONFIG_POD8: Mux control for byte 8 of trace-0 Dial enums: POD_INP8=>0b00000 POD_INP9=>0b00001 POD_INP10=>0b00010 POD_INP0=>0b00011 POD_INP1=>0b00100 POD_INP2=>0b00101 POD_INP3=>0b00110 POD_INP4=>0b00111 POD_INP5=>0b01000 POD_INP6=>0b01001 POD_INP7=>0b01010 SNP_DEBUG0_ROT0=>0b01011 SNP_DEBUG0_ROT16=>0b01100 SNP_DEBUG0_ROT32=>0b01101 SNP_DEBUG1_ROT0=>0b01110 SNP_DEBUG1_ROT16=>0b01111 SNP_DEBUG1_ROT32=>0b10000 ATR_DEBUG0_ROT0=>0b10001 ATR_DEBUG0_ROT16=>0b10010 ATR_DEBUG0_ROT32=>0b10011 ATSD_DEBUG0_ROT0=>0b10100 ATSD_DEBUG0_ROT16=>0b10101 ATSD_DEBUG0_ROT32=>0b10110 ATSD_DEBUG1_ROT0=>0b10111 ATSD_DEBUG1_ROT16=>0b11000 ATSD_DEBUG1_ROT32=>0b11001 ATSD_DEBUG2_ROT0=>0b11010 ATSD_DEBUG2_ROT16=>0b11011 ATSD_DEBUG2_ROT32=>0b11100 ATSD_DEBUG4_ROT0=>0b11101 ATSD_DEBUG4_ROT16=>0b11110 ATSD_DEBUG4_ROT32=>0b11111 | |
| 45:49 | RW | RW | DEBUG0_CONFIG_POD9: Mux control for byte 9 of trace-0 Dial enums: POD_INP9=>0b00000 POD_INP10=>0b00001 POD_INP0=>0b00010 POD_INP1=>0b00011 POD_INP2=>0b00100 POD_INP3=>0b00101 POD_INP4=>0b00110 POD_INP5=>0b00111 POD_INP6=>0b01000 POD_INP7=>0b01001 POD_INP8=>0b01010 SNP_DEBUG0_ROT0=>0b01011 SNP_DEBUG0_ROT16=>0b01100 SNP_DEBUG0_ROT32=>0b01101 SNP_DEBUG1_ROT0=>0b01110 SNP_DEBUG1_ROT16=>0b01111 SNP_DEBUG1_ROT32=>0b10000 ATR_DEBUG0_ROT0=>0b10001 ATR_DEBUG0_ROT16=>0b10010 ATR_DEBUG0_ROT32=>0b10011 ATSD_DEBUG0_ROT0=>0b10100 ATSD_DEBUG0_ROT16=>0b10101 ATSD_DEBUG0_ROT32=>0b10110 ATSD_DEBUG1_ROT0=>0b10111 ATSD_DEBUG1_ROT16=>0b11000 ATSD_DEBUG1_ROT32=>0b11001 ATSD_DEBUG2_ROT0=>0b11010 ATSD_DEBUG2_ROT16=>0b11011 ATSD_DEBUG2_ROT32=>0b11100 ATSD_DEBUG4_ROT0=>0b11101 ATSD_DEBUG4_ROT16=>0b11110 ATSD_DEBUG4_ROT32=>0b11111 | |
| 50:54 | RW | RW | DEBUG0_CONFIG_POD10: Mux control for byte 10 of trace-0 Dial enums: POD_INP10=>0b00000 POD_INP0=>0b00001 POD_INP1=>0b00010 POD_INP2=>0b00011 POD_INP3=>0b00100 POD_INP4=>0b00101 POD_INP5=>0b00110 POD_INP6=>0b00111 POD_INP7=>0b01000 POD_INP8=>0b01001 POD_INP9=>0b01010 SNP_DEBUG0_ROT0=>0b01011 SNP_DEBUG0_ROT16=>0b01100 SNP_DEBUG0_ROT32=>0b01101 SNP_DEBUG1_ROT0=>0b01110 SNP_DEBUG1_ROT16=>0b01111 SNP_DEBUG1_ROT32=>0b10000 ATR_DEBUG0_ROT0=>0b10001 ATR_DEBUG0_ROT16=>0b10010 ATR_DEBUG0_ROT32=>0b10011 ATSD_DEBUG0_ROT0=>0b10100 ATSD_DEBUG0_ROT16=>0b10101 ATSD_DEBUG0_ROT32=>0b10110 ATSD_DEBUG1_ROT0=>0b10111 ATSD_DEBUG1_ROT16=>0b11000 ATSD_DEBUG1_ROT32=>0b11001 ATSD_DEBUG2_ROT0=>0b11010 ATSD_DEBUG2_ROT16=>0b11011 ATSD_DEBUG2_ROT32=>0b11100 ATSD_DEBUG4_ROT0=>0b11101 ATSD_DEBUG4_ROT16=>0b11110 ATSD_DEBUG4_ROT32=>0b11111 | |
| 55:62 | RW | RW | DEBUG0_CONFIG_RESERVED1: reserved | |
| 63 | RW | RW | DEBUG0_CONFIG_ACT: Enable clock-gates for debug trace latches | |
| XTS Debug1 config register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010AF7 (SCOM) 0000000013710038 (PAU_RING) | |||
| Name: | PAU3.XTS.REG.DEBUG1_CONFIG | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.XTS.REG.DEBUG1_CONFIGQ.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:4 | RW | RW | DEBUG1_CONFIG_POD0: Mux control for byte 0 of trace-1 Dial enums: POD_INP0=>0b00000 POD_INP1=>0b00001 POD_INP2=>0b00010 POD_INP3=>0b00011 POD_INP4=>0b00100 POD_INP5=>0b00101 POD_INP6=>0b00110 POD_INP7=>0b00111 POD_INP8=>0b01000 POD_INP9=>0b01001 POD_INP10=>0b01010 SNP_DEBUG0_ROT0=>0b01011 SNP_DEBUG0_ROT16=>0b01100 SNP_DEBUG0_ROT32=>0b01101 SNP_DEBUG1_ROT0=>0b01110 SNP_DEBUG1_ROT16=>0b01111 SNP_DEBUG1_ROT32=>0b10000 ATR_DEBUG0_ROT0=>0b10001 ATR_DEBUG0_ROT16=>0b10010 ATR_DEBUG0_ROT32=>0b10011 ATSD_DEBUG0_ROT0=>0b10100 ATSD_DEBUG0_ROT16=>0b10101 ATSD_DEBUG0_ROT32=>0b10110 ATSD_DEBUG1_ROT0=>0b10111 ATSD_DEBUG1_ROT16=>0b11000 ATSD_DEBUG1_ROT32=>0b11001 ATSD_DEBUG2_ROT0=>0b11010 ATSD_DEBUG2_ROT16=>0b11011 ATSD_DEBUG2_ROT32=>0b11100 ATSD_DEBUG4_ROT0=>0b11101 ATSD_DEBUG4_ROT16=>0b11110 ATSD_DEBUG4_ROT32=>0b11111 | |
| 5:9 | RW | RW | DEBUG1_CONFIG_POD1: Mux control for byte 1 of trace-1 Dial enums: POD_INP1=>0b00000 POD_INP2=>0b00001 POD_INP3=>0b00010 POD_INP4=>0b00011 POD_INP5=>0b00100 POD_INP6=>0b00101 POD_INP7=>0b00110 POD_INP8=>0b00111 POD_INP9=>0b01000 POD_INP10=>0b01001 POD_INP0=>0b01010 SNP_DEBUG0_ROT0=>0b01011 SNP_DEBUG0_ROT16=>0b01100 SNP_DEBUG0_ROT32=>0b01101 SNP_DEBUG1_ROT0=>0b01110 SNP_DEBUG1_ROT16=>0b01111 SNP_DEBUG1_ROT32=>0b10000 ATR_DEBUG0_ROT0=>0b10001 ATR_DEBUG0_ROT16=>0b10010 ATR_DEBUG0_ROT32=>0b10011 ATSD_DEBUG0_ROT0=>0b10100 ATSD_DEBUG0_ROT16=>0b10101 ATSD_DEBUG0_ROT32=>0b10110 ATSD_DEBUG1_ROT0=>0b10111 ATSD_DEBUG1_ROT16=>0b11000 ATSD_DEBUG1_ROT32=>0b11001 ATSD_DEBUG2_ROT0=>0b11010 ATSD_DEBUG2_ROT16=>0b11011 ATSD_DEBUG2_ROT32=>0b11100 ATSD_DEBUG4_ROT0=>0b11101 ATSD_DEBUG4_ROT16=>0b11110 ATSD_DEBUG4_ROT32=>0b11111 | |
| 10:14 | RW | RW | DEBUG1_CONFIG_POD2: Mux control for byte 2 of trace-1 Dial enums: POD_INP2=>0b00000 POD_INP3=>0b00001 POD_INP4=>0b00010 POD_INP5=>0b00011 POD_INP6=>0b00100 POD_INP7=>0b00101 POD_INP8=>0b00110 POD_INP9=>0b00111 POD_INP10=>0b01000 POD_INP0=>0b01001 POD_INP1=>0b01010 SNP_DEBUG0_ROT0=>0b01011 SNP_DEBUG0_ROT16=>0b01100 SNP_DEBUG0_ROT32=>0b01101 SNP_DEBUG1_ROT0=>0b01110 SNP_DEBUG1_ROT16=>0b01111 SNP_DEBUG1_ROT32=>0b10000 ATR_DEBUG0_ROT0=>0b10001 ATR_DEBUG0_ROT16=>0b10010 ATR_DEBUG0_ROT32=>0b10011 ATSD_DEBUG0_ROT0=>0b10100 ATSD_DEBUG0_ROT16=>0b10101 ATSD_DEBUG0_ROT32=>0b10110 ATSD_DEBUG1_ROT0=>0b10111 ATSD_DEBUG1_ROT16=>0b11000 ATSD_DEBUG1_ROT32=>0b11001 ATSD_DEBUG2_ROT0=>0b11010 ATSD_DEBUG2_ROT16=>0b11011 ATSD_DEBUG2_ROT32=>0b11100 ATSD_DEBUG4_ROT0=>0b11101 ATSD_DEBUG4_ROT16=>0b11110 ATSD_DEBUG4_ROT32=>0b11111 | |
| 15:19 | RW | RW | DEBUG1_CONFIG_POD3: Mux control for byte 3 of trace-1 Dial enums: POD_INP3=>0b00000 POD_INP4=>0b00001 POD_INP5=>0b00010 POD_INP6=>0b00011 POD_INP7=>0b00100 POD_INP8=>0b00101 POD_INP9=>0b00110 POD_INP10=>0b00111 POD_INP0=>0b01000 POD_INP1=>0b01001 POD_INP2=>0b01010 SNP_DEBUG0_ROT0=>0b01011 SNP_DEBUG0_ROT16=>0b01100 SNP_DEBUG0_ROT32=>0b01101 SNP_DEBUG1_ROT0=>0b01110 SNP_DEBUG1_ROT16=>0b01111 SNP_DEBUG1_ROT32=>0b10000 ATR_DEBUG0_ROT0=>0b10001 ATR_DEBUG0_ROT16=>0b10010 ATR_DEBUG0_ROT32=>0b10011 ATSD_DEBUG0_ROT0=>0b10100 ATSD_DEBUG0_ROT16=>0b10101 ATSD_DEBUG0_ROT32=>0b10110 ATSD_DEBUG1_ROT0=>0b10111 ATSD_DEBUG1_ROT16=>0b11000 ATSD_DEBUG1_ROT32=>0b11001 ATSD_DEBUG2_ROT0=>0b11010 ATSD_DEBUG2_ROT16=>0b11011 ATSD_DEBUG2_ROT32=>0b11100 ATSD_DEBUG4_ROT0=>0b11101 ATSD_DEBUG4_ROT16=>0b11110 ATSD_DEBUG4_ROT32=>0b11111 | |
| 20:24 | RW | RW | DEBUG1_CONFIG_POD4: Mux control for byte 4 of trace-1 Dial enums: POD_INP4=>0b00000 POD_INP5=>0b00001 POD_INP6=>0b00010 POD_INP7=>0b00011 POD_INP8=>0b00100 POD_INP9=>0b00101 POD_INP10=>0b00110 POD_INP0=>0b00111 POD_INP1=>0b01000 POD_INP2=>0b01001 POD_INP3=>0b01010 SNP_DEBUG0_ROT0=>0b01011 SNP_DEBUG0_ROT16=>0b01100 SNP_DEBUG0_ROT32=>0b01101 SNP_DEBUG1_ROT0=>0b01110 SNP_DEBUG1_ROT16=>0b01111 SNP_DEBUG1_ROT32=>0b10000 ATR_DEBUG0_ROT0=>0b10001 ATR_DEBUG0_ROT16=>0b10010 ATR_DEBUG0_ROT32=>0b10011 ATSD_DEBUG0_ROT0=>0b10100 ATSD_DEBUG0_ROT16=>0b10101 ATSD_DEBUG0_ROT32=>0b10110 ATSD_DEBUG1_ROT0=>0b10111 ATSD_DEBUG1_ROT16=>0b11000 ATSD_DEBUG1_ROT32=>0b11001 ATSD_DEBUG2_ROT0=>0b11010 ATSD_DEBUG2_ROT16=>0b11011 ATSD_DEBUG2_ROT32=>0b11100 ATSD_DEBUG4_ROT0=>0b11101 ATSD_DEBUG4_ROT16=>0b11110 ATSD_DEBUG4_ROT32=>0b11111 | |
| 25:29 | RW | RW | DEBUG1_CONFIG_POD5: Mux control for byte 5 of trace-1 Dial enums: POD_INP5=>0b00000 POD_INP6=>0b00001 POD_INP7=>0b00010 POD_INP8=>0b00011 POD_INP9=>0b00100 POD_INP10=>0b00101 POD_INP0=>0b00110 POD_INP1=>0b00111 POD_INP2=>0b01000 POD_INP3=>0b01001 POD_INP4=>0b01010 SNP_DEBUG0_ROT0=>0b01011 SNP_DEBUG0_ROT16=>0b01100 SNP_DEBUG0_ROT32=>0b01101 SNP_DEBUG1_ROT0=>0b01110 SNP_DEBUG1_ROT16=>0b01111 SNP_DEBUG1_ROT32=>0b10000 ATR_DEBUG0_ROT0=>0b10001 ATR_DEBUG0_ROT16=>0b10010 ATR_DEBUG0_ROT32=>0b10011 ATSD_DEBUG0_ROT0=>0b10100 ATSD_DEBUG0_ROT16=>0b10101 ATSD_DEBUG0_ROT32=>0b10110 ATSD_DEBUG1_ROT0=>0b10111 ATSD_DEBUG1_ROT16=>0b11000 ATSD_DEBUG1_ROT32=>0b11001 ATSD_DEBUG2_ROT0=>0b11010 ATSD_DEBUG2_ROT16=>0b11011 ATSD_DEBUG2_ROT32=>0b11100 ATSD_DEBUG4_ROT0=>0b11101 ATSD_DEBUG4_ROT16=>0b11110 ATSD_DEBUG4_ROT32=>0b11111 | |
| 30:34 | RW | RW | DEBUG1_CONFIG_POD6: Mux control for byte 6 of trace-1 Dial enums: POD_INP6=>0b00000 POD_INP7=>0b00001 POD_INP8=>0b00010 POD_INP9=>0b00011 POD_INP10=>0b00100 POD_INP0=>0b00101 POD_INP1=>0b00110 POD_INP2=>0b00111 POD_INP3=>0b01000 POD_INP4=>0b01001 POD_INP5=>0b01010 SNP_DEBUG0_ROT0=>0b01011 SNP_DEBUG0_ROT16=>0b01100 SNP_DEBUG0_ROT32=>0b01101 SNP_DEBUG1_ROT0=>0b01110 SNP_DEBUG1_ROT16=>0b01111 SNP_DEBUG1_ROT32=>0b10000 ATR_DEBUG0_ROT0=>0b10001 ATR_DEBUG0_ROT16=>0b10010 ATR_DEBUG0_ROT32=>0b10011 ATSD_DEBUG0_ROT0=>0b10100 ATSD_DEBUG0_ROT16=>0b10101 ATSD_DEBUG0_ROT32=>0b10110 ATSD_DEBUG1_ROT0=>0b10111 ATSD_DEBUG1_ROT16=>0b11000 ATSD_DEBUG1_ROT32=>0b11001 ATSD_DEBUG2_ROT0=>0b11010 ATSD_DEBUG2_ROT16=>0b11011 ATSD_DEBUG2_ROT32=>0b11100 ATSD_DEBUG4_ROT0=>0b11101 ATSD_DEBUG4_ROT16=>0b11110 ATSD_DEBUG4_ROT32=>0b11111 | |
| 35:39 | RW | RW | DEBUG1_CONFIG_POD7: Mux control for byte 7 of trace-1 Dial enums: POD_INP7=>0b00000 POD_INP8=>0b00001 POD_INP9=>0b00010 POD_INP10=>0b00011 POD_INP0=>0b00100 POD_INP1=>0b00101 POD_INP2=>0b00110 POD_INP3=>0b00111 POD_INP4=>0b01000 POD_INP5=>0b01001 POD_INP6=>0b01010 SNP_DEBUG0_ROT0=>0b01011 SNP_DEBUG0_ROT16=>0b01100 SNP_DEBUG0_ROT32=>0b01101 SNP_DEBUG1_ROT0=>0b01110 SNP_DEBUG1_ROT16=>0b01111 SNP_DEBUG1_ROT32=>0b10000 ATR_DEBUG0_ROT0=>0b10001 ATR_DEBUG0_ROT16=>0b10010 ATR_DEBUG0_ROT32=>0b10011 ATSD_DEBUG0_ROT0=>0b10100 ATSD_DEBUG0_ROT16=>0b10101 ATSD_DEBUG0_ROT32=>0b10110 ATSD_DEBUG1_ROT0=>0b10111 ATSD_DEBUG1_ROT16=>0b11000 ATSD_DEBUG1_ROT32=>0b11001 ATSD_DEBUG2_ROT0=>0b11010 ATSD_DEBUG2_ROT16=>0b11011 ATSD_DEBUG2_ROT32=>0b11100 ATSD_DEBUG4_ROT0=>0b11101 ATSD_DEBUG4_ROT16=>0b11110 ATSD_DEBUG4_ROT32=>0b11111 | |
| 40:44 | RW | RW | DEBUG1_CONFIG_POD8: Mux control for byte 8 of trace-1 Dial enums: POD_INP8=>0b00000 POD_INP9=>0b00001 POD_INP10=>0b00010 POD_INP0=>0b00011 POD_INP1=>0b00100 POD_INP2=>0b00101 POD_INP3=>0b00110 POD_INP4=>0b00111 POD_INP5=>0b01000 POD_INP6=>0b01001 POD_INP7=>0b01010 SNP_DEBUG0_ROT0=>0b01011 SNP_DEBUG0_ROT16=>0b01100 SNP_DEBUG0_ROT32=>0b01101 SNP_DEBUG1_ROT0=>0b01110 SNP_DEBUG1_ROT16=>0b01111 SNP_DEBUG1_ROT32=>0b10000 ATR_DEBUG0_ROT0=>0b10001 ATR_DEBUG0_ROT16=>0b10010 ATR_DEBUG0_ROT32=>0b10011 ATSD_DEBUG0_ROT0=>0b10100 ATSD_DEBUG0_ROT16=>0b10101 ATSD_DEBUG0_ROT32=>0b10110 ATSD_DEBUG1_ROT0=>0b10111 ATSD_DEBUG1_ROT16=>0b11000 ATSD_DEBUG1_ROT32=>0b11001 ATSD_DEBUG2_ROT0=>0b11010 ATSD_DEBUG2_ROT16=>0b11011 ATSD_DEBUG2_ROT32=>0b11100 ATSD_DEBUG4_ROT0=>0b11101 ATSD_DEBUG4_ROT16=>0b11110 ATSD_DEBUG4_ROT32=>0b11111 | |
| 45:49 | RW | RW | DEBUG1_CONFIG_POD9: Mux control for byte 9 of trace-1 Dial enums: POD_INP9=>0b00000 POD_INP10=>0b00001 POD_INP0=>0b00010 POD_INP1=>0b00011 POD_INP2=>0b00100 POD_INP3=>0b00101 POD_INP4=>0b00110 POD_INP5=>0b00111 POD_INP6=>0b01000 POD_INP7=>0b01001 POD_INP8=>0b01010 SNP_DEBUG0_ROT0=>0b01011 SNP_DEBUG0_ROT16=>0b01100 SNP_DEBUG0_ROT32=>0b01101 SNP_DEBUG1_ROT0=>0b01110 SNP_DEBUG1_ROT16=>0b01111 SNP_DEBUG1_ROT32=>0b10000 ATR_DEBUG0_ROT0=>0b10001 ATR_DEBUG0_ROT16=>0b10010 ATR_DEBUG0_ROT32=>0b10011 ATSD_DEBUG0_ROT0=>0b10100 ATSD_DEBUG0_ROT16=>0b10101 ATSD_DEBUG0_ROT32=>0b10110 ATSD_DEBUG1_ROT0=>0b10111 ATSD_DEBUG1_ROT16=>0b11000 ATSD_DEBUG1_ROT32=>0b11001 ATSD_DEBUG2_ROT0=>0b11010 ATSD_DEBUG2_ROT16=>0b11011 ATSD_DEBUG2_ROT32=>0b11100 ATSD_DEBUG4_ROT0=>0b11101 ATSD_DEBUG4_ROT16=>0b11110 ATSD_DEBUG4_ROT32=>0b11111 | |
| 50:54 | RW | RW | DEBUG1_CONFIG_POD10: Mux control for byte 10 of trace-1 Dial enums: POD_INP10=>0b00000 POD_INP0=>0b00001 POD_INP1=>0b00010 POD_INP2=>0b00011 POD_INP3=>0b00100 POD_INP4=>0b00101 POD_INP5=>0b00110 POD_INP6=>0b00111 POD_INP7=>0b01000 POD_INP8=>0b01001 POD_INP9=>0b01010 SNP_DEBUG0_ROT0=>0b01011 SNP_DEBUG0_ROT16=>0b01100 SNP_DEBUG0_ROT32=>0b01101 SNP_DEBUG1_ROT0=>0b01110 SNP_DEBUG1_ROT16=>0b01111 SNP_DEBUG1_ROT32=>0b10000 ATR_DEBUG0_ROT0=>0b10001 ATR_DEBUG0_ROT16=>0b10010 ATR_DEBUG0_ROT32=>0b10011 ATSD_DEBUG0_ROT0=>0b10100 ATSD_DEBUG0_ROT16=>0b10101 ATSD_DEBUG0_ROT32=>0b10110 ATSD_DEBUG1_ROT0=>0b10111 ATSD_DEBUG1_ROT16=>0b11000 ATSD_DEBUG1_ROT32=>0b11001 ATSD_DEBUG2_ROT0=>0b11010 ATSD_DEBUG2_ROT16=>0b11011 ATSD_DEBUG2_ROT32=>0b11100 ATSD_DEBUG4_ROT0=>0b11101 ATSD_DEBUG4_ROT16=>0b11110 ATSD_DEBUG4_ROT32=>0b11111 | |
| 55:62 | RW | RW | DEBUG1_CONFIG_RESERVED1: reserved | |
| 63 | RW | RW | DEBUG1_CONFIG_ACT: Enable clock-gates for debug trace latches | |
| pau xts pmulet count register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010AF8 (SCOM) 0000000013710040 (PAU_RING) | |||
| Name: | PAU3.XTS.REG.XTS_PMU_CNT | |||
| Constant(s): | ||||
| Comments: | The PAU XTS PMULet Count Register contains the PMULet counters in XTS (4 x 16b) | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:15 | PAU3.XTS.REG.PMLET.COUNTER0_CNT_Q_0_INST.LATC.L2(0:15) [0000000000000000] | |||
| 16:31 | PAU3.XTS.REG.PMLET.COUNTER1_CNT_Q_0_INST.LATC.L2(0:15) [0000000000000000] | |||
| 32:47 | PAU3.XTS.REG.PMLET.COUNTER2_CNT_Q_0_INST.LATC.L2(0:15) [0000000000000000] | |||
| 48:63 | PAU3.XTS.REG.PMLET.COUNTER3_CNT_Q_0_INST.LATC.L2(0:15) [0000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:15 | ROX | ROX | XTS_PMU_CNT0: PMULet Counter 0 | |
| 16:31 | ROX | ROX | XTS_PMU_CNT1: PMULet Counter 1 | |
| 32:47 | ROX | ROX | XTS_PMU_CNT2: PMULet Counter 2 | |
| 48:63 | ROX | ROX | XTS_PMU_CNT3: PMULet Counter 3 | |
| XTS ATRMiss Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010AFA (SCOM) 0000000013710050 (PAU_RING) | |||
| Name: | PAU3.XTS.REG.XTS_ATRMISS | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 15:51 | PAU3.XTS.REG.ATRMISS_ADDRQ.LATC.L2(15:51) [0000000000000000000000000000000000000] | |||
| 54 | PAU3.XTS.REG.ATRMISS_FLAG_OTHERQ.LATC.L2(0) [0] | |||
| 55 | PAU3.XTS.REG.ATRMISS_FLAG_PREFQ.LATC.L2(0) [0] | |||
| 56 | PAU3.XTS.REG.ATRMISS_FLAG_DMDQ.LATC.L2(0) [0] | |||
| 57 | PAU3.XTS.REG.ATRMISS_FLAG_MAPQ.LATC.L2(0) [0] | |||
| 58 | PAU3.XTS.REG.ATRMISS_FLAG_FENCEQ.LATC.L2(0) [0] | |||
| 59 | PAU3.XTS.REG.ATRMISS_RETIREQ.LATC.L2(0) [0] | |||
| 60 | PAU3.XTS.REG.ATRMISS_IRQENAQ.LATC.L2(0) [0] | |||
| 61 | PAU3.XTS.REG.ATRMISS_SECONDQ.LATC.L2(0) [0] | |||
| 62 | PAU3.XTS.REG.ATRMISS_TRIGGEREDQ.LATC.L2(0) [0] | |||
| 63 | PAU3.XTS.REG.ATRMISS_ENAQ.LATC.L2(0) [0] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:14 | RO | RO | constant=0b000000000000000 | |
| 15:51 | RWX | RWX | XTS_ATRMISS_ADDR: Holds captured effective address, cleared when reading the atrmissclr register | |
| 52:53 | RO | RO | constant=0b00 | |
| 54 | RW | RW | XTS_ATRMISS_FLAG_OTHER: enable IRQ and capture for misses caused by other issues, i.e., prefetch page size mismatch | |
| 55 | RW | RW | XTS_ATRMISS_FLAG_PREF: enable IRQ and capture for misses caused by prefetch NMMU requests | |
| 56 | RW | RW | XTS_ATRMISS_FLAG_DMD: enable IRQ and capture for misses caused by demand NMMU requests | |
| 57 | RW | RW | XTS_ATRMISS_FLAG_MAP: enable IRQ and capture for misses caused by BDF/PASID map look-up | |
| 58 | RW | RW | XTS_ATRMISS_FLAG_FENCE: enable IRQ and capture for misses caused by fencing | |
| 59 | RW | RW | XTS_ATRMISS_RETIRE: If set, launch IRQ after ATR response sent to GPU, otherwise launch IRQ immediately on miss | |
| 60 | RW | RW | XTS_ATRMISS_IRQENA: if set, triggers interrupt on qualifying ATR miss (IRQ is independent from capture) | |
| 61 | RWX | RWX | XTS_ATRMISS_SECOND: set to one by second ATR miss capture, cleared when reading the atrmissclr register | |
| 62 | RWX | RWX | XTS_ATRMISS_TRIGGERED: capture only if this bit is clear, set to one by HW on first ATR miss capture, cleared when reading the atrmissclr register | |
| 63 | RW | RW | XTS_ATRMISS_ENA: Enable ATR attr capture on miss | |
| XTS ATRMissClear Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010AFB (SCOM) 0000000013710058 (PAU_RING) | |||
| Name: | PAU3.XTS.REG.XTS_ATRMISSCLR | |||
| Constant(s): | ||||
| Comments: | Reading this register causes clearing of a subset of fields of the atrmiss as well as atrmiss2 register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 15:51 | PAU3.XTS.REG.ATRMISS_ADDRQ.LATC.L2(15:51) [0000000000000000000000000000000000000] | |||
| 54 | PAU3.XTS.REG.ATRMISS_FLAG_OTHERQ.LATC.L2(0) [0] | |||
| 55 | PAU3.XTS.REG.ATRMISS_FLAG_PREFQ.LATC.L2(0) [0] | |||
| 56 | PAU3.XTS.REG.ATRMISS_FLAG_DMDQ.LATC.L2(0) [0] | |||
| 57 | PAU3.XTS.REG.ATRMISS_FLAG_MAPQ.LATC.L2(0) [0] | |||
| 58 | PAU3.XTS.REG.ATRMISS_FLAG_FENCEQ.LATC.L2(0) [0] | |||
| 59 | PAU3.XTS.REG.ATRMISS_RETIREQ.LATC.L2(0) [0] | |||
| 60 | PAU3.XTS.REG.ATRMISS_IRQENAQ.LATC.L2(0) [0] | |||
| 61 | PAU3.XTS.REG.ATRMISS_SECONDQ.LATC.L2(0) [0] | |||
| 62 | PAU3.XTS.REG.ATRMISS_TRIGGEREDQ.LATC.L2(0) [0] | |||
| 63 | PAU3.XTS.REG.ATRMISS_ENAQ.LATC.L2(0) [0] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:14 | RO | RO | constant=0b000000000000000 | |
| 15:51 | ROX | ROX | XTS_ATRMISS_ADDR: Holds captured effective address, cleared when reading the atrmissclr register | |
| 52:53 | RO | RO | constant=0b00 | |
| 54 | ROX | ROX | XTS_ATRMISS_FLAG_OTHER: enable IRQ and capture for misses caused by other issues, i.e., prefetch page size mismatch | |
| 55 | ROX | ROX | XTS_ATRMISS_FLAG_PREF: enable IRQ and capture for misses caused by prefetch NMMU requests | |
| 56 | ROX | ROX | XTS_ATRMISS_FLAG_DMD: enable IRQ and capture for misses caused by demand NMMU requests | |
| 57 | ROX | ROX | XTS_ATRMISS_FLAG_MAP: enable IRQ and capture for misses caused by BDF/PASID map look-up | |
| 58 | ROX | ROX | XTS_ATRMISS_FLAG_FENCE: enable IRQ and capture for misses caused by fencing | |
| 59 | ROX | ROX | XTS_ATRMISS_RETIRE: If set, launch IRQ after ATR response sent to GPU, otherwise launch IRQ immediately on miss | |
| 60 | ROX | ROX | XTS_ATRMISS_IRQENA: if set, triggers interrupt on qualifying ATR miss (IRQ is independent from capture) | |
| 61 | ROX | ROX | XTS_ATRMISS_SECOND: set to one by second ATR miss capture, cleared when reading the atrmissclr register | |
| 62 | ROX | ROX | XTS_ATRMISS_TRIGGERED: capture only if this bit is clear, set to one by HW on first ATR miss capture, cleared when reading the atrmissclr register | |
| 63 | ROX | ROX | XTS_ATRMISS_ENA: Enable ATR attr capture on miss | |
| XTS ATRMiss Register 2 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010AFC (SCOM) 0000000013710060 (PAU_RING) | |||
| Name: | PAU3.XTS.REG.XTS_ATRMISS2 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 27 | PAU3.XTS.REG.ATRMISS_GPAQ.LATC.L2(0) [0] | |||
| 28:43 | PAU3.XTS.REG.ATRMISS_BDFQ.LATC.L2(0:15) [0000000000000000] | |||
| 44:63 | PAU3.XTS.REG.ATRMISS_PASIDQ.LATC.L2(0:19) [00000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:26 | RO | RO | constant=0b000000000000000000000000000 | |
| 27 | RWX | RWX | XTS_ATRMISS_GPA: Holds captured GPA flag, cleared when reading the atrmissclr register | |
| 28:43 | RWX | RWX | XTS_ATRMISS_BDF: Holds captured BDF, cleared when reading the atrmissclr register | |
| 44:63 | RWX | RWX | XTS_ATRMISS_PASID: Holds capture PASID, cleared when reading the atrmissclr register | |
| XTS Config3 Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010AFD (SCOM) 0000000013710068 (PAU_RING) | |||
| Name: | PAU3.XTS.REG.XTS_CONFIG3 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.XTS.REG.XTS_CONFIG3Q.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:3 | RW | RW | XTS_CONFIG3_CAP_RESERVE: Time out select for ATSD | |
| 4 | RW | RW | XTS_CONFIG3_ATSD_ALIGN: if set, forces alignment of ATSD address to page size | |
| 5 | RW | RW | XTS_CONFIG3_MMIOSD_OCAPI: enables OpenCAPI and AME MMIO controlled translation shoot downs | |
| 6 | RW | RW | XTS_CONFIG3_TLBIE_OVERLAP_OP2_EN: Enables NCU snoopers to expect overlapping of tlbi_op2 with tlbi_set | |
| 7 | RW | RW | XTS_CONFIG3_NVLINK_16CHIP_MODE: 0/1 = compress & decompress NVLink addresses for 8-chip support / 16-chip support | |
| 8 | RW | RW | XTS_CONFIG3_HANG_PULSE_DIS: if set, disables TLBIE Snooper data hang detect | |
| 9:18 | RW | RW | XTS_CONFIG3_TLB_SNOOP_DATA_POLL_PULSE_DIV: TLBIE Snooper data hang divider. | |
| 19:63 | RW | RW | XTS_CONFIG3_UNUSED: XTS config3 unused/reserved bits for future use | |
| XTS MMIO ATSD0 LPARID register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B10 (SCOM) 0000000013710100 (PAU_RING) | |||
| Name: | PAU3.XTS.ATSD.XTS_ATSD_HYP0 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 51 | PAU3.XTS.ATSD.SM0_MSRHVQ.LATC.L2(0) [0] | |||
| 52:63 | PAU3.XTS.ATSD.SM0_ADDR1Q.LATC.L2(52:63) [000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:50 | RO | RO | constant=0b000000000000000000000000000000000000000000000000000 | |
| 51 | RW | RW | XTS_ATSD_HYP0_MSRHV: MSR(HV) value for MMIO ATSD control entry 0 | |
| 52:63 | RW | RW | XTS_ATSD_HYP0_LPARID: LPARID value for MMIO ATSD control entry 0 | |
| XTS MMIO ATSD1 LPARID register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B11 (SCOM) 0000000013710108 (PAU_RING) | |||
| Name: | PAU3.XTS.ATSD.XTS_ATSD_HYP1 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 51 | PAU3.XTS.ATSD.SM1_MSRHVQ.LATC.L2(0) [0] | |||
| 52:63 | PAU3.XTS.ATSD.SM1_ADDR1Q.LATC.L2(52:63) [000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:50 | RO | RO | constant=0b000000000000000000000000000000000000000000000000000 | |
| 51 | RW | RW | XTS_ATSD_HYP1_MSRHV: MSR(HV) value for MMIO ATSD control entry 1 | |
| 52:63 | RW | RW | XTS_ATSD_HYP1_LPARID: LPARID value for MMIO ATSD control entry 1 | |
| XTS MMIO ATSD2 LPARID register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B12 (SCOM) 0000000013710110 (PAU_RING) | |||
| Name: | PAU3.XTS.ATSD.XTS_ATSD_HYP2 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 51 | PAU3.XTS.ATSD.SM2_MSRHVQ.LATC.L2(0) [0] | |||
| 52:63 | PAU3.XTS.ATSD.SM2_ADDR1Q.LATC.L2(52:63) [000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:50 | RO | RO | constant=0b000000000000000000000000000000000000000000000000000 | |
| 51 | RW | RW | XTS_ATSD_HYP2_MSRHV: MSR(HV) value for MMIO ATSD control entry 2 | |
| 52:63 | RW | RW | XTS_ATSD_HYP2_LPARID: LPARID value for MMIO ATSD control entry 2 | |
| XTS MMIO ATSD3 LPARID register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B13 (SCOM) 0000000013710118 (PAU_RING) | |||
| Name: | PAU3.XTS.ATSD.XTS_ATSD_HYP3 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 51 | PAU3.XTS.ATSD.SM3_MSRHVQ.LATC.L2(0) [0] | |||
| 52:63 | PAU3.XTS.ATSD.SM3_ADDR1Q.LATC.L2(52:63) [000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:50 | RO | RO | constant=0b000000000000000000000000000000000000000000000000000 | |
| 51 | RW | RW | XTS_ATSD_HYP3_MSRHV: MSR(HV) value for MMIO ATSD control entry 3 | |
| 52:63 | RW | RW | XTS_ATSD_HYP3_LPARID: LPARID value for MMIO ATSD control entry 3 | |
| XTS MMIO ATSD4 LPARID register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B14 (SCOM) 0000000013710120 (PAU_RING) | |||
| Name: | PAU3.XTS.ATSD.XTS_ATSD_HYP4 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 51 | PAU3.XTS.ATSD.SM4_MSRHVQ.LATC.L2(0) [0] | |||
| 52:63 | PAU3.XTS.ATSD.SM4_ADDR1Q.LATC.L2(52:63) [000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:50 | RO | RO | constant=0b000000000000000000000000000000000000000000000000000 | |
| 51 | RW | RW | XTS_ATSD_HYP4_MSRHV: MSR(HV) value for MMIO ATSD control entry 4 | |
| 52:63 | RW | RW | XTS_ATSD_HYP4_LPARID: LPARID value for MMIO ATSD control entry 4 | |
| XTS MMIO ATSD5 LPARID register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B15 (SCOM) 0000000013710128 (PAU_RING) | |||
| Name: | PAU3.XTS.ATSD.XTS_ATSD_HYP5 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 51 | PAU3.XTS.ATSD.SM5_MSRHVQ.LATC.L2(0) [0] | |||
| 52:63 | PAU3.XTS.ATSD.SM5_ADDR1Q.LATC.L2(52:63) [000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:50 | RO | RO | constant=0b000000000000000000000000000000000000000000000000000 | |
| 51 | RW | RW | XTS_ATSD_HYP5_MSRHV: MSR(HV) value for MMIO ATSD control entry 5 | |
| 52:63 | RW | RW | XTS_ATSD_HYP5_LPARID: LPARID value for MMIO ATSD control entry 5 | |
| XTS MMIO ATSD6 LPARID register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B16 (SCOM) 0000000013710130 (PAU_RING) | |||
| Name: | PAU3.XTS.ATSD.XTS_ATSD_HYP6 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 51 | PAU3.XTS.ATSD.SM6_MSRHVQ.LATC.L2(0) [0] | |||
| 52:63 | PAU3.XTS.ATSD.SM6_ADDR1Q.LATC.L2(52:63) [000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:50 | RO | RO | constant=0b000000000000000000000000000000000000000000000000000 | |
| 51 | RW | RW | XTS_ATSD_HYP6_MSRHV: MSR(HV) value for MMIO ATSD control entry 6 | |
| 52:63 | RW | RW | XTS_ATSD_HYP6_LPARID: LPARID value for MMIO ATSD control entry 6 | |
| XTS MMIO ATSD7 LPARID register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B17 (SCOM) 0000000013710138 (PAU_RING) | |||
| Name: | PAU3.XTS.ATSD.XTS_ATSD_HYP7 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 51 | PAU3.XTS.ATSD.SM7_MSRHVQ.LATC.L2(0) [0] | |||
| 52:63 | PAU3.XTS.ATSD.SM7_ADDR1Q.LATC.L2(52:63) [000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:50 | RO | RO | constant=0b000000000000000000000000000000000000000000000000000 | |
| 51 | RW | RW | XTS_ATSD_HYP7_MSRHV: MSR(HV) value for MMIO ATSD control entry 7 | |
| 52:63 | RW | RW | XTS_ATSD_HYP7_LPARID: LPARID value for MMIO ATSD control entry 7 | |
| XTS MMIO ATSD8 LPARID register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B18 (SCOM) 0000000013710140 (PAU_RING) | |||
| Name: | PAU3.XTS.ATSD.XTS_ATSD_HYP8 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 51 | PAU3.XTS.ATSD.SM8_MSRHVQ.LATC.L2(0) [0] | |||
| 52:63 | PAU3.XTS.ATSD.SM8_ADDR1Q.LATC.L2(52:63) [000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:50 | RO | RO | constant=0b000000000000000000000000000000000000000000000000000 | |
| 51 | RW | RW | XTS_ATSD_HYP8_MSRHV: MSR(HV) value for MMIO ATSD control entry 8 | |
| 52:63 | RW | RW | XTS_ATSD_HYP8_LPARID: LPARID value for MMIO ATSD control entry 8 | |
| XTS MMIO ATSD9 LPARID register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B19 (SCOM) 0000000013710148 (PAU_RING) | |||
| Name: | PAU3.XTS.ATSD.XTS_ATSD_HYP9 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 51 | PAU3.XTS.ATSD.SM9_MSRHVQ.LATC.L2(0) [0] | |||
| 52:63 | PAU3.XTS.ATSD.SM9_ADDR1Q.LATC.L2(52:63) [000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:50 | RO | RO | constant=0b000000000000000000000000000000000000000000000000000 | |
| 51 | RW | RW | XTS_ATSD_HYP9_MSRHV: MSR(HV) value for MMIO ATSD control entry 9 | |
| 52:63 | RW | RW | XTS_ATSD_HYP9_LPARID: LPARID value for MMIO ATSD control entry 9 | |
| XTS MMIO ATSD10 LPARID register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B1A (SCOM) 0000000013710150 (PAU_RING) | |||
| Name: | PAU3.XTS.ATSD.XTS_ATSD_HYP10 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 51 | PAU3.XTS.ATSD.SM10_MSRHVQ.LATC.L2(0) [0] | |||
| 52:63 | PAU3.XTS.ATSD.SM10_ADDR1Q.LATC.L2(52:63) [000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:50 | RO | RO | constant=0b000000000000000000000000000000000000000000000000000 | |
| 51 | RW | RW | XTS_ATSD_HYP10_MSRHV: MSR(HV) value for MMIO ATSD control entry 10 | |
| 52:63 | RW | RW | XTS_ATSD_HYP10_LPARID: LPARID value for MMIO ATSD control entry 10 | |
| XTS MMIO ATSD11 LPARID register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B1B (SCOM) 0000000013710158 (PAU_RING) | |||
| Name: | PAU3.XTS.ATSD.XTS_ATSD_HYP11 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 51 | PAU3.XTS.ATSD.SM11_MSRHVQ.LATC.L2(0) [0] | |||
| 52:63 | PAU3.XTS.ATSD.SM11_ADDR1Q.LATC.L2(52:63) [000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:50 | RO | RO | constant=0b000000000000000000000000000000000000000000000000000 | |
| 51 | RW | RW | XTS_ATSD_HYP11_MSRHV: MSR(HV) value for MMIO ATSD control entry 11 | |
| 52:63 | RW | RW | XTS_ATSD_HYP11_LPARID: LPARID value for MMIO ATSD control entry 11 | |
| XTS MMIO ATSD12 LPARID register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B1C (SCOM) 0000000013710160 (PAU_RING) | |||
| Name: | PAU3.XTS.ATSD.XTS_ATSD_HYP12 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 51 | PAU3.XTS.ATSD.SM12_MSRHVQ.LATC.L2(0) [0] | |||
| 52:63 | PAU3.XTS.ATSD.SM12_ADDR1Q.LATC.L2(52:63) [000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:50 | RO | RO | constant=0b000000000000000000000000000000000000000000000000000 | |
| 51 | RW | RW | XTS_ATSD_HYP12_MSRHV: MSR(HV) value for MMIO ATSD control entry 12 | |
| 52:63 | RW | RW | XTS_ATSD_HYP12_LPARID: LPARID value for MMIO ATSD control entry 12 | |
| XTS MMIO ATSD13 LPARID register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B1D (SCOM) 0000000013710168 (PAU_RING) | |||
| Name: | PAU3.XTS.ATSD.XTS_ATSD_HYP13 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 51 | PAU3.XTS.ATSD.SM13_MSRHVQ.LATC.L2(0) [0] | |||
| 52:63 | PAU3.XTS.ATSD.SM13_ADDR1Q.LATC.L2(52:63) [000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:50 | RO | RO | constant=0b000000000000000000000000000000000000000000000000000 | |
| 51 | RW | RW | XTS_ATSD_HYP13_MSRHV: MSR(HV) value for MMIO ATSD control entry 13 | |
| 52:63 | RW | RW | XTS_ATSD_HYP13_LPARID: LPARID value for MMIO ATSD control entry 13 | |
| XTS MMIO ATSD14 LPARID register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B1E (SCOM) 0000000013710170 (PAU_RING) | |||
| Name: | PAU3.XTS.ATSD.XTS_ATSD_HYP14 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 51 | PAU3.XTS.ATSD.SM14_MSRHVQ.LATC.L2(0) [0] | |||
| 52:63 | PAU3.XTS.ATSD.SM14_ADDR1Q.LATC.L2(52:63) [000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:50 | RO | RO | constant=0b000000000000000000000000000000000000000000000000000 | |
| 51 | RW | RW | XTS_ATSD_HYP14_MSRHV: MSR(HV) value for MMIO ATSD control entry 14 | |
| 52:63 | RW | RW | XTS_ATSD_HYP14_LPARID: LPARID value for MMIO ATSD control entry 14 | |
| XTS MMIO ATSD15 LPARID register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B1F (SCOM) 0000000013710178 (PAU_RING) | |||
| Name: | PAU3.XTS.ATSD.XTS_ATSD_HYP15 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 51 | PAU3.XTS.ATSD.SM15_MSRHVQ.LATC.L2(0) [0] | |||
| 52:63 | PAU3.XTS.ATSD.SM15_ADDR1Q.LATC.L2(52:63) [000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:50 | RO | RO | constant=0b000000000000000000000000000000000000000000000000000 | |
| 51 | RW | RW | XTS_ATSD_HYP15_MSRHV: MSR(HV) value for MMIO ATSD control entry 15 | |
| 52:63 | RW | RW | XTS_ATSD_HYP15_LPARID: LPARID value for MMIO ATSD control entry 15 | |
| Debug Config | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B30 (SCOM) 0000000013720000 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.DEBUG_CONFIG | |||
| Constant(s): | ||||
| Comments: | Debug Config register Selects between PAU internal or misc macro debug bus to route the to the 2 external debug busses. The debug bus is 11 bytes wide, with each byte selected independently using 2 bit control. 0b00 = PAU internal debug bus 0b01 = Reserved 0b10 = Reserved 0b11 = MISC macro debug bus | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.MISC.REGS.DEBUG_CONFIGQ.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:1 | RW | RW | MISC_DEBUG_CONFIG_BUS0BYTE0: 2b select for external bus 0, byte 0 | |
| 2:3 | RW | RW | MISC_DEBUG_CONFIG_BUS0BYTE1: 2b select for external bus 0, byte 1 | |
| 4:5 | RW | RW | MISC_DEBUG_CONFIG_BUS0BYTE2: 2b select for external bus 0, byte 2 | |
| 6:7 | RW | RW | MISC_DEBUG_CONFIG_BUS0BYTE3: 2b select for external bus 0, byte 3 | |
| 8:9 | RW | RW | MISC_DEBUG_CONFIG_BUS0BYTE4: 2b select for external bus 0, byte 4 | |
| 10:11 | RW | RW | MISC_DEBUG_CONFIG_BUS0BYTE5: 2b select for external bus 0, byte 5 | |
| 12:13 | RW | RW | MISC_DEBUG_CONFIG_BUS0BYTE6: 2b select for external bus 0, byte 6 | |
| 14:15 | RW | RW | MISC_DEBUG_CONFIG_BUS0BYTE7: 2b select for external bus 0, byte 7 | |
| 16:17 | RW | RW | MISC_DEBUG_CONFIG_BUS0BYTE8: 2b select for external bus 0, byte 8 | |
| 18:19 | RW | RW | MISC_DEBUG_CONFIG_BUS0BYTE9: 2b select for external bus 0, byte 9 | |
| 20:21 | RW | RW | MISC_DEBUG_CONFIG_BUS0BYTE10: 2b select for external bus 0, byte 10 | |
| 22:23 | RW | RW | MISC_DEBUG_CONFIG_BUS1BYTE0: 2b select for external bus 1, byte 0 | |
| 24:25 | RW | RW | MISC_DEBUG_CONFIG_BUS1BYTE1: 2b select for external bus 1, byte 1 | |
| 26:27 | RW | RW | MISC_DEBUG_CONFIG_BUS1BYTE2: 2b select for external bus 1, byte 2 | |
| 28:29 | RW | RW | MISC_DEBUG_CONFIG_BUS1BYTE3: 2b select for external bus 1, byte 3 | |
| 30:31 | RW | RW | MISC_DEBUG_CONFIG_BUS1BYTE4: 2b select for external bus 1, byte 4 | |
| 32:33 | RW | RW | MISC_DEBUG_CONFIG_BUS1BYTE5: 2b select for external bus 1, byte 5 | |
| 34:35 | RW | RW | MISC_DEBUG_CONFIG_BUS1BYTE6: 2b select for external bus 1, byte 6 | |
| 36:37 | RW | RW | MISC_DEBUG_CONFIG_BUS1BYTE7: 2b select for external bus 1, byte 7 | |
| 38:39 | RW | RW | MISC_DEBUG_CONFIG_BUS1BYTE8: 2b select for external bus 1, byte 8 | |
| 40:41 | RW | RW | MISC_DEBUG_CONFIG_BUS1BYTE9: 2b select for external bus 1, byte 9 | |
| 42:43 | RW | RW | MISC_DEBUG_CONFIG_BUS1BYTE10: 2b select for external bus 1, byte 10 | |
| 44:62 | RW | RW | RESERVED: Reserved | |
| 63 | RW | RW | ACT_DEBUG: Clock activate MISC macro debug logic | |
| Optical IO Transport Mux Config | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B33 (SCOM) 0000000013720018 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.OPTICAL_IO_CONFIG | |||
| Constant(s): | ||||
| Comments: | Inbound Mux controls for link transport buses from link PHY to PAU. | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:3 | PAU3.MISC.REGS.OPTICAL_IO_CONFIGQ.LATC.L2(0:3) [0000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | PAU_TRANSPORT_NTL0_NOT_OTH: Even OTL inbound PHY source for PAU4-7. 0b0=select matching PHY, 0b1=select other PHY. Spare in PAU0/3. | |
| 1 | RW | RW | PAU_TRANSPORT_NTL1_NOT_OTH: Odd OTL inbound PHY source for PAU4-7. 0b0=select matching PHY, 0b1=select other PHY. Spare in PAU0/3. | |
| 2 | RW | RW | PAU_TRANSPORT_OTL0_NOT_OTH: spare | |
| 3 | RW | RW | PAU_TRANSPORT_OTL1_NOT_OTH: spare | |
| 4:63 | RO | RO | constant=0b000000000000000000000000000000000000000000000000000000000000 | |
| MISC c_err_rpt hold bits | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B34 (SCOM) 0000000013720020 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.MISC_HOLD | |||
| Constant(s): | ||||
| Comments: | c_err_rpt hold latches read-with-clear reg | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:3 | PAU3.MISC.REGS.NDLQ_E.HOLD_LATCH_INST.HOLD.LATC.L2(0:3) [0000] | |||
| 4:7 | PAU3.MISC.REGS.MISCQ_E.HOLD_LATCH_INST.HOLD.LATC.L2(0:3) [0000] | |||
| 8:9 | PAU3.MISC.REGS.OTLQ_E.HOLD_LATCH_INST.HOLD.LATC.L2(0:1) [00] | |||
| 10 | PAU3.MISC.REGS.ATLQ_E.HOLD_LATCH_INST.HOLD.LATC.L2(0) [0] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_NDL0_STALL: Interrupt Request NDL Brick0 Stall | |
| 1 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_NDL0_NOSTALL: Interrupt Request NDL Brick0 No-Stall | |
| 2 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_NDL1_STALL: Interrupt Request NDL Brick1 Stall | |
| 3 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_NDL1_NOSTALL: Interrupt Request NDL Brick1 No-Stall | |
| 4 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MISC_RING_ERRP: PAU Register Ring error (ie noack) | |
| 5 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MISC_IBAR_ERRP: Parity error from interrupt base real address register | |
| 6 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MISC_SCOMDAA_ERRP: Parity error on Indirect SCOM Address register | |
| 7 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_MISC_CNTL_ERRP: Parity error on MISC Control register | |
| 8 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_RX00_FAULT: Interrupt Request OTL Brick2 STACK0 SLICE0 Translation Fault | |
| 9 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_RX01_FAULT: Interrupt Request OTL Brick3 STACK0 SLICE1 Translation Fault | |
| 10 | RWX_WCLRREG | RWX_WCLRREG | IDIAL_RX20_FAULT: Interrupt Request AME | |
| 11:63 | RO | RO | constant=0b00000000000000000000000000000000000000000000000000000 | |
| MISC c_err_rpt mask bits | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B35 (SCOM) 0000000013720028 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.MISC_MASK | |||
| Constant(s): | ||||
| Comments: | c_err_rpt mask latches read-only reg | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:3 | PAU3.MISC.REGS.NDLQ_E_MASK.LATC.L2(0:3) [0000] | |||
| 4:7 | PAU3.MISC.REGS.MISCQ_E_MASK.LATC.L2(0:3) [0000] | |||
| 8:9 | PAU3.MISC.REGS.OTLQ_E_MASK.LATC.L2(0:1) [00] | |||
| 10 | PAU3.MISC.REGS.ATLQ_E_MASK.LATC.L2(0) [0] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:10 | ROX | ROX | IDIAL_MISC_MASK: c_err_rpt mask latches read-only reg | |
| 11:63 | RO | RO | constant=0b00000000000000000000000000000000000000000000000000000 | |
| MISC Configuration | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B36 (SCOM) 0000000013720030 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.MISC_CONFIG | |||
| Constant(s): | ||||
| Comments: | Configures MISC | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.MISC.REGS.MISC_CONFIGQ.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:4 | RW | RW | CONFIG_SYNC_WAIT: Number of clock cycles from sync request to sync valid (masks round-trip staging latency MISC/ATS/CTL). Must be >= ATS config_sync_wait+8 | |
| 5 | RW | RW | PERF_CONFIG_ENABLE: 0b1 Enables performance monitor events | |
| 6 | RW | RW | PERF_CONFIG_PE_MASK: 0b1 Enables the selection of performance monitor events by PE ID | |
| 7:10 | RW | RW | PERF_CONFIG_PE_MATCH: PE ID to select for performance monitor events (when enabled) | |
| 11 | RW | RW | IPI_PS: Inter Processor Interrupt Page Size, 0b0=4kB, 0b1=64kB | |
| 12 | RW | RW | IPI_OS: Inter Processor Interrupt Operating System, 0b0=AIX, 0b1=Linux | |
| 13 | RW | RW | OC_ATS_SYNC_START: Issue start sync to ATS on OCAPI Interrupts, 0b0=disable, 0b1=enable | |
| 14 | RW | RW | CQ_RESP_VALID_ENABLE: CQ to MISC interrupt response interface enabled, 0b0=disable, 0b1=enable | |
| 15 | RW | RW | NV_MODE: Nvlink mode bit, 0b0=disable, 0b1=enable | |
| 16 | RW | RW | OC_MODE: OpenCapi mode bit, 0b0=disable, 0b1=enable | |
| 17 | RW | RW | AME_MODE: AME mode bit, 0b0=disable, 0b1=enable | |
| 18:63 | RW | RW | CONFIG_MISC_RSVD: Reserved | |
| PAU Freeze-on-error Enable for FIR Register 0 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B38 (SCOM) 0000000013720040 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.FREEZE_0_CONFIG | |||
| Constant(s): | ||||
| Comments: | PAU Freeze-on-error Enable 0. 0b1=enable | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.MISC.REGS.FREEZE_0_CONFIGQ.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:63 | RW | RW | CONFIG_FREEZE_0: Enable for FIR Register 0 | |
| PAU Freeze-on-error Enable for FIR Register 1 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B39 (SCOM) 0000000013720048 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.FREEZE_1_CONFIG | |||
| Constant(s): | ||||
| Comments: | PAU Freeze-on-error Enable 0. 0b1=enable | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.MISC.REGS.FREEZE_1_CONFIGQ.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:63 | RW | RW | CONFIG_FREEZE_1: Enable for FIR Register 1 | |
| PAU Fence-on-error Enable for FIR Register 0 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B3A (SCOM) 0000000013720050 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.FENCE_0_CONFIG | |||
| Constant(s): | ||||
| Comments: | PAU Fence-on-error Enable. 0b1=enable | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.MISC.REGS.FENCE_0_CONFIGQ.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:63 | RW | RW | CONFIG_FENCE_0: Enable for FIR Register 0 | |
| PAU Fence-on-error Enable for FIR Register 1 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B3B (SCOM) 0000000013720058 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.FENCE_1_CONFIG | |||
| Constant(s): | ||||
| Comments: | PAU Fence-on-error Enable. 0b1=enable | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.MISC.REGS.FENCE_1_CONFIGQ.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:63 | RW | RW | CONFIG_FENCE_1: Enable for FIR Register 1 | |
| PAU Interrupt-on-error Enable for FIR Register 0 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B3C (SCOM) 0000000013720060 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.INT_0_CONFIG | |||
| Constant(s): | ||||
| Comments: | PAU Interrupt-on-error Enable. 0b1=enable | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.MISC.REGS.INT_0_CONFIGQ.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:63 | RW | RW | CONFIG_INT_0: Enable for FIR Register 0 | |
| PAU Interrupt-on-error Enable for FIR Register 1 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B3D (SCOM) 0000000013720068 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.INT_1_CONFIG | |||
| Constant(s): | ||||
| Comments: | PAU Interrupt-on-error Enable. 0b1=enable | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.MISC.REGS.INT_1_CONFIGQ.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:63 | RW | RW | CONFIG_INT_1: Enable for FIR Register 1 | |
| PAU Indirect SCOM Address | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B3E (SCOM) 0000000013720070 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.DA_ADDR | |||
| Constant(s): | ||||
| Comments: | PAU Indirect SCOM Address register For usage, see PAU Indirect SCOM Data register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.MISC.REGS.DA_ADDRQ.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:23 | RW | RW | MISC_DA_ADDR: Indirect SCOM Address | |
| 24:25 | RW | RW | MISC_DA_LEN: Indirect SCOM Length. 0b00=1B, 0b01=2B, 0b10=4B, 0b11=8B | |
| 26:63 | RW | RW | MISC_DA_RSVD: Reserved | |
| PAU Indirect SCOM Data | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B3F (SCOM) | |||
| Name: | PAU3.MISC.REGS.DA_DATA | |||
| Constant(s): | ||||
| Comments: | PAU Indirect SCOM Data register. A SCOM read/write of this register performs an Indirect SCOM PAU Ring read/write of register at address stored in the PAU Indirect SCOM Address register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| Bit(s) | SCOM | Dial: Description | ||
| 0:63 | RO | constant=0b0000000000000000000000000000000000000000000000000000000000000000 | ||
| PAU Version Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B40 (SCOM) 0000000013720080 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.PAU_VERSION | |||
| Constant(s): | ||||
| Comments: | PAU Version Register Scan-only latches with default init value x000000A350000001 | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.MISC.REGS.NPU_VERSIONQ.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:23 | RO | RO | PAU_VERSION_RSVD0: Reserved | |
| 24:31 | RO | RO | PAU_VERSION_MAJOR: Major Revision ID. Indicates that the PAU implements version 3 of the NVLink specification | |
| 32:35 | RO | RO | PAU_VERSION_P10: Indicates P10 version of PAU | |
| 36:47 | RO | RO | PAU_VERSION_RSVD1: Reserved | |
| 48:63 | RO | RO | PAU_VERSION_MINOR: EC version of the PAU | |
| PAU Scope for CQ CTL/SM Errors | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B41 (SCOM) 0000000013720088 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.ERR_SCOPE_CTL_CONFIG | |||
| Constant(s): | ||||
| Comments: | PAU Scope for CQ CTL/SM Errors. See FIR register for error details | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:15 | PAU3.MISC.REGS.ERR_SCOPE_CTL_CONFIGQ.LATC.L2(0:15) [0000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:15 | RW | RW | CONFIG_ERR_SCOPE_CTL: 0b0=brick(s) scope; 0b1=PAU scope | |
| 16:63 | RO | RO | constant=0b000000000000000000000000000000000000000000000000 | |
| PAU Ring ACK Error from MISC Master (SCOM) | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B42 (SCOM) 0000000013720090 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.ERR_INFO_PAU_RING_ADDR | |||
| Constant(s): | ||||
| Comments: | PAU Ring ACK error information from MISC Master (SCOM Direct or Indirect) | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:27 | PAU3.MISC.REGS.ERR_INFO_NPU_RING_ADDRQ.LATC.L2(0:27) [0000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:23 | RWX | RWX | MISC_PAU_RING_ERR_ADDR: PAU Ring Address | |
| 24:25 | RWX | RWX | MISC_PAU_RING_ERR_LENR: PAU Ring Length | |
| 26 | RWX | RWX | MISC_PAU_RING_ERR_RNW: PAU Ring Read/Not-Write | |
| 27 | RWX | RWX | MISC_PAU_RING_ERR_DA_OP: PAU Ring Indirect SCOM | |
| 28:63 | RO | RO | constant=0b000000000000000000000000000000000000 | |
| PAU Interrupt Base Address Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B43 (SCOM) 0000000013720098 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.INT_BAR | |||
| Constant(s): | ||||
| Comments: | PAU Interrupt Base Address Register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:39 | PAU3.MISC.REGS.INT_BARQ.LATC.L2(0:39) [0000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:39 | RW | RW | CONFIG_INT_BAR: Powerbus address(12 to 51) Bits used depend on configuration 4kB AIX (13 to 44) 4kB Linux (13 to 45) 64kB AIX (13 to 40) 64kB Linux (13 to 41) (46 to 51) never used | |
| 40:63 | RO | RO | constant=0b000000000000000000000000 | |
| PAU Error Brick Group Register 0 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B44 (SCOM) 00000000137200A0 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.ERROR_BRICK_GROUP_CONFIG | |||
| Constant(s): | ||||
| Comments: | PAU Error Brick Group for Freeze & Fence | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:59 | PAU3.MISC.REGS.ERROR_BRICK_GROUP_CONFIGQ.LATC.L2(0:59) [000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:11 | RW | RW | CONFIG_ERR_GROUP_BRK0: Error brick group for brick 0 | |
| 12:23 | RW | RW | CONFIG_ERR_GROUP_BRK1: Error brick group for brick 1 | |
| 24:35 | RW | RW | CONFIG_ERR_GROUP_BRK2: Error brick group for brick 2 | |
| 36:47 | RW | RW | CONFIG_ERR_GROUP_BRK3: Error brick group for brick 3 | |
| 48:59 | RW | RW | CONFIG_ERR_GROUP_BRK4: Error brick group for brick 4 | |
| 60:63 | RO | RO | constant=0b0000 | |
| PAU Freeze State | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B45 (SCOM) 00000000137200A8 (PAU_RING) | |||
| Name: | PAU3.MISC.FREEZE_STATE | |||
| Constant(s): | ||||
| Comments: | PAU freeze state per BDF-to-PE map Read returns freeze state Write data bit 0 to 0b1 to clear freeze bit 0. Write data bit 18 to 0b1 to set freeze bit 0. Write data bit 1 to 0b1 to clear freeze bit 1. Write data bit 19 to 0b1 to set freeze bit 1. Write data bit 2 to 0b1 to clear freeze bit 2. Write data bit 20 to 0b1 to set freeze bit 2. Write data bit 3 to 0b1 to clear freeze bit 3. Write data bit 21 to 0b1 to set freeze bit 3. Write data bit 4 to 0b1 to clear freeze bit 4. Write data bit 22 to 0b1 to set freeze bit 4. Write data bit 5 to 0b1 to clear freeze bit 5. Write data bit 23 to 0b1 to set freeze bit 5. Write data bit 6 to 0b1 to clear freeze bit 6. Write data bit 24 to 0b1 to set freeze bit 6. Write data bit 7 to 0b1 to clear freeze bit 7. Write data bit 25 to 0b1 to set freeze bit 7. Write data bit 8 to 0b1 to clear freeze bit 8. Write data bit 26 to 0b1 to set freeze bit 8. Write data bit 9 to 0b1 to clear freeze bit 9. Write data bit 27 to 0b1 to set freeze bit 9. Write data bit 10 to 0b1 to clear freeze bit 10. Write data bit 28 to 0b1 to set freeze bit 10. Write data bit 11 to 0b1 to clear freeze bit 11. Write data bit 29 to 0b1 to set freeze bit 11. Write data bit 12 to 0b1 to clear freeze bit 12. Write data bit 30 to 0b1 to set freeze bit 12. Write data bit 13 to 0b1 to clear freeze bit 13. Write data bit 31 to 0b1 to set freeze bit 13. Write data bit 14 to 0b1 to clear freeze bit 14. Write data bit 32 to 0b1 to set freeze bit 14. Write data bit 15 to 0b1 to clear freeze bit 15. Write data bit 33 to 0b1 to set freeze bit 15. May also be set by hardware error Bits are reset dominant if both the set and clear bits are active when the register is written. | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0 | PAU3.MISC.REGS.FREEZE_BDF2PE_0Q.LATC.L2(0) [0] | |||
| 1 | PAU3.MISC.REGS.FREEZE_BDF2PE_1Q.LATC.L2(0) [0] | |||
| 2 | PAU3.MISC.REGS.FREEZE_BDF2PE_2Q.LATC.L2(0) [0] | |||
| 3 | PAU3.MISC.REGS.FREEZE_BDF2PE_3Q.LATC.L2(0) [0] | |||
| 4 | PAU3.MISC.REGS.FREEZE_BDF2PE_4Q.LATC.L2(0) [0] | |||
| 5 | PAU3.MISC.REGS.FREEZE_BDF2PE_5Q.LATC.L2(0) [0] | |||
| 6 | PAU3.MISC.REGS.FREEZE_BDF2PE_6Q.LATC.L2(0) [0] | |||
| 7 | PAU3.MISC.REGS.FREEZE_BDF2PE_7Q.LATC.L2(0) [0] | |||
| 8 | PAU3.MISC.REGS.FREEZE_BDF2PE_8Q.LATC.L2(0) [0] | |||
| 9 | PAU3.MISC.REGS.FREEZE_BDF2PE_9Q.LATC.L2(0) [0] | |||
| 10 | PAU3.MISC.REGS.FREEZE_BDF2PE_10Q.LATC.L2(0) [0] | |||
| 11 | PAU3.MISC.REGS.FREEZE_BDF2PE_11Q.LATC.L2(0) [0] | |||
| 12 | PAU3.MISC.REGS.FREEZE_BDF2PE_12Q.LATC.L2(0) [0] | |||
| 13 | PAU3.MISC.REGS.FREEZE_BDF2PE_13Q.LATC.L2(0) [0] | |||
| 14 | PAU3.MISC.REGS.FREEZE_BDF2PE_14Q.LATC.L2(0) [0] | |||
| 15 | PAU3.MISC.REGS.FREEZE_BDF2PE_15Q.LATC.L2(0) [0] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX_WCLEAR | RWX_WCLEAR | FREEZE_BDF2PE_0: entry 0 | |
| 1 | RWX_WCLEAR | RWX_WCLEAR | FREEZE_BDF2PE_1: entry 1 | |
| 2 | RWX_WCLEAR | RWX_WCLEAR | FREEZE_BDF2PE_2: entry 2 | |
| 3 | RWX_WCLEAR | RWX_WCLEAR | FREEZE_BDF2PE_3: entry 3 | |
| 4 | RWX_WCLEAR | RWX_WCLEAR | FREEZE_BDF2PE_4: entry 4 | |
| 5 | RWX_WCLEAR | RWX_WCLEAR | FREEZE_BDF2PE_5: entry 5 | |
| 6 | RWX_WCLEAR | RWX_WCLEAR | FREEZE_BDF2PE_6: entry 6 | |
| 7 | RWX_WCLEAR | RWX_WCLEAR | FREEZE_BDF2PE_7: entry 7 | |
| 8 | RWX_WCLEAR | RWX_WCLEAR | FREEZE_BDF2PE_8: entry 8 | |
| 9 | RWX_WCLEAR | RWX_WCLEAR | FREEZE_BDF2PE_9: entry 9 | |
| 10 | RWX_WCLEAR | RWX_WCLEAR | FREEZE_BDF2PE_10: entry 10 | |
| 11 | RWX_WCLEAR | RWX_WCLEAR | FREEZE_BDF2PE_11: entry 11 | |
| 12 | RWX_WCLEAR | RWX_WCLEAR | FREEZE_BDF2PE_12: entry 12 | |
| 13 | RWX_WCLEAR | RWX_WCLEAR | FREEZE_BDF2PE_13: entry 13 | |
| 14 | RWX_WCLEAR | RWX_WCLEAR | FREEZE_BDF2PE_14: entry 14 | |
| 15 | RWX_WCLEAR | RWX_WCLEAR | FREEZE_BDF2PE_15: entry 15 | |
| 16:63 | RO | RO | constant=0b000000000000000000000000000000000000000000000000 | |
| PAU Fence State | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B46 (SCOM) 00000000137200B0 (PAU_RING) | |||
| Name: | PAU3.MISC.FENCE_STATE | |||
| Constant(s): | ||||
| Comments: | PAU fence state per brick Read returns fence state Write data bit 0 to 0b1 to clear fence bit 0. Write data bit 12 to 0b1 to set fence bit 0. Write data bit 1 to 0b1 to clear fence bit 1. Write data bit 13 to 0b1 to set fence bit 1. Write data bit 2 to 0b1 to clear fence bit 2. Write data bit 14 to 0b1 to set fence bit 2. Write data bit 3 to 0b1 to clear fence bit 3. Write data bit 15 to 0b1 to set fence bit 3. Write data bit 4 to 0b1 to clear fence bit 4. Write data bit 16 to 0b1 to set fence bit 4. May also be set by hardware error Bits are reset dominant if both the set and clear bits are active when the register is written. | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0 | PAU3.MISC.REGS.FENCE_BRK0Q.LATC.L2(0) [0] | |||
| 1 | PAU3.MISC.REGS.FENCE_BRK1Q.LATC.L2(0) [0] | |||
| 2 | PAU3.MISC.REGS.FENCE_BRK2Q.LATC.L2(0) [0] | |||
| 3 | PAU3.MISC.REGS.FENCE_BRK3Q.LATC.L2(0) [0] | |||
| 4 | PAU3.MISC.REGS.FENCE_BRK4Q.LATC.L2(0) [0] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX_WCLEAR | RWX_WCLEAR | FENCE_BRK0: brick 0 | |
| 1 | RWX_WCLEAR | RWX_WCLEAR | FENCE_BRK1: brick 1 | |
| 2 | ROX | ROX | FENCE_BRK2: brick 2 | |
| 3 | ROX | ROX | FENCE_BRK3: brick 3 | |
| 4 | RWX_WCLEAR | RWX_WCLEAR | FENCE_BRK4: brick 4 | |
| 5:56 | RO | RO | constant=0b0000000000000000000000000000000000000000000000000000 | |
| PAU Interrupt Request | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B47 (SCOM) 00000000137200B8 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.INT_REQ | |||
| Constant(s): | ||||
| Comments: | PAU interrupt request per source Read returns interrupt request Write 1 to set interrupt request. Write 0 to all bits to clear all interrupt requests | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:3 | PAU3.MISC.REGS.INT_REQQ.LATC.L2(0:3) [0000] | |||
| 12:13 | PAU3.MISC.REGS.INT_REQQ.LATC.L2(12:13) [00] | |||
| 18:21 | PAU3.MISC.REGS.INT_REQQ.LATC.L2(18:21) [0000] | |||
| 23:24 | PAU3.MISC.REGS.INT_REQQ.LATC.L2(23:24) [00] | |||
| 35:40 | PAU3.MISC.REGS.INT_REQQ.LATC.L2(35:40) [000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX_WOR | RWX_WOR | INTERRUPT_00: NDL stall, brick 0 | |
| 1 | RWX_WOR | RWX_WOR | INTERRUPT_01: NDL nostall, brick 0 | |
| 2 | RWX_WOR | RWX_WOR | INTERRUPT_02: NDL stall, brick 1 | |
| 3 | RWX_WOR | RWX_WOR | INTERRUPT_03: NDL nostall, brick 1 | |
| 4:11 | RO | RO | constant=0b00000000 | |
| 12 | RWX_WOR | RWX_WOR | INTERRUPT_12: NTL brick 0 | |
| 13 | RWX_WOR | RWX_WOR | INTERRUPT_13: NTL brick 1 | |
| 14:17 | RO | RO | constant=0b0000 | |
| 18 | RWX_WOR | RWX_WOR | INTERRUPT_18: TCE translation | |
| 19 | RWX_WOR | RWX_WOR | INTERRUPT_19: ATS translation | |
| 20 | RWX_WOR | RWX_WOR | INTERRUPT_20: CTL or DAT | |
| 21 | RWX_WOR | RWX_WOR | INTERRUPT_21: MISC | |
| 22 | RO | RO | constant=0b0 | |
| 23 | RWX_WOR | RWX_WOR | INTERRUPT_23: AME brick interrupt | |
| 24 | RWX_WOR | RWX_WOR | INTERRUPT_24: AME Translation Fault | |
| 25:34 | RO | RO | constant=0b0000000000 | |
| 35 | RWX_WOR | RWX_WOR | INTERRUPT_35: OTL Translation Fault, brick 0 | |
| 36 | RWX_WOR | RWX_WOR | INTERRUPT_36: OTL Translation Fault, brick 1 | |
| 37 | RWX_WOR | RWX_WOR | INTERRUPT_37: OTL brick 0 | |
| 38 | RWX_WOR | RWX_WOR | INTERRUPT_38: OTL brick 1 | |
| 39 | RWX_WOR | RWX_WOR | INTERRUPT_39: XSL brick 0 | |
| 40 | RWX_WOR | RWX_WOR | INTERRUPT_40: XSL brick 1 | |
| 41:63 | RO | RO | constant=0b00000000000000000000000 | |
| BDF-to-PE map 0 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B50 (SCOM) 0000000013720100 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.BDF2PE_0_CONFIG | |||
| Constant(s): | ||||
| Comments: | Configured BDF-to-PE mapping #0 Note: Across all 6 bricks of a PAU, each BDF may map to at most 1 PE | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:23 | PAU3.MISC.REGS.BDF2PE_0_CONFIGQ.LATC.L2(0:23) [000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_BDF2PE_0_ENABLE: 0/1 = This BDF-to-PE mapping is disabled/enabled | |
| 1:3 | RW | RW | CONFIG_BDF2PE_0_RESERVED: Reserved | |
| 4:7 | RW | RW | CONFIG_BDF2PE_0_PE: PE (Partitionable Endpoint) associated with this BDF | |
| 8:23 | RW | RW | CONFIG_BDF2PE_0_BDF: BDF (Bus-Device-Function) mapped to this PE | |
| 24:63 | RO | RO | constant=0b0000000000000000000000000000000000000000 | |
| BDF-to-PE map 1 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B51 (SCOM) 0000000013720108 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.BDF2PE_1_CONFIG | |||
| Constant(s): | ||||
| Comments: | Configured BDF-to-PE mapping #1 Note: Across all 6 bricks of a PAU, each BDF may map to at most 1 PE | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:23 | PAU3.MISC.REGS.BDF2PE_1_CONFIGQ.LATC.L2(0:23) [000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_BDF2PE_1_ENABLE: 0/1 = This BDF-to-PE mapping is disabled/enabled | |
| 1:3 | RW | RW | CONFIG_BDF2PE_1_RESERVED: Reserved | |
| 4:7 | RW | RW | CONFIG_BDF2PE_1_PE: PE (Partitionable Endpoint) associated with this BDF | |
| 8:23 | RW | RW | CONFIG_BDF2PE_1_BDF: BDF (Bus-Device-Function) mapped to this PE | |
| 24:63 | RO | RO | constant=0b0000000000000000000000000000000000000000 | |
| BDF-to-PE map 2 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B52 (SCOM) 0000000013720110 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.BDF2PE_2_CONFIG | |||
| Constant(s): | ||||
| Comments: | Configured BDF-to-PE mapping #2 Note: Across all 6 bricks of a PAU, each BDF may map to at most 1 PE | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:23 | PAU3.MISC.REGS.BDF2PE_2_CONFIGQ.LATC.L2(0:23) [000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_BDF2PE_2_ENABLE: 0/1 = This BDF-to-PE mapping is disabled/enabled | |
| 1:3 | RW | RW | CONFIG_BDF2PE_2_RESERVED: Reserved | |
| 4:7 | RW | RW | CONFIG_BDF2PE_2_PE: PE (Partitionable Endpoint) associated with this BDF | |
| 8:23 | RW | RW | CONFIG_BDF2PE_2_BDF: BDF (Bus-Device-Function) mapped to this PE | |
| 24:63 | RO | RO | constant=0b0000000000000000000000000000000000000000 | |
| BDF-to-PE map 3 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B53 (SCOM) 0000000013720118 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.BDF2PE_3_CONFIG | |||
| Constant(s): | ||||
| Comments: | Configured BDF-to-PE mapping #3 Note: Across all 6 bricks of a PAU, each BDF may map to at most 1 PE | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:23 | PAU3.MISC.REGS.BDF2PE_3_CONFIGQ.LATC.L2(0:23) [000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_BDF2PE_3_ENABLE: 0/1 = This BDF-to-PE mapping is disabled/enabled | |
| 1:3 | RW | RW | CONFIG_BDF2PE_3_RESERVED: Reserved | |
| 4:7 | RW | RW | CONFIG_BDF2PE_3_PE: PE (Partitionable Endpoint) associated with this BDF | |
| 8:23 | RW | RW | CONFIG_BDF2PE_3_BDF: BDF (Bus-Device-Function) mapped to this PE | |
| 24:63 | RO | RO | constant=0b0000000000000000000000000000000000000000 | |
| BDF-to-PE map 4 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B54 (SCOM) 0000000013720120 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.BDF2PE_4_CONFIG | |||
| Constant(s): | ||||
| Comments: | Configured BDF-to-PE mapping #4 Note: Across all 6 bricks of a PAU, each BDF may map to at most 1 PE | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:23 | PAU3.MISC.REGS.BDF2PE_4_CONFIGQ.LATC.L2(0:23) [000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_BDF2PE_4_ENABLE: 0/1 = This BDF-to-PE mapping is disabled/enabled | |
| 1:3 | RW | RW | CONFIG_BDF2PE_4_RESERVED: Reserved | |
| 4:7 | RW | RW | CONFIG_BDF2PE_4_PE: PE (Partitionable Endpoint) associated with this BDF | |
| 8:23 | RW | RW | CONFIG_BDF2PE_4_BDF: BDF (Bus-Device-Function) mapped to this PE | |
| 24:63 | RO | RO | constant=0b0000000000000000000000000000000000000000 | |
| BDF-to-PE map 5 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B55 (SCOM) 0000000013720128 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.BDF2PE_5_CONFIG | |||
| Constant(s): | ||||
| Comments: | Configured BDF-to-PE mapping #5 Note: Across all 6 bricks of a PAU, each BDF may map to at most 1 PE | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:23 | PAU3.MISC.REGS.BDF2PE_5_CONFIGQ.LATC.L2(0:23) [000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_BDF2PE_5_ENABLE: 0/1 = This BDF-to-PE mapping is disabled/enabled | |
| 1:3 | RW | RW | CONFIG_BDF2PE_5_RESERVED: Reserved | |
| 4:7 | RW | RW | CONFIG_BDF2PE_5_PE: PE (Partitionable Endpoint) associated with this BDF | |
| 8:23 | RW | RW | CONFIG_BDF2PE_5_BDF: BDF (Bus-Device-Function) mapped to this PE | |
| 24:63 | RO | RO | constant=0b0000000000000000000000000000000000000000 | |
| BDF-to-PE map 6 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B56 (SCOM) 0000000013720130 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.BDF2PE_6_CONFIG | |||
| Constant(s): | ||||
| Comments: | Configured BDF-to-PE mapping #6 Note: Across all 6 bricks of a PAU, each BDF may map to at most 1 PE | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:23 | PAU3.MISC.REGS.BDF2PE_6_CONFIGQ.LATC.L2(0:23) [000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_BDF2PE_6_ENABLE: 0/1 = This BDF-to-PE mapping is disabled/enabled | |
| 1:3 | RW | RW | CONFIG_BDF2PE_6_RESERVED: Reserved | |
| 4:7 | RW | RW | CONFIG_BDF2PE_6_PE: PE (Partitionable Endpoint) associated with this BDF | |
| 8:23 | RW | RW | CONFIG_BDF2PE_6_BDF: BDF (Bus-Device-Function) mapped to this PE | |
| 24:63 | RO | RO | constant=0b0000000000000000000000000000000000000000 | |
| BDF-to-PE map 7 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B57 (SCOM) 0000000013720138 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.BDF2PE_7_CONFIG | |||
| Constant(s): | ||||
| Comments: | Configured BDF-to-PE mapping #7 Note: Across all 6 bricks of a PAU, each BDF may map to at most 1 PE | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:23 | PAU3.MISC.REGS.BDF2PE_7_CONFIGQ.LATC.L2(0:23) [000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_BDF2PE_7_ENABLE: 0/1 = This BDF-to-PE mapping is disabled/enabled | |
| 1:3 | RW | RW | CONFIG_BDF2PE_7_RESERVED: Reserved | |
| 4:7 | RW | RW | CONFIG_BDF2PE_7_PE: PE (Partitionable Endpoint) associated with this BDF | |
| 8:23 | RW | RW | CONFIG_BDF2PE_7_BDF: BDF (Bus-Device-Function) mapped to this PE | |
| 24:63 | RO | RO | constant=0b0000000000000000000000000000000000000000 | |
| BDF-to-PE map 8 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B58 (SCOM) 0000000013720140 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.BDF2PE_8_CONFIG | |||
| Constant(s): | ||||
| Comments: | Configured BDF-to-PE mapping #8 Note: Across all 6 bricks of a PAU, each BDF may map to at most 1 PE | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:23 | PAU3.MISC.REGS.BDF2PE_8_CONFIGQ.LATC.L2(0:23) [000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_BDF2PE_8_ENABLE: 0/1 = This BDF-to-PE mapping is disabled/enabled | |
| 1:3 | RW | RW | CONFIG_BDF2PE_8_RESERVED: Reserved | |
| 4:7 | RW | RW | CONFIG_BDF2PE_8_PE: PE (Partitionable Endpoint) associated with this BDF | |
| 8:23 | RW | RW | CONFIG_BDF2PE_8_BDF: BDF (Bus-Device-Function) mapped to this PE | |
| 24:63 | RO | RO | constant=0b0000000000000000000000000000000000000000 | |
| BDF-to-PE map 9 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B59 (SCOM) 0000000013720148 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.BDF2PE_9_CONFIG | |||
| Constant(s): | ||||
| Comments: | Configured BDF-to-PE mapping #9 Note: Across all 6 bricks of a PAU, each BDF may map to at most 1 PE | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:23 | PAU3.MISC.REGS.BDF2PE_9_CONFIGQ.LATC.L2(0:23) [000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_BDF2PE_9_ENABLE: 0/1 = This BDF-to-PE mapping is disabled/enabled | |
| 1:3 | RW | RW | CONFIG_BDF2PE_9_RESERVED: Reserved | |
| 4:7 | RW | RW | CONFIG_BDF2PE_9_PE: PE (Partitionable Endpoint) associated with this BDF | |
| 8:23 | RW | RW | CONFIG_BDF2PE_9_BDF: BDF (Bus-Device-Function) mapped to this PE | |
| 24:63 | RO | RO | constant=0b0000000000000000000000000000000000000000 | |
| BDF-to-PE map 10 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B5A (SCOM) 0000000013720150 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.BDF2PE_10_CONFIG | |||
| Constant(s): | ||||
| Comments: | Configured BDF-to-PE mapping #10 Note: Across all 6 bricks of a PAU, each BDF may map to at most 1 PE | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:23 | PAU3.MISC.REGS.BDF2PE_10_CONFIGQ.LATC.L2(0:23) [000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_BDF2PE_10_ENABLE: 0/1 = This BDF-to-PE mapping is disabled/enabled | |
| 1:3 | RW | RW | CONFIG_BDF2PE_10_RESERVED: Reserved | |
| 4:7 | RW | RW | CONFIG_BDF2PE_10_PE: PE (Partitionable Endpoint) associated with this BDF | |
| 8:23 | RW | RW | CONFIG_BDF2PE_10_BDF: BDF (Bus-Device-Function) mapped to this PE | |
| 24:63 | RO | RO | constant=0b0000000000000000000000000000000000000000 | |
| BDF-to-PE map 11 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B5B (SCOM) 0000000013720158 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.BDF2PE_11_CONFIG | |||
| Constant(s): | ||||
| Comments: | Configured BDF-to-PE mapping #11 Note: Across all 6 bricks of a PAU, each BDF may map to at most 1 PE | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:23 | PAU3.MISC.REGS.BDF2PE_11_CONFIGQ.LATC.L2(0:23) [000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_BDF2PE_11_ENABLE: 0/1 = This BDF-to-PE mapping is disabled/enabled | |
| 1:3 | RW | RW | CONFIG_BDF2PE_11_RESERVED: Reserved | |
| 4:7 | RW | RW | CONFIG_BDF2PE_11_PE: PE (Partitionable Endpoint) associated with this BDF | |
| 8:23 | RW | RW | CONFIG_BDF2PE_11_BDF: BDF (Bus-Device-Function) mapped to this PE | |
| 24:63 | RO | RO | constant=0b0000000000000000000000000000000000000000 | |
| BDF-to-PE map 12 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B5C (SCOM) 0000000013720160 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.BDF2PE_12_CONFIG | |||
| Constant(s): | ||||
| Comments: | Configured BDF-to-PE mapping #12 Note: Across all 6 bricks of a PAU, each BDF may map to at most 1 PE | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:23 | PAU3.MISC.REGS.BDF2PE_12_CONFIGQ.LATC.L2(0:23) [000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_BDF2PE_12_ENABLE: 0/1 = This BDF-to-PE mapping is disabled/enabled | |
| 1:3 | RW | RW | CONFIG_BDF2PE_12_RESERVED: Reserved | |
| 4:7 | RW | RW | CONFIG_BDF2PE_12_PE: PE (Partitionable Endpoint) associated with this BDF | |
| 8:23 | RW | RW | CONFIG_BDF2PE_12_BDF: BDF (Bus-Device-Function) mapped to this PE | |
| 24:63 | RO | RO | constant=0b0000000000000000000000000000000000000000 | |
| BDF-to-PE map 13 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B5D (SCOM) 0000000013720168 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.BDF2PE_13_CONFIG | |||
| Constant(s): | ||||
| Comments: | Configured BDF-to-PE mapping #13 Note: Across all 6 bricks of a PAU, each BDF may map to at most 1 PE | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:23 | PAU3.MISC.REGS.BDF2PE_13_CONFIGQ.LATC.L2(0:23) [000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_BDF2PE_13_ENABLE: 0/1 = This BDF-to-PE mapping is disabled/enabled | |
| 1:3 | RW | RW | CONFIG_BDF2PE_13_RESERVED: Reserved | |
| 4:7 | RW | RW | CONFIG_BDF2PE_13_PE: PE (Partitionable Endpoint) associated with this BDF | |
| 8:23 | RW | RW | CONFIG_BDF2PE_13_BDF: BDF (Bus-Device-Function) mapped to this PE | |
| 24:63 | RO | RO | constant=0b0000000000000000000000000000000000000000 | |
| BDF-to-PE map 14 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B5E (SCOM) 0000000013720170 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.BDF2PE_14_CONFIG | |||
| Constant(s): | ||||
| Comments: | Configured BDF-to-PE mapping #14 Note: Across all 6 bricks of a PAU, each BDF may map to at most 1 PE | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:23 | PAU3.MISC.REGS.BDF2PE_14_CONFIGQ.LATC.L2(0:23) [000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_BDF2PE_14_ENABLE: 0/1 = This BDF-to-PE mapping is disabled/enabled | |
| 1:3 | RW | RW | CONFIG_BDF2PE_14_RESERVED: Reserved | |
| 4:7 | RW | RW | CONFIG_BDF2PE_14_PE: PE (Partitionable Endpoint) associated with this BDF | |
| 8:23 | RW | RW | CONFIG_BDF2PE_14_BDF: BDF (Bus-Device-Function) mapped to this PE | |
| 24:63 | RO | RO | constant=0b0000000000000000000000000000000000000000 | |
| BDF-to-PE map 15 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B5F (SCOM) 0000000013720178 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.BDF2PE_15_CONFIG | |||
| Constant(s): | ||||
| Comments: | Configured BDF-to-PE mapping #15 Note: Across all 6 bricks of a PAU, each BDF may map to at most 1 PE | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:23 | PAU3.MISC.REGS.BDF2PE_15_CONFIGQ.LATC.L2(0:23) [000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RW | RW | CONFIG_BDF2PE_15_ENABLE: 0/1 = This BDF-to-PE mapping is disabled/enabled | |
| 1:3 | RW | RW | CONFIG_BDF2PE_15_RESERVED: Reserved | |
| 4:7 | RW | RW | CONFIG_BDF2PE_15_PE: PE (Partitionable Endpoint) associated with this BDF | |
| 8:23 | RW | RW | CONFIG_BDF2PE_15_BDF: BDF (Bus-Device-Function) mapped to this PE | |
| 24:63 | RO | RO | constant=0b0000000000000000000000000000000000000000 | |
| PESTB Data for PE 0 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B70 (SCOM) 0000000013720200 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.PESTB_DATA_PE0 | |||
| Constant(s): | ||||
| Comments: | Records which PEs are running/frozen | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0 | PAU3.MISC.REGS.PESTB_DATA_PE0Q.LATC.L2(0) [0] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX | RWX | DMA_STOPPED_STATE_PE0: 0/1 = This PE is running/frozen | |
| 1:63 | RO | RO | constant=0b000000000000000000000000000000000000000000000000000000000000000 | |
| PESTB Data for PE 1 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B71 (SCOM) 0000000013720208 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.PESTB_DATA_PE1 | |||
| Constant(s): | ||||
| Comments: | Records which PEs are running/frozen | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0 | PAU3.MISC.REGS.PESTB_DATA_PE1Q.LATC.L2(0) [0] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX | RWX | DMA_STOPPED_STATE_PE1: 0/1 = This PE is running/frozen | |
| 1:63 | RO | RO | constant=0b000000000000000000000000000000000000000000000000000000000000000 | |
| PESTB Data for PE 2 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B72 (SCOM) 0000000013720210 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.PESTB_DATA_PE2 | |||
| Constant(s): | ||||
| Comments: | Records which PEs are running/frozen | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0 | PAU3.MISC.REGS.PESTB_DATA_PE2Q.LATC.L2(0) [0] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX | RWX | DMA_STOPPED_STATE_PE2: 0/1 = This PE is running/frozen | |
| 1:63 | RO | RO | constant=0b000000000000000000000000000000000000000000000000000000000000000 | |
| PESTB Data for PE 3 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B73 (SCOM) 0000000013720218 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.PESTB_DATA_PE3 | |||
| Constant(s): | ||||
| Comments: | Records which PEs are running/frozen | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0 | PAU3.MISC.REGS.PESTB_DATA_PE3Q.LATC.L2(0) [0] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX | RWX | DMA_STOPPED_STATE_PE3: 0/1 = This PE is running/frozen | |
| 1:63 | RO | RO | constant=0b000000000000000000000000000000000000000000000000000000000000000 | |
| PESTB Data for PE 4 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B74 (SCOM) 0000000013720220 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.PESTB_DATA_PE4 | |||
| Constant(s): | ||||
| Comments: | Records which PEs are running/frozen | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0 | PAU3.MISC.REGS.PESTB_DATA_PE4Q.LATC.L2(0) [0] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX | RWX | DMA_STOPPED_STATE_PE4: 0/1 = This PE is running/frozen | |
| 1:63 | RO | RO | constant=0b000000000000000000000000000000000000000000000000000000000000000 | |
| PESTB Data for PE 5 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B75 (SCOM) 0000000013720228 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.PESTB_DATA_PE5 | |||
| Constant(s): | ||||
| Comments: | Records which PEs are running/frozen | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0 | PAU3.MISC.REGS.PESTB_DATA_PE5Q.LATC.L2(0) [0] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX | RWX | DMA_STOPPED_STATE_PE5: 0/1 = This PE is running/frozen | |
| 1:63 | RO | RO | constant=0b000000000000000000000000000000000000000000000000000000000000000 | |
| PESTB Data for PE 6 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B76 (SCOM) 0000000013720230 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.PESTB_DATA_PE6 | |||
| Constant(s): | ||||
| Comments: | Records which PEs are running/frozen | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0 | PAU3.MISC.REGS.PESTB_DATA_PE6Q.LATC.L2(0) [0] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX | RWX | DMA_STOPPED_STATE_PE6: 0/1 = This PE is running/frozen | |
| 1:63 | RO | RO | constant=0b000000000000000000000000000000000000000000000000000000000000000 | |
| PESTB Data for PE 7 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B77 (SCOM) 0000000013720238 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.PESTB_DATA_PE7 | |||
| Constant(s): | ||||
| Comments: | Records which PEs are running/frozen | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0 | PAU3.MISC.REGS.PESTB_DATA_PE7Q.LATC.L2(0) [0] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX | RWX | DMA_STOPPED_STATE_PE7: 0/1 = This PE is running/frozen | |
| 1:63 | RO | RO | constant=0b000000000000000000000000000000000000000000000000000000000000000 | |
| PESTB Data for PE 8 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B78 (SCOM) 0000000013720240 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.PESTB_DATA_PE8 | |||
| Constant(s): | ||||
| Comments: | Records which PEs are running/frozen | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0 | PAU3.MISC.REGS.PESTB_DATA_PE8Q.LATC.L2(0) [0] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX | RWX | DMA_STOPPED_STATE_PE8: 0/1 = This PE is running/frozen | |
| 1:63 | RO | RO | constant=0b000000000000000000000000000000000000000000000000000000000000000 | |
| PESTB Data for PE 9 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B79 (SCOM) 0000000013720248 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.PESTB_DATA_PE9 | |||
| Constant(s): | ||||
| Comments: | Records which PEs are running/frozen | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0 | PAU3.MISC.REGS.PESTB_DATA_PE9Q.LATC.L2(0) [0] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX | RWX | DMA_STOPPED_STATE_PE9: 0/1 = This PE is running/frozen | |
| 1:63 | RO | RO | constant=0b000000000000000000000000000000000000000000000000000000000000000 | |
| PESTB Data for PE 10 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B7A (SCOM) 0000000013720250 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.PESTB_DATA_PE10 | |||
| Constant(s): | ||||
| Comments: | Records which PEs are running/frozen | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0 | PAU3.MISC.REGS.PESTB_DATA_PE10Q.LATC.L2(0) [0] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX | RWX | DMA_STOPPED_STATE_PE10: 0/1 = This PE is running/frozen | |
| 1:63 | RO | RO | constant=0b000000000000000000000000000000000000000000000000000000000000000 | |
| PESTB Data for PE 11 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B7B (SCOM) 0000000013720258 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.PESTB_DATA_PE11 | |||
| Constant(s): | ||||
| Comments: | Records which PEs are running/frozen | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0 | PAU3.MISC.REGS.PESTB_DATA_PE11Q.LATC.L2(0) [0] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX | RWX | DMA_STOPPED_STATE_PE11: 0/1 = This PE is running/frozen | |
| 1:63 | RO | RO | constant=0b000000000000000000000000000000000000000000000000000000000000000 | |
| PESTB Data for PE 12 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B7C (SCOM) 0000000013720260 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.PESTB_DATA_PE12 | |||
| Constant(s): | ||||
| Comments: | Records which PEs are running/frozen | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0 | PAU3.MISC.REGS.PESTB_DATA_PE12Q.LATC.L2(0) [0] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX | RWX | DMA_STOPPED_STATE_PE12: 0/1 = This PE is running/frozen | |
| 1:63 | RO | RO | constant=0b000000000000000000000000000000000000000000000000000000000000000 | |
| PESTB Data for PE 13 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B7D (SCOM) 0000000013720268 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.PESTB_DATA_PE13 | |||
| Constant(s): | ||||
| Comments: | Records which PEs are running/frozen | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0 | PAU3.MISC.REGS.PESTB_DATA_PE13Q.LATC.L2(0) [0] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX | RWX | DMA_STOPPED_STATE_PE13: 0/1 = This PE is running/frozen | |
| 1:63 | RO | RO | constant=0b000000000000000000000000000000000000000000000000000000000000000 | |
| PESTB Data for PE 14 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B7E (SCOM) 0000000013720270 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.PESTB_DATA_PE14 | |||
| Constant(s): | ||||
| Comments: | Records which PEs are running/frozen | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0 | PAU3.MISC.REGS.PESTB_DATA_PE14Q.LATC.L2(0) [0] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX | RWX | DMA_STOPPED_STATE_PE14: 0/1 = This PE is running/frozen | |
| 1:63 | RO | RO | constant=0b000000000000000000000000000000000000000000000000000000000000000 | |
| PESTB Data for PE 15 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B7F (SCOM) 0000000013720278 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.PESTB_DATA_PE15 | |||
| Constant(s): | ||||
| Comments: | Records which PEs are running/frozen | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0 | PAU3.MISC.REGS.PESTB_DATA_PE15Q.LATC.L2(0) [0] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX | RWX | DMA_STOPPED_STATE_PE15: 0/1 = This PE is running/frozen | |
| 1:63 | RO | RO | constant=0b000000000000000000000000000000000000000000000000000000000000000 | |
| PESTB Address for PE 0 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B80 (SCOM) 0000000013720280 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.PESTB_ADDR_PE0 | |||
| Constant(s): | ||||
| Comments: | Records which NVLink Address caused PE freeze state Only valid for TCE addresss translation TVT error, TVT address truncation error and page access error (ATS macro error bits 0,1,2,3,4), otherwise zero | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:36 | PAU3.MISC.REGS.PESTB_ADDR_PE0Q.LATC.L2(0:36) [0000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:36 | RWX | RWX | DMA_STOPPED_STATE_ADDR_PE0: PESTB(0 to 36) = Coherent Bus(15 to 51) = NVLink Address(48 to 12) | |
| 37:63 | RO | RO | constant=0b000000000000000000000000000 | |
| PESTB Address for PE 1 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B81 (SCOM) 0000000013720288 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.PESTB_ADDR_PE1 | |||
| Constant(s): | ||||
| Comments: | Records which NVLink Address caused PE freeze state Only valid for TCE addresss translation TVT error, TVT address truncation error and page access error (ATS macro error bits 0,1,2,3,4), otherwise zero | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:36 | PAU3.MISC.REGS.PESTB_ADDR_PE1Q.LATC.L2(0:36) [0000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:36 | RWX | RWX | DMA_STOPPED_STATE_ADDR_PE1: PESTB(0 to 36) = Coherent Bus(15 to 51) = NVLink Address(48 to 12) | |
| 37:63 | RO | RO | constant=0b000000000000000000000000000 | |
| PESTB Address for PE 2 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B82 (SCOM) 0000000013720290 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.PESTB_ADDR_PE2 | |||
| Constant(s): | ||||
| Comments: | Records which NVLink Address caused PE freeze state Only valid for TCE addresss translation TVT error, TVT address truncation error and page access error (ATS macro error bits 0,1,2,3,4), otherwise zero | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:36 | PAU3.MISC.REGS.PESTB_ADDR_PE2Q.LATC.L2(0:36) [0000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:36 | RWX | RWX | DMA_STOPPED_STATE_ADDR_PE2: PESTB(0 to 36) = Coherent Bus(15 to 51) = NVLink Address(48 to 12) | |
| 37:63 | RO | RO | constant=0b000000000000000000000000000 | |
| PESTB Address for PE 3 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B83 (SCOM) 0000000013720298 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.PESTB_ADDR_PE3 | |||
| Constant(s): | ||||
| Comments: | Records which NVLink Address caused PE freeze state Only valid for TCE addresss translation TVT error, TVT address truncation error and page access error (ATS macro error bits 0,1,2,3,4), otherwise zero | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:36 | PAU3.MISC.REGS.PESTB_ADDR_PE3Q.LATC.L2(0:36) [0000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:36 | RWX | RWX | DMA_STOPPED_STATE_ADDR_PE3: PESTB(0 to 36) = Coherent Bus(15 to 51) = NVLink Address(48 to 12) | |
| 37:63 | RO | RO | constant=0b000000000000000000000000000 | |
| PESTB Address for PE 4 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B84 (SCOM) 00000000137202A0 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.PESTB_ADDR_PE4 | |||
| Constant(s): | ||||
| Comments: | Records which NVLink Address caused PE freeze state Only valid for TCE addresss translation TVT error, TVT address truncation error and page access error (ATS macro error bits 0,1,2,3,4), otherwise zero | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:36 | PAU3.MISC.REGS.PESTB_ADDR_PE4Q.LATC.L2(0:36) [0000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:36 | RWX | RWX | DMA_STOPPED_STATE_ADDR_PE4: PESTB(0 to 36) = Coherent Bus(15 to 51) = NVLink Address(48 to 12) | |
| 37:63 | RO | RO | constant=0b000000000000000000000000000 | |
| PESTB Address for PE 5 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B85 (SCOM) 00000000137202A8 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.PESTB_ADDR_PE5 | |||
| Constant(s): | ||||
| Comments: | Records which NVLink Address caused PE freeze state Only valid for TCE addresss translation TVT error, TVT address truncation error and page access error (ATS macro error bits 0,1,2,3,4), otherwise zero | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:36 | PAU3.MISC.REGS.PESTB_ADDR_PE5Q.LATC.L2(0:36) [0000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:36 | RWX | RWX | DMA_STOPPED_STATE_ADDR_PE5: PESTB(0 to 36) = Coherent Bus(15 to 51) = NVLink Address(48 to 12) | |
| 37:63 | RO | RO | constant=0b000000000000000000000000000 | |
| PESTB Address for PE 6 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B86 (SCOM) 00000000137202B0 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.PESTB_ADDR_PE6 | |||
| Constant(s): | ||||
| Comments: | Records which NVLink Address caused PE freeze state Only valid for TCE addresss translation TVT error, TVT address truncation error and page access error (ATS macro error bits 0,1,2,3,4), otherwise zero | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:36 | PAU3.MISC.REGS.PESTB_ADDR_PE6Q.LATC.L2(0:36) [0000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:36 | RWX | RWX | DMA_STOPPED_STATE_ADDR_PE6: PESTB(0 to 36) = Coherent Bus(15 to 51) = NVLink Address(48 to 12) | |
| 37:63 | RO | RO | constant=0b000000000000000000000000000 | |
| PESTB Address for PE 7 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B87 (SCOM) 00000000137202B8 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.PESTB_ADDR_PE7 | |||
| Constant(s): | ||||
| Comments: | Records which NVLink Address caused PE freeze state Only valid for TCE addresss translation TVT error, TVT address truncation error and page access error (ATS macro error bits 0,1,2,3,4), otherwise zero | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:36 | PAU3.MISC.REGS.PESTB_ADDR_PE7Q.LATC.L2(0:36) [0000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:36 | RWX | RWX | DMA_STOPPED_STATE_ADDR_PE7: PESTB(0 to 36) = Coherent Bus(15 to 51) = NVLink Address(48 to 12) | |
| 37:63 | RO | RO | constant=0b000000000000000000000000000 | |
| PESTB Address for PE 8 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B88 (SCOM) 00000000137202C0 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.PESTB_ADDR_PE8 | |||
| Constant(s): | ||||
| Comments: | Records which NVLink Address caused PE freeze state Only valid for TCE addresss translation TVT error, TVT address truncation error and page access error (ATS macro error bits 0,1,2,3,4), otherwise zero | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:36 | PAU3.MISC.REGS.PESTB_ADDR_PE8Q.LATC.L2(0:36) [0000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:36 | RWX | RWX | DMA_STOPPED_STATE_ADDR_PE8: PESTB(0 to 36) = Coherent Bus(15 to 51) = NVLink Address(48 to 12) | |
| 37:63 | RO | RO | constant=0b000000000000000000000000000 | |
| PESTB Address for PE 9 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B89 (SCOM) 00000000137202C8 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.PESTB_ADDR_PE9 | |||
| Constant(s): | ||||
| Comments: | Records which NVLink Address caused PE freeze state Only valid for TCE addresss translation TVT error, TVT address truncation error and page access error (ATS macro error bits 0,1,2,3,4), otherwise zero | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:36 | PAU3.MISC.REGS.PESTB_ADDR_PE9Q.LATC.L2(0:36) [0000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:36 | RWX | RWX | DMA_STOPPED_STATE_ADDR_PE9: PESTB(0 to 36) = Coherent Bus(15 to 51) = NVLink Address(48 to 12) | |
| 37:63 | RO | RO | constant=0b000000000000000000000000000 | |
| PESTB Address for PE 10 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B8A (SCOM) 00000000137202D0 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.PESTB_ADDR_PE10 | |||
| Constant(s): | ||||
| Comments: | Records which NVLink Address caused PE freeze state Only valid for TCE addresss translation TVT error, TVT address truncation error and page access error (ATS macro error bits 0,1,2,3,4), otherwise zero | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:36 | PAU3.MISC.REGS.PESTB_ADDR_PE10Q.LATC.L2(0:36) [0000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:36 | RWX | RWX | DMA_STOPPED_STATE_ADDR_PE10: PESTB(0 to 36) = Coherent Bus(15 to 51) = NVLink Address(48 to 12) | |
| 37:63 | RO | RO | constant=0b000000000000000000000000000 | |
| PESTB Address for PE 11 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B8B (SCOM) 00000000137202D8 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.PESTB_ADDR_PE11 | |||
| Constant(s): | ||||
| Comments: | Records which NVLink Address caused PE freeze state Only valid for TCE addresss translation TVT error, TVT address truncation error and page access error (ATS macro error bits 0,1,2,3,4), otherwise zero | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:36 | PAU3.MISC.REGS.PESTB_ADDR_PE11Q.LATC.L2(0:36) [0000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:36 | RWX | RWX | DMA_STOPPED_STATE_ADDR_PE11: PESTB(0 to 36) = Coherent Bus(15 to 51) = NVLink Address(48 to 12) | |
| 37:63 | RO | RO | constant=0b000000000000000000000000000 | |
| PESTB Address for PE 12 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B8C (SCOM) 00000000137202E0 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.PESTB_ADDR_PE12 | |||
| Constant(s): | ||||
| Comments: | Records which NVLink Address caused PE freeze state Only valid for TCE addresss translation TVT error, TVT address truncation error and page access error (ATS macro error bits 0,1,2,3,4), otherwise zero | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:36 | PAU3.MISC.REGS.PESTB_ADDR_PE12Q.LATC.L2(0:36) [0000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:36 | RWX | RWX | DMA_STOPPED_STATE_ADDR_PE12: PESTB(0 to 36) = Coherent Bus(15 to 51) = NVLink Address(48 to 12) | |
| 37:63 | RO | RO | constant=0b000000000000000000000000000 | |
| PESTB Address for PE 13 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B8D (SCOM) 00000000137202E8 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.PESTB_ADDR_PE13 | |||
| Constant(s): | ||||
| Comments: | Records which NVLink Address caused PE freeze state Only valid for TCE addresss translation TVT error, TVT address truncation error and page access error (ATS macro error bits 0,1,2,3,4), otherwise zero | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:36 | PAU3.MISC.REGS.PESTB_ADDR_PE13Q.LATC.L2(0:36) [0000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:36 | RWX | RWX | DMA_STOPPED_STATE_ADDR_PE13: PESTB(0 to 36) = Coherent Bus(15 to 51) = NVLink Address(48 to 12) | |
| 37:63 | RO | RO | constant=0b000000000000000000000000000 | |
| PESTB Address for PE 14 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B8E (SCOM) 00000000137202F0 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.PESTB_ADDR_PE14 | |||
| Constant(s): | ||||
| Comments: | Records which NVLink Address caused PE freeze state Only valid for TCE addresss translation TVT error, TVT address truncation error and page access error (ATS macro error bits 0,1,2,3,4), otherwise zero | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:36 | PAU3.MISC.REGS.PESTB_ADDR_PE14Q.LATC.L2(0:36) [0000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:36 | RWX | RWX | DMA_STOPPED_STATE_ADDR_PE14: PESTB(0 to 36) = Coherent Bus(15 to 51) = NVLink Address(48 to 12) | |
| 37:63 | RO | RO | constant=0b000000000000000000000000000 | |
| PESTB Address for PE 15 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B8F (SCOM) 00000000137202F8 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.PESTB_ADDR_PE15 | |||
| Constant(s): | ||||
| Comments: | Records which NVLink Address caused PE freeze state Only valid for TCE addresss translation TVT error, TVT address truncation error and page access error (ATS macro error bits 0,1,2,3,4), otherwise zero | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:36 | PAU3.MISC.REGS.PESTB_ADDR_PE15Q.LATC.L2(0:36) [0000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:36 | RWX | RWX | DMA_STOPPED_STATE_ADDR_PE15: PESTB(0 to 36) = Coherent Bus(15 to 51) = NVLink Address(48 to 12) | |
| 37:63 | RO | RO | constant=0b000000000000000000000000000 | |
| System Interrupt Log Register 0 for PE 0 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B90 (SCOM) 0000000013720300 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.INT_LOG_0_PE0 | |||
| Constant(s): | ||||
| Comments: | Records which error caused a System Interrupt for each PE | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.MISC.REGS.INT_LOG_0_PE0Q.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX | RWX | INT_LOG_0_ERR_PE0_VLD: Contents valid (freeze on 1st capture) | |
| 1:60 | RWX | RWX | INT_LOG_0_ERR_PE0_LVL: Interrupt requester (see Interrupt Level) | |
| 61:63 | RWX | RWX | INT_LOG_0_ERR_PE0_RSVD0: Reserved | |
| System Interrupt Log Register 0 for PE 1 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B91 (SCOM) 0000000013720308 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.INT_LOG_0_PE1 | |||
| Constant(s): | ||||
| Comments: | Records which error caused a System Interrupt for each PE | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.MISC.REGS.INT_LOG_0_PE1Q.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX | RWX | INT_LOG_0_ERR_PE1_VLD: Contents valid (freeze on 1st capture) | |
| 1:60 | RWX | RWX | INT_LOG_0_ERR_PE1_LVL: Interrupt requester (see Interrupt Level) | |
| 61:63 | RWX | RWX | INT_LOG_0_ERR_PE1_RSVD0: Reserved | |
| System Interrupt Log Register 0 for PE 2 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B92 (SCOM) 0000000013720310 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.INT_LOG_0_PE2 | |||
| Constant(s): | ||||
| Comments: | Records which error caused a System Interrupt for each PE | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.MISC.REGS.INT_LOG_0_PE2Q.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX | RWX | INT_LOG_0_ERR_PE2_VLD: Contents valid (freeze on 1st capture) | |
| 1:60 | RWX | RWX | INT_LOG_0_ERR_PE2_LVL: Interrupt requester (see Interrupt Level) | |
| 61:63 | RWX | RWX | INT_LOG_0_ERR_PE2_RSVD0: Reserved | |
| System Interrupt Log Register 0 for PE 3 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B93 (SCOM) 0000000013720318 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.INT_LOG_0_PE3 | |||
| Constant(s): | ||||
| Comments: | Records which error caused a System Interrupt for each PE | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.MISC.REGS.INT_LOG_0_PE3Q.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX | RWX | INT_LOG_0_ERR_PE3_VLD: Contents valid (freeze on 1st capture) | |
| 1:60 | RWX | RWX | INT_LOG_0_ERR_PE3_LVL: Interrupt requester (see Interrupt Level) | |
| 61:63 | RWX | RWX | INT_LOG_0_ERR_PE3_RSVD0: Reserved | |
| System Interrupt Log Register 0 for PE 4 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B94 (SCOM) 0000000013720320 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.INT_LOG_0_PE4 | |||
| Constant(s): | ||||
| Comments: | Records which error caused a System Interrupt for each PE | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.MISC.REGS.INT_LOG_0_PE4Q.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX | RWX | INT_LOG_0_ERR_PE4_VLD: Contents valid (freeze on 1st capture) | |
| 1:60 | RWX | RWX | INT_LOG_0_ERR_PE4_LVL: Interrupt requester (see Interrupt Level) | |
| 61:63 | RWX | RWX | INT_LOG_0_ERR_PE4_RSVD0: Reserved | |
| System Interrupt Log Register 0 for PE 5 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B95 (SCOM) 0000000013720328 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.INT_LOG_0_PE5 | |||
| Constant(s): | ||||
| Comments: | Records which error caused a System Interrupt for each PE | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.MISC.REGS.INT_LOG_0_PE5Q.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX | RWX | INT_LOG_0_ERR_PE5_VLD: Contents valid (freeze on 1st capture) | |
| 1:60 | RWX | RWX | INT_LOG_0_ERR_PE5_LVL: Interrupt requester (see Interrupt Level) | |
| 61:63 | RWX | RWX | INT_LOG_0_ERR_PE5_RSVD0: Reserved | |
| System Interrupt Log Register 0 for PE 6 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B96 (SCOM) 0000000013720330 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.INT_LOG_0_PE6 | |||
| Constant(s): | ||||
| Comments: | Records which error caused a System Interrupt for each PE | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.MISC.REGS.INT_LOG_0_PE6Q.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX | RWX | INT_LOG_0_ERR_PE6_VLD: Contents valid (freeze on 1st capture) | |
| 1:60 | RWX | RWX | INT_LOG_0_ERR_PE6_LVL: Interrupt requester (see Interrupt Level) | |
| 61:63 | RWX | RWX | INT_LOG_0_ERR_PE6_RSVD0: Reserved | |
| System Interrupt Log Register 0 for PE 7 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B97 (SCOM) 0000000013720338 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.INT_LOG_0_PE7 | |||
| Constant(s): | ||||
| Comments: | Records which error caused a System Interrupt for each PE | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.MISC.REGS.INT_LOG_0_PE7Q.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX | RWX | INT_LOG_0_ERR_PE7_VLD: Contents valid (freeze on 1st capture) | |
| 1:60 | RWX | RWX | INT_LOG_0_ERR_PE7_LVL: Interrupt requester (see Interrupt Level) | |
| 61:63 | RWX | RWX | INT_LOG_0_ERR_PE7_RSVD0: Reserved | |
| System Interrupt Log Register 0 for PE 8 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B98 (SCOM) 0000000013720340 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.INT_LOG_0_PE8 | |||
| Constant(s): | ||||
| Comments: | Records which error caused a System Interrupt for each PE | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.MISC.REGS.INT_LOG_0_PE8Q.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX | RWX | INT_LOG_0_ERR_PE8_VLD: Contents valid (freeze on 1st capture) | |
| 1:60 | RWX | RWX | INT_LOG_0_ERR_PE8_LVL: Interrupt requester (see Interrupt Level) | |
| 61:63 | RWX | RWX | INT_LOG_0_ERR_PE8_RSVD0: Reserved | |
| System Interrupt Log Register 0 for PE 9 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B99 (SCOM) 0000000013720348 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.INT_LOG_0_PE9 | |||
| Constant(s): | ||||
| Comments: | Records which error caused a System Interrupt for each PE | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.MISC.REGS.INT_LOG_0_PE9Q.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX | RWX | INT_LOG_0_ERR_PE9_VLD: Contents valid (freeze on 1st capture) | |
| 1:60 | RWX | RWX | INT_LOG_0_ERR_PE9_LVL: Interrupt requester (see Interrupt Level) | |
| 61:63 | RWX | RWX | INT_LOG_0_ERR_PE9_RSVD0: Reserved | |
| System Interrupt Log Register 0 for PE 10 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B9A (SCOM) 0000000013720350 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.INT_LOG_0_PE10 | |||
| Constant(s): | ||||
| Comments: | Records which error caused a System Interrupt for each PE | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.MISC.REGS.INT_LOG_0_PE10Q.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX | RWX | INT_LOG_0_ERR_PE10_VLD: Contents valid (freeze on 1st capture) | |
| 1:60 | RWX | RWX | INT_LOG_0_ERR_PE10_LVL: Interrupt requester (see Interrupt Level) | |
| 61:63 | RWX | RWX | INT_LOG_0_ERR_PE10_RSVD0: Reserved | |
| System Interrupt Log Register 0 for PE 11 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B9B (SCOM) 0000000013720358 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.INT_LOG_0_PE11 | |||
| Constant(s): | ||||
| Comments: | Records which error caused a System Interrupt for each PE | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.MISC.REGS.INT_LOG_0_PE11Q.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX | RWX | INT_LOG_0_ERR_PE11_VLD: Contents valid (freeze on 1st capture) | |
| 1:60 | RWX | RWX | INT_LOG_0_ERR_PE11_LVL: Interrupt requester (see Interrupt Level) | |
| 61:63 | RWX | RWX | INT_LOG_0_ERR_PE11_RSVD0: Reserved | |
| System Interrupt Log Register 0 for PE 12 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B9C (SCOM) 0000000013720360 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.INT_LOG_0_PE12 | |||
| Constant(s): | ||||
| Comments: | Records which error caused a System Interrupt for each PE | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.MISC.REGS.INT_LOG_0_PE12Q.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX | RWX | INT_LOG_0_ERR_PE12_VLD: Contents valid (freeze on 1st capture) | |
| 1:60 | RWX | RWX | INT_LOG_0_ERR_PE12_LVL: Interrupt requester (see Interrupt Level) | |
| 61:63 | RWX | RWX | INT_LOG_0_ERR_PE12_RSVD0: Reserved | |
| System Interrupt Log Register 0 for PE 13 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B9D (SCOM) 0000000013720368 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.INT_LOG_0_PE13 | |||
| Constant(s): | ||||
| Comments: | Records which error caused a System Interrupt for each PE | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.MISC.REGS.INT_LOG_0_PE13Q.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX | RWX | INT_LOG_0_ERR_PE13_VLD: Contents valid (freeze on 1st capture) | |
| 1:60 | RWX | RWX | INT_LOG_0_ERR_PE13_LVL: Interrupt requester (see Interrupt Level) | |
| 61:63 | RWX | RWX | INT_LOG_0_ERR_PE13_RSVD0: Reserved | |
| System Interrupt Log Register 0 for PE 14 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B9E (SCOM) 0000000013720370 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.INT_LOG_0_PE14 | |||
| Constant(s): | ||||
| Comments: | Records which error caused a System Interrupt for each PE | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.MISC.REGS.INT_LOG_0_PE14Q.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX | RWX | INT_LOG_0_ERR_PE14_VLD: Contents valid (freeze on 1st capture) | |
| 1:60 | RWX | RWX | INT_LOG_0_ERR_PE14_LVL: Interrupt requester (see Interrupt Level) | |
| 61:63 | RWX | RWX | INT_LOG_0_ERR_PE14_RSVD0: Reserved | |
| System Interrupt Log Register 0 for PE 15 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010B9F (SCOM) 0000000013720378 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.INT_LOG_0_PE15 | |||
| Constant(s): | ||||
| Comments: | Records which error caused a System Interrupt for each PE | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.MISC.REGS.INT_LOG_0_PE15Q.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX | RWX | INT_LOG_0_ERR_PE15_VLD: Contents valid (freeze on 1st capture) | |
| 1:60 | RWX | RWX | INT_LOG_0_ERR_PE15_LVL: Interrupt requester (see Interrupt Level) | |
| 61:63 | RWX | RWX | INT_LOG_0_ERR_PE15_RSVD0: Reserved | |
| System Interrupt Log Register 1 for PE 0 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010BA0 (SCOM) 0000000013720380 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.INT_LOG_1_PE0 | |||
| Constant(s): | ||||
| Comments: | Records error details for error caused a System Interrupt for each PE | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.MISC.REGS.INT_LOG_1_PE0Q.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX | RWX | INT_LOG_1_ERR_PE0_VLD: Contents valid (freeze on 1st capture) | |
| 1:32 | RWX | RWX | INT_LOG_1_ERR_PE0_DETAIL: Error detail for requester (see FIR 0/1/2 register). If >1 simultaneous interrupt requester to same PE, capture priority is Interrupt Level 0 (highest) to Level 59. If redundant interrupt request to different PE, capture details for new PE (ie. ATS interrupt to PE A in progress, then ATS interrupt to PE B) | |
| 33:56 | RWX | RWX | INT_LOG_1_ERR_PE0_CQ: Interrupt requester, additional detail CQ events: CTL0 brk0/1/2/3, CTL1 brk4/5/6/7, CTL2 brk8/9/10/11, DAT0 brk0/1/2/3, DAT1 brk4/5/6/7, DAT2 brk8/9/10/11 | |
| 57:63 | RWX | RWX | INT_LOG_1_ERR_PE0_RSVD0: Reserved | |
| System Interrupt Log Register 1 for PE 1 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010BA1 (SCOM) 0000000013720388 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.INT_LOG_1_PE1 | |||
| Constant(s): | ||||
| Comments: | Records error details for error caused a System Interrupt for each PE | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.MISC.REGS.INT_LOG_1_PE1Q.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX | RWX | INT_LOG_1_ERR_PE1_VLD: Contents valid (freeze on 1st capture) | |
| 1:32 | RWX | RWX | INT_LOG_1_ERR_PE1_DETAIL: Error detail for requester (see FIR 0/1/2 register). If >1 simultaneous interrupt requester to same PE, capture priority is Interrupt Level 0 (highest) to Level 59. If redundant interrupt request to different PE, capture details for new PE (ie. ATS interrupt to PE A in progress, then ATS interrupt to PE B) | |
| 33:56 | RWX | RWX | INT_LOG_1_ERR_PE1_CQ: Interrupt requester, additional detail CQ events: CTL0 brk0/1/2/3, CTL1 brk4/5/6/7, CTL2 brk8/9/10/11, DAT0 brk0/1/2/3, DAT1 brk4/5/6/7, DAT2 brk8/9/10/11 | |
| 57:63 | RWX | RWX | INT_LOG_1_ERR_PE1_RSVD0: Reserved | |
| System Interrupt Log Register 1 for PE 2 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010BA2 (SCOM) 0000000013720390 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.INT_LOG_1_PE2 | |||
| Constant(s): | ||||
| Comments: | Records error details for error caused a System Interrupt for each PE | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.MISC.REGS.INT_LOG_1_PE2Q.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX | RWX | INT_LOG_1_ERR_PE2_VLD: Contents valid (freeze on 1st capture) | |
| 1:32 | RWX | RWX | INT_LOG_1_ERR_PE2_DETAIL: Error detail for requester (see FIR 0/1/2 register). If >1 simultaneous interrupt requester to same PE, capture priority is Interrupt Level 0 (highest) to Level 59. If redundant interrupt request to different PE, capture details for new PE (ie. ATS interrupt to PE A in progress, then ATS interrupt to PE B) | |
| 33:56 | RWX | RWX | INT_LOG_1_ERR_PE2_CQ: Interrupt requester, additional detail CQ events: CTL0 brk0/1/2/3, CTL1 brk4/5/6/7, CTL2 brk8/9/10/11, DAT0 brk0/1/2/3, DAT1 brk4/5/6/7, DAT2 brk8/9/10/11 | |
| 57:63 | RWX | RWX | INT_LOG_1_ERR_PE2_RSVD0: Reserved | |
| System Interrupt Log Register 1 for PE 3 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010BA3 (SCOM) 0000000013720398 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.INT_LOG_1_PE3 | |||
| Constant(s): | ||||
| Comments: | Records error details for error caused a System Interrupt for each PE | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.MISC.REGS.INT_LOG_1_PE3Q.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX | RWX | INT_LOG_1_ERR_PE3_VLD: Contents valid (freeze on 1st capture) | |
| 1:32 | RWX | RWX | INT_LOG_1_ERR_PE3_DETAIL: Error detail for requester (see FIR 0/1/2 register). If >1 simultaneous interrupt requester to same PE, capture priority is Interrupt Level 0 (highest) to Level 59. If redundant interrupt request to different PE, capture details for new PE (ie. ATS interrupt to PE A in progress, then ATS interrupt to PE B) | |
| 33:56 | RWX | RWX | INT_LOG_1_ERR_PE3_CQ: Interrupt requester, additional detail CQ events: CTL0 brk0/1/2/3, CTL1 brk4/5/6/7, CTL2 brk8/9/10/11, DAT0 brk0/1/2/3, DAT1 brk4/5/6/7, DAT2 brk8/9/10/11 | |
| 57:63 | RWX | RWX | INT_LOG_1_ERR_PE3_RSVD0: Reserved | |
| System Interrupt Log Register 1 for PE 4 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010BA4 (SCOM) 00000000137203A0 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.INT_LOG_1_PE4 | |||
| Constant(s): | ||||
| Comments: | Records error details for error caused a System Interrupt for each PE | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.MISC.REGS.INT_LOG_1_PE4Q.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX | RWX | INT_LOG_1_ERR_PE4_VLD: Contents valid (freeze on 1st capture) | |
| 1:32 | RWX | RWX | INT_LOG_1_ERR_PE4_DETAIL: Error detail for requester (see FIR 0/1/2 register). If >1 simultaneous interrupt requester to same PE, capture priority is Interrupt Level 0 (highest) to Level 59. If redundant interrupt request to different PE, capture details for new PE (ie. ATS interrupt to PE A in progress, then ATS interrupt to PE B) | |
| 33:56 | RWX | RWX | INT_LOG_1_ERR_PE4_CQ: Interrupt requester, additional detail CQ events: CTL0 brk0/1/2/3, CTL1 brk4/5/6/7, CTL2 brk8/9/10/11, DAT0 brk0/1/2/3, DAT1 brk4/5/6/7, DAT2 brk8/9/10/11 | |
| 57:63 | RWX | RWX | INT_LOG_1_ERR_PE4_RSVD0: Reserved | |
| System Interrupt Log Register 1 for PE 5 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010BA5 (SCOM) 00000000137203A8 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.INT_LOG_1_PE5 | |||
| Constant(s): | ||||
| Comments: | Records error details for error caused a System Interrupt for each PE | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.MISC.REGS.INT_LOG_1_PE5Q.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX | RWX | INT_LOG_1_ERR_PE5_VLD: Contents valid (freeze on 1st capture) | |
| 1:32 | RWX | RWX | INT_LOG_1_ERR_PE5_DETAIL: Error detail for requester (see FIR 0/1/2 register). If >1 simultaneous interrupt requester to same PE, capture priority is Interrupt Level 0 (highest) to Level 59. If redundant interrupt request to different PE, capture details for new PE (ie. ATS interrupt to PE A in progress, then ATS interrupt to PE B) | |
| 33:56 | RWX | RWX | INT_LOG_1_ERR_PE5_CQ: Interrupt requester, additional detail CQ events: CTL0 brk0/1/2/3, CTL1 brk4/5/6/7, CTL2 brk8/9/10/11, DAT0 brk0/1/2/3, DAT1 brk4/5/6/7, DAT2 brk8/9/10/11 | |
| 57:63 | RWX | RWX | INT_LOG_1_ERR_PE5_RSVD0: Reserved | |
| System Interrupt Log Register 1 for PE 6 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010BA6 (SCOM) 00000000137203B0 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.INT_LOG_1_PE6 | |||
| Constant(s): | ||||
| Comments: | Records error details for error caused a System Interrupt for each PE | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.MISC.REGS.INT_LOG_1_PE6Q.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX | RWX | INT_LOG_1_ERR_PE6_VLD: Contents valid (freeze on 1st capture) | |
| 1:32 | RWX | RWX | INT_LOG_1_ERR_PE6_DETAIL: Error detail for requester (see FIR 0/1/2 register). If >1 simultaneous interrupt requester to same PE, capture priority is Interrupt Level 0 (highest) to Level 59. If redundant interrupt request to different PE, capture details for new PE (ie. ATS interrupt to PE A in progress, then ATS interrupt to PE B) | |
| 33:56 | RWX | RWX | INT_LOG_1_ERR_PE6_CQ: Interrupt requester, additional detail CQ events: CTL0 brk0/1/2/3, CTL1 brk4/5/6/7, CTL2 brk8/9/10/11, DAT0 brk0/1/2/3, DAT1 brk4/5/6/7, DAT2 brk8/9/10/11 | |
| 57:63 | RWX | RWX | INT_LOG_1_ERR_PE6_RSVD0: Reserved | |
| System Interrupt Log Register 1 for PE 7 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010BA7 (SCOM) 00000000137203B8 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.INT_LOG_1_PE7 | |||
| Constant(s): | ||||
| Comments: | Records error details for error caused a System Interrupt for each PE | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.MISC.REGS.INT_LOG_1_PE7Q.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX | RWX | INT_LOG_1_ERR_PE7_VLD: Contents valid (freeze on 1st capture) | |
| 1:32 | RWX | RWX | INT_LOG_1_ERR_PE7_DETAIL: Error detail for requester (see FIR 0/1/2 register). If >1 simultaneous interrupt requester to same PE, capture priority is Interrupt Level 0 (highest) to Level 59. If redundant interrupt request to different PE, capture details for new PE (ie. ATS interrupt to PE A in progress, then ATS interrupt to PE B) | |
| 33:56 | RWX | RWX | INT_LOG_1_ERR_PE7_CQ: Interrupt requester, additional detail CQ events: CTL0 brk0/1/2/3, CTL1 brk4/5/6/7, CTL2 brk8/9/10/11, DAT0 brk0/1/2/3, DAT1 brk4/5/6/7, DAT2 brk8/9/10/11 | |
| 57:63 | RWX | RWX | INT_LOG_1_ERR_PE7_RSVD0: Reserved | |
| System Interrupt Log Register 1 for PE 8 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010BA8 (SCOM) 00000000137203C0 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.INT_LOG_1_PE8 | |||
| Constant(s): | ||||
| Comments: | Records error details for error caused a System Interrupt for each PE | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.MISC.REGS.INT_LOG_1_PE8Q.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX | RWX | INT_LOG_1_ERR_PE8_VLD: Contents valid (freeze on 1st capture) | |
| 1:32 | RWX | RWX | INT_LOG_1_ERR_PE8_DETAIL: Error detail for requester (see FIR 0/1/2 register). If >1 simultaneous interrupt requester to same PE, capture priority is Interrupt Level 0 (highest) to Level 59. If redundant interrupt request to different PE, capture details for new PE (ie. ATS interrupt to PE A in progress, then ATS interrupt to PE B) | |
| 33:56 | RWX | RWX | INT_LOG_1_ERR_PE8_CQ: Interrupt requester, additional detail CQ events: CTL0 brk0/1/2/3, CTL1 brk4/5/6/7, CTL2 brk8/9/10/11, DAT0 brk0/1/2/3, DAT1 brk4/5/6/7, DAT2 brk8/9/10/11 | |
| 57:63 | RWX | RWX | INT_LOG_1_ERR_PE8_RSVD0: Reserved | |
| System Interrupt Log Register 1 for PE 9 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010BA9 (SCOM) 00000000137203C8 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.INT_LOG_1_PE9 | |||
| Constant(s): | ||||
| Comments: | Records error details for error caused a System Interrupt for each PE | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.MISC.REGS.INT_LOG_1_PE9Q.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX | RWX | INT_LOG_1_ERR_PE9_VLD: Contents valid (freeze on 1st capture) | |
| 1:32 | RWX | RWX | INT_LOG_1_ERR_PE9_DETAIL: Error detail for requester (see FIR 0/1/2 register). If >1 simultaneous interrupt requester to same PE, capture priority is Interrupt Level 0 (highest) to Level 59. If redundant interrupt request to different PE, capture details for new PE (ie. ATS interrupt to PE A in progress, then ATS interrupt to PE B) | |
| 33:56 | RWX | RWX | INT_LOG_1_ERR_PE9_CQ: Interrupt requester, additional detail CQ events: CTL0 brk0/1/2/3, CTL1 brk4/5/6/7, CTL2 brk8/9/10/11, DAT0 brk0/1/2/3, DAT1 brk4/5/6/7, DAT2 brk8/9/10/11 | |
| 57:63 | RWX | RWX | INT_LOG_1_ERR_PE9_RSVD0: Reserved | |
| System Interrupt Log Register 1 for PE 10 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010BAA (SCOM) 00000000137203D0 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.INT_LOG_1_PE10 | |||
| Constant(s): | ||||
| Comments: | Records error details for error caused a System Interrupt for each PE | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.MISC.REGS.INT_LOG_1_PE10Q.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX | RWX | INT_LOG_1_ERR_PE10_VLD: Contents valid (freeze on 1st capture) | |
| 1:32 | RWX | RWX | INT_LOG_1_ERR_PE10_DETAIL: Error detail for requester (see FIR 0/1/2 register). If >1 simultaneous interrupt requester to same PE, capture priority is Interrupt Level 0 (highest) to Level 59. If redundant interrupt request to different PE, capture details for new PE (ie. ATS interrupt to PE A in progress, then ATS interrupt to PE B) | |
| 33:56 | RWX | RWX | INT_LOG_1_ERR_PE10_CQ: Interrupt requester, additional detail CQ events: CTL0 brk0/1/2/3, CTL1 brk4/5/6/7, CTL2 brk8/9/10/11, DAT0 brk0/1/2/3, DAT1 brk4/5/6/7, DAT2 brk8/9/10/11 | |
| 57:63 | RWX | RWX | INT_LOG_1_ERR_PE10_RSVD0: Reserved | |
| System Interrupt Log Register 1 for PE 11 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010BAB (SCOM) 00000000137203D8 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.INT_LOG_1_PE11 | |||
| Constant(s): | ||||
| Comments: | Records error details for error caused a System Interrupt for each PE | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.MISC.REGS.INT_LOG_1_PE11Q.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX | RWX | INT_LOG_1_ERR_PE11_VLD: Contents valid (freeze on 1st capture) | |
| 1:32 | RWX | RWX | INT_LOG_1_ERR_PE11_DETAIL: Error detail for requester (see FIR 0/1/2 register). If >1 simultaneous interrupt requester to same PE, capture priority is Interrupt Level 0 (highest) to Level 59. If redundant interrupt request to different PE, capture details for new PE (ie. ATS interrupt to PE A in progress, then ATS interrupt to PE B) | |
| 33:56 | RWX | RWX | INT_LOG_1_ERR_PE11_CQ: Interrupt requester, additional detail CQ events: CTL0 brk0/1/2/3, CTL1 brk4/5/6/7, CTL2 brk8/9/10/11, DAT0 brk0/1/2/3, DAT1 brk4/5/6/7, DAT2 brk8/9/10/11 | |
| 57:63 | RWX | RWX | INT_LOG_1_ERR_PE11_RSVD0: Reserved | |
| System Interrupt Log Register 1 for PE 12 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010BAC (SCOM) 00000000137203E0 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.INT_LOG_1_PE12 | |||
| Constant(s): | ||||
| Comments: | Records error details for error caused a System Interrupt for each PE | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.MISC.REGS.INT_LOG_1_PE12Q.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX | RWX | INT_LOG_1_ERR_PE12_VLD: Contents valid (freeze on 1st capture) | |
| 1:32 | RWX | RWX | INT_LOG_1_ERR_PE12_DETAIL: Error detail for requester (see FIR 0/1/2 register). If >1 simultaneous interrupt requester to same PE, capture priority is Interrupt Level 0 (highest) to Level 59. If redundant interrupt request to different PE, capture details for new PE (ie. ATS interrupt to PE A in progress, then ATS interrupt to PE B) | |
| 33:56 | RWX | RWX | INT_LOG_1_ERR_PE12_CQ: Interrupt requester, additional detail CQ events: CTL0 brk0/1/2/3, CTL1 brk4/5/6/7, CTL2 brk8/9/10/11, DAT0 brk0/1/2/3, DAT1 brk4/5/6/7, DAT2 brk8/9/10/11 | |
| 57:63 | RWX | RWX | INT_LOG_1_ERR_PE12_RSVD0: Reserved | |
| System Interrupt Log Register 1 for PE 13 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010BAD (SCOM) 00000000137203E8 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.INT_LOG_1_PE13 | |||
| Constant(s): | ||||
| Comments: | Records error details for error caused a System Interrupt for each PE | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.MISC.REGS.INT_LOG_1_PE13Q.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX | RWX | INT_LOG_1_ERR_PE13_VLD: Contents valid (freeze on 1st capture) | |
| 1:32 | RWX | RWX | INT_LOG_1_ERR_PE13_DETAIL: Error detail for requester (see FIR 0/1/2 register). If >1 simultaneous interrupt requester to same PE, capture priority is Interrupt Level 0 (highest) to Level 59. If redundant interrupt request to different PE, capture details for new PE (ie. ATS interrupt to PE A in progress, then ATS interrupt to PE B) | |
| 33:56 | RWX | RWX | INT_LOG_1_ERR_PE13_CQ: Interrupt requester, additional detail CQ events: CTL0 brk0/1/2/3, CTL1 brk4/5/6/7, CTL2 brk8/9/10/11, DAT0 brk0/1/2/3, DAT1 brk4/5/6/7, DAT2 brk8/9/10/11 | |
| 57:63 | RWX | RWX | INT_LOG_1_ERR_PE13_RSVD0: Reserved | |
| System Interrupt Log Register 1 for PE 14 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010BAE (SCOM) 00000000137203F0 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.INT_LOG_1_PE14 | |||
| Constant(s): | ||||
| Comments: | Records error details for error caused a System Interrupt for each PE | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.MISC.REGS.INT_LOG_1_PE14Q.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX | RWX | INT_LOG_1_ERR_PE14_VLD: Contents valid (freeze on 1st capture) | |
| 1:32 | RWX | RWX | INT_LOG_1_ERR_PE14_DETAIL: Error detail for requester (see FIR 0/1/2 register). If >1 simultaneous interrupt requester to same PE, capture priority is Interrupt Level 0 (highest) to Level 59. If redundant interrupt request to different PE, capture details for new PE (ie. ATS interrupt to PE A in progress, then ATS interrupt to PE B) | |
| 33:56 | RWX | RWX | INT_LOG_1_ERR_PE14_CQ: Interrupt requester, additional detail CQ events: CTL0 brk0/1/2/3, CTL1 brk4/5/6/7, CTL2 brk8/9/10/11, DAT0 brk0/1/2/3, DAT1 brk4/5/6/7, DAT2 brk8/9/10/11 | |
| 57:63 | RWX | RWX | INT_LOG_1_ERR_PE14_RSVD0: Reserved | |
| System Interrupt Log Register 1 for PE 15 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010BAF (SCOM) 00000000137203F8 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.INT_LOG_1_PE15 | |||
| Constant(s): | ||||
| Comments: | Records error details for error caused a System Interrupt for each PE | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.MISC.REGS.INT_LOG_1_PE15Q.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0 | RWX | RWX | INT_LOG_1_ERR_PE15_VLD: Contents valid (freeze on 1st capture) | |
| 1:32 | RWX | RWX | INT_LOG_1_ERR_PE15_DETAIL: Error detail for requester (see FIR 0/1/2 register). If >1 simultaneous interrupt requester to same PE, capture priority is Interrupt Level 0 (highest) to Level 59. If redundant interrupt request to different PE, capture details for new PE (ie. ATS interrupt to PE A in progress, then ATS interrupt to PE B) | |
| 33:56 | RWX | RWX | INT_LOG_1_ERR_PE15_CQ: Interrupt requester, additional detail CQ events: CTL0 brk0/1/2/3, CTL1 brk4/5/6/7, CTL2 brk8/9/10/11, DAT0 brk0/1/2/3, DAT1 brk4/5/6/7, DAT2 brk8/9/10/11 | |
| 57:63 | RWX | RWX | INT_LOG_1_ERR_PE15_RSVD0: Reserved | |
| PAU Fence-on-error Enable for FIR Register 2 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010BB0 (SCOM) 0000000013720400 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.FENCE_2_CONFIG | |||
| Constant(s): | ||||
| Comments: | PAU Fence-on-error Enable. 0b1=enable | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.MISC.REGS.FENCE_2_CONFIGQ.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:63 | RW | RW | CONFIG_FENCE_2: Enable for FIR Register 2 | |
| PAU Interrupt-on-error Enable for FIR Register 2 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010BB1 (SCOM) 0000000013720408 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.INT_2_CONFIG | |||
| Constant(s): | ||||
| Comments: | PAU Interrupt-on-error Enable. 0b1=enable | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.MISC.REGS.INT_2_CONFIGQ.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:63 | RW | RW | CONFIG_INT_2: Enable for FIR Register 2 | |
| PAU Error Brick Group Register 1 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010BB2 (SCOM) 0000000013720410 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.ERROR_BRICK_GROUP_CONFIG1 | |||
| Constant(s): | ||||
| Comments: | PAU Error Brick Group for Freeze & Fence | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:59 | PAU3.MISC.REGS.ERROR_BRICK_GROUP_CONFIG1Q.LATC.L2(0:59) [000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:11 | RW | RW | CONFIG_ERR_GROUP_BRK5: Error brick group for brick 5 | |
| 12:23 | RW | RW | CONFIG_ERR_GROUP_BRK6: Error brick group for brick 6 | |
| 24:35 | RW | RW | CONFIG_ERR_GROUP_BRK7: Error brick group for brick 7 | |
| 36:47 | RW | RW | CONFIG_ERR_GROUP_BRK8: Error brick group for brick 8 | |
| 48:59 | RW | RW | CONFIG_ERR_GROUP_BRK9: Error brick group for brick 9 | |
| 60:63 | RO | RO | constant=0b0000 | |
| PAU Error Brick Group Register 2 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010BB3 (SCOM) 0000000013720418 (PAU_RING) | |||
| Name: | PAU3.MISC.REGS.ERROR_BRICK_GROUP_CONFIG2 | |||
| Constant(s): | ||||
| Comments: | PAU Error Brick Group for Freeze & Fence | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:23 | PAU3.MISC.REGS.ERROR_BRICK_GROUP_CONFIG2Q.LATC.L2(0:23) [000000000000000000000000] | |||
| Bit(s) | SCOM | PAU_RING | Dial: Description | |
| 0:11 | RW | RW | CONFIG_ERR_GROUP_BRK10: Error brick group for brick 10 | |
| 12:23 | RW | RW | CONFIG_ERR_GROUP_BRK11: Error brick group for brick 11 | |
| 24:63 | RO | RO | constant=0b0000000000000000000000000000000000000000 | |
| PAU FIR Register 0 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010C00 (SCOM) 0000000011010C01 (SCOM1) 0000000011010C02 (SCOM2) | |||
| Name: | PAU3.FIR_REG_0 | |||
| Constant(s): | ||||
| Comments: | Local FIR register for the PAU (1 of 3) | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.MISC.SCOMFIR.SAT20.PAR_OFF.LEM_FIR.LOCALFIR.FIR.FIR.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | SCOM1 | SCOM2 | Dial: Description |
| 0 | RWX | WOX_AND | WOX_OR | NTL_ARRAY_CE: NTL array CE |
| 1 | RWX | WOX_AND | WOX_OR | NTL_ARRAY_HDR_UE: NTL header array UE |
| 2 | RWX | WOX_AND | WOX_OR | NTL_ARRAY_DATA_UE: NTL data array UE |
| 3 | RWX | WOX_AND | WOX_OR | NTL_NVL_FLIT_PERR: NTL NVLInk Control/Header/AE Parity error |
| 4 | RWX | WOX_AND | WOX_OR | NTL_NVL_DATA_PERR: NTL NVLink Data Parity error |
| 5 | RWX | WOX_AND | WOX_OR | NTL_NVL_PKT_MALFOR: NTL NVLink Malformed Packet (illegal Cmd encode, etc.) |
| 6 | RWX | WOX_AND | WOX_OR | NTL_NVL_PKT_UNSUPPORTED: NTL NVLink Unsupported Packet (receiving DGD, receiving Atomic with unsupported DatLen, etc) |
| 7 | RWX | WOX_AND | WOX_OR | NTL_NVL_CONFIG_ERR: NTL NVLink Config errors (Credits received > max configured) |
| 8 | RWX | WOX_AND | WOX_OR | NTL_NVL_CRC_ERR: NTL NVLink CRC errors or LMD=Stomp |
| 9 | RWX | WOX_AND | WOX_OR | NTL_PRI_ERR: NTL PRI errors (errors returned by NDL Wrapper on PRI interface) |
| 10 | RWX | WOX_AND | WOX_OR | NTL_LOGIC_ERR: NTL logic error (overflow, underflow, etc) |
| 11 | RWX | WOX_AND | WOX_OR | NTL_LMD_POISON: NTL LMD=Data Poison |
| 12 | RWX | WOX_AND | WOX_OR | NTL_ARRAY_DATA_SUE: NTL data array SUE |
| 13 | RWX | WOX_AND | WOX_OR | CTL_ARRAY_CE: CQ CTL/SM ASBE Array single-bit correctable error |
| 14 | RWX | WOX_AND | WOX_OR | CTL_PBUS_RECOV_ERR: CQ CTL/SM PBR PowerBus Recoverable (ex: abort_trm CResp) |
| 15 | RWX | WOX_AND | WOX_OR | CTL_REG_RING_ERR: CQ CTL/SM REG Register ring error (ie noack) |
| 16 | RWX | WOX_AND | WOX_OR | CTL_MMIO_ST_DATA_UE: CQ CTL/SM DUE Data Uncorrectable error for MMIO store data |
| 17 | RWX | WOX_AND | WOX_OR | CTL_PEF: CQ CTL/SM UT=1 to frozen PE (for naples this was in AT as part of the PCT lookup). |
| 18 | RWX | WOX_AND | WOX_OR | CTL_NVL_CFG_ERR: CQ CTL/SM NCF NVLink configuration error (ex: Probe missed its GPUBAR) |
| 19 | RWX | WOX_AND | WOX_OR | CTL_NVL_FATAL_ERR: CQ CTL/SM NVF NVLink fatal (ex: rcv data resp to write req) |
| 20 | RWX | WOX_AND | WOX_OR | RESERVED_1: CQ CTL/SM OCR OpenCAPI Recoverable, Command failed (ex: SUE data to memory, a*_failed response to AFU, etc) and brick not fenced. |
| 21 | RWX | WOX_AND | WOX_OR | CTL_ARRAY_UE: CQ CTL/SM AUE Array uncorrectable error |
| 22 | RWX | WOX_AND | WOX_OR | CTL_PBUS_PERR: CQ CTL/SM PBP PowerBus parity error |
| 23 | RWX | WOX_AND | WOX_OR | CTL_PBUS_FATAL_ERR: CQ CTL/SM PBF PowerBus Fatal (ex: addr_error CResp) |
| 24 | RWX | WOX_AND | WOX_OR | CTL_PBUS_CONFIG_ERR: CQ CTL/SM PBC PowerBus configuration error (ex: group > 3) |
| 25 | RWX | WOX_AND | WOX_OR | CTL_FWD_PROGRESS_ERR: CQ CTL/SM FWD Forward-Progress (internal timer or rpt_hang.data) |
| 26 | RWX | WOX_AND | WOX_OR | CTL_LOGIC_ERR: CQ CTL/SM NLG PAU Logic error (ex: invalid state, missed table lookup, etc.) |
| 27 | RWX | WOX_AND | WOX_OR | CTL_RSVD_14: Cresp=Addr_Error received for a load command (PowerBus LD_cresp_addr_error) |
| 28 | RWX | WOX_AND | WOX_OR | CTL_RSVD_15: Cresp=Addr_Error received for a store command (PowerBus ST_cresp_addr_error) |
| 29 | RWX | WOX_AND | WOX_OR | DAT_DATA_BE_UE: CQ DAT ECC UE on data/BE arrays. Relevant word is marked with SUE |
| 30 | RWX | WOX_AND | WOX_OR | DAT_DATA_BE_CE: CQ DAT ECC CE on data/BE arrays |
| 31 | RWX | WOX_AND | WOX_OR | DAT_DATA_BE_PERR: CQ DAT parity error on data/BE latches. Relevant word is marked with SUE |
| 32 | RWX | WOX_AND | WOX_OR | DAT_CREG_PERR: CQ DAT parity errors on configuration registers |
| 33 | RWX | WOX_AND | WOX_OR | DAT_RTAG_PERR: CQ DAT parity errors on received PowerBus rtag |
| 34 | RWX | WOX_AND | WOX_OR | DAT_STATE_PERR: CQ DAT parity errors on internal state latches |
| 35 | RWX | WOX_AND | WOX_OR | DAT_LOGIC_ERR: CQ DAT logic error (invalid state bit patterns, credit overflow, etc.) |
| 36 | RWX | WOX_AND | WOX_OR | DAT_DATA_BE_SUE: CQ_DAT ECC SUE on data/BE arrays that can be due to poisoned data from GPU |
| 37 | RWX | WOX_AND | WOX_OR | DAT_PBRX_SUE: CQ_DAT ECC SUE on PB receive data (CANNOT be due to poisoned data from GPU) |
| 38 | RWX | WOX_AND | WOX_OR | DAT_RSVD_9: CQ DAT Reserved, macro bit 9 |
| 39 | RWX | WOX_AND | WOX_OR | DAT_RSVD_10: CQ DAT Reserved, macro bit 10 |
| 40 | RWX | WOX_AND | WOX_OR | XTS_INT: XTS internal logic error |
| 41 | RWX | WOX_AND | WOX_OR | XTS_SRAM_CE: XTS correctable errors in XTS internal SRAM |
| 42 | RWX | WOX_AND | WOX_OR | XTS_SRAM_UE: XTS uncorrectable errors in XTS internal SRAM |
| 43 | RWX | WOX_AND | WOX_OR | XTS_PROTOCOL_CE: XTS correctable error on incoming stack transactions |
| 44 | RWX | WOX_AND | WOX_OR | XTS_PROTOCOL_UE: XTS uncorrectable/protocol errors on incoming stack transaction |
| 45 | RWX | WOX_AND | WOX_OR | XTS_PBUS_PROTOCOL: XTS protocol errors on incoming PBUS transaction |
| 46 | RWX | WOX_AND | WOX_OR | XTS_RSVD_6: XTS Translate Request Fail |
| 47 | RWX | WOX_AND | WOX_OR | XTS_EARLY_HANG_WARN: XTS informational fir that is set when the snooper retries a rpt_hang.check or rpt_hang.poll command. |
| 48 | RWX | WOX_AND | WOX_OR | XTS_RSVD_8: XTS Reserved, macro bit 8 |
| 49 | RWX | WOX_AND | WOX_OR | XTS_RSVD_9: XTS Reserved, macro bit 9 |
| 50 | RWX | WOX_AND | WOX_OR | XTS_RSVD_10: XTS Reserved, macro bit 10 |
| 51 | RWX | WOX_AND | WOX_OR | XTS_RSVD_11: XTS Reserved, macro bit 11 |
| 52 | RWX | WOX_AND | WOX_OR | XTS_RSVD_12: XTS Reserved, macro bit 12 |
| 53 | RWX | WOX_AND | WOX_OR | XTS_RSVD_13: XTS Reserved, macro bit 13 |
| 54 | RWX | WOX_AND | WOX_OR | XTS_RSVD_14: XTS Reserved, macro bit 14 |
| 55 | RWX | WOX_AND | WOX_OR | XTS_RSVD_15: XTS Reserved, macro bit 15 |
| 56 | RWX | WOX_AND | WOX_OR | XTS_RSVD_16: XTS Reserved, macro bit 16 |
| 57 | RWX | WOX_AND | WOX_OR | XTS_RSVD_17: XTS Reserved, macro bit 17 |
| 58 | RWX | WOX_AND | WOX_OR | XTS_RSVD_18: XTS Reserved, macro bit 18 |
| 59 | RWX | WOX_AND | WOX_OR | AME_RSVD_INT: AME Reserved, interrupt |
| 60 | RWX | WOX_AND | WOX_OR | AME_RSVD_0: AME data ECC UE |
| 61 | RWX | WOX_AND | WOX_OR | AME_RSVD_1: AME data SUE |
| 62 | RWX | WOX_AND | WOX_OR | FIR0_RSVD_62: Unused FIR |
| 63 | RWX | WOX_AND | WOX_OR | FIR0_RSVD_63: Unused FIR |
| PAU FIR Mask Register 0 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010C03 (SCOM) 0000000011010C04 (SCOM1) 0000000011010C05 (SCOM2) | |||
| Name: | PAU3.FIR_MASK_REG_0 | |||
| Constant(s): | ||||
| Comments: | Mask Select for the FIR bits | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.MISC.SCOMFIR.SAT20.PAR_OFF.LEM_FIR.LOCALFIR.FIR.FIR_MASK.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | SCOM1 | SCOM2 | Dial: Description |
| 0:63 | RW | WO_AND | WO_OR | FIR_MASK_0: Mask select for corresponding bit in FIR (Action0, Action1, Mask) = Action Select (0,0,0) = Checkstop Error (0,1,0) = Recoverable Error (1,0,0) = Not Used (1,1,0) = Local Core Checkstop / GX freeze (x,x,1) = MASKED |
| PAU FIR Action 0 Register 0 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010C06 (SCOM) | |||
| Name: | PAU3.FIR_ACTION0_REG_0 | |||
| Constant(s): | ||||
| Comments: | Action Select for the FIR bits | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.MISC.SCOMFIR.SAT20.PAR_OFF.LEM_FIR.LOCALFIR.FIR.DO_ACTION0.FIR_ACTION0.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:63 | RW | FIR_ACTION0_0: MSB of action select for corresponding bit in FIR (Action0, Action1, Mask) = Action Select (0,0,0) = Checkstop Error (0,1,0) = Recoverable Error (1,0,0) = Not Used (1,1,0) = Local Core Checkstop / GX freeze (x,x,1) = MASKED | ||
| PAU FIR Action 1 Register 0 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010C07 (SCOM) | |||
| Name: | PAU3.FIR_ACTION1_REG_0 | |||
| Constant(s): | ||||
| Comments: | Action Select for the FIR bits | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.MISC.SCOMFIR.SAT20.PAR_OFF.LEM_FIR.LOCALFIR.FIR.DO_ACTION1.FIR_ACTION1.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:63 | RW | FIR_ACTION1_0: MSB of action select for corresponding bit in FIR (Action0, Action1, Mask) = Action Select (0,0,0) = Checkstop Error (0,1,0) = Recoverable Error (1,0,0) = Not Used (1,1,0) = Local Core Checkstop / GX freeze (x,x,1) = MASKED | ||
| Secure Memory Facility Configuration Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011010C0A (SCOM) | |||
| Name: | PAU3.SMF_CONFIG_REG_0 | |||
| Constant(s): | ||||
| Comments: | Secure Memory Facility Configuration Register bits, SCOM-only | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:1 | PAU3.MISC.SCOMFIR.SMF_CONFIG_REGQ.LATC.L2(0:1) [00] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:1 | RW | SMF_CONFIG0: Secure Memory Facility Configuration 00 = SMF Disabled 01 = Reserved 10 = SMF Enabled but PAU is not in secure space. Ignore BAR Secure Memory bit. Prevent mastering RA(15)=1. 11 = SMF Enabled and PAU is in secure space. GPU/AFU Memory BAR can specify secure AFU memeory. | ||
| 2:63 | RO | constant=0b00000000000000000000000000000000000000000000000000000000000000 | ||
| PAU FIR Register 1 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010C40 (SCOM) 0000000011010C41 (SCOM1) 0000000011010C42 (SCOM2) | |||
| Name: | PAU3.FIR_REG_1 | |||
| Constant(s): | ||||
| Comments: | Local FIR register for the PAU (2 of 3) | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.MISC.SCOMFIR.SAT21.PAR_OFF.LEM_FIR.LOCALFIR.FIR.FIR.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | SCOM1 | SCOM2 | Dial: Description |
| 0 | RWX | WOX_AND | WOX_OR | NDL_BRK0_STALL: NDL Brick0 stall |
| 1 | RWX | WOX_AND | WOX_OR | NDL_BRK0_NOSTALL: NDL Brick0 nostall |
| 2 | RWX | WOX_AND | WOX_OR | NDL_BRK1_STALL: NDL Brick1 stall |
| 3 | RWX | WOX_AND | WOX_OR | NDL_BRK1_NOSTALL: NDL Brick1 nostall |
| 4 | RWX | WOX_AND | WOX_OR | NDL_BRK2_STALL: NDL Brick2 stall |
| 5 | RWX | WOX_AND | WOX_OR | NDL_BRK2_NOSTALL: NDL Brick2 nostall |
| 6 | RWX | WOX_AND | WOX_OR | NDL_BRK3_STALL: NDL Brick3 stall |
| 7 | RWX | WOX_AND | WOX_OR | NDL_BRK3_NOSTALL: NDL Brick3 nostall |
| 8 | RWX | WOX_AND | WOX_OR | NDL_BRK4_STALL: NDL Brick4 stall |
| 9 | RWX | WOX_AND | WOX_OR | NDL_BRK4_NOSTALL: NDL Brick4 nostall |
| 10 | RWX | WOX_AND | WOX_OR | NDL_BRK5_STALL: NDL Brick5 stall |
| 11 | RWX | WOX_AND | WOX_OR | NDL_BRK5_NOSTALL: NDL Brick5 nostall |
| 12 | RWX | WOX_AND | WOX_OR | MISC_REG_RING_ERR: MISC Register ring error (noack, >1 ack) |
| 13 | RWX | WOX_AND | WOX_OR | MISC_INT_RA_PERR: MISC Parity error from interrupt base real address register |
| 14 | RWX | WOX_AND | WOX_OR | MISC_DA_ADDR_PERR: MISC Parity error on Indirect SCOM Address register |
| 15 | RWX | WOX_AND | WOX_OR | MISC_CTRL_PERR: MISC Parity error on MISC Control register |
| 16 | RWX | WOX_AND | WOX_OR | FIR1_RSVD_16: FIR1 Reserved, bit 16 |
| 17 | RWX | WOX_AND | WOX_OR | ATS_TVT_ENTRY_INVALID: ATS Invalid TVT entry (TCE Table Size = 0b00000) |
| 18 | RWX | WOX_AND | WOX_OR | ATS_TVT_ADDR_RANGE_ERR: ATS TVT Address range error (no xlate: EA out of range; xlate: unused EA bits non-zero, TVE uses > max # EA bits) |
| 19 | RWX | WOX_AND | WOX_OR | ATS_TCE_PAGE_ACCESS_CA_ERR: ATS TCE Page access error during TCE cache lookup |
| 20 | RWX | WOX_AND | WOX_OR | ATS_TCE_CACHE_MULT_HIT_ERR: ATS Effective Address hit multiple TCE cache entries |
| 21 | RWX | WOX_AND | WOX_OR | ATS_TCE_PAGE_ACCESS_TW_ERR: ATS TCE Page access error during TCE table-walk |
| 22 | RWX | WOX_AND | WOX_OR | ATS_TCE_REQ_TO_ERR: ATS Timeout on TCE tree walk |
| 23 | RWX | WOX_AND | WOX_OR | ATS_TCD_PERR: ATS Parity error on TCE cache directory array |
| 24 | RWX | WOX_AND | WOX_OR | ATS_TDR_PERR: ATS Parity error on TCE cache data array |
| 25 | RWX | WOX_AND | WOX_OR | ATS_AT_EA_UE: ATS ECC UE on Effective Address array |
| 26 | RWX | WOX_AND | WOX_OR | ATS_AT_EA_CE: ATS ECC CE on Effective Address array |
| 27 | RWX | WOX_AND | WOX_OR | ATS_AT_TDRMEM_UE: ATS ECC UE on TDRmem array (table-walk state machine also hangs) |
| 28 | RWX | WOX_AND | WOX_OR | ATS_AT_TDRMEM_CE: ATS ECC CE on TDRmem array |
| 29 | RWX | WOX_AND | WOX_OR | ATS_AT_RSPOUT_UE: ATS ECC UE on CQ CTL DMA Read data to TDR_mem array during table-walk |
| 30 | RWX | WOX_AND | WOX_OR | ATS_AT_RSPOUT_CE: ATS ECC CE on CQ CTL DMA Read data to TDR_mem array during table-walk |
| 31 | RWX | WOX_AND | WOX_OR | ATS_TVT_PERR: ATS Parity error on TVT entry |
| 32 | RWX | WOX_AND | WOX_OR | ATS_IODA_ADDR_PERR: ATS Parity error on IODA Address Register |
| 33 | RWX | WOX_AND | WOX_OR | ATS_PAU_CTRL_PERR: ATS Parity error on ATS Control Register |
| 34 | RWX | WOX_AND | WOX_OR | ATS_PAU_TOR_PERR: ATS Parity error on ATS Timeout Control register |
| 35 | RWX | WOX_AND | WOX_OR | ATS_INVAL_IODA_TBL_SEL: ATS Invalid IODA Table Address Register Table Select entry |
| 36 | RWX | WOX_AND | WOX_OR | ATS_RSVD_19: ATS Reserved, macro bit 19 |
| 37 | RWX | WOX_AND | WOX_OR | XSL_KILL_XLATE_EPOCH_TIMEOUT: kill xlate epoch timeout. |
| 38 | RWX | WOX_AND | WOX_OR | XSL_RSVD_19: XSL Reserved, macro bit 19. |
| 39 | RWX | WOX_AND | WOX_OR | XSL_RSVD_20: XSL Reserved, macro bit 20. |
| 40 | RWX | WOX_AND | WOX_OR | XSL_RSVD_21: XSL Reserved, macro bit 21. |
| 41 | RWX | WOX_AND | WOX_OR | XSL_RSVD_22: XSL Reserved, macro bit 22. |
| 42 | RWX | WOX_AND | WOX_OR | XSL_RSVD_23: XSL Reserved, macro bit 23. |
| 43 | RWX | WOX_AND | WOX_OR | XSL_RSVD_24: XSL Reserved, macro bit 24. |
| 44 | RWX | WOX_AND | WOX_OR | XSL_RSVD_25: XSL Reserved, macro bit 25. |
| 45 | RWX | WOX_AND | WOX_OR | XSL_RSVD_26: XSL Reserved, macro bit 26. |
| 46 | RWX | WOX_AND | WOX_OR | XSL_RSVD_27: XSL Reserved, macro bit 27. |
| 47 | RWX | WOX_AND | WOX_OR | NDL_BRK6_STALL: NDL Brick6 stall |
| 48 | RWX | WOX_AND | WOX_OR | NDL_BRK6_NOSTALL: NDL Brick6 nostall |
| 49 | RWX | WOX_AND | WOX_OR | NDL_BRK7_STALL: NDL Brick7 stall |
| 50 | RWX | WOX_AND | WOX_OR | NDL_BRK7_NOSTALL: NDL Brick7 nostall |
| 51 | RWX | WOX_AND | WOX_OR | NDL_BRK8_STALL: NDL Brick8 stall |
| 52 | RWX | WOX_AND | WOX_OR | NDL_BRK8_NOSTALL: NDL Brick8 nostall |
| 53 | RWX | WOX_AND | WOX_OR | NDL_BRK9_STALL: NDL Brick9 stall |
| 54 | RWX | WOX_AND | WOX_OR | NDL_BRK9_NOSTALL: NDL Brick9 nostall |
| 55 | RWX | WOX_AND | WOX_OR | NDL_BRK10_STALL: NDL Brick10 stall |
| 56 | RWX | WOX_AND | WOX_OR | NDL_BRK10_NOSTALL: NDL Brick10 nostall |
| 57 | RWX | WOX_AND | WOX_OR | NDL_BRK11_STALL: NDL Brick11 stall |
| 58 | RWX | WOX_AND | WOX_OR | NDL_BRK11_NOSTALL: NDL Brick11 nostall |
| 59 | RWX | WOX_AND | WOX_OR | AME_RSVD_2: AME ECC CE |
| 60 | RWX | WOX_AND | WOX_OR | SCOMSAT00_ERR: MISC Pervasive SCOM satellite signaled internal FSM error (ring 0, sat 0) |
| 61 | RWX | WOX_AND | WOX_OR | SCOMSAT01_ERR: MISC Pervasive SCOM satellite signaled internal FSM error (ring 0, sat 1) |
| 62 | RWX | WOX_AND | WOX_OR | FIR1_RSVD_62: Unused FIR |
| 63 | RWX | WOX_AND | WOX_OR | FIR1_RSVD_63: Unused FIR |
| PAU FIR Mask Register 1 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010C43 (SCOM) 0000000011010C44 (SCOM1) 0000000011010C45 (SCOM2) | |||
| Name: | PAU3.FIR_MASK_REG_1 | |||
| Constant(s): | ||||
| Comments: | Mask Select for the FIR bits | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.MISC.SCOMFIR.SAT21.PAR_OFF.LEM_FIR.LOCALFIR.FIR.FIR_MASK.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | SCOM1 | SCOM2 | Dial: Description |
| 0:63 | RW | WO_AND | WO_OR | FIR_MASK_1: Mask select for corresponding bit in FIR (Action0, Action1, Mask) = Action Select (0,0,0) = Checkstop Error (0,1,0) = Recoverable Error (1,0,0) = Not Used (1,1,0) = Local Core Checkstop / GX freeze (x,x,1) = MASKED |
| PAU FIR Action 0 Register 1 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010C46 (SCOM) | |||
| Name: | PAU3.FIR_ACTION0_REG_1 | |||
| Constant(s): | ||||
| Comments: | Action Select for the FIR bits | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.MISC.SCOMFIR.SAT21.PAR_OFF.LEM_FIR.LOCALFIR.FIR.DO_ACTION0.FIR_ACTION0.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:63 | RW | FIR_ACTION0_1: MSB of action select for corresponding bit in FIR (Action0, Action1, Mask) = Action Select (0,0,0) = Checkstop Error (0,1,0) = Recoverable Error (1,0,0) = Not Used (1,1,0) = Local Core Checkstop / GX freeze (x,x,1) = MASKED | ||
| PAU FIR Action 1 Register 1 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010C47 (SCOM) | |||
| Name: | PAU3.FIR_ACTION1_REG_1 | |||
| Constant(s): | ||||
| Comments: | Action Select for the FIR bits | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.MISC.SCOMFIR.SAT21.PAR_OFF.LEM_FIR.LOCALFIR.FIR.DO_ACTION1.FIR_ACTION1.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:63 | RW | FIR_ACTION1_1: MSB of action select for corresponding bit in FIR (Action0, Action1, Mask) = Action Select (0,0,0) = Checkstop Error (0,1,0) = Recoverable Error (1,0,0) = Not Used (1,1,0) = Local Core Checkstop / GX freeze (x,x,1) = MASKED | ||
| PAU FIR Register 2 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010C80 (SCOM) 0000000011010C81 (SCOM1) 0000000011010C82 (SCOM2) | |||
| Name: | PAU3.FIR_REG_2 | |||
| Constant(s): | ||||
| Comments: | Local FIR register for the PAU (3 of 3) | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.MISC.SCOMFIR.SAT22.PAR_OFF.LEM_FIR.LOCALFIR.FIR.FIR.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | SCOM1 | SCOM2 | Dial: Description |
| 0 | RWX | WOX_AND | WOX_OR | OTL_BRK2_XLAT_FAULT: OTL Brick2 translation fault |
| 1 | RWX | WOX_AND | WOX_OR | OTL_BRK3_XLAT_FAULT: OTL Brick3 translation fault |
| 2 | RWX | WOX_AND | WOX_OR | OTL_BRK4_XLAT_FAULT: OTL Brick4 translation fault |
| 3 | RWX | WOX_AND | WOX_OR | OTL_BRK5_XLAT_FAULT: OTL Brick5 translation fault |
| 4 | RWX | WOX_AND | WOX_OR | OTL_TL_CRD_OVF: OTL TL credit counter overflow caused by return_tl_credits. |
| 5 | RWX | WOX_AND | WOX_OR | OTL_RXI_ACTAG_IDX: OTL RX acTag specified in a command is outside the configured specification set. |
| 6 | RWX | WOX_AND | WOX_OR | OTL_RXI_ACTAG_INV: OTL RX acTag specified in the command points to an invalid entry. |
| 7 | RWX | WOX_AND | WOX_OR | OTL_RXI_OPC_RSVD: OTL RX reserved opcode used. |
| 8 | RWX | WOX_AND | WOX_OR | OTL_RXI_RTC_POS: OTL RX return_tl_credit command found outside slot0. |
| 9 | RWX | WOX_AND | WOX_OR | OTL_RXI_TMPL: OTL RX bad opcode and template combination. |
| 10 | RWX | WOX_AND | WOX_OR | OTL_RXI_TMPL_UNS: OTL RX unsupported template format. |
| 11 | RWX | WOX_AND | WOX_OR | OTL_RXI_TMPL_X00: OTL RX bad template x00 format. |
| 12 | RWX | WOX_AND | WOX_OR | OTL_RXI_CTLFLIT_OVERRUN: OTL RX control flit overrun. |
| 13 | RWX | WOX_AND | WOX_OR | OTL_RXI_UNEXPECTED_DATA_FLIT: OTL RX unexpected data flit. |
| 14 | RWX | WOX_AND | WOX_OR | OTL_RXI_LINK_DOWN: OTL RX DL link down. |
| 15 | RWX | WOX_AND | WOX_OR | OTL_RXI_BAD_DATA_RECEIVED_CMD: OTL RX bad data received on command. |
| 16 | RWX | WOX_AND | WOX_OR | OTL_RXI_BAD_DATA_RECEIVED_RESP_RXI_BAD_DATA_RECEIVED_RESP: OTL RX bad data received on response. |
| 17 | RWX | WOX_AND | WOX_OR | OTL_RXI_RESPONSE_NOT_ALLOWED: OTL RX AP response not allowed (CAPPTag not recognized). |
| 18 | RWX | WOX_AND | WOX_OR | OTL_PERR: OR of all OTL parity errors. |
| 19 | RWX | WOX_AND | WOX_OR | OTL_CE: OR of all OTL ECC CE errors. |
| 20 | RWX | WOX_AND | WOX_OR | OTL_UE: OR of all OTL ECC UE errors. |
| 21 | RWX | WOX_AND | WOX_OR | OTL_RXO_OP_ERRORS: RXO OP Errors. |
| 22 | RWX | WOX_AND | WOX_OR | OTL_RXO_INTERNAL_ERRORS: RXO Internal Errors. |
| 23 | RWX | WOX_AND | WOX_OR | OTL_RXI_FIFO_OVERRUN: OTL RXI fifo overrun. |
| 24 | RWX | WOX_AND | WOX_OR | OTL_RXI_CNTL_FLIT_DATA_RUN_LENGTH_INV: OTL RXI control flit data run length invalid. |
| 25 | RWX | WOX_AND | WOX_OR | OTL_RXI_OPCODE_UTIL_DL_EQ_ZERO: OTL RXI opcode utilizing dLength specifies dL=0b00 or other invalid dL (hw539630). |
| 26 | RWX | WOX_AND | WOX_OR | OTL_RXI_BAD_DATA_RECEIVED_VC2: OTL RXI bad data received vc2. |
| 27 | RWX | WOX_AND | WOX_OR | OTL_RXI_DCP2FIFO_OVERRUN: OTL RXI dcp2 fifo overrun. |
| 28 | RWX | WOX_AND | WOX_OR | OTL_RXI_VC1FIFO_OVERRUN: OTL RXI vc1 fifo overrun. |
| 29 | RWX | WOX_AND | WOX_OR | OTL_RXI_VC2FIFO_OVERRUN: OTL RXI vc2 fifo overrun. |
| 30 | RWX | WOX_AND | WOX_OR | OTL_DATA_LENGTH_UNSUPPORTED: Opcode data length not supported. |
| 31 | RWX | WOX_AND | WOX_OR | TXI_OPCODE_ERROR: OTL TXI opcode error. |
| 32 | RWX | WOX_AND | WOX_OR | RXI_MALFORMED_PACKET_TYPE4: malformed packet error type 4 (rxi_misc_error_fieldrsvdne0_tlvc2). |
| 33 | RWX | WOX_AND | WOX_OR | HAPPI_NO_BAR_MATCH: OTL Happi no bar match |
| 34 | RWX | WOX_AND | WOX_OR | OTL_RSVD_30: OTL Reserved, macro bit 30. |
| 35 | RWX | WOX_AND | WOX_OR | OTL_RSVD_31: OTL Reserved, macro bit 31. |
| 36 | RWX | WOX_AND | WOX_OR | XSL_MMIO_INVALIDATE_REQ_WHILE_1_INPROG: MMIO invalidate requested while one is in progress. |
| 37 | RWX | WOX_AND | WOX_OR | XSL_UNEXPECTED_ITAG_PORT_0: Unexpected ITAG returned on itag completion port 0. |
| 38 | RWX | WOX_AND | WOX_OR | XSL_UNEXPECTED_ITAG_PORT_1: Unexpected ITAG returned on itag completion port 1. |
| 39 | RWX | WOX_AND | WOX_OR | XSL_UNEXPECTED_RD_PEE_COMPLETION: Unexpected Read PEE completion. |
| 40 | RWX | WOX_AND | WOX_OR | XSL_UNEXPECTED_CO_RESP: Unexpected Checkout response. |
| 41 | RWX | WOX_AND | WOX_OR | XSL_XLAT_REQ_WHILE_SPAP_INVALID: Translation request while SPAP is invalid. |
| 42 | RWX | WOX_AND | WOX_OR | XSL_INVALID_PEE: Read a PEE which was not valid. |
| 43 | RWX | WOX_AND | WOX_OR | XSL_BLOOM_FILTER_PROTECT_ERR: Bloom filter protection error. |
| 44 | RWX | WOX_AND | WOX_OR | XSL_NEW_ITAG_MATCHING_ACTIVE_ECOE: Translation request to non-valid TA. |
| 45 | RWX | WOX_AND | WOX_OR | XSL_TA_XLAT_REQ_TO_AN_INVALID_TA: TA Translation request to an invalid TA. |
| 46 | RWX | WOX_AND | WOX_OR | XSL_CE: correctable array error (SBE). |
| 47 | RWX | WOX_AND | WOX_OR | XSL_UE: uncorrectable array error (UE or parity). |
| 48 | RWX | WOX_AND | WOX_OR | XSL_SLBI_TLBI_BUFF_OVERFLOW: S/TLBI buffer overflow. |
| 49 | RWX | WOX_AND | WOX_OR | XSL_SBE_CORR_ERR_PB_CHKOUT_RSP_DATA: SBE correctable error on Powerbus checkout response data or Powerbus PEE read data. |
| 50 | RWX | WOX_AND | WOX_OR | XSL_UE_PB_CHKOUT_RSP_DATA: UE uncorrectable error on Powerbus checkout response data or Powerbus PEE read data. |
| 51 | RWX | WOX_AND | WOX_OR | XSL_SUE_PB_CHKOUT_RSP_DATA: SUE error on Powerbus checkout response data or Powerbus PEE read data. |
| 52 | RWX | WOX_AND | WOX_OR | XSL_NONZERO_BAR_MODE_PA_MEM_HIT: PA mem_hit when bar mode is nonzero . |
| 53 | RWX | WOX_AND | WOX_OR | XSL_RSVD_17: XSL Reserved, macro bit 17. |
| 54 | RWX | WOX_AND | WOX_OR | OTL_BRK0_XLAT_FAULT: OTL Brick0 translation fault |
| 55 | RWX | WOX_AND | WOX_OR | OTL_BRK1_XLAT_FAULT: OTL Brick1 translation fault |
| 56 | RWX | WOX_AND | WOX_OR | AME_RSVD_3: AME ECC UE on control information or state bit errors that are contained within AME and ATL |
| 57 | RWX | WOX_AND | WOX_OR | AME_RSVD_4: AME ECC UE on control information or state bit errors that can affect correctness of external logic such as XSL castout |
| 58 | RWX | WOX_AND | WOX_OR | AME_RSVD_5: AME Logic errors that are contained within AME and ATL |
| 59 | RWX | WOX_AND | WOX_OR | AME_RSVD_6: AME Logic errors that can affect correctness of external logic such as XSL castout |
| 60 | RWX | WOX_AND | WOX_OR | AME_RSVD_7: AME firmware-detected fatal error conditions |
| 61 | RWX | WOX_AND | WOX_OR | AME_RSVD_8: AME Reserved |
| 62 | RWX | WOX_AND | WOX_OR | FIR2_RSVD_62: Unused FIR |
| 63 | RWX | WOX_AND | WOX_OR | FIR2_RSVD_63: Unused FIR |
| PAU FIR Mask Register 2 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010C83 (SCOM) 0000000011010C84 (SCOM1) 0000000011010C85 (SCOM2) | |||
| Name: | PAU3.FIR_MASK_REG_2 | |||
| Constant(s): | ||||
| Comments: | Mask Select for the FIR bits | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.MISC.SCOMFIR.SAT22.PAR_OFF.LEM_FIR.LOCALFIR.FIR.FIR_MASK.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | SCOM1 | SCOM2 | Dial: Description |
| 0:63 | RW | WO_AND | WO_OR | FIR_MASK_2: Mask select for corresponding bit in FIR (Action0, Action1, Mask) = Action Select (0,0,0) = Checkstop Error (0,1,0) = Recoverable Error (1,0,0) = Not Used (1,1,0) = Local Core Checkstop / GX freeze (x,x,1) = MASKED |
| PAU FIR Action 0 Register 2 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010C86 (SCOM) | |||
| Name: | PAU3.FIR_ACTION0_REG_2 | |||
| Constant(s): | ||||
| Comments: | Action Select for the FIR bits | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.MISC.SCOMFIR.SAT22.PAR_OFF.LEM_FIR.LOCALFIR.FIR.DO_ACTION0.FIR_ACTION0.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:63 | RW | FIR_ACTION0_2: MSB of action select for corresponding bit in FIR (Action0, Action1, Mask) = Action Select (0,0,0) = Checkstop Error (0,1,0) = Recoverable Error (1,0,0) = Not Used (1,1,0) = Local Core Checkstop / GX freeze (x,x,1) = MASKED | ||
| PAU FIR Action 1 Register 2 | ||||
|---|---|---|---|---|
| Addr: |
0000000011010C87 (SCOM) | |||
| Name: | PAU3.FIR_ACTION1_REG_2 | |||
| Constant(s): | ||||
| Comments: | Action Select for the FIR bits | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PAU3.MISC.SCOMFIR.SAT22.PAR_OFF.LEM_FIR.LOCALFIR.FIR.DO_ACTION1.FIR_ACTION1.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:63 | RW | FIR_ACTION1_2: MSB of action select for corresponding bit in FIR (Action0, Action1, Mask) = Action Select (0,0,0) = Checkstop Error (0,1,0) = Recoverable Error (1,0,0) = Not Used (1,1,0) = Local Core Checkstop / GX freeze (x,x,1) = MASKED | ||
| PowerBus Transaction Layer FIR0 register | ||||
|---|---|---|---|---|
| Addr: |
0000000011011800 (SCOM) 0000000011011801 (SCOM1) 0000000011011802 (SCOM2) | |||
| Name: | PB.PTLSCOM23.PB_PTL_FIR_REG | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:39 | PB.PTLSCOM23.FIR.PAR_OFF.LEM_FIR.LOCALFIR.FIR.FIR.LATC.L2(0:39) [0000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | SCOM1 | SCOM2 | Dial: Description |
| 0 | RWX | WOX_AND | WOX_OR | FMR00_TRAINED: fmr00 trained. Even PTL, even half. |
| 1 | RWX | WOX_AND | WOX_OR | FMR01_TRAINED: fmr01 trained. Even PTL, odd half. |
| 2 | RWX | WOX_AND | WOX_OR | FMR02_TRAINED: fmr02 trained. Odd PTL, even half. |
| 3 | RWX | WOX_AND | WOX_OR | FMR03_TRAINED: fmr03 trained. Odd PTL, odd half. |
| 4 | RWX | WOX_AND | WOX_OR | DOB01_UE: dob01 ue |
| 5 | RWX | WOX_AND | WOX_OR | DOB01_CE: dob01 ce |
| 6 | RWX | WOX_AND | WOX_OR | DOB01_SUE: dob01 sue |
| 7 | RWX | WOX_AND | WOX_OR | DOB01_ERR: data outbound switch internal error - even PTL. |
| 8 | RWX | WOX_AND | WOX_OR | DOB23_UE: dob23 ue |
| 9 | RWX | WOX_AND | WOX_OR | DOB23_CE: dob23 ce |
| 10 | RWX | WOX_AND | WOX_OR | DOB23_SUE: dob23 sue |
| 11 | RWX | WOX_AND | WOX_OR | DOB23_ERR: data outbound switch internal error - odd PTL. |
| 12 | RWX | WOX_AND | WOX_OR | FRAMER00_ATTN: Even PTL, even framer internal error |
| 13 | RWX | WOX_AND | WOX_OR | CROB01_ATTN: Even PTL, outbound switch cmd/presp/cresp internal error |
| 14 | RWX | WOX_AND | WOX_OR | FRAMER01_ATTN: Even PTL, odd framer internal error |
| 15 | RWX | WOX_AND | WOX_OR | FRAMER02_ATTN: Odd PTL, even framer internal error |
| 16 | RWX | WOX_AND | WOX_OR | CROB23_ATTN: Odd PTL, outbound switch cmd/presp/cresp internal error |
| 17 | RWX | WOX_AND | WOX_OR | FRAMER03_ATTN: Odd PTL, odd framer internal error |
| 18 | RWX | WOX_AND | WOX_OR | PARSER00_ATTN: Even PTL, even parser internal error |
| 19 | RWX | WOX_AND | WOX_OR | PARSER01_ATTN: Even PTL, odd parser internal error |
| 20 | RWX | WOX_AND | WOX_OR | PARSER02_ATTN: Odd PTL, even parser internal error |
| 21 | RWX | WOX_AND | WOX_OR | PARSER03_ATTN: Odd PTL, odd parser internal error |
| 22 | RWX | WOX_AND | WOX_OR | LINK_DOWN_0_ATTN: Even PTL, even link down |
| 23 | RWX | WOX_AND | WOX_OR | LINK_DOWN_1_ATTN: Even PTL, odd link down |
| 24 | RWX | WOX_AND | WOX_OR | LINK_DOWN_2_ATTN: Odd PTL, even link down |
| 25 | RWX | WOX_AND | WOX_OR | LINK_DOWN_3_ATTN: Odd PTL, odd link down |
| 26 | RWX | WOX_AND | WOX_OR | DIB01_ERR: Even PTL data inbound switch internal error |
| 27 | RWX | WOX_AND | WOX_OR | DIB23_ERR: Odd PTL data inbound switch internal error |
| 28 | RWX | WOX_AND | WOX_OR | MB00_SPATTN: mailbox 00 special attention. Gets set to 1 when a remote chip writes PB_MAILBOX_00_REG. |
| 29 | RWX | WOX_AND | WOX_OR | MB01_SPATTN: mailbox 01 special attention. Gets set to 1 when a remote chip writes PB_MAILBOX_01_REG. |
| 30 | RWX | WOX_AND | WOX_OR | MB10_SPATTN: mailbox 10 special attention. Gets set to 1 when a remote chip writes PB_MAILBOX_10_REG. |
| 31 | RWX | WOX_AND | WOX_OR | MB11_SPATTN: mailbox 11 special attention. Gets set to 1 when a remote chip writes PB_MAILBOX_11_REG. |
| 32 | RWX | WOX_AND | WOX_OR | MB20_SPATTN: mailbox 20 special attention. Gets set to 1 when a remote chip writes PB_MAILBOX_20_REG. |
| 33 | RWX | WOX_AND | WOX_OR | MB21_SPATTN: mailbox 21 special attention. Gets set to 1 when a remote chip writes PB_MAILBOX_21_REG. |
| 34 | RWX | WOX_AND | WOX_OR | MB30_SPATTN: mailbox 30 special attention. Gets set to 1 when a remote chip writes PB_MAILBOX_30_REG. |
| 35 | RWX | WOX_AND | WOX_OR | MB31_SPATTN: mailbox 31 special attention. Gets set to 1 when a remote chip writes PB_MAILBOX_31_REG. |
| 36 | RWX | WOX_AND | WOX_OR | PTL0_SPARE: ptl0 spare |
| 37 | RWX | WOX_AND | WOX_OR | PTL1_SPARE: ptl1 spare |
| 38 | RWX | WOX_AND | WOX_OR | PTL2_SPARE: ptl2 spare |
| 39 | RWX | WOX_AND | WOX_OR | PTL3_SPARE: ptl3 spare |
| PowerBus Transaction Layer FIR0 Mask Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011011803 (SCOM) 0000000011011804 (SCOM1) 0000000011011805 (SCOM2) | |||
| Name: | PB.PTLSCOM23.PB_PTL_FIR_MASK_REG | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:39 | PB.PTLSCOM23.FIR.PAR_OFF.LEM_FIR.LOCALFIR.FIR.FIR_MASK.LATC.L2(0:39) [0000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | SCOM1 | SCOM2 | Dial: Description |
| 0 | RWX | WOX_AND | WOX_OR | FMR00_TRAINED_MASK: fmr00 trained mask |
| 1 | RWX | WOX_AND | WOX_OR | FMR01_TRAINED_MASK: fmr01 trained mask |
| 2 | RWX | WOX_AND | WOX_OR | FMR02_TRAINED_MASK: fmr02 trained mask |
| 3 | RWX | WOX_AND | WOX_OR | FMR03_TRAINED_MASK: fmr03 trained mask |
| 4 | RWX | WOX_AND | WOX_OR | DOB01_UE_MASK: dob01 ue mask |
| 5 | RWX | WOX_AND | WOX_OR | DOB01_CE_MASK: dob01 ce mask |
| 6 | RWX | WOX_AND | WOX_OR | DOB01_SUE_MASK: dob01 sue mask |
| 7 | RWX | WOX_AND | WOX_OR | DOB01_ERR_MASK: dob01 err mask |
| 8 | RWX | WOX_AND | WOX_OR | DOB23_UE_MASK: dob23 ue mask |
| 9 | RWX | WOX_AND | WOX_OR | DOB23_CE_MASK: dob23 ce mask |
| 10 | RWX | WOX_AND | WOX_OR | DOB23_SUE_MASK: dob23 sue mask |
| 11 | RWX | WOX_AND | WOX_OR | DOB23_ERR_MASK: dob23 err mask |
| 12 | RWX | WOX_AND | WOX_OR | FRAMER00_ATTN_MASK: framer00 attn mask |
| 13 | RWX | WOX_AND | WOX_OR | CROB01_ATTN_MASK: crob01 attn mask |
| 14 | RWX | WOX_AND | WOX_OR | FRAMER01_ATTN_MASK: framer01 attn mask |
| 15 | RWX | WOX_AND | WOX_OR | FRAMER02_ATTN_MASK: framer02 attn mask |
| 16 | RWX | WOX_AND | WOX_OR | CROB23_ATTN_MASK: crob23 attn mask |
| 17 | RWX | WOX_AND | WOX_OR | FRAMER03_ATTN_MASK: framer03 attn mask |
| 18 | RWX | WOX_AND | WOX_OR | PARSER00_ATTN_MASK: parser00 attn mask |
| 19 | RWX | WOX_AND | WOX_OR | PARSER01_ATTN_MASK: parser01 attn mask |
| 20 | RWX | WOX_AND | WOX_OR | PARSER02_ATTN_MASK: parser02 attn mask |
| 21 | RWX | WOX_AND | WOX_OR | PARSER03_ATTN_MASK: parser03 attn mask |
| 22 | RWX | WOX_AND | WOX_OR | LINK_DOWN_0_ATTN_MASK: link down 0 attn mask |
| 23 | RWX | WOX_AND | WOX_OR | LINK_DOWN_1_ATTN_MASK: link down 1 attn mask |
| 24 | RWX | WOX_AND | WOX_OR | LINK_DOWN_2_ATTN_MASK: link down 2 attn mask |
| 25 | RWX | WOX_AND | WOX_OR | LINK_DOWN_3_ATTN_MASK: link down 3 attn |
| 26 | RWX | WOX_AND | WOX_OR | DIB01_ERR_MASK: dib01 err mask |
| 27 | RWX | WOX_AND | WOX_OR | DIB23_ERR_MASK: dib23 err mask |
| 28 | RWX | WOX_AND | WOX_OR | MB00_SPATTN_MASK: mb00 spattn mask |
| 29 | RWX | WOX_AND | WOX_OR | MB01_SPATTN_MASK: mb01 spattn mask |
| 30 | RWX | WOX_AND | WOX_OR | MB10_SPATTN_MASK: mb10 spattn mask |
| 31 | RWX | WOX_AND | WOX_OR | MB11_SPATTN_MASK: mb11 spattn mask |
| 32 | RWX | WOX_AND | WOX_OR | MB20_SPATTN_MASK: mb20 spattn mask |
| 33 | RWX | WOX_AND | WOX_OR | MB21_SPATTN_MASK: mb21 spattn mask |
| 34 | RWX | WOX_AND | WOX_OR | MB30_SPATTN_MASK: mb30 spattn mask |
| 35 | RWX | WOX_AND | WOX_OR | MB31_SPATTN_MASK: mb31 spattn mask |
| 36 | RWX | WOX_AND | WOX_OR | PTL0_SPARE_MASK: ptl0 spare mask |
| 37 | RWX | WOX_AND | WOX_OR | PTL1_SPARE_MASK: ptl1 spare mask |
| 38 | RWX | WOX_AND | WOX_OR | PTL2_SPARE_MASK: ptl2 spare mask |
| 39 | RWX | WOX_AND | WOX_OR | PTL3_SPARE_MASK: ptl3 spare mask |
| PowerBus Transaction Layer FIR Action 0 Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011011806 (SCOM) | |||
| Name: | PB.PTLSCOM23.PB_PTL_FIR_ACTION0_REG | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:39 | PB.PTLSCOM23.FIR.PAR_OFF.LEM_FIR.LOCALFIR.FIR.DO_ACTION0.FIR_ACTION0.LATC.L2(0:39) [0000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:39 | RW | PB_PTL_FIR_ACTION0: PowerBus Transaction Layer action select for corresponding bit in FIR (Action0,Action1) = Action Select (0,0) = Checkstop (0,1) = Recoverable Error to Service Processor (1,0) = Special Attention to Service Processor (1,1) = Invalid | ||
| PowerBus Transaction Layer FIR Action 1 Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011011807 (SCOM) | |||
| Name: | PB.PTLSCOM23.PB_PTL_FIR_ACTION1_REG | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:39 | PB.PTLSCOM23.FIR.PAR_OFF.LEM_FIR.LOCALFIR.FIR.DO_ACTION1.FIR_ACTION1.LATC.L2(0:39) [0000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:39 | RW | PB_PTL_FIR_ACTION1: PowerBus FIR LSB of action select for corresponding bit in FIR (Action0,Action1) = Action Select (0,0) = Checkstop (0,1) = Recoverable Error to Service Processor (1,0) = Special Attention to Service Processor (1,1) = Invalid | ||
| PowerBus Transaction Layer FIR WOF Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011011808 (SCOM) | |||
| Name: | PB.PTLSCOM23.PB_PTL_FIR_WOF_REG | |||
| Constant(s): | ||||
| Comments: | Who is on first register indicates which error occurred first | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:39 | PB.PTLSCOM23.FIR.PAR_OFF.LEM_FIR.LOCALFIR.FIR.WOF_LAT_YES.WOF.LATC.L2(0:39) [0000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:39 | RWX_WCLRREG | PB_PTL_FIR_WOF: WOF Register locks on first error | ||
| PowerBus TL Framer/Parser 01 Config Register | ||||
|---|---|---|---|---|
| Addr: |
000000001101180A (SCOM) | |||
| Name: | PB.PTLSCOM23.PB_FP01_CFG | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PB.PTLSCOM23.FP01_CFG_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | RW | FP0_CREDIT_PRIORITY_4_NOT_8: fp0 credit priority 4 not 8 | ||
| 1 | RW | FP0_DISABLE_GATHERING: fp0 disable data gathering | ||
| 2 | RW | FP0_DISABLE_CMD_COMPRESSION: fp0 disable cmd compression | ||
| 3 | RW | FP0_DISABLE_PRSP_COMPRESSION: fp0 disable prsp compression | ||
| 4:9 | RW | FP0_LL_CREDIT_FW_LIMIT: fmr0 framebuffer credit full-width credit limit. Equation = ROUND((-8.5 * pau freq/opt freq) + 21.5). | ||
| 10:15 | RW | FP0_LL_CREDIT_HW_LIMIT: fmr0 framebuffer credit half-width credit limit. Equation = ROUND((-5.1 * pau freq/opt freq) + 12.1). | ||
| 16:19 | RW | FP0_LL_CREDIT_QW_LIMIT: fmr0 framebuffer credit quarter-width credit limit. Always set it to 0x4. | ||
| 20 | RW | FP0_FMR_ENABLE_1PER4_PRESP: fmr0 enable one presp per 4 cycles per port (default is 1 every 2 cycles) | ||
| 21:23 | RW | FP01_CMD_EXP_TIME: obs/fmr/prs cmd expiration time = (value * 4) + 3 | ||
| 24 | RW | FP0_RUN_AFTER_FRAME_ERROR: fp0 run after frame error | ||
| 25 | RW | FP0_BRICKWALL_CREDITS_TO_NEST: 1=brickwall credits to nest (stress) 0=every other cycle max. (default) | ||
| 26:31 | RW | FP0_PRS_SPARE: fp0 parser spare | ||
| 32 | RW | FP1_CREDIT_PRIORITY_4_NOT_8: fp1 credit priority 4 not 8 | ||
| 33 | RW | FP1_DISABLE_GATHERING: fp1 disable data gathering | ||
| 34 | RW | FP1_DISABLE_CMD_COMPRESSION: fp1 disable cmd compression | ||
| 35 | RW | FP1_DISABLE_PRSP_COMPRESSION: fp1 disable prsp compression | ||
| 36:41 | RW | FP1_LL_CREDIT_FW_LIMIT: fmr1 framebuffer credit full-width credit limit. Equation = ROUND((-8.5 * pau freq/opt freq) + 21.5). | ||
| 42:47 | RW | FP1_LL_CREDIT_HW_LIMIT: fmr1 framebuffer credit half-width credit limit. Equation = ROUND((-5.1 * pau freq/opt freq) + 12.1). | ||
| 48:51 | RW | FP1_LL_CREDIT_QW_LIMIT: fmr1 framebuffer credit quarter-width credit limit. Always set it to 0x4. | ||
| 52 | RW | FP1_FMR_ENABLE_1PER4_PRESP: fmr1 enable one presp per 4 cycles per port (default is 1 every 2 cycles) | ||
| 53:55 | RW | FP1_FMR_SPARE: fp1 framer spare | ||
| 56 | RW | FP1_RUN_AFTER_FRAME_ERROR: fp1 run after frame error | ||
| 57 | RW | FP1_BRICKWALL_CREDITS_TO_NEST: 1=brickwall credits to nest (stress) 0=every other cycle max. (default) | ||
| 58:63 | RW | FP1_PRS_SPARE: fp1 parser spare | ||
| PowerBus TL Framer/Parser 23 Config Register | ||||
|---|---|---|---|---|
| Addr: |
000000001101180B (SCOM) | |||
| Name: | PB.PTLSCOM23.PB_FP23_CFG | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PB.PTLSCOM23.FP23_CFG_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | RW | FP2_CREDIT_PRIORITY_4_NOT_8: fp2 credit priority 4 not 8 | ||
| 1 | RW | FP2_DISABLE_GATHERING: fp2 disable data gathering | ||
| 2 | RW | FP2_DISABLE_CMD_COMPRESSION: fp2 disable cmd compression | ||
| 3 | RW | FP2_DISABLE_PRSP_COMPRESSION: fp2 disable prsp compression | ||
| 4:9 | RW | FP2_LL_CREDIT_FW_LIMIT: fmr2 framebuffer credit full-width credit limit. Equation = ROUND((-8.5 * pau freq/opt freq) + 21.5). | ||
| 10:15 | RW | FP2_LL_CREDIT_HW_LIMIT: fmr2 framebuffer credit half-width credit limit. Equation = ROUND((-5.1 * pau freq/opt freq) + 12.1). | ||
| 16:19 | RW | FP2_LL_CREDIT_QW_LIMIT: fmr2 framebuffer credit quarter-width credit limit. Always set it to 0x4. | ||
| 20 | RW | FP2_FMR_ENABLE_1PER4_PRESP: fmr2 enable one presp per 4 cycles per port (default is 1 every 2 cycles) | ||
| 21:23 | RW | FP23_CMD_EXP_TIME: obs/fmr/prs cmd expiration time = (value * 4) + 3 | ||
| 24 | RW | FP2_RUN_AFTER_FRAME_ERROR: fp2 run after frame error | ||
| 25 | RW | FP2_BRICKWALL_CREDITS_TO_NEST: 1=brickwall credits to nest (stress) 0=every other cycle max. (default) | ||
| 26:31 | RW | FP2_PRS_SPARE: fp2 parser spare | ||
| 32 | RW | FP3_CREDIT_PRIORITY_4_NOT_8: fp3 credit priority 4 not 8 | ||
| 33 | RW | FP3_DISABLE_GATHERING: fmr3 disable data gathering | ||
| 34 | RW | FP3_DISABLE_CMD_COMPRESSION: fmr3 disable cmd compression | ||
| 35 | RW | FP3_DISABLE_PRSP_COMPRESSION: fmr3 disable prsp compression | ||
| 36:41 | RW | FP3_LL_CREDIT_FW_LIMIT: fp3 framebuffer credit full-width credit limit. Equation = ROUND((-8.5 * pau freq/opt freq) + 21.5). | ||
| 42:47 | RW | FP3_LL_CREDIT_HW_LIMIT: fp3 framebuffer credit half-width credit limit. Equation = ROUND((-5.1 * pau freq/opt freq) + 12.1). | ||
| 48:51 | RW | FP3_LL_CREDIT_QW_LIMIT: fp3 framebuffer credit quarter-width credit limit. Always set it to 0x4. | ||
| 52 | RW | FP3_FMR_ENABLE_1PER4_PRESP: fmr3_enable one presp per 4 cycles per port (default is 1 every 2 cycles) | ||
| 53:55 | RW | FP3_FMR_SPARE: fp3 framer spare | ||
| 56 | RW | FP3_RUN_AFTER_FRAME_ERROR: fp3 run after frame error | ||
| 57 | RW | FP3_BRICKWALL_CREDITS_TO_NEST: 1=brickwall credits to nest (stress) 0=every other cycle max. (default) | ||
| 58:63 | RW | FP3_PRS_SPARE: fp3 parser spare | ||
| PowerBus TL RCmd Rate Control Register | ||||
|---|---|---|---|---|
| Addr: |
000000001101180C (SCOM) | |||
| Name: | PB.PTLSCOM23.RCMD_RATE_CFG | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:39 | PB.PTLSCOM23.RCMD_RATE_CFG_Q_0_INST.LATC.L2(0:39) [0000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:7 | RW | PTLX_RCMD_RATE: Link X RCmd rate config. Max command rate = 1 cmd/(ptlx_rcmd_rate + 1) PAU cycles, per rCmd port. The sum of ptlx_rcmd_rate and ptlx_rcmd_rate_adder must be less than 127, and ptlx_rcmd_rate needs to be faster than the FIXME dial that controls ring traffic to the links. | ||
| 8:15 | RW | PTLY_RCMD_RATE: Link Y RCmd rate config. Max command rate = 1 cmd/(ptlx_rcmd_rate + 1) PAU cycles, per rCmd port. The sum of ptly_rcmd_rate and ptly_rcmd_rate_adder must be less than 127, and ptly_rcmd_rate needs to be faster than the FIXME dial that controls ring traffic to the links. | ||
| 16:19 | RW | PTLX_RCMD_RATE_ADDER: Link X RCmd rate adjust config. Add this value to ptlx_rcmd_rate when the outbound data queues are backed up and are requesting more link bandwidth. When invoked, it can lead to extra command drops. The lower the value, the fewer extra drops, but also less link BW dedicated to data. See pb_cfg_link01_hi_backoff_limit in PB_TL_LINK_DATA_01_CFG_REG. Set to 0 to disable the function. | ||
| 20:23 | RW | PTLY_RCMD_RATE_ADDER: Link Y RCmd rate adjust config. Add this value to ptly_rcmd_rate when the outbound data queues are backed up and are requesting more link bandwidth. When invoked, it can lead to extra command drops. The lower the value, the fewer extra drops, but also less link BW dedicated to data. See pb_cfg_link23_hi_backoff_limit in PB_TL_LINK_DATA_23_CFG_REG. Set to 0 to disable the function. | ||
| 24 | RW | PTLX_DISABLE_TURBO: 1=Disable Link X RCmd rate turbo mode. PTL will no longer respond to cmd[port]_ax[link]_cpb_lcl. | ||
| 25 | RW | PTLX_CMD_GAP_REFERENCE: 0=count cycles, 1=count frames. | ||
| 26 | RW | PTLX_CMD_GAP_MODE: 0=adaptive, 1=use the ptlx_cmd_gap_cfg value. | ||
| 27 | RW | PTLX_CMD_GAP_TABLE: 0=use conservative gap table, 1=use aggressive gap table. | ||
| 28 | RW | PTLX_DISABLE_CREDIT_BANK: Disable ASY RC credit banking during TDM mode. | ||
| 29:31 | RW | PTLX_CMD_GAP_CFG: Link X RCmd gap control per port. Tells CROB how many gap cycles or frames from command win to next command presented to framer, per port. 0-7 cycles or frames between commands. Default=011. This setting controls the minimum crob->fmr command rate at all times, but especially during stop_cmds and turbo_mode. Does not necessarily control the gap between frames, especially during a replay, unless ptlx_cmd_gap_reference=1. | ||
| 32 | RW | PTLY_DISABLE_TURBO: 1=Disable Link Y RCmd rate turbo mode. PTL will no longer respond to cmd[port]_ax[link]_cpb_lcl. | ||
| 33 | RW | PTLY_CMD_GAP_REFERENCE: 0=count cycles, 1=count frames. | ||
| 34 | RW | PTLY_CMD_GAP_MODE: 0=adaptive, 1=use the ptly_cmd_gap_cfg value. | ||
| 35 | RW | PTLY_CMD_GAP_TABLE: 0=use conservative gap table, 1=use aggressive gap table. | ||
| 36 | RW | PTLY_DISABLE_CREDIT_BANK: Disable ASY RC credit banking during TDM mode. | ||
| 37:39 | RW | PTLY_CMD_GAP_CFG: Link Y RCmd gap control per port. Tells CROB how many gap cycles or frames from command win to next command presented to framer, per port. 0-7 cycles or frames between commands. Default=011. This setting controls the minimum crob->fmr command rate at all times, but especially during stop_cmds and turbo_mode. Does not necessarily control the gap between frames, especially during a replay, unless ptly_cmd_gap_reference=1. | ||
| PowerBus TL Link Error Injection Control Register | ||||
|---|---|---|---|---|
| Addr: |
000000001101180D (SCOM) | |||
| Name: | PB.PTLSCOM23.PB_TL_LINK_ERR_INJECT_REG | |||
| Constant(s): | ||||
| Comments: | This register controls the injection of errors for data coming inbound from the link and being forwarded to the on-chip data network. When tl_err_inj_stuck is set, the designated links are injected on the designated bits for every quadword passing through. Even PTL half-links inject on even DWs, odd PTL half-links inject on odd DWs. When tl_err_inj_single is set (and _stuck is not), the designated links are injected on the designated bits for only the NEXT QW to come in off the link, starting about 3 cycles after the scom write completes. | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:7 | PB.PTLSCOM23.ERR_INJECT_CFG_Q_0_INST.LATC.L2(0:7) [00000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | RW | tl_err_inj_stuck | ||
| 1 | WO_1P | tl_err_inj_single | ||
| 2 | RW | tl_err_inj_bit_17 | ||
| 3 | RW | tl_err_inj_bit_23 | ||
| 4 | RW | tl_err_inj_link_0_evn | ||
| 5 | RW | tl_err_inj_link_0_odd | ||
| 6 | RW | tl_err_inj_link_1_evn | ||
| 7 | RW | tl_err_inj_link_1_odd | ||
| PowerBus TL Link Delay 0123 Register | ||||
|---|---|---|---|---|
| Addr: |
000000001101180E (SCOM) | |||
| Name: | PB.PTLSCOM23.PB_TL_LINK_DLY_0123_REG | |||
| Constant(s): | ||||
| Comments: | Each 12-bit field shows the round-trip delay for the designated link, framer->link->parser->framer->link->parser->framer. If the leftmost bit is a 1, a replay or other slowdown occurred during the measurement, and the delay needs to be remeasured via use of the PB_TL_LINK_RT_DELAY_CTL_REG. | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 4:15 | PB.PTLSCOM23.PTLX0_SCOM_LINK_DELAY(0:11) [000000000000] | |||
| 20:31 | PB.PTLSCOM23.PTLX1_SCOM_LINK_DELAY(0:11) [000000000000] | |||
| 36:47 | PB.PTLSCOM23.PTLY0_SCOM_LINK_DELAY(0:11) [000000000000] | |||
| 52:63 | PB.PTLSCOM23.PTLY1_SCOM_LINK_DELAY(0:11) [000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:3 | RO | constant=0b0000 | ||
| 4:15 | ROX | ptlx0_link_delay | ||
| 16:19 | RO | constant=0b0000 | ||
| 20:31 | ROX | ptlx1_link_delay | ||
| 32:35 | RO | constant=0b0000 | ||
| 36:47 | ROX | ptly0_link_delay | ||
| 48:51 | RO | constant=0b0000 | ||
| 52:63 | ROX | ptly1_link_delay | ||
| PowerBus TL Link Data Buffer 01 Config Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011011810 (SCOM) | |||
| Name: | PB.PTLSCOM23.PB_TL_LINK_DATA_01_CFG_REG | |||
| Constant(s): | ||||
| Comments: | This register controls the even PTL inbound/outbound data facilities in this corner. When scom_ptlx_emulation_mode is set, this PTL should not be active, and bits 32:39 assume the following function instead: 32 = CResp Credit delay. 0=2*(128-N) delay, 1=3*(128-N) delay, per N=bits 33:39. 33:39 = N. Valid values are 0x01 to 0x7F. The delay of the emulated (fake) null presps will be approx. (3 * (128-N)) + TBD cycles. See CDIAL PTLX_EMULATION_MODE_CFG | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:39 | PB.PTLSCOM23.DIBDOB01_CFG_Q_0_INST.LATC.L2(0:39) [0000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | RW | PB_CFG_DIBDOB01_SP_0: spare bit | ||
| 1:7 | RW | PB_CFG_LINK01_DOB_VC0_LIMIT: Link01 DOB VC0 limit - # of VC0 octwords to allow in flight. | ||
| 8 | RW | PB_CFG_DIBDOB01_SP_1: pb cfg dibdob sp 1 | ||
| 9:15 | RW | PB_CFG_LINK01_DOB_VC1_LIMIT: Link01 DOB VC1 limit - # of VC1 octwords to allow in flight. | ||
| 16:23 | RW | PB_CFG_LINK01_HI_BACKOFF_LIMIT: Link01 Hi threshold limit for invoking local command rate backoff - range is 0 to 128. When outbound # of octwords pending reaches this level, DOB will request a local command rate slowdown until the # pending reaches the lo_backoff_limit. Does not get invoked if we have insufficient credits to send data over the link. | ||
| 24:31 | RW | PB_CFG_LINK01_LO_BACKOFF_LIMIT: Link01 Lo threshold limit for revoking local command rate backoff - range is 0 to 128. When outbound # of octwords pending drops to this level, DOB will request the local command rate to go back to the normal rate. | ||
| 32:36 | RW | PB_CFG_LINK01_DIB_VC_LIMIT: pb cfg link01 dib vc limit - limit per VC for data inbound to trunk (set to 31/16 for 1/2 channels in use) (both links use same credit pool) | ||
| 37 | RW | PB_CFG_LINK01_DIB_RTAG_DATA_ASY_LIMIT: rtag and data limit for async fed by dib. 0 = 16 slots, 1 = 15 slots | ||
| 38:39 | RW | PB_CFG_DIBDOB01_SP_2: pb cfg dibdob sp 2 | ||
| PowerBus TL Link Data Buffer 23 Config Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011011811 (SCOM) | |||
| Name: | PB.PTLSCOM23.PB_TL_LINK_DATA_23_CFG_REG | |||
| Constant(s): | ||||
| Comments: | This register controls the odd PTL inbound/outbound data facilities in this corner. When scom_ptly_emulation_mode is set, this PTL should not be active, and bits 32:39 assume the following function instead: 32 = CResp Credit delay. 0=2*(128-N) delay, 1=3*(128-N) delay, per N=bits 33:39. 33:39 = N. Valid values are 0x01 to 0x7F. The delay of the emulated (fake) null presps will be approx. (3 * (128-N)) + TBD cycles. See CDIAL PTLY_EMULATION_MODE_CFG | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:39 | PB.PTLSCOM23.DIBDOB23_CFG_Q_0_INST.LATC.L2(0:39) [0000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | RW | PB_CFG_DIBDOB23_SP_0: spare bit | ||
| 1:7 | RW | PB_CFG_LINK23_DOB_VC0_LIMIT: Link23 DOB VC0 limit - # of VC0 octwords to allow in flight. | ||
| 8 | RW | PB_CFG_DIBDOB23_SP_1: pb cfg dibdob sp 1 | ||
| 9:15 | RW | PB_CFG_LINK23_DOB_VC1_LIMIT: Link23 DOB VC1 limit - # of VC1 octwords to allow in flight. | ||
| 16:23 | RW | PB_CFG_LINK23_HI_BACKOFF_LIMIT: Link23 Hi threshold limit for invoking local command rate backoff - range is 0 to 128. When outbound # of octwords pending reaches this level, DOB will request a local command rate slowdown until the # pending reaches the lo_backoff_limit. Does not get invoked if we have insufficient credits to send data over the link. | ||
| 24:31 | RW | PB_CFG_LINK23_LO_BACKOFF_LIMIT: Link23 Lo threshold limit for revoking local command rate backoff - range is 0 to 128. When outbound # of octwords pending drops to this level, DOB will request the local command rate to go back to the normal rate. | ||
| 32:36 | RW | PB_CFG_LINK23_DIB_VC_LIMIT: pb cfg link23 dib vc limit - limit per VC for data inbound to trunk (set to 31/16 for 1/2 channels in use) (both links use same credit pool) | ||
| 37 | RW | PB_CFG_LINK23_DIB_RTAG_DATA_ASY_LIMIT: rtag and data limit for async fed by dib. 0 - 16 slots, 1 - 15 slots | ||
| 38:39 | RW | PB_CFG_DIBDOB23_SP_2: pb cfg dibdob sp 2 | ||
| PowerBus TL Link 01 Syndrome Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011011812 (SCOM) | |||
| Name: | PB.PTLSCOM23.PB_TL_LINK_SYN_01_REG | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PB.PTLSCOM23.REG12_RD_DATA_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:7 | ROX | dob00_scom_syn0 | ||
| 8:15 | ROX | dob00_scom_syn1 | ||
| 16:23 | ROX | dob00_scom_syn2 | ||
| 24:31 | ROX | dob00_scom_syn3 | ||
| 32:39 | ROX | dob01_scom_syn0 | ||
| 40:47 | ROX | dob01_scom_syn1 | ||
| 48:55 | ROX | dob01_scom_syn2 | ||
| 56:63 | ROX | dob01_scom_syn3 | ||
| PowerBus TL Link 23 Syndrome Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011011813 (SCOM) | |||
| Name: | PB.PTLSCOM23.PB_TL_LINK_SYN_23_REG | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PB.PTLSCOM23.REG13_RD_DATA_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:7 | ROX | dob02_scom_syn0 | ||
| 8:15 | ROX | dob02_scom_syn1 | ||
| 16:23 | ROX | dob02_scom_syn2 | ||
| 24:31 | ROX | dob02_scom_syn3 | ||
| 32:39 | ROX | dob03_scom_syn0 | ||
| 40:47 | ROX | dob03_scom_syn1 | ||
| 48:55 | ROX | dob03_scom_syn2 | ||
| 56:63 | ROX | dob03_scom_syn3 | ||
| PowerBus SMP Link 01 PowerSave Mode Config Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011011814 (SCOM) | |||
| Name: | PB.PTLSCOM23.PB_PSAVE01_MODE_CFG | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:15 | PB.PTLSCOM23.PB_PSAVE01_MODE_CFG_Q_0_INST.LATC.L2(0:15) [0000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:1 | RW | PSAVE01_MODE: Power Save Mode, three special modes are provided to enable stress testing in the lab and verification 0b00 = Normal mode - use content of PB_PSAVE01_MISC_CFG to make width-change decisions based on interface behavior (provided PSAVE01_MODE_CFG has at least 2 widths configured) 0b01 = Staircase mode - loop sequentially through available widths (never skipping an intermediate width) using only utilization count values to define the period at each level. 0b10 = Random Sequence mode - move randomly through available widths (but never skipping an intermediate width) using LFSR values to define the periods, not the LUC/HUC values. 0b11 = Random Staircase mode - loop all the way down through available widths, then all the way up, using LFSR values to define the periods, not the LUC/HUC values. Note: this mechanism is disabled if bits(2:4) are 1-hot, and is fully enabled if bits(0:4) = "11111". Note: the value of this dial is technically a don t care unless more than one bit is set in the width dial Dial enums: NORMAL=>0b00 STAIRCASE=>0b01 RANDOM=>0b10 RANDOMSTAIR=>0b11 | ||
| 2:4 | RW | PSAVE01_WIDTH: Link Width Enables = Full|Half|Quarter - the Link Layer MUST be programmed with compatible settings. One of the two chips at either end of an AX link (the master) can have this dial set to any valid setting. The other chip (the slave) MUST be programmed to 000. 0b000 = Disabled. Output defaults to Full width, same as 100, and gates off all internal clocks in the psave circuit. 0b001 = Only Quarter width enabled 0b010 = Only Half width enabled 0b011 = Only Half and Quarter widths enabled - NOT SUPPORTED 0b100 = Only full width enabled 0b101 = Only Full and Quarter enabled 0b110 = Only Full and Half enabled 0b111 = All three widths enabled - NOT SUPPORTED Dial enums: DISABLED=>0b000 QUARTER=>0b001 HALF=>0b010 FULL=>0b100 FULL_QUARTER=>0b101 FULL_HALF=>0b110 | ||
| 5:7 | RW | PSAVE01_SPARE: PSAVE01 spare | ||
| 8:15 | RW | PSAVE01_MIN_RAND_UC: Random mode minimum utilization count. Minimum size to allow a LUC or HUC to be, which, combined with PSAVE01_WSIZE then sets the minimum time in any link width. | ||
| PowerBus SMP Link 01 PowerSave Misc Config Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011011815 (SCOM) | |||
| Name: | PB.PTLSCOM23.PB_PSAVE01_MISC_CFG | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:58 | PB.PTLSCOM23.PB_PSAVE01_MISC_CFG_Q_0_INST.LATC.L2(0:58) [00000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:7 | RW | PSAVE01_HALF_LUC: Half-width Low Utilization Count - When in full width mode, this specifies how many consecutive sample windows need to be below the psave01_half_lut utilization threshold to kick the link into the next narrower configured width. Must be > 0. | ||
| 8:15 | RW | PSAVE01_HALF_HUC: Half-width High Utilization Count - When in Half-width mode, this specifies how many consecutive sample windows need to be above the psave01_half_hut utilization threshold to kick the link into full-width mode. Must be > 0. | ||
| 16:20 | RW | PSAVE01_HALF_LUT: Half-width Low Utilization Threshold - if in full-width mode, and utilization during a sample window is below (n+1)/32, (n=0 to 31, 3.125% steps) increment the low utilization consecutive window counter. If above, reset it. Note: the logic only looks at the 5 most significant bits of interest, and thus is effectively doing a round-down function when checking the utilization count against the threshold. The n+1 accounts for this behavior. Programming Constraint: LUT < HUT. | ||
| 21:25 | RW | PSAVE01_HALF_HUT: Half-width High Utilization Threshold - if in Half-width mode, and utilization during a sample window is above n/32, (n=0 to 31, 3.125% steps) increment the high utilization consecutive window counter. If below, reset it. Note: the logic only looks at the 5 most significant bits of interest, and thus is effectively doing a round-down function when checking the utilization count against the threshold, but the n/32 properly accounts for this behavior. | ||
| 26:27 | RW | PSAVE01_HALF_SPARE: spare | ||
| 28:35 | RW | PSAVE01_QTR_LUC: Quarter-width Low Utilization Count - When in Half-width mode (or Full when Half is disabled), this specifies how many consecutive sample windows need to be below the psave01_qtr_lut utilization threshold to kick the link into Quarter-width mode. Must be > 0. | ||
| 36:43 | RW | PSAVE01_QTR_HUC: Quarter-width High Utilization Countt - When in Quarter-width mode, this specifies how many consecutive sample windows need to be above the psave01_qtr_hut utilization threshold to kick the link into the next higher configured width. Must be > 0. | ||
| 44:48 | RW | PSAVE01_QTR_LUT: Quarter-width Low Utilization Threshold - if in Half-width mode (or Full when Half is disabled), and utilization during a sample window is below (n+1)/32, (n=0 to 31, 3.125% steps) increment the low utilization consecutive window counter. If above, reset it. Note: the logic only looks at the 5 most significant bits of interest, and thus is effectively doing a round-down function when checking the utilization count against the threshold. The n+1 accounts for this behavior. Programming Constraint: LUT < HUT. | ||
| 49:53 | RW | PSAVE01_QTR_HUT: Quarter-width High Utilization Threshold - if in Quarter-width mode, and utilization during a sample window is above n/32, (n=0 to 31, 3.125% steps) increment the high utilization consecutive window counter. If below, reset it. Note: the logic only looks at the 5 most significant bits of interest, and thus is effectively doing a round-down function when checking the utilization count against the threshold, but the n/32 properly accounts for this behavior. | ||
| 54:55 | RW | PSAVE01_QTR_SPARE: spare | ||
| 56:58 | RW | PSAVE01_WSIZE: psave sample window size: wsize = 2**(n+8) useable cycles. A usable cycle is defined as a cycle when the transport layer has a credit to transmit link content. The wsize limits are 256 - 32K. The utilization counters are 8 bits, so the maximum possible period for sampling data to make a decision is 32Kx256=8M cycles, or, approximately 4 milliseconds. | ||
| PowerBus SMP Link 23 PowerSave Mode Config Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011011816 (SCOM) | |||
| Name: | PB.PTLSCOM23.PB_PSAVE23_MODE_CFG | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:15 | PB.PTLSCOM23.PB_PSAVE23_MODE_CFG_Q_0_INST.LATC.L2(0:15) [0000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:1 | RW | PSAVE23_MODE: Power Save Mode, three special modes are provided to enable stress testing in the lab and verification 0b00 = Normal mode - use content of PB_PSAVE23_MISC_CFG to make width-change decisions based on interface behavior (provided PSAVE23_MODE_CFG has at least 2 widths configured) 0b01 = Staircase mode - loop sequentially through available widths (never skipping an intermediate width) using only utilization count values to define the period at each level. 0b10 = Random Sequence mode - move randomly through available widths (but never skipping an intermediate width) using LFSR values to define the periods, not the LUC/HUC values. 0b11 = Random Staircase mode - loop all the way down through available widths, then all the way up, using LFSR values to define the periods, not the LUC/HUC values. Note: this mechanism is disabled if bits(2:4) are 1-hot, and is fully enabled if bits(0:4) = "11111". Note: the value of this dial is technically a don t care unless more than one bit is set in the width dial Dial enums: NORMAL=>0b00 STAIRCASE=>0b01 RANDOM=>0b10 RANDOMSTAIR=>0b11 | ||
| 2:4 | RW | PSAVE23_WIDTH: Link Width Enables = Full|Half|Quarter - the Link Layer MUST be programmed with compatible settings. 0b000 = Disabled (Output defaults to Full width, same as 100, and gates off all internal clocks in the psave circuit.) 0b001 = Only Quarter width enabled 0b010 = Only Half width enabled 0b011 = Only Half and Quarter widths enabled - NOT SUPPORTED 0b100 = Only full width enabled 0b101 = Only Full and Quarter enabled 0b110 = Only Full and Half enabled 0b111 = All three widths enabled - NOT SUPPORTED Dial enums: DISABLED=>0b000 QUARTER=>0b001 HALF=>0b010 FULL=>0b100 FULL_QUARTER=>0b101 FULL_HALF=>0b110 | ||
| 5:7 | RW | PSAVE23_SPARE: PSAVE23 spare | ||
| 8:15 | RW | PSAVE23_MIN_RAND_UC: Random mode minimum utilization count. Minimum size to allow a LUC or HUC to be, which, combined with PSAVE23_WSIZE then sets the minimum time in any link width. | ||
| PowerBus SMP Link 01 PowerSave Misc Config Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011011817 (SCOM) | |||
| Name: | PB.PTLSCOM23.PB_PSAVE23_MISC_CFG | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:58 | PB.PTLSCOM23.PB_PSAVE23_MISC_CFG_Q_0_INST.LATC.L2(0:58) [00000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:7 | RW | PSAVE23_HALF_LUC: Half-width Low Utilization Count - When in full width mode, this specifies how many consecutive sample windows need to be below the psave23_half_lut utilization threshold to kick the link into the next narrower configured width. | ||
| 8:15 | RW | PSAVE23_HALF_HUC: Half-width High Utilization Count - When in Half-width mode, this specifies how many consecutive sample windows need to be above the psave23_half_hut utilization threshold to kick the link into full-width mode. | ||
| 16:20 | RW | PSAVE23_HALF_LUT: Half-width Low Utilization Threshold - if in full-width mode, and utilization during a sample window is below (n+1)/32, (n=0 to 31, 3.125% steps) increment the low utilization consecutive window counter. If above, reset it. Note: the logic only looks at the 5 most significant bits of interest, and thus is effectively doing a round-down function when checking the utilization count against the threshold. The n+1 accounts for this behavior. | ||
| 21:25 | RW | PSAVE23_HALF_HUT: Half-width High Utilization Threshold - if in Half-width mode, and utilization during a sample window is above n/32, (n=0 to 31, 3.125% steps) increment the high utilization consecutive window counter. If below, reset it. Note: the logic only looks at the 5 most significant bits of interest, and thus is effectively doing a round-down function when checking the utilization count against the threshold, but the n/32 properly accounts for this behavior. | ||
| 26:27 | RW | PSAVE23_HALF_SPARE: spare | ||
| 28:35 | RW | PSAVE23_QTR_LUC: Quarter-width Low Utilization Count - When in Half-width mode (or Full when Half is disabled), this specifies how many consecutive sample windows need to be below the psave23_qtr_lut utilization threshold to kick the link into Quarter-width mode. | ||
| 36:43 | RW | PSAVE23_QTR_HUC: Quarter-width High Utilization Countt - When in Quarter-width mode, this specifies how many consecutive sample windows need to be above the psave23_qtr_hut utilization threshold to kick the link into the next higher configured width. | ||
| 44:48 | RW | PSAVE23_QTR_LUT: Quarter-width Low Utilization Threshold - if in Half-width mode (or Full when Half is disabled), and utilization during a sample window is below (n+1)/32, (n=0 to 31, 3.125% steps) increment the low utilization consecutive window counter. If above, reset it. Note: the logic only looks at the 5 most significant bits of interest, and thus is effectively doing a round-down function when checking the utilization count against the threshold. The n+1 accounts for this behavior. | ||
| 49:53 | RW | PSAVE23_QTR_HUT: Quarter-width High Utilization Threshold - if in Quarter-width mode, and utilization during a sample window is above n/32, (n=0 to 31, 3.125% steps) increment the high utilization consecutive window counter. If below, reset it. Note: the logic only looks at the 5 most significant bits of interest, and thus is effectively doing a round-down function when checking the utilization count against the threshold, but the n/32 properly accounts for this behavior. | ||
| 54:55 | RW | PSAVE23_QTR_SPARE: spare | ||
| 56:58 | RW | PSAVE23_WSIZE: psave sample window size: wsize = 2**(n+8) useable cycles. A usable cycle is defined as a cycle when the transport layer has a credit to transmit link content. The wsize limits are 256 - 32K. The utilization counters are 8 bits, so the maximum possible period for sampling data to make a decision is 32Kx256=8M cycles, or, approximately 4 milliseconds. | ||
| PowerBus TL Link UE/CE/SUE Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011011818 (SCOM) | |||
| Name: | PB.PTLSCOM23.PB_EN_DOB_ECC_ERR_REG | |||
| Constant(s): | ||||
| Comments: | Can be reset via scom_ptlx_reset_keeper and/or scom_ptly_reset_keeper. (Which also resets all the related c_err_rpt regs.) | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:23 | PB.PTLSCOM23.PTLX_SCOM_DATA_ERR_BUS_Q_0_INST.LATC.L2(0:23) [000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:3 | ROX | dob01_ue | ||
| 4:7 | ROX | dob01_ce | ||
| 8:11 | ROX | dob01_sue | ||
| 12:15 | ROX | dob23_ue | ||
| 16:19 | ROX | dob23_ce | ||
| 20:23 | ROX | dob23_sue | ||
| PowerBus TL Round-Trip Delay Control Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011011819 (SCOM) | |||
| Name: | PB.PTLSCOM23.PB_TL_LINK_RT_DELAY_CTL_REG | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:7 | PB.PTLSCOM23.REG19_Q_0_INST.LATC.L2(0:7) [00000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:1 | WO_1P | PB_TL_LINK01_RT_DELAY_CTL_SET: setting a bit to 1 (auto reset to 0) causes the matching half-link to attempt to do a round-trip delay calculation. results end up in the pb_tl_link_dly_*_reg regs. | ||
| 2:3 | WO_1P | PB_TL_LINK23_RT_DELAY_CTL_SET: setting a bit to 1 (auto reset to 0) causes the matching half-link to attempt to do a round-trip delay calculation. results end up in the pb_tl_link_dly_*_reg regs. | ||
| 4:5 | RWX_WCLRPART | PB_TL_LINK01_RT_DELAY_CTL_STAT: a write of the reg resets these bits. they get set to 1 when a requested round-trip calculation completes. | ||
| 6:7 | RWX_WCLRPART | PB_TL_LINK23_RT_DELAY_CTL_STAT: a write of the reg resets these bits. they get set to 1 when a requested round-trip calculation completes. | ||
| PowerBus TL PMU Control register | ||||
|---|---|---|---|---|
| Addr: |
000000001101181A (SCOM) | |||
| Name: | PB.PTLSCOM23.PB_CFG_TLPM_REG | |||
| Constant(s): | ||||
| Comments: | This register controls how the PTL PMUlets count the 32-bit event bus that is presented to them. To configure the bus, see PB_CFG_TLPM_MUX1_REG and PB_CFG_TLPM_MUX2_REG. | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:55 | PB.PTLSCOM23.PB_CFG_TLPM_REG_Q_0_INST.LATC.L2(0:55) [00000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | RW | PB_CFG_TLPM_EN: Enable tlpm Performance Monitor. default=0. | ||
| 1 | RW | PB_CFG_TLPM_RESET_MODE: Performance Monitor Reset Mode; 0=reset_on_rd, 1=reset_on_wr. default=0. | ||
| 2 | RW | PB_CFG_TLPM_COUNTER_MODE: 0=freeze on counter max, 1= Free running. default=0. | ||
| 3 | RW | PB_CFG_TLPM_GLOBAL_PMISC_DIS: Disable Global PMU PMISC operation. default=0. | ||
| 4 | RW | PB_CFG_TLPM_GLOBAL_PMISC_MODE: Configure Global PMU PMISC operation. 0=level {L=pause, H=run} 1=level w/reset 0->1 default=0. | ||
| 5 | RW | PB_CFG_TLPM_EXTERNAL_FREEZE: CNPM Freeze Enable. 0=Disable CNPM freeze. 1=Enable CNPM freeze. If a CNPM counter maxes out, the TLPM counters will freeze. Freeze requires pb_cfg_tlpm_counter_mode=0. default=0. | ||
| 6:7 | RW | PB_CFG_TLPM_0_1_OP: Performance Monitor Bit 0/1 Select; 00=sel_a, 01=sel_b ,10=add_ab, 11=cycles Dial enums: SEL_A=>0b00 SEL_B=>0b01 ADD_AB=>0b10 CYCLES=>0b11 | ||
| 8:9 | RW | PB_CFG_TLPM_2_3_OP: Performance Monitor Bit 2/3 Select; 00=sel_a, 01=sel_b ,10=add_ab, 11=cycles Dial enums: SEL_A=>0b00 SEL_B=>0b01 ADD_AB=>0b10 CYCLES=>0b11 | ||
| 10:11 | RW | PB_CFG_TLPM_4_5_OP: Performance Monitor Bit 4/5 Select; 00=sel_a, 01=sel_b ,10=add_ab, 11=cycles Dial enums: SEL_A=>0b00 SEL_B=>0b01 ADD_AB=>0b10 CYCLES=>0b11 | ||
| 12:13 | RW | PB_CFG_TLPM_6_7_OP: Performance Monitor Bit 6/7 Select; 00=sel_a, 01=sel_b ,10=add_ab, 11=cycles Dial enums: SEL_A=>0b00 SEL_B=>0b01 ADD_AB=>0b10 CYCLES=>0b11 | ||
| 14:15 | RW | PB_CFG_TLPM_8_9_OP: Performance Monitor Bit 8/9 Select; 00=sel_a, 01=sel_b ,10=add_ab, 11=cycles Dial enums: SEL_A=>0b00 SEL_B=>0b01 ADD_AB=>0b10 CYCLES=>0b11 | ||
| 16:17 | RW | PB_CFG_TLPM_10_11_OP: Performance Monitor Bit 10/11 Select; 00=sel_a, 01=sel_b ,10=add_ab, 11=cycles Dial enums: SEL_A=>0b00 SEL_B=>0b01 ADD_AB=>0b10 CYCLES=>0b11 | ||
| 18:19 | RW | PB_CFG_TLPM_12_13_OP: Performance Monitor Bit 12/13 Select; 00=sel_a, 01=sel_b ,10=add_ab, 11=cycles Dial enums: SEL_A=>0b00 SEL_B=>0b01 ADD_AB=>0b10 CYCLES=>0b11 | ||
| 20:21 | RW | PB_CFG_TLPM_14_15_OP: Performance Monitor Bit 14/15 Select; 00=sel_a, 01=sel_b ,10=add_ab, 11=cycles Dial enums: SEL_A=>0b00 SEL_B=>0b01 ADD_AB=>0b10 CYCLES=>0b11 | ||
| 22:23 | RW | PB_CFG_TLPM_16_17_OP: Performance Monitor Bit 16/17 Select; 00=sel_a, 01=sel_b ,10=add_ab, 11=cycles Dial enums: SEL_A=>0b00 SEL_B=>0b01 ADD_AB=>0b10 CYCLES=>0b11 | ||
| 24:25 | RW | PB_CFG_TLPM_18_19_OP: Performance Monitor Bit 18/19 Select; 00=sel_a, 01=sel_b ,10=add_ab, 11=cycles Dial enums: SEL_A=>0b00 SEL_B=>0b01 ADD_AB=>0b10 CYCLES=>0b11 | ||
| 26:27 | RW | PB_CFG_TLPM_20_21_OP: Performance Monitor Bit 20/21 Select; 00=sel_a, 01=sel_b ,10=add_ab, 11=cycles Dial enums: SEL_A=>0b00 SEL_B=>0b01 ADD_AB=>0b10 CYCLES=>0b11 | ||
| 28:29 | RW | PB_CFG_TLPM_22_23_OP: Performance Monitor Bit 22/23 Select; 00=sel_a, 01=sel_b ,10=add_ab, 11=cycles Dial enums: SEL_A=>0b00 SEL_B=>0b01 ADD_AB=>0b10 CYCLES=>0b11 | ||
| 30:31 | RW | PB_CFG_TLPM_24_25_OP: Performance Monitor Bit 24/25 Select; 00=sel_a, 01=sel_b ,10=add_ab, 11=cycles Dial enums: SEL_A=>0b00 SEL_B=>0b01 ADD_AB=>0b10 CYCLES=>0b11 | ||
| 32:33 | RW | PB_CFG_TLPM_26_27_OP: Performance Monitor Bit 26/27 Select; 00=sel_a, 01=sel_b ,10=add_ab, 11=cycles Dial enums: SEL_A=>0b00 SEL_B=>0b01 ADD_AB=>0b10 CYCLES=>0b11 | ||
| 34:35 | RW | PB_CFG_TLPM_28_29_OP: Performance Monitor Bit 28/29 Select; 00=sel_a, 01=sel_b ,10=add_ab, 11=cycles Dial enums: SEL_A=>0b00 SEL_B=>0b01 ADD_AB=>0b10 CYCLES=>0b11 | ||
| 36:37 | RW | PB_CFG_TLPM_30_31_OP: Performance Monitor Bit 30/31 Select; 00=sel_a, 01=sel_b ,10=add_ab, 11=cycles Dial enums: SEL_A=>0b00 SEL_B=>0b01 ADD_AB=>0b10 CYCLES=>0b11 | ||
| 38:40 | RW | PB_CFG_TLPM_CASCADE_PMU0: PMU0 cascade counters Dial enums: NONE0=>0b000 C0_C1=>0b001 C1_C2=>0b010 C2_C3=>0b011 NONE1=>0b100 C1_C0=>0b101 C2_C1=>0b110 C3_C2=>0b111 | ||
| 41:43 | RW | PB_CFG_TLPM_CASCADE_PMU1: PMU1 cascade counters Dial enums: NONE0=>0b000 C0_C1=>0b001 C1_C2=>0b010 C2_C3=>0b011 NONE1=>0b100 C1_C0=>0b101 C2_C1=>0b110 C3_C2=>0b111 | ||
| 44:46 | RW | PB_CFG_TLPM_CASCADE_PMU2: PMU0 cascade counters Dial enums: NONE0=>0b000 C0_C1=>0b001 C1_C2=>0b010 C2_C3=>0b011 NONE1=>0b100 C1_C0=>0b101 C2_C1=>0b110 C3_C2=>0b111 | ||
| 47:49 | RW | PB_CFG_TLPM_CASCADE_PMU3: PMU3 cascade counters Dial enums: NONE0=>0b000 C0_C1=>0b001 C1_C2=>0b010 C2_C3=>0b011 NONE1=>0b100 C1_C0=>0b101 C2_C1=>0b110 C3_C2=>0b111 | ||
| 50:55 | RW | PB_CFG_TLPM_SPARE: PMU CTL spare | ||
| PowerBus AX PMU0_TLPM Counter reg | ||||
|---|---|---|---|---|
| Addr: |
000000001101181B (SCOM) | |||
| Name: | PB.PTLSCOM23.PB_PMU0_TLPM_COUNTER | |||
| Constant(s): | ||||
| Comments: | 00:15 pb_event_pmu0_tlpmw_counter0(0:15) 16:31 pb_event_pmu0_tlpmw_counter1(0:15) 32:47 pb_event_pmu0_tlpmw_counter2(0:15) 48:63 pb_event_pmu0_tlpmw_counter3(0:31) | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:15 | PB.PTLSCOM23.TLPMU0.COUNTER0_CNT_Q_0_INST.LATC.L2(0:15) [0000000000000000] | |||
| 16:31 | PB.PTLSCOM23.TLPMU0.COUNTER1_CNT_Q_0_INST.LATC.L2(0:15) [0000000000000000] | |||
| 32:47 | PB.PTLSCOM23.TLPMU0.COUNTER2_CNT_Q_0_INST.LATC.L2(0:15) [0000000000000000] | |||
| 48:63 | PB.PTLSCOM23.TLPMU0.COUNTER3_CNT_Q_0_INST.LATC.L2(0:15) [0000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:15 | RWX_WCLRREG | pb_event_pmu0_tlpmw_counter0 | ||
| 16:31 | RWX_WCLRREG | pb_event_pmu0_tlpmw_counter1 | ||
| 32:47 | RWX_WCLRREG | pb_event_pmu0_tlpmw_counter2 | ||
| 48:63 | RWX_WCLRREG | pb_event_pmu0_tlpmw_counter3 | ||
| PowerBus AX PMU1_TLPM Counter reg | ||||
|---|---|---|---|---|
| Addr: |
000000001101181C (SCOM) | |||
| Name: | PB.PTLSCOM23.PB_PMU1_TLPM_COUNTER | |||
| Constant(s): | ||||
| Comments: | 00:15 pb_event_pmu1_tlpmw_counter0(0:15) 16:31 pb_event_pmu1_tlpmw_counter1(0:15) 32:47 pb_event_pmu1_tlpmw_counter2(0:15) 48:63 pb_event_pmu1_tlpmw_counter3(0:31) | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:15 | PB.PTLSCOM23.TLPMU1.COUNTER0_CNT_Q_0_INST.LATC.L2(0:15) [0000000000000000] | |||
| 16:31 | PB.PTLSCOM23.TLPMU1.COUNTER1_CNT_Q_0_INST.LATC.L2(0:15) [0000000000000000] | |||
| 32:47 | PB.PTLSCOM23.TLPMU1.COUNTER2_CNT_Q_0_INST.LATC.L2(0:15) [0000000000000000] | |||
| 48:63 | PB.PTLSCOM23.TLPMU1.COUNTER3_CNT_Q_0_INST.LATC.L2(0:15) [0000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:15 | RWX_WCLRREG | pb_event_pmu1_tlpmw_counter0 | ||
| 16:31 | RWX_WCLRREG | pb_event_pmu1_tlpmw_counter1 | ||
| 32:47 | RWX_WCLRREG | pb_event_pmu1_tlpmw_counter2 | ||
| 48:63 | RWX_WCLRREG | pb_event_pmu1_tlpmw_counter3 | ||
| PowerBus AX PMU2_TLPM Counter reg | ||||
|---|---|---|---|---|
| Addr: |
000000001101181D (SCOM) | |||
| Name: | PB.PTLSCOM23.PB_PMU2_TLPM_COUNTER | |||
| Constant(s): | ||||
| Comments: | 00:15 pb_event_pmu2_tlpmw_counter0(0:15) 16:31 pb_event_pmu2_tlpmw_counter1(0:15) 32:47 pb_event_pmu2_tlpmw_counter2(0:15) 48:63 pb_event_pmu2_tlpmw_counter3(0:31) | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:15 | PB.PTLSCOM23.TLPMU2.COUNTER0_CNT_Q_0_INST.LATC.L2(0:15) [0000000000000000] | |||
| 16:31 | PB.PTLSCOM23.TLPMU2.COUNTER1_CNT_Q_0_INST.LATC.L2(0:15) [0000000000000000] | |||
| 32:47 | PB.PTLSCOM23.TLPMU2.COUNTER2_CNT_Q_0_INST.LATC.L2(0:15) [0000000000000000] | |||
| 48:63 | PB.PTLSCOM23.TLPMU2.COUNTER3_CNT_Q_0_INST.LATC.L2(0:15) [0000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:15 | RWX_WCLRREG | pb_event_pmu2_tlpmw_counter0 | ||
| 16:31 | RWX_WCLRREG | pb_event_pmu2_tlpmw_counter1 | ||
| 32:47 | RWX_WCLRREG | pb_event_pmu2_tlpmw_counter2 | ||
| 48:63 | RWX_WCLRREG | pb_event_pmu2_tlpmw_counter3 | ||
| PowerBus AX PMU3_TLPM Counter reg | ||||
|---|---|---|---|---|
| Addr: |
000000001101181E (SCOM) | |||
| Name: | PB.PTLSCOM23.PB_PMU3_TLPM_COUNTER | |||
| Constant(s): | ||||
| Comments: | 00:15 pb_event_pmu3_tlpmw_counter0(0:15) 16:31 pb_event_pmu3_tlpmw_counter1(0:15) 32:47 pb_event_pmu3_tlpmw_counter2(0:15) 48:63 pb_event_pmu3_tlpmw_counter3(0:31) | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:15 | PB.PTLSCOM23.TLPMU3.COUNTER0_CNT_Q_0_INST.LATC.L2(0:15) [0000000000000000] | |||
| 16:31 | PB.PTLSCOM23.TLPMU3.COUNTER1_CNT_Q_0_INST.LATC.L2(0:15) [0000000000000000] | |||
| 32:47 | PB.PTLSCOM23.TLPMU3.COUNTER2_CNT_Q_0_INST.LATC.L2(0:15) [0000000000000000] | |||
| 48:63 | PB.PTLSCOM23.TLPMU3.COUNTER3_CNT_Q_0_INST.LATC.L2(0:15) [0000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:15 | RWX_WCLRREG | pb_event_pmu3_tlpmw_counter0 | ||
| 16:31 | RWX_WCLRREG | pb_event_pmu3_tlpmw_counter1 | ||
| 32:47 | RWX_WCLRREG | pb_event_pmu3_tlpmw_counter2 | ||
| 48:63 | RWX_WCLRREG | pb_event_pmu3_tlpmw_counter3 | ||
| PowerBus Endcap PMU Control register | ||||
|---|---|---|---|---|
| Addr: |
000000001101181F (SCOM) | |||
| Name: | PB.PTLSCOM23.PB_CFG_CNPM_REG | |||
| Constant(s): | ||||
| Comments: | 00 = pb_cfg_cnpm_en 01 = pb_cfg_cnpm_reset_mode 02 = pb_cfg_cnpm_counter_mode 03 = pb_cfg_cnpm_global_pmisc_dis 04 = pb_cfg_cnpm_global_pmisc_mode 05 = pb_cfg_cnpm_external_freeze 06:07 = pb_cfg_cnpm_op_0 - 00=Select event 00, 01=Select event 01, 10=ADD events 00 & 01, 11 Count cycles (timebase). 08:09 = pb_cfg_cnpm_op_1 - 00=Select event 02, 01=Select event 03, 10=ADD events 02 & 03, 11 Count cycles (timebase). 10:11 = pb_cfg_cnpm_op_2 - 00=Select event 04, 01=Select event 05, 10=ADD events 04 & 05, 11 Count cycles (timebase). 12:13 = pb_cfg_cnpm_op_3 - 00=Select event 06, 01=Select event 07, 10=ADD events 06 & 07, 11 Count cycles (timebase). 14:15 = pb_cfg_cnpm_op_4 - 00=Select event 08, 01=Select event 09, 10=ADD events 08 & 09, 11 Count cycles (timebase). 16:17 = pb_cfg_cnpm_op_5 - 00=Select event 10, 01=Select event 11, 10=ADD events 10 & 11, 11 Count cycles (timebase). 18:19 = pb_cfg_cnpm_op_6 - 00=Select event 12, 01=Select event 13, 10=ADD events 12 & 13, 11 Count cycles (timebase). 20:21 = pb_cfg_cnpm_op_7 - 00=Select event 14, 01=Select event 15, 10=ADD events 14 & 15, 11 Count cycles (timebase). 22:23 = pb_cfg_cnpm_op_8 - 00=Select event 16, 01=Select event 17, 10=ADD events 16 & 17, 11 Count cycles (timebase). 24:25 = pb_cfg_cnpm_op_9 - 00=Select event 18, 01=Select event 19, 10=ADD events 18 & 19, 11 Count cycles (timebase). 26:27 = pb_cfg_cnpm_op_10 - 00=Select event 20, 01=Select event 21, 10=ADD events 20 & 21, 11 Count cycles (timebase). 28:29 = pb_cfg_cnpm_op_11 - 00=Select event 22, 01=Select event 23, 10=ADD events 22 & 23, 11 Count cycles (timebase). 30:31 = pb_cfg_cnpm_op_12 - 00=Select event 24, 01=Select event 25, 10=ADD events 24 & 25, 11 Count cycles (timebase). 32:33 = pb_cfg_cnpm_op_13 - 00=Select event 26, 01=Select event 27, 10=ADD events 26 & 27, 11 Count cycles (timebase). 34:35 = pb_cfg_cnpm_op_14 - 00=Select event 28, 01=Select event 29, 10=ADD events 28 & 29, 11 Count cycles (timebase). 36:37 = pb_cfg_cnpm_op_15 - 00=Select event 30, 01=Select event 31, 10=ADD events 30 & 31, 11 Count cycles (timebase). 38:40 = pb_cfg_cnpm_cascade_pmulet0 - x00 Do not cascade, 001 Cascade c0 -> c1, 010 Cascade c1 -> c2, 011 Cascade c2 -> c3, 101 Cascade c1 -> c0, 110 Cascade c2 -> c1, 111 Cascade c3 -> c2 41:43 = pb_cfg_cnpm_cascade_pmulet1 - x00 Do not cascade, 001 Cascade c0 -> c1, 010 Cascade c1 -> c2, 011 Cascade c2 -> c3, 101 Cascade c1 -> c0, 110 Cascade c2 -> c1, 111 Cascade c3 -> c2 44:46 = pb_cfg_cnpm_cascade_pmulet2 - x00 Do not cascade, 001 Cascade c0 -> c1, 010 Cascade c1 -> c2, 011 Cascade c2 -> c3, 101 Cascade c1 -> c0, 110 Cascade c2 -> c1, 111 Cascade c3 -> c2 47:49 = pb_cfg_cnpm_cascade_pmulet3 - x00 Do not cascade, 001 Cascade c0 -> c1, 010 Cascade c1 -> c2, 011 Cascade c2 -> c3, 101 Cascade c1 -> c0, 110 Cascade c2 -> c1, 111 Cascade c3 -> c2 50:55 = pb_cfg_cnpm_spare | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:55 | PB.PTLSCOM23.PB_CFG_CNPM_REG_Q_0_INST.LATC.L2(0:55) [00000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | RW | PB_CFG_CNPM_EN: Enable cnpm Performance Monitor. default=0. | ||
| 1 | RW | PB_CFG_CNPM_RESET_MODE: Performance Monitor Reset Mode; 0=reset_on_rd, 1=reset_on_wr. default=0. | ||
| 2 | RW | PB_CFG_CNPM_COUNTER_MODE: 0=freeze on counter max, 1= Free running. default=0. | ||
| 3 | RW | PB_CFG_CNPM_GLOBAL_PMISC_DIS: Disable Global PMU PMISC operation. default=0. | ||
| 4 | RW | PB_CFG_CNPM_GLOBAL_PMISC_MODE: Configure Global PMU PMISC operation. 0=level {L=pause, H=run} 1=level w/reset 0->1 default=0. | ||
| 5 | RW | PB_CFG_CNPM_EXTERNAL_FREEZE: TLPM Freeze Enable. 0=Disable TLPM freeze. 1=Enable TLPM freeze. If a TLPM counter maxes out, the CNPM counters will freeze. Freeze requires pb_cfg_cnpm_counter_mode=0. default=0. | ||
| 6:7 | RW | PB_CFG_CNPM_0_1_OP: Performance Monitor Bit 0/1 Select; 00=sel_a, 01=sel_b ,10=add_ab, 11=cycles Dial enums: SEL_A=>0b00 SEL_B=>0b01 ADD_AB=>0b10 CYCLES=>0b11 | ||
| 8:9 | RW | PB_CFG_CNPM_2_3_OP: Performance Monitor Bit 2/3 Select; 00=sel_a, 01=sel_b ,10=add_ab, 11=cycles Dial enums: SEL_A=>0b00 SEL_B=>0b01 ADD_AB=>0b10 CYCLES=>0b11 | ||
| 10:11 | RW | PB_CFG_CNPM_4_5_OP: Performance Monitor Bit 4/5 Select; 00=sel_a, 01=sel_b ,10=add_ab, 11=cycles Dial enums: SEL_A=>0b00 SEL_B=>0b01 ADD_AB=>0b10 CYCLES=>0b11 | ||
| 12:13 | RW | PB_CFG_CNPM_6_7_OP: Performance Monitor Bit 6/7 Select; 00=sel_a, 01=sel_b ,10=add_ab, 11=cycles Dial enums: SEL_A=>0b00 SEL_B=>0b01 ADD_AB=>0b10 CYCLES=>0b11 | ||
| 14:15 | RW | PB_CFG_CNPM_8_9_OP: Performance Monitor Bit 8/9 Select; 00=sel_a, 01=sel_b ,10=add_ab, 11=cycles Dial enums: SEL_A=>0b00 SEL_B=>0b01 ADD_AB=>0b10 CYCLES=>0b11 | ||
| 16:17 | RW | PB_CFG_CNPM_10_11_OP: Performance Monitor Bit 10/11 Select; 00=sel_a, 01=sel_b ,10=add_ab, 11=cycles Dial enums: SEL_A=>0b00 SEL_B=>0b01 ADD_AB=>0b10 CYCLES=>0b11 | ||
| 18:19 | RW | PB_CFG_CNPM_12_13_OP: Performance Monitor Bit 12/13 Select; 00=sel_a, 01=sel_b ,10=add_ab, 11=cycles Dial enums: SEL_A=>0b00 SEL_B=>0b01 ADD_AB=>0b10 CYCLES=>0b11 | ||
| 20:21 | RW | PB_CFG_CNPM_14_15_OP: Performance Monitor Bit 14/15 Select; 00=sel_a, 01=sel_b ,10=add_ab, 11=cycles Dial enums: SEL_A=>0b00 SEL_B=>0b01 ADD_AB=>0b10 CYCLES=>0b11 | ||
| 22:23 | RW | PB_CFG_CNPM_16_17_OP: Performance Monitor Bit 16/17 Select; 00=sel_a, 01=sel_b ,10=add_ab, 11=cycles Dial enums: SEL_A=>0b00 SEL_B=>0b01 ADD_AB=>0b10 CYCLES=>0b11 | ||
| 24:25 | RW | PB_CFG_CNPM_18_19_OP: Performance Monitor Bit 18/19 Select; 00=sel_a, 01=sel_b ,10=add_ab, 11=cycles Dial enums: SEL_A=>0b00 SEL_B=>0b01 ADD_AB=>0b10 CYCLES=>0b11 | ||
| 26:27 | RW | PB_CFG_CNPM_20_21_OP: Performance Monitor Bit 20/21 Select; 00=sel_a, 01=sel_b ,10=add_ab, 11=cycles Dial enums: SEL_A=>0b00 SEL_B=>0b01 ADD_AB=>0b10 CYCLES=>0b11 | ||
| 28:29 | RW | PB_CFG_CNPM_22_23_OP: Performance Monitor Bit 22/23 Select; 00=sel_a, 01=sel_b ,10=add_ab, 11=cycles Dial enums: SEL_A=>0b00 SEL_B=>0b01 ADD_AB=>0b10 CYCLES=>0b11 | ||
| 30:31 | RW | PB_CFG_CNPM_24_25_OP: Performance Monitor Bit 24/25 Select; 00=sel_a, 01=sel_b ,10=add_ab, 11=cycles Dial enums: SEL_A=>0b00 SEL_B=>0b01 ADD_AB=>0b10 CYCLES=>0b11 | ||
| 32:33 | RW | PB_CFG_CNPM_26_27_OP: Performance Monitor Bit 26/27 Select; 00=sel_a, 01=sel_b ,10=add_ab, 11=cycles Dial enums: SEL_A=>0b00 SEL_B=>0b01 ADD_AB=>0b10 CYCLES=>0b11 | ||
| 34:35 | RW | PB_CFG_CNPM_28_29_OP: Performance Monitor Bit 28/29 Select; 00=sel_a, 01=sel_b ,10=add_ab, 11=cycles Dial enums: SEL_A=>0b00 SEL_B=>0b01 ADD_AB=>0b10 CYCLES=>0b11 | ||
| 36:37 | RW | PB_CFG_CNPM_30_31_OP: Performance Monitor Bit 30/31 Select; 00=sel_a, 01=sel_b ,10=add_ab, 11=cycles Dial enums: SEL_A=>0b00 SEL_B=>0b01 ADD_AB=>0b10 CYCLES=>0b11 | ||
| 38:40 | RW | PB_CFG_CNPM_CASCADE_PMU0: PMU0 cascade counters Dial enums: NONE0=>0b000 C0_C1=>0b001 C1_C2=>0b010 C2_C3=>0b011 NONE1=>0b100 C1_C0=>0b101 C2_C1=>0b110 C3_C2=>0b111 | ||
| 41:43 | RW | PB_CFG_CNPM_CASCADE_PMU1: PMU1 cascade counters Dial enums: NONE0=>0b000 C0_C1=>0b001 C1_C2=>0b010 C2_C3=>0b011 NONE1=>0b100 C1_C0=>0b101 C2_C1=>0b110 C3_C2=>0b111 | ||
| 44:46 | RW | PB_CFG_CNPM_CASCADE_PMU2: PMU0 cascade counters Dial enums: NONE0=>0b000 C0_C1=>0b001 C1_C2=>0b010 C2_C3=>0b011 NONE1=>0b100 C1_C0=>0b101 C2_C1=>0b110 C3_C2=>0b111 | ||
| 47:49 | RW | PB_CFG_CNPM_CASCADE_PMU3: PMU3 cascade counters Dial enums: NONE0=>0b000 C0_C1=>0b001 C1_C2=>0b010 C2_C3=>0b011 NONE1=>0b100 C1_C0=>0b101 C2_C1=>0b110 C3_C2=>0b111 | ||
| 50:55 | RW | PB_CFG_CNPM_SPARE: PMU CTL spare | ||
| PowerBus AX/Endcap CNPM/TLPM Prescale Config Reg | ||||
|---|---|---|---|---|
| Addr: |
0000000011011820 (SCOM) | |||
| Name: | PB.PTLSCOM23.PB_CNPM_PMU_PRESCALER | |||
| Constant(s): | ||||
| Comments: | Each 2-bit field configures the prescaler setting for the named pmu[n]_counter[m] CNPM events (events coming off of the PB) are already scaled by 2 bits due to a clock domain crossing, resulting in these prescale values for CNPM counters: 00 = 22bit prescaler 01 = 18bit prescaler 10 = 10bit prescaler 11 = 6bit prescaler TLPM events (transaction layer events) come in raw, resulting in these prescale values for TLPM counters: 00 = 20bit prescaler 01 = 16bit prescaler 10 = 8bit prescaler 11 = 4bit prescaler | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PB.PTLSCOM23.PB_CFG_CNPM_PRESCALE_REG_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:1 | RW | PB_CFG_CNPM_PRESCALER_GRP0_C0: Performance Monitor Prescaler Select; 00=22bit, 01=18bit, 10=10bit, 11=6bit Dial enums: P22=>0b00 P18=>0b01 P10=>0b10 P6=>0b11 | ||
| 2:3 | RW | PB_CFG_CNPM_PRESCALER_GRP0_C1: Performance Monitor Prescaler Select; 00=22bit, 01=18bit, 10=10bit, 11=6bit Dial enums: P22=>0b00 P18=>0b01 P10=>0b10 P6=>0b11 | ||
| 4:5 | RW | PB_CFG_CNPM_PRESCALER_GRP0_C2: Performance Monitor Prescaler Select; 00=22bit, 01=18bit, 10=10bit, 11=6bit Dial enums: P22=>0b00 P18=>0b01 P10=>0b10 P6=>0b11 | ||
| 6:7 | RW | PB_CFG_CNPM_PRESCALER_GRP0_C3: Performance Monitor Prescaler Select; 00=22bit, 01=18bit, 10=10bit, 11=6bit Dial enums: P22=>0b00 P18=>0b01 P10=>0b10 P6=>0b11 | ||
| 8:9 | RW | PB_CFG_CNPM_PRESCALER_GRP1_C0: Performance Monitor Prescaler Select; 00=22bit, 01=18bit, 10=10bit, 11=6bit Dial enums: P22=>0b00 P18=>0b01 P10=>0b10 P6=>0b11 | ||
| 10:11 | RW | PB_CFG_CNPM_PRESCALER_GRP1_C1: Performance Monitor Prescaler Select; 00=22bit, 01=18bit, 10=10bit, 11=6bit Dial enums: P22=>0b00 P18=>0b01 P10=>0b10 P6=>0b11 | ||
| 12:13 | RW | PB_CFG_CNPM_PRESCALER_GRP1_C2: Performance Monitor Prescaler Select; 00=22bit, 01=18bit, 10=10bit, 11=6bit Dial enums: P22=>0b00 P18=>0b01 P10=>0b10 P6=>0b11 | ||
| 14:15 | RW | PB_CFG_CNPM_PRESCALER_GRP1_C3: Performance Monitor Prescaler Select; 00=22bit, 01=18bit, 10=10bit, 11=6bit Dial enums: P22=>0b00 P18=>0b01 P10=>0b10 P6=>0b11 | ||
| 16:17 | RW | PB_CFG_CNPM_PRESCALER_GRP2_C0: Performance Monitor Prescaler Select; 00=22bit, 01=18bit, 10=10bit, 11=6bit Dial enums: P22=>0b00 P18=>0b01 P10=>0b10 P6=>0b11 | ||
| 18:19 | RW | PB_CFG_CNPM_PRESCALER_GRP2_C1: Performance Monitor Prescaler Select; 00=22bit, 01=18bit, 10=10bit, 11=6bit Dial enums: P22=>0b00 P18=>0b01 P10=>0b10 P6=>0b11 | ||
| 20:21 | RW | PB_CFG_CNPM_PRESCALER_GRP2_C2: Performance Monitor Prescaler Select; 00=22bit, 01=18bit, 10=10bit, 11=6bit Dial enums: P22=>0b00 P18=>0b01 P10=>0b10 P6=>0b11 | ||
| 22:23 | RW | PB_CFG_CNPM_PRESCALER_GRP2_C3: Performance Monitor Prescaler Select; 00=22bit, 01=18bit, 10=10bit, 11=6bit Dial enums: P22=>0b00 P18=>0b01 P10=>0b10 P6=>0b11 | ||
| 24:25 | RW | PB_CFG_CNPM_PRESCALER_GRP3_C0: Performance Monitor Prescaler Select; 00=22bit, 01=18bit, 10=10bit, 11=6bit Dial enums: P22=>0b00 P18=>0b01 P10=>0b10 P6=>0b11 | ||
| 26:27 | RW | PB_CFG_CNPM_PRESCALER_GRP3_C1: Performance Monitor Prescaler Select; 00=22bit, 01=18bit, 10=10bit, 11=6bit Dial enums: P22=>0b00 P18=>0b01 P10=>0b10 P6=>0b11 | ||
| 28:29 | RW | PB_CFG_CNPM_PRESCALER_GRP3_C2: Performance Monitor Prescaler Select; 00=22bit, 01=18bit, 10=10bit, 11=6bit Dial enums: P22=>0b00 P18=>0b01 P10=>0b10 P6=>0b11 | ||
| 30:31 | RW | PB_CFG_CNPM_PRESCALER_GRP3_C3: Performance Monitor Prescaler Select; 00=22bit, 01=18bit, 10=10bit, 11=6bit Dial enums: P22=>0b00 P18=>0b01 P10=>0b10 P6=>0b11 | ||
| 32:33 | RW | PB_CFG_TLPM_PRESCALER_GRP0_C0: Performance Monitor Prescaler Select; 00=20bit, 01=16bit ,10=8bit, 11=4bit Dial enums: P20=>0b00 P16=>0b01 P8=>0b10 P4=>0b11 | ||
| 34:35 | RW | PB_CFG_TLPM_PRESCALER_GRP0_C1: Performance Monitor Prescaler Select; 00=20bit, 01=16bit ,10=8bit, 11=4bit Dial enums: P20=>0b00 P16=>0b01 P8=>0b10 P4=>0b11 | ||
| 36:37 | RW | PB_CFG_TLPM_PRESCALER_GRP0_C2: Performance Monitor Prescaler Select; 00=20bit, 01=16bit ,10=8bit, 11=4bit Dial enums: P20=>0b00 P16=>0b01 P8=>0b10 P4=>0b11 | ||
| 38:39 | RW | PB_CFG_TLPM_PRESCALER_GRP0_C3: Performance Monitor Prescaler Select; 00=20bit, 01=16bit ,10=8bit, 11=4bit Dial enums: P20=>0b00 P16=>0b01 P8=>0b10 P4=>0b11 | ||
| 40:41 | RW | PB_CFG_TLPM_PRESCALER_GRP1_C0: Performance Monitor Prescaler Select; 00=20bit, 01=16bit ,10=8bit, 11=4bit Dial enums: P20=>0b00 P16=>0b01 P8=>0b10 P4=>0b11 | ||
| 42:43 | RW | PB_CFG_TLPM_PRESCALER_GRP1_C1: Performance Monitor Prescaler Select; 00=20bit, 01=16bit ,10=8bit, 11=4bit Dial enums: P20=>0b00 P16=>0b01 P8=>0b10 P4=>0b11 | ||
| 44:45 | RW | PB_CFG_TLPM_PRESCALER_GRP1_C2: Performance Monitor Prescaler Select; 00=20bit, 01=16bit ,10=8bit, 11=4bit Dial enums: P20=>0b00 P16=>0b01 P8=>0b10 P4=>0b11 | ||
| 46:47 | RW | PB_CFG_TLPM_PRESCALER_GRP1_C3: Performance Monitor Prescaler Select; 00=20bit, 01=16bit ,10=8bit, 11=4bit Dial enums: P20=>0b00 P16=>0b01 P8=>0b10 P4=>0b11 | ||
| 48:49 | RW | PB_CFG_TLPM_PRESCALER_GRP2_C0: Performance Monitor Prescaler Select; 00=20bit, 01=16bit ,10=8bit, 11=4bit Dial enums: P20=>0b00 P16=>0b01 P8=>0b10 P4=>0b11 | ||
| 50:51 | RW | PB_CFG_TLPM_PRESCALER_GRP2_C1: Performance Monitor Prescaler Select; 00=20bit, 01=16bit ,10=8bit, 11=4bit Dial enums: P20=>0b00 P16=>0b01 P8=>0b10 P4=>0b11 | ||
| 52:53 | RW | PB_CFG_TLPM_PRESCALER_GRP2_C2: Performance Monitor Prescaler Select; 00=20bit, 01=16bit ,10=8bit, 11=4bit Dial enums: P20=>0b00 P16=>0b01 P8=>0b10 P4=>0b11 | ||
| 54:55 | RW | PB_CFG_TLPM_PRESCALER_GRP2_C3: Performance Monitor Prescaler Select; 00=20bit, 01=16bit ,10=8bit, 11=4bit Dial enums: P20=>0b00 P16=>0b01 P8=>0b10 P4=>0b11 | ||
| 56:57 | RW | PB_CFG_TLPM_PRESCALER_GRP3_C0: Performance Monitor Prescaler Select; 00=20bit, 01=16bit ,10=8bit, 11=4bit Dial enums: P20=>0b00 P16=>0b01 P8=>0b10 P4=>0b11 | ||
| 58:59 | RW | PB_CFG_TLPM_PRESCALER_GRP3_C1: Performance Monitor Prescaler Select; 00=20bit, 01=16bit ,10=8bit, 11=4bit Dial enums: P20=>0b00 P16=>0b01 P8=>0b10 P4=>0b11 | ||
| 60:61 | RW | PB_CFG_TLPM_PRESCALER_GRP3_C2: Performance Monitor Prescaler Select; 00=20bit, 01=16bit ,10=8bit, 11=4bit Dial enums: P20=>0b00 P16=>0b01 P8=>0b10 P4=>0b11 | ||
| 62:63 | RW | PB_CFG_TLPM_PRESCALER_GRP3_C3: Performance Monitor Prescaler Select; 00=20bit, 01=16bit ,10=8bit, 11=4bit Dial enums: P20=>0b00 P16=>0b01 P8=>0b10 P4=>0b11 | ||
| PowerBus Endcap PMU0_CNPM Counter reg | ||||
|---|---|---|---|---|
| Addr: |
0000000011011821 (SCOM) | |||
| Name: | PB.PTLSCOM23.PB_PMU0_CNPM_COUNTER | |||
| Constant(s): | ||||
| Comments: | 00:15 pb_event_pmu0_cnpmw_counter0(0:15) 16:31 pb_event_pmu0_cnpmw_counter1(0:15) 32:47 pb_event_pmu0_cnpmw_counter2(0:15) 48:63 pb_event_pmu0_cnpmw_counter3(0:15) | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:15 | PB.PTLSCOM23.PMU0.COUNTER0_CNT_Q_0_INST.LATC.L2(0:15) [0000000000000000] | |||
| 16:31 | PB.PTLSCOM23.PMU0.COUNTER1_CNT_Q_0_INST.LATC.L2(0:15) [0000000000000000] | |||
| 32:47 | PB.PTLSCOM23.PMU0.COUNTER2_CNT_Q_0_INST.LATC.L2(0:15) [0000000000000000] | |||
| 48:63 | PB.PTLSCOM23.PMU0.COUNTER3_CNT_Q_0_INST.LATC.L2(0:15) [0000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:15 | RWX_WCLRREG | pb_event_pmu0_cnpmw_counter0 | ||
| 16:31 | RWX_WCLRREG | pb_event_pmu0_cnpmw_counter1 | ||
| 32:47 | RWX_WCLRREG | pb_event_pmu0_cnpmw_counter2 | ||
| 48:63 | RWX_WCLRREG | pb_event_pmu0_cnpmw_counter3 | ||
| PowerBus Endcap PMU1_CNPM Counter reg | ||||
|---|---|---|---|---|
| Addr: |
0000000011011822 (SCOM) | |||
| Name: | PB.PTLSCOM23.PB_PMU1_CNPM_COUNTER | |||
| Constant(s): | ||||
| Comments: | 00:15 pb_event_pmu1_cnpmw_counter0(0:15) 16:31 pb_event_pmu1_cnpmw_counter1(0:15) 32:47 pb_event_pmu1_cnpmw_counter2(0:15) 48:63 pb_event_pmu1_cnpmw_counter3(0:15) | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:15 | PB.PTLSCOM23.PMU1.COUNTER0_CNT_Q_0_INST.LATC.L2(0:15) [0000000000000000] | |||
| 16:31 | PB.PTLSCOM23.PMU1.COUNTER1_CNT_Q_0_INST.LATC.L2(0:15) [0000000000000000] | |||
| 32:47 | PB.PTLSCOM23.PMU1.COUNTER2_CNT_Q_0_INST.LATC.L2(0:15) [0000000000000000] | |||
| 48:63 | PB.PTLSCOM23.PMU1.COUNTER3_CNT_Q_0_INST.LATC.L2(0:15) [0000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:15 | RWX_WCLRREG | pb_event_pmu1_cnpmw_counter0 | ||
| 16:31 | RWX_WCLRREG | pb_event_pmu1_cnpmw_counter1 | ||
| 32:47 | RWX_WCLRREG | pb_event_pmu1_cnpmw_counter2 | ||
| 48:63 | RWX_WCLRREG | pb_event_pmu1_cnpmw_counter3 | ||
| PowerBus Endcap PMU2_CNPM Counter reg | ||||
|---|---|---|---|---|
| Addr: |
0000000011011823 (SCOM) | |||
| Name: | PB.PTLSCOM23.PB_PMU2_CNPM_COUNTER | |||
| Constant(s): | ||||
| Comments: | 00:15 pb_event_pmu2_cnpmw_counter0(0:15) 16:31 pb_event_pmu2_cnpmw_counter1(0:15) 32:47 pb_event_pmu2_cnpmw_counter2(0:15) 48:63 pb_event_pmu2_cnpmw_counter3(0:15) | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:15 | PB.PTLSCOM23.PMU2.COUNTER0_CNT_Q_0_INST.LATC.L2(0:15) [0000000000000000] | |||
| 16:31 | PB.PTLSCOM23.PMU2.COUNTER1_CNT_Q_0_INST.LATC.L2(0:15) [0000000000000000] | |||
| 32:47 | PB.PTLSCOM23.PMU2.COUNTER2_CNT_Q_0_INST.LATC.L2(0:15) [0000000000000000] | |||
| 48:63 | PB.PTLSCOM23.PMU2.COUNTER3_CNT_Q_0_INST.LATC.L2(0:15) [0000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:15 | RWX_WCLRREG | pb_event_pmu2_cnpmw_counter0 | ||
| 16:31 | RWX_WCLRREG | pb_event_pmu2_cnpmw_counter1 | ||
| 32:47 | RWX_WCLRREG | pb_event_pmu2_cnpmw_counter2 | ||
| 48:63 | RWX_WCLRREG | pb_event_pmu2_cnpmw_counter3 | ||
| PowerBus Endcap PMU3_CNPM Counter reg | ||||
|---|---|---|---|---|
| Addr: |
0000000011011824 (SCOM) | |||
| Name: | PB.PTLSCOM23.PB_PMU3_CNPM_COUNTER | |||
| Constant(s): | ||||
| Comments: | 00:15 pb_event_pmu3_cnpmw_counter0(0:15) 16:31 pb_event_pmu3_cnpmw_counter1(0:15) 32:47 pb_event_pmu3_cnpmw_counter2(0:15) 48:63 pb_event_pmu3_cnpmw_counter3(0:15) | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:15 | PB.PTLSCOM23.PMU3.COUNTER0_CNT_Q_0_INST.LATC.L2(0:15) [0000000000000000] | |||
| 16:31 | PB.PTLSCOM23.PMU3.COUNTER1_CNT_Q_0_INST.LATC.L2(0:15) [0000000000000000] | |||
| 32:47 | PB.PTLSCOM23.PMU3.COUNTER2_CNT_Q_0_INST.LATC.L2(0:15) [0000000000000000] | |||
| 48:63 | PB.PTLSCOM23.PMU3.COUNTER3_CNT_Q_0_INST.LATC.L2(0:15) [0000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:15 | RWX_WCLRREG | pb_event_pmu3_cnpmw_counter0 | ||
| 16:31 | RWX_WCLRREG | pb_event_pmu3_cnpmw_counter1 | ||
| 32:47 | RWX_WCLRREG | pb_event_pmu3_cnpmw_counter2 | ||
| 48:63 | RWX_WCLRREG | pb_event_pmu3_cnpmw_counter3 | ||
| PowerBus AX TL Miscellaneous Config Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011011825 (SCOM) | |||
| Name: | PB.PTLSCOM23.PB_MISC_CFG | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:5 | PB.PTLSCOM23.MISC_CFG_Q_0_INST.LATC.L2(0:5) [000000] | |||
| 6:7 | PB.PTLSCOM23.MISC_CFG_Q_6_INST.LATC.L2(6:7) [00] | |||
| 8:51 | PB.PTLSCOM23.MISC_CFG_Q_8_INST.LATC.L2(8:51) [00000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | RW | SCOM_PTLX0_ENABLE: enable x0 TL | ||
| 1 | RW | SCOM_PTLX1_ENABLE: enable x1 TL | ||
| 2 | RW | SCOM_PTLY0_ENABLE: enable y0 TL | ||
| 3 | RW | SCOM_PTLY1_ENABLE: enable y1 TL | ||
| 4 | RW | SCOM_PTLX_IS_LOGICAL_PAIR: ptlx is a logical pair | ||
| 5 | RW | SCOM_PTLY_IS_LOGICAL_PAIR: ptly is a logical pair | ||
| 6 | WO_1P | SCOM_PTLX_RESET_KEEPER: scom ptlx reset keeper - resets all the c_err_report regs in the even PTL in this corner. | ||
| 7 | WO_1P | SCOM_PTLY_RESET_KEEPER: scom ptly reset keeper - resets all the c_err_report regs in the odd PTL in this corner. | ||
| 8 | RW | TRANSPORT_0_ENABLE: transport 0 enable | ||
| 9 | RW | TRANSPORT_1_ENABLE: transport 1 enable | ||
| 10 | RW | TRANSPORT_2_ENABLE: transport 2 enable | ||
| 11 | RW | TRANSPORT_3_ENABLE: transport 3 enable | ||
| 12 | RW | TRANSPORT_0_IB_MUX_CTL0: transport 0 ib mux ctl0 | ||
| 13 | RW | TRANSPORT_PAU0_EVN_IB_MUX_EN: PAU 4/6 even inbound mux clock enable. (PAU 0/3 have no mux). | ||
| 14 | RW | TRANSPORT_1_IB_MUX_CTL0: transport 1 ib mux ctl0 | ||
| 15 | RW | TRANSPORT_PAU0_ODD_IB_MUX_EN: PAU 4/6 odd inbound mux clock enable. (PAU 0/3 have no mux). | ||
| 16 | RW | TRANSPORT_2_IB_MUX_CTL0: transport 2 ib mux ctl0 | ||
| 17 | RW | TRANSPORT_PAU1_EVN_IB_MUX_EN: PAU 5/7 even inbound mux clock enable. | ||
| 18 | RW | TRANSPORT_3_IB_MUX_CTL0: transport 3 ib mux ctl0 | ||
| 19 | RW | TRANSPORT_PAU1_ODD_IB_MUX_EN: PAU 5/7 odd inbound mux clock enable. | ||
| 20 | RW | TRANSPORT_0_OB_MUX_CTL0: transport 0 ob mux ctl0 | ||
| 21 | RW | TRANSPORT_0_OB_MUX_CTL1: transport 0 ob mux ctl1 | ||
| 22 | RW | TRANSPORT_0_OB_MUX_CTL2: transport 0 ob mux ctl2 | ||
| 23 | RW | TRANSPORT_0_OB_MUX_CTL3: transport 0 ob mux ctl3 | ||
| 24 | RW | TRANSPORT_1_OB_MUX_CTL0: transport 1 ob mux ctl0 | ||
| 25 | RW | TRANSPORT_1_OB_MUX_CTL1: transport 1 ob mux ctl1 | ||
| 26 | RW | TRANSPORT_1_OB_MUX_CTL2: transport 1 ob mux ctl2 | ||
| 27 | RW | TRANSPORT_1_OB_MUX_CTL3: transport 1 ob mux ctl3 | ||
| 28 | RW | TRANSPORT_2_OB_MUX_CTL0: transport 2 ob mux ctl0 | ||
| 29 | RW | TRANSPORT_2_OB_MUX_CTL1: transport 2 ob mux ctl1 | ||
| 30 | RW | TRANSPORT_2_OB_MUX_CTL2: transport 2 ob mux ctl2 | ||
| 31 | RW | TRANSPORT_2_OB_MUX_CTL3: transport 2 ob mux ctl3 | ||
| 32 | RW | TRANSPORT_3_OB_MUX_CTL0: transport 3 ob mux ctl0 | ||
| 33 | RW | TRANSPORT_3_OB_MUX_CTL1: transport 3 ob mux ctl1 | ||
| 34 | RW | TRANSPORT_3_OB_MUX_CTL2: transport 3 ob mux ctl2 | ||
| 35 | RW | TRANSPORT_3_OB_MUX_CTL3: transport 3 ob mux ctl3 | ||
| 36 | RW | SCOM_PTLX_EMULATION_MODE: PTLX Emulation mode. This PTL will generate fake null presps for outbound commands, and this PTL should be otherwise disabled and not connected to any other chip. (CDial PTLX_mode=OFF). Important: The PB_TL_LINK_DATA_01_CFG_REG / CDIAL PTLX_EMULATION_MODE_CFG must be properly configured before turning emulation mode on. | ||
| 37 | RW | SCOM_PTLY_EMULATION_MODE: PTLY Emulation mode. This PTL will generate fake null presps for outbound commands, and this PTL should be otherwise disabled and not connected to any other chip. (CDial PTLY_mode=OFF). Important: The PB_TL_LINK_DATA_23_CFG_REG / CDIAL PTLY_EMULATION_MODE_CFG must be properly configured before turning emulation mode on. | ||
| 38 | RW | TRANSPORT_PRI_BUS_CTL: NPU PRI bus mux control. Used to control the PRI bus crossbar switch. See the PB-level PRI_##_CFG CDIALs. 0=route each PAU to its matching OPT. 1=cross the connections. | ||
| 39 | RW | ENABLE_DEGRADED_MODE: Enable degraded mode - if a logical pair goes to quarter mode, or fails down to half width, double the value of ptlx_rcmd_rate and ptly_rcmd_rate. If you use this mode, you need to account for it in your epsilon calculations as it increases command latency through the outbound async crossing. | ||
| 40 | RW | HW517132_DISABLE: Disable the fix for HW517132 - PTLSCOM fails to detect half-link has come back up. | ||
| 41:51 | RW | MISC_SPARE: misc spare | ||
| PowerBus TL Link Trace Config Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011011826 (SCOM) | |||
| Name: | PB.PTLSCOM23.PB_TRACE_CFG | |||
| Constant(s): | ||||
| Comments: | 8-bit trace group encodes: bit 2 is used by each ptl as a evn/odd PTL match indicator bit 3 is used by fmr/prs as a evn/odd half-link match indicator 00 - disabled 01 - ptlevn evn inbound link 02 - ptlevn evn inbnd dhdr 03 - ptlevn 0s 04 - ptlevn evn outbnd dhdr 05 - ptlevn evn outbnd link 06 - ptlevn 0s 07 - ptlevn dob grants 08 - ptlevn dob eb grp0 09 - ptlevn dob eb grp1 0A - ptlevn dob eb grp2 0B - ptlevn dob eb grp3 0C - ptlevn dob wb grp0 0D - ptlevn dob wb grp1 0E - ptlevn dob wb grp2 0F - ptlevn dob wb grp3 10 - ptlevn 0s 11 - ptlevn odd inbound link 12 - ptlevn odd inbnd dhdr pos 0 13 - ptlevn 0s 14 - ptlevn odd outbnd dhdr pos 0 15 - ptlevn odd outbound link 16 - ptlevn 0s 17 - ptlevn 0s 18 - ptlevn dib wins 1A - ptlevn dib evn dhdr 1B - ptlevn dib odd dhdr 1C - ptlevn 0s 1D - ptlevn 0s 1E - ptlevn 0s 1F - perftrace_en 20 - disabled 21 - ptlodd evn inbound link 22 - ptlodd evn inbnd dhdr 23 - ptlodd 0s 24 - ptlodd evn outbnd dhdr 25 - ptlodd evn outbnd link 26 - ptlodd 0s 27 - ptlodd dob grants 28 - ptlodd dob eb grp0 29 - ptlodd dob eb grp1 2A - ptlodd dob eb grp2 2B - ptlodd dob eb grp3 2C - ptlodd dob wb grp0 2D - ptlodd dob wb grp1 2E - ptlodd dob wb grp2 2F - ptlodd dob wb grp3 30 - ptlodd 0s 31 - ptlodd odd inbound link 32 - ptlodd odd inbnd dhdr pos 0 33 - ptlodd 0s 34 - ptlodd odd outbnd dhdr pos 0 35 - ptlodd odd outbound link 36 - ptlodd 0s 37 - ptlodd 0s 38 - ptlodd dib wins 3A - ptlodd dib evn dhdr 3B - ptlodd dib odd dhdr 3C - ptlodd 0s 3D - ptlodd 0s 3E - ptlodd 0s 3F - perftrace_en | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:31 | PB.PTLSCOM23.TRACE_CFG_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:7 | RW | PTL_CFG_TRACE0L_SEL: ptl cfg trace0 left half bus select | ||
| 8:15 | RW | PTL_CFG_TRACE0R_SEL: ptl cfg trace0 right half bus select | ||
| 16:23 | RW | PTL_CFG_TRACE1L_SEL: ptl cfg trace1 left half bus select | ||
| 24:31 | RW | PTL_CFG_TRACE1R_SEL: ptl cfg trace1 right half bus select | ||
| PowerBus TL LINK Framer0123 Error Readout Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011011827 (SCOM) | |||
| Name: | PB.PTLSCOM23.PB_FM0123_ERR | |||
| Constant(s): | ||||
| Comments: | Can be reset via scom_ptlx_reset_keeper and/or scom_ptly_reset_keeper. (Which also resets all the related c_err_rpt regs.) | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:15 | PB.PTLSCOM23.PTLX_SCOM_FMR0_ERR_BUS_Q_0_INST.LATC.L2(0:15) [0000000000000000] | |||
| 16:31 | PB.PTLSCOM23.PTLX_SCOM_FMR1_ERR_BUS_Q_0_INST.LATC.L2(0:15) [0000000000000000] | |||
| 32:47 | PB.PTLSCOM23.PTLY_SCOM_FMR0_ERR_BUS_Q_0_INST.LATC.L2(0:15) [0000000000000000] | |||
| 48:63 | PB.PTLSCOM23.PTLY_SCOM_FMR1_ERR_BUS_Q_0_INST.LATC.L2(0:15) [0000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | ROX | fmr0_control_error | ||
| 1 | ROX | fmr0_addr_perr | ||
| 2 | ROX | fmr0_cc0_crediterr | ||
| 3 | ROX | fmr0_cc1_crediterr | ||
| 4 | ROX | fmr0_cc2_crediterr | ||
| 5 | ROX | fmr0_cc3_crediterr | ||
| 6 | ROX | fmr0_dat_hi_perr | ||
| 7 | ROX | fmr0_dat_lo_perr | ||
| 8 | ROX | fmr0_frame_crediterr | ||
| 9 | ROX | fmr0_internal_err | ||
| 10 | ROX | fmr0_prsp_ptyerr | ||
| 11 | ROX | fmr0_ttag_perr | ||
| 12 | ROX | fmr0_vc0_crediterr | ||
| 13 | ROX | fmr0_vc1_crediterr | ||
| 14 | ROX | fmr0_rtag_ptyerr | ||
| 15 | ROX | fmr0_rtag_misc_pty | ||
| 16 | ROX | fmr1_control_error | ||
| 17 | ROX | fmr1_addr_perr | ||
| 18 | ROX | fmr1_cc0_crediterr | ||
| 19 | ROX | fmr1_cc1_crediterr | ||
| 20 | ROX | fmr1_cc2_crediterr | ||
| 21 | ROX | fmr1_cc3_crediterr | ||
| 22 | ROX | fmr1_dat_hi_perr | ||
| 23 | ROX | fmr1_dat_lo_perr | ||
| 24 | ROX | fmr1_frame_crediterr | ||
| 25 | ROX | fmr1_internal_err | ||
| 26 | ROX | fmr1_prsp_ptyerr | ||
| 27 | ROX | fmr1_ttag_perr | ||
| 28 | ROX | fmr1_vc0_crediterr | ||
| 29 | ROX | fmr1_vc1_crediterr | ||
| 30 | ROX | fmr1_rtag_ptyerr | ||
| 31 | ROX | fmr1_rtag_misc_pty | ||
| 32 | ROX | fmr2_control_error | ||
| 33 | ROX | fmr2_addr_perr | ||
| 34 | ROX | fmr2_cc0_crediterr | ||
| 35 | ROX | fmr2_cc1_crediterr | ||
| 36 | ROX | fmr2_cc2_crediterr | ||
| 37 | ROX | fmr2_cc3_crediterr | ||
| 38 | ROX | fmr2_dat_hi_perr | ||
| 39 | ROX | fmr2_dat_lo_perr | ||
| 40 | ROX | fmr2_frame_crediterr | ||
| 41 | ROX | fmr2_internal_err | ||
| 42 | ROX | fmr2_prsp_ptyerr | ||
| 43 | ROX | fmr2_ttag_perr | ||
| 44 | ROX | fmr2_vc0_crediterr | ||
| 45 | ROX | fmr2_vc1_crediterr | ||
| 46 | ROX | fmr2_rtag_ptyerr | ||
| 47 | ROX | fmr2_rtag_misc_pty | ||
| 48 | ROX | fmr3_control_error | ||
| 49 | ROX | fmr3_addr_perr | ||
| 50 | ROX | fmr3_cc0_crediterr | ||
| 51 | ROX | fmr3_cc1_crediterr | ||
| 52 | ROX | fmr3_cc2_crediterr | ||
| 53 | ROX | fmr3_cc3_crediterr | ||
| 54 | ROX | fmr3_dat_hi_perr | ||
| 55 | ROX | fmr3_dat_lo_perr | ||
| 56 | ROX | fmr3_frame_crediterr | ||
| 57 | ROX | fmr3_internal_err | ||
| 58 | ROX | fmr3_prsp_ptyerr | ||
| 59 | ROX | fmr3_ttag_perr | ||
| 60 | ROX | fmr3_vc0_crediterr | ||
| 61 | ROX | fmr3_vc1_crediterr | ||
| 62 | ROX | fmr3_rtag_ptyerr | ||
| 63 | ROX | fmr3_rtag_misc_pty | ||
| PowerBus TL Link DOB01/DIB01 internal errors | ||||
|---|---|---|---|---|
| Addr: |
0000000011011828 (SCOM) | |||
| Name: | PB.PTLSCOM23.PB_DOB01_DIB01_INT_ERR_REG | |||
| Constant(s): | ||||
| Comments: | Can be reset via scom_ptlx_reset_keeper and/or scom_ptly_reset_keeper. (Which also resets all the related c_err_rpt regs.) | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:51 | PB.PTLSCOM23.PTLX_SCOM_DOBDIB01_ERR_BUS_Q_0_INST.LATC.L2(0:51) [0000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | ROX | dob01_rtag_pbiterr | ||
| 1 | ROX | dob01_rtag_perr | ||
| 2 | ROX | dob01_misc_perr | ||
| 3 | ROX | dob01_f0vc0_evenperr | ||
| 4 | ROX | dob01_f0vc0_oddperr | ||
| 5 | ROX | dob01_f0vc1_evenperr | ||
| 6 | ROX | dob01_f0vc1_oddperr | ||
| 7 | ROX | dob01_f1vc0_evenperr | ||
| 8 | ROX | dob01_f1vc0_oddperr | ||
| 9 | ROX | dob01_f1vc1_evenperr | ||
| 10 | ROX | dob01_f1vc1_oddperr | ||
| 11 | ROX | dob01_f0_underflow | ||
| 12 | ROX | dob01_f0_overflow | ||
| 13 | ROX | dob01_f1_underflow | ||
| 14 | ROX | dob01_f1_overflow | ||
| 15 | ROX | dob01_vc0_underflow | ||
| 16 | ROX | dob01_vc0_overflow | ||
| 17 | ROX | dob01_vc1_underflow | ||
| 18 | ROX | dob01_vc1_overflow | ||
| 19 | ROX | dob01_f0vc0_underflow | ||
| 20 | ROX | dob01_f0vc0_overflow | ||
| 21 | ROX | dob01_f0vc1_underflow | ||
| 22 | ROX | dob01_f0vc1_overflow | ||
| 23 | ROX | dob01_f1vc0_underflow | ||
| 24 | ROX | dob01_f1vc0_overflow | ||
| 25 | ROX | dob01_f1vc1_underflow | ||
| 26 | ROX | dob01_f1vc1_overflow | ||
| 27 | ROX | dob01_vc0_prefetch_overflow | ||
| 28 | ROX | dob01_vc1_prefetch_overflow | ||
| 29 | ROX | dib01_evn0_underflow | ||
| 30 | ROX | dib01_evn0_overflow | ||
| 31 | ROX | dib01_evn1_underflow | ||
| 32 | ROX | dib01_evn1_overflow | ||
| 33 | ROX | dib01_rtag_pbiterr | ||
| 34 | ROX | dib01_rtag_perr | ||
| 35 | ROX | dib01_misc_perr | ||
| 36 | ROX | dib01_odd0_underflow | ||
| 37 | ROX | dib01_odd0_overflow | ||
| 38 | ROX | dib01_odd1_underflow | ||
| 39 | ROX | dib01_odd1_overflow | ||
| 40 | ROX | dib01_rtag_underflow | ||
| 41 | ROX | dib01_rtag_overflow | ||
| 42 | ROX | dib01_data_underflow | ||
| 43 | ROX | dib01_data_overflow | ||
| 44 | ROX | dib01_vc0_underflow | ||
| 45 | ROX | dib01_vc0_overflow | ||
| 46 | ROX | dib01_vc1_underflow | ||
| 47 | ROX | dib01_vc1_overflow | ||
| 48 | ROX | dob01_f0vc0_over_underflow | ||
| 49 | ROX | dob01_f0vc1_over_underflow | ||
| 50 | ROX | dob01_f1vc0_over_underflow | ||
| 51 | ROX | dob01_f1vc1_over_underflow | ||
| PowerBus TL LINK Parser0123 Error Readout Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011011829 (SCOM) | |||
| Name: | PB.PTLSCOM23.PB_PR0123_ERR | |||
| Constant(s): | ||||
| Comments: | note: the data parity error is byte parity across 16 bytes. You can isolate the byte via a matching PB.PTL#.pr#.dat_perrq_e register bit if you generate a scan ring dump. This register can be reset via scom_ptlx_reset_keeper and/or scom_ptly_reset_keeper. (Which also resets all the related c_err_rpt regs.) | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:12 | PB.PTLSCOM23.PTLX_SCOM_PRS0_ERR_BUS_Q_0_INST.LATC.L2(0:12) [0000000000000] | |||
| 13 | PB.PTLSCOM23.LINK_DOWNQ_E.HOLD_LATCH_INST.HOLD.LATC.L2(0) [0] | |||
| 16:28 | PB.PTLSCOM23.PTLX_SCOM_PRS1_ERR_BUS_Q_0_INST.LATC.L2(0:12) [0000000000000] | |||
| 29 | PB.PTLSCOM23.LINK_DOWNQ_E.HOLD_LATCH_INST.HOLD.LATC.L2(1) [0] | |||
| 32:44 | PB.PTLSCOM23.PTLY_SCOM_PRS0_ERR_BUS_Q_0_INST.LATC.L2(0:12) [0000000000000] | |||
| 45 | PB.PTLSCOM23.LINK_DOWNQ_E.HOLD_LATCH_INST.HOLD.LATC.L2(2) [0] | |||
| 48:60 | PB.PTLSCOM23.PTLY_SCOM_PRS1_ERR_BUS_Q_0_INST.LATC.L2(0:12) [0000000000000] | |||
| 61 | PB.PTLSCOM23.LINK_DOWNQ_E.HOLD_LATCH_INST.HOLD.LATC.L2(3) [0] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | ROX | prs0_address_pty | ||
| 1 | ROX | prs0_atag_pty | ||
| 2 | ROX | prs0_cc0_crediterr | ||
| 3 | ROX | prs0_cc1_crediterr | ||
| 4 | ROX | prs0_cc2_crediterr | ||
| 5 | ROX | prs0_cc3_crediterr | ||
| 6 | ROX | prs0_control_error | ||
| 7 | ROX | prs0_data_pty_err | ||
| 8 | ROX | prs0_rtag_misc_pty | ||
| 9 | ROX | prs0_rtag_pty | ||
| 10 | ROX | prs0_ttag_pty | ||
| 11 | ROX | prs0_vc0_crediterr | ||
| 12 | ROX | prs0_vc1_crediterr | ||
| 13 | ROX | LINK_DOWNQ_E_HOLD: Link Down Error. Link was up, but has gone completely down. 1 bit per half-link in this chip corner. A link that is configured as is_logical_pair will not fire an error until both halves go down. | ||
| 14:15 | RO | constant=0b00 | ||
| 16 | ROX | prs1_address_pty | ||
| 17 | ROX | prs1_atag_pty | ||
| 18 | ROX | prs1_cc0_crediterr | ||
| 19 | ROX | prs1_cc1_crediterr | ||
| 20 | ROX | prs1_cc2_crediterr | ||
| 21 | ROX | prs1_cc3_crediterr | ||
| 22 | ROX | prs1_control_error | ||
| 23 | ROX | prs1_data_pty_err | ||
| 24 | ROX | prs1_rtag_misc_pty | ||
| 25 | ROX | prs1_rtag_pty | ||
| 26 | ROX | prs1_ttag_pty | ||
| 27 | ROX | prs1_vc0_crediterr | ||
| 28 | ROX | prs1_vc1_crediterr | ||
| 29 | ROX | LINK_DOWNQ_E_HOLD: Link Down Error. Link was up, but has gone completely down. 1 bit per half-link in this chip corner. A link that is configured as is_logical_pair will not fire an error until both halves go down. | ||
| 30:31 | RO | constant=0b00 | ||
| 32 | ROX | prs2_address_pty | ||
| 33 | ROX | prs2_atag_pty | ||
| 34 | ROX | prs2_cc0_crediterr | ||
| 35 | ROX | prs2_cc1_crediterr | ||
| 36 | ROX | prs2_cc2_crediterr | ||
| 37 | ROX | prs2_cc3_crediterr | ||
| 38 | ROX | prs2_control_error | ||
| 39 | ROX | prs2_data_pty_err | ||
| 40 | ROX | prs2_rtag_misc_pty | ||
| 41 | ROX | prs2_rtag_pty | ||
| 42 | ROX | prs2_ttag_pty | ||
| 43 | ROX | prs2_vc0_crediterr | ||
| 44 | ROX | prs2_vc1_crediterr | ||
| 45 | ROX | LINK_DOWNQ_E_HOLD: Link Down Error. Link was up, but has gone completely down. 1 bit per half-link in this chip corner. A link that is configured as is_logical_pair will not fire an error until both halves go down. | ||
| 46:47 | RO | constant=0b00 | ||
| 48 | ROX | prs3_address_pty | ||
| 49 | ROX | prs3_atag_pty | ||
| 50 | ROX | prs3_cc0_crediterr | ||
| 51 | ROX | prs3_cc1_crediterr | ||
| 52 | ROX | prs3_cc2_crediterr | ||
| 53 | ROX | prs3_cc3_crediterr | ||
| 54 | ROX | prs3_control_error | ||
| 55 | ROX | prs3_data_pty_err | ||
| 56 | ROX | prs3_rtag_misc_pty | ||
| 57 | ROX | prs3_rtag_pty | ||
| 58 | ROX | prs3_ttag_pty | ||
| 59 | ROX | prs3_vc0_crediterr | ||
| 60 | ROX | prs3_vc1_crediterr | ||
| 61 | ROX | LINK_DOWNQ_E_HOLD: Link Down Error. Link was up, but has gone completely down. 1 bit per half-link in this chip corner. A link that is configured as is_logical_pair will not fire an error until both halves go down. | ||
| 62:63 | RO | constant=0b00 | ||
| PowerBus TL Link DOB23/DIB23 internal errors | ||||
|---|---|---|---|---|
| Addr: |
000000001101182A (SCOM) | |||
| Name: | PB.PTLSCOM23.PB_DOB23_DIB23_INT_ERR_REG | |||
| Constant(s): | ||||
| Comments: | This register can be reset via scom_ptlx_reset_keeper and/or scom_ptly_reset_keeper. (Which also resets all the related c_err_rpt regs.) | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:51 | PB.PTLSCOM23.PTLX_SCOM_DOBDIB23_ERR_BUS_Q_0_INST.LATC.L2(0:51) [0000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | ROX | dob23_rtag_pbiterr | ||
| 1 | ROX | dob23_rtag_perr | ||
| 2 | ROX | dob23_misc_perr | ||
| 3 | ROX | dob23_f0vc0_evenperr | ||
| 4 | ROX | dob23_f0vc0_oddperr | ||
| 5 | ROX | dob23_f0vc1_evenperr | ||
| 6 | ROX | dob23_f0vc1_oddperr | ||
| 7 | ROX | dob23_f1vc0_evenperr | ||
| 8 | ROX | dob23_f1vc0_oddperr | ||
| 9 | ROX | dob23_f1vc1_evenperr | ||
| 10 | ROX | dob23_f1vc1_oddperr | ||
| 11 | ROX | dob23_f0_underflow | ||
| 12 | ROX | dob23_f0_overflow | ||
| 13 | ROX | dob23_f1_underflow | ||
| 14 | ROX | dob23_f1_overflow | ||
| 15 | ROX | dob23_vc0_underflow | ||
| 16 | ROX | dob23_vc0_overflow | ||
| 17 | ROX | dob23_vc1_underflow | ||
| 18 | ROX | dob23_vc1_overflow | ||
| 19 | ROX | dob23_f0vc0_underflow | ||
| 20 | ROX | dob23_f0vc0_overflow | ||
| 21 | ROX | dob23_f0vc1_underflow | ||
| 22 | ROX | dob23_f0vc1_overflow | ||
| 23 | ROX | dob23_f1vc0_underflow | ||
| 24 | ROX | dob23_f1vc0_overflow | ||
| 25 | ROX | dob23_f1vc1_underflow | ||
| 26 | ROX | dob23_f1vc1_overflow | ||
| 27 | ROX | dob23_vc0_prefetch_overflow | ||
| 28 | ROX | dob23_vc1_prefetch_overflow | ||
| 29 | ROX | dib23_evn0_underflow | ||
| 30 | ROX | dib23_evn0_overflow | ||
| 31 | ROX | dib23_evn1_underflow | ||
| 32 | ROX | dib23_evn1_overflow | ||
| 33 | ROX | dib23_rtag_pbiterr | ||
| 34 | ROX | dib23_rtag_perr | ||
| 35 | ROX | dib23_misc_perr | ||
| 36 | ROX | dib23_odd0_underflow | ||
| 37 | ROX | dib23_odd0_overflow | ||
| 38 | ROX | dib23_odd1_underflow | ||
| 39 | ROX | dib23_odd1_overflow | ||
| 40 | ROX | dib23_rtag_underflow | ||
| 41 | ROX | dib23_rtag_overflow | ||
| 42 | ROX | dib23_data_underflow | ||
| 43 | ROX | dib23_data_overflow | ||
| 44 | ROX | dib23_vc0_underflow | ||
| 45 | ROX | dib23_vc0_overflow | ||
| 46 | ROX | dib23_vc1_underflow | ||
| 47 | ROX | dib23_vc1_overflow | ||
| 48 | ROX | dob23_dibf0vc0_over_underflow | ||
| 49 | ROX | dob23_dibf0vc1_over_underflow | ||
| 50 | ROX | dob23_dibf1vc0_over_underflow | ||
| 51 | ROX | dob23_dibf1vc1_over_underflow | ||
| PowerBus TL LINK Perftrace Config Register | ||||
|---|---|---|---|---|
| Addr: |
000000001101182B (SCOM) | |||
| Name: | PB.PTLSCOM23.PB_PERFTRACE_CFG_REG | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:11 | PB.PTLSCOM23.PERFTRACE_CFG_Q_0_INST.LATC.L2(0:11) [000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | RW | PERFTRACE_HI_ENABLE: perftrace hi enable - mux perftrace data onto trace bus 0 | ||
| 1 | RW | PERFTRACE_HI_FIXED_WINDOW_MODE: perftrace hi fixed window mode - take a sample every 255 or 255x128 cycles | ||
| 2 | RW | PERFTRACE_HI_PRESCALE_MODE: perftrace hi prescale mode - wide-angle view - perfcounts are prescaled by 128 | ||
| 3 | RW | PTSPARE6: ptspare6 | ||
| 4 | RW | PERFTRACE_LO_ENABLE: perftrace lo enable - mux perftrace data onto trace bus 1 | ||
| 5 | RW | PERFTRACE_LO_FIXED_WINDOW_MODE: perftrace lo fixed window mode - take a sample every 255 or 255x128 cycles | ||
| 6 | RW | PERFTRACE_LO_PRESCALE_MODE: perftrace lo prescale mode - wide-angle view - perfcounts are prescaled by 128 | ||
| 7 | RW | PTSPARE7: ptspare7 | ||
| 8:9 | RW | PERFTRACE_HI_SELECT: perftrace hi select - which 10 events get counted on the hi trace bus: 0=count tlpmu_ebus_q(0 to 9), 1=count tlpmu_ebus_q(16 to 25), 2=count pb_ptlscom_ebus(0 to 9), 3=count pb_ptlscom_ebus(16 to 25) | ||
| 10:11 | RW | PERFTRACE_LO_SELECT: perftrace lo select - which 10 events get counted on the lo trace bus: 0=count tlpmu_ebus_q(0 to 9), 1=count tlpmu_ebus_q(16 to 25), 2=count pb_ptlscom_ebus(0 to 9), 3=count pb_ptlscom_ebus(16 to 25) | ||
| PowerBus TL PMU Event Selection Control Register | ||||
|---|---|---|---|---|
| Addr: |
000000001101182C (SCOM) | |||
| Name: | PB.PTLSCOM23.PB_CFG_TLPM_MUX1_REG | |||
| Constant(s): | ||||
| Comments: | There are a total of 16 event select dials, 9 here, and 7 more in PB_CFG_TLPM_MUX2_REG. These choose 16 events from each link and place them on the 32-bit TL event bus for counting by the TL pmulets. In addition, bit 63 selects which event bus format to use - see the description of the alt_events dial. The event select encodes are: event code (decimal) event 0 framer0 - nothing 1 framer0 - any rcmd - event 2 framer0 - cresp - event 3 framer0 - any presp - event 4 framer0 - dhdr - event 5 framer0 - data - event 6 framer0 - credit - event 7 framer0 - rcmd drop - event 8 framer0 - presp drop - dropped at this chip - event 9 framer0 - presp drop - dropped at remote chip - event 10 framer0 - cmd utilization n/16 per available cycle 11 framer0 - presp util n/16 per available cycle 12 framer0 - dhdr+data util n/16 per available cycle 13 framer0 - total utilization n/16 per available cycle 14 framer0 - cycles (available)(generally 4/5, unless replays happening) - event 15 framer0 - tdm_mode cycles (raw) - event 16 parser0 - nothing 17 parser0 - any rcmd - event 18 parser0 - cresp - event 19 parser0 - any presp - event 20 parser0 - dhdr - event 21 parser0 - data - event 22 parser0 - credit - event 23 parser0 - rcmd drop - event 24 parser0 - presp drop - dropped at this chip - event 25 parser0 - presp drop - dropped at remote chip - event 26 parser0 - cmd utilization n/16 per available cycle 27 parser0 - presp util n/16 per available cycle 28 parser0 - dhdr+data util n/16 per available cycle 29 parser0 - total utilization n/16 per available cycle 30 parser0 - cycles (available)(generally 4/5, unless replays happening) - event 31 parser0 - tdm_mode cycles (raw) - event 32 framer1 - nothing 33 framer1 - any rcmd - event 34 framer1 - cresp - event 35 framer1 - any presp - event 36 framer1 - dhdr - event 37 framer1 - data - event 38 framer1 - credit - event 39 framer1 - rcmd drop - event 40 framer1 - presp drop - dropped at this chip - event 41 framer1 - presp drop - dropped at remote chip - event 42 framer1 - cmd utilization n/16 per available cycle 43 framer1 - presp util n/16 per available cycle 44 framer1 - dhdr+data util n/16 per available cycle 45 framer1 - total utilization n/16 per available cycle 46 framer1 - cycles (available)(generally 4/5, unless replays happening) - event 47 framer1 - tdm_mode cycles (raw) - event 48 parser1 - nothing 49 parser1 - any rcmd - event 50 parser1 - cresp - event 51 parser1 - any presp - event 52 parser1 - dhdr - event 53 parser1 - data - event 54 parser1 - credit - event 55 parser1 - rcmd drop - event 56 parser1 - presp drop - dropped at this chip - event 57 parser1 - presp drop - dropped at remote chip - event 58 parser1 - cmd utilization n/16 per available cycle 59 parser1 - presp util n/16 per available cycle 60 parser1 - dhdr+data util n/16 per available cycle 61 parser1 - total utilization n/16 per available cycle 62 parser1 - cycles (available)(generally 4/5, unless replays happening) - event 63 parser1 - tdm_mode cycles (raw) - event 64 DOB west f0vc0 rtag cache entry evicted 65 DOB west f0vc1 rtag cache entry evicted 66 DOB west f1vc0 rtag cache entry evicted 67 DOB west f1vc1 rtag cache entry evicted 68 DOB west f0vc0 rtag cache entry 3+ hits 69 DOB west f0vc1 rtag cache entry 3+ hits 70 DOB west f1vc0 rtag cache entry 3+ hits 71 DOB west f1vc1 rtag cache entry 3+ hits 72 DOB west vc0 OW sent to fmr0 73 DOB west vc1 OW sent to fmr0 74 DOB west vc0 OW sent to fmr1 75 DOB west vc1 OW sent to fmr1 76 DOB west OW latency total (one OW tracked at a time) 77 DOB west OW latency event (total/event = avg. latency through DOB) (one OW tracked at a time) 78 DOB west OW count - all 79 DOB west OW rtag cache hit 80 DOB east f0vc0 rtag cache entry evicted 81 DOB east f0vc1 rtag cache entry evicted 82 DOB east f1vc0 rtag cache entry evicted 83 DOB east f1vc1 rtag cache entry evicted 84 DOB east f0vc0 rtag cache entry 3+ hits 85 DOB east f0vc1 rtag cache entry 3+ hits 86 DOB east f1vc0 rtag cache entry 3+ hits 87 DOB east f1vc1 rtag cache entry 3+ hits 88 DOB east vc0 OW sent to fmr0 89 DOB east vc1 OW sent to fmr0 90 DOB east vc0 OW sent to fmr1 91 DOB east vc1 OW sent to fmr1 92 DOB east OW latency total (one OW tracked at a time) 93 DOB east OW latency event (total/event = avg. latency through DOB) (one OW tracked at a time) 94 DOB east OW count - all 95 DOB east OW rtag cache hit 96-127 reserved | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PB.PTLSCOM23.TLPM_MUX1_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:6 | RW | LINK_EVENT_0: link event 0 selector | ||
| 7:13 | RW | LINK_EVENT_1: link event 1 selector | ||
| 14:20 | RW | LINK_EVENT_2: link event 2 selector | ||
| 21:27 | RW | LINK_EVENT_3: link event 3 selector | ||
| 28:34 | RW | LINK_EVENT_4: link event 4 selector | ||
| 35:41 | RW | LINK_EVENT_5: link event 5 selector | ||
| 42:48 | RW | LINK_EVENT_6: link event 6 selector | ||
| 49:55 | RW | LINK_EVENT_7: link event 7 selector | ||
| 56:62 | RW | LINK_EVENT_8: link event 8 selector | ||
| 63 | RW | ALT_EVENTS: Event configurator: 0 = Even PTL events 0:15 on even event bits 0:30, and Odd PTL events 0:15 on odd event bits 1:31 1 = Even PTL events 0:15 on event bits 0:15, and Odd PTL events 0:15 on event bits 16:31 | ||
| PowerBus TL PMU Event Selection Control Register | ||||
|---|---|---|---|---|
| Addr: |
000000001101182D (SCOM) | |||
| Name: | PB.PTLSCOM23.PB_CFG_TLPM_MUX2_REG | |||
| Constant(s): | ||||
| Comments: | There are a total of 16 event select dials, 7 here, and 9 more in PB_CFG_TLPM_MUX1_REG. These choose 16 events from each link and place them on the 32-bit TL event bus for counting by the TL pmulets. See the event select encodes in the PB_CFG_TLPM_MUX1_REG section | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:48 | PB.PTLSCOM23.TLPM_MUX2_Q_0_INST.LATC.L2(0:48) [0000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:6 | RW | LINK_EVENT_9: link event 9 selector | ||
| 7:13 | RW | LINK_EVENT_10: link event 10 selector | ||
| 14:20 | RW | LINK_EVENT_11: link event 11 selector | ||
| 21:27 | RW | LINK_EVENT_12: link event 12 selector | ||
| 28:34 | RW | LINK_EVENT_13: link event 13 selector | ||
| 35:41 | RW | LINK_EVENT_14: link event 14 selector | ||
| 42:48 | RW | LINK_EVENT_15: link event 15 selector | ||
| PowerBus TL Link Mailbox Control Register | ||||
|---|---|---|---|---|
| Addr: |
000000001101182E (SCOM) | |||
| Name: | PB.PTLSCOM23.PB_MAILBOX_CTL_REG | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:15 | PB.PTLSCOM23.MAILBOX_CTL_Q_0_INST.LATC.L2(0:15) [0000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | RWX | MB_VALID: written to 1 to start operation, reads 1 if in progress, 0 when done | ||
| 1 | RW | MB_WR_NOT_RD: Written to 1 for a write operation, 0 for a read. To do a write, first write your desired data to the PBO_MAILBOX_DATA_REG, then write this reg with a write command, and the mailbox_id and link_id bits set for your desired destination. To do a read, write this reg with a read command, and the mailbox_id and link_id bits set for your desired destination. Monitor this reg to see when complete, then read the PBO_MAILBOX_DATA_REG to extract the resulting data. | ||
| 2 | RWX_WCLRPART | MB_BAD_ADDR: (read-only) set if last operation was invalid (bad address) Note - this bit will get set if you target a half-link that has gone down. However, the op can still succeed if the link was originally a logical pair and the other half of the link is still up. In that case, mb_sent (bit 5) will get set, and the op will complete. | ||
| 3 | RWX_WCLRPART | MB_LINK_DOWN: (read-only) set if link goes down during the op | ||
| 4 | RWX_WCLRPART | MB_CORRUPT: (read-only) set if last operation corrupted (return response address mismatch) | ||
| 5 | RWX_WCLRPART | MB_SENT: (read-only) set when op is sent to framer | ||
| 6 | RWX_WCLRPART | MB_BAD_WRITE: (read-only) set on write to this register when already active | ||
| 7 | WO_1P | MB_RESET: Write to a 1 to reset hung mailbox logic caused by a link going down. Auto reset to 0. | ||
| 8 | RW | MAILBOX_ID: Mailbox ID - there are two mailboxes per half-link, 0 and 1. Mailbox 0 is subject to tp_pb_abus_security_lock_dc, mailbox 1 is not. | ||
| 9:11 | RW | MB_LINK_ID: Index of the half-link of interest on the chip where PB_MAILBOX_CTL_REG is being written. 0=PTL[0,2,4,6]_evn 1=PTL[0,2,4,6]_odd 2=PTL[1,3,5,7]_evn 3=PTL[1,3,5,7]_odd 4-7=reserved Note: mailbox affiliation on the other side is by PHYSICAL connection. For example, if you have chipA.PTL0_evn connected to chipB.PTL5_odd (meaning, the half-links are are physically crossed in the board or cable connections), writing to chipA.PTL01 index 0, mailbox 0, will place the data in chipB index 3, mailbox 0, i.e., the PBO_MAILBOX_30_REG in the receiving chip. | ||
| 12:15 | RW | MB_SPARE: mb spare | ||
| PowerBus TL Link Mailbox Data Movement Register. This is the data source for a write of a remote mailbox write, or the holding reg for remote mailbox read return data | ||||
|---|---|---|---|---|
| Addr: |
000000001101182F (SCOM) | |||
| Name: | PB.PTLSCOM23.PB_MAILBOX_DATA_REG | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PB.PTLSCOM23.MAILBOX_DATA_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:63 | RWX | |||
| PowerBus TL Link Mailbox 00 Register (PTL0246_evn_0 - secure). | ||||
|---|---|---|---|---|
| Addr: |
0000000011011830 (SCOM) | |||
| Name: | PB.PTLSCOM23.PB_MAILBOX_00_REG | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PB.PTLSCOM23.REG30_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:63 | RWX | |||
| PowerBus TL Link Mailbox 01 Register (PTL0246_evn_1). | ||||
|---|---|---|---|---|
| Addr: |
0000000011011831 (SCOM) | |||
| Name: | PB.PTLSCOM23.PB_MAILBOX_01_REG | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PB.PTLSCOM23.REG31_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:63 | RWX | |||
| PowerBus TL Link Mailbox 10 Register (PTL0246_odd_0 - secure). | ||||
|---|---|---|---|---|
| Addr: |
0000000011011832 (SCOM) | |||
| Name: | PB.PTLSCOM23.PB_MAILBOX_10_REG | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PB.PTLSCOM23.REG32_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:63 | RWX | |||
| PowerBus TL Link Mailbox 11 Register (PTL0246_odd_1). | ||||
|---|---|---|---|---|
| Addr: |
0000000011011833 (SCOM) | |||
| Name: | PB.PTLSCOM23.PB_MAILBOX_11_REG | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PB.PTLSCOM23.REG33_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:63 | RWX | |||
| PowerBus TL Link Mailbox 20 Register (PTL1357_evn_0 - secure). | ||||
|---|---|---|---|---|
| Addr: |
0000000011011834 (SCOM) | |||
| Name: | PB.PTLSCOM23.PB_MAILBOX_20_REG | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PB.PTLSCOM23.REG34_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:63 | RWX | |||
| PowerBus TL Link Mailbox 21 Register (PTL1357_evn_1). | ||||
|---|---|---|---|---|
| Addr: |
0000000011011835 (SCOM) | |||
| Name: | PB.PTLSCOM23.PB_MAILBOX_21_REG | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PB.PTLSCOM23.REG35_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:63 | RWX | |||
| PowerBus TL Link Mailbox 30 Register (PTL1357_odd_0 - secure). | ||||
|---|---|---|---|---|
| Addr: |
0000000011011836 (SCOM) | |||
| Name: | PB.PTLSCOM23.PB_MAILBOX_30_REG | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PB.PTLSCOM23.REG36_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:63 | RWX | |||
| PowerBus TL Link Mailbox 31 Register (PTL1357_odd_1). | ||||
|---|---|---|---|---|
| Addr: |
0000000011011837 (SCOM) | |||
| Name: | PB.PTLSCOM23.PB_MAILBOX_31_REG | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | PB.PTLSCOM23.REG37_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:63 | RWX | |||
| Pervasive FIR Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011012C00 (SCOM) 0000000011012C01 (SCOM1) 0000000011012C02 (SCOM2) | |||
| Name: | IOO1_OMI45.PHY_SCOM_MAC.FIR_REG | |||
| Constant(s): | ||||
| Comments: | Local FIR register for the chip pervasive logic | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:26 | IOO1_OMI45.PHY_SCOM_MAC.SCOMFIR.PAR_ON.LEM_FIR.LOCALFIR.FIR.FIR.LATC.L2(0:26) [000000000000000000000000000] | |||
| Bit(s) | SCOM | SCOM1 | SCOM2 | Dial: Description |
| 0 | RWX | WOX_AND | WOX_OR | FIR_IOO0_RX_INVALID_STATE_OR_PARITY_ERROR: FIR Register - A RX state machine parity or mode register parity error has occurred (IOO0). |
| 1 | RWX | WOX_AND | WOX_OR | FIR_IOO1_RX_INVALID_STATE_OR_PARITY_ERROR: FIR Register - A RX state machine parity or mode register parity error has occurred (IOO1). |
| 2 | RWX | WOX_AND | WOX_OR | FIR_OMI0_RX_INVALID_STATE_OR_PARITY_ERROR: FIR Register - A RX state machine parity or mode register parity error has occurred (OMI0). |
| 3 | RWX | WOX_AND | WOX_OR | FIR_OMI1_RX_INVALID_STATE_OR_PARITY_ERROR: FIR Register - A RX state machine parity or mode register parity error has occurred (OMI1). |
| 4 | RWX | WOX_AND | WOX_OR | FIR_IOO0_TX_INVALID_STATE_OR_PARITY_ERROR: FIR Register - A TX state machine parity or mode register parity error has occurred (IOO0). |
| 5 | RWX | WOX_AND | WOX_OR | FIR_IOO1_TX_INVALID_STATE_OR_PARITY_ERROR: FIR Register - A TX state machine parity or mode register parity error has occurred (IOO1). |
| 6 | RWX | WOX_AND | WOX_OR | FIR_OMI0_TX_INVALID_STATE_OR_PARITY_ERROR: FIR Register - A TX state machine parity or mode register parity error has occurred (OMI0). |
| 7 | RWX | WOX_AND | WOX_OR | FIR_OMI1_TX_INVALID_STATE_OR_PARITY_ERROR: FIR Register - A TX state machine parity or mode register parity error has occurred (OMI1). |
| 8 | RWX | WOX_AND | WOX_OR | FIR_ZCAL_INVALID_STATE_OR_PARITY_ERROR: FIR Register - A TX ZCAL state machine parity or mode register parity error has occurred. |
| 9 | RWX | WOX_AND | WOX_OR | FIR_PPE_INT_HWERROR: FIR Register - A PPE internal error has occurred. |
| 10 | RWX | WOX_AND | WOX_OR | FIR_PPE_EXT_HWERROR: FIR Register - A PPE external error has occurred. |
| 11 | RWX | WOX_AND | WOX_OR | FIR_PPE_HALT_WATCHDOG_OR_INTERRUPT: FIR Register - A PPE Halt due to Watchdog or Interrupt has occurred. |
| 12 | RWX | WOX_AND | WOX_OR | FIR_PPE_HALT_DEBUG: FIR Register - A PPE Halt due to Debug has occurred. |
| 13 | RWX | WOX_AND | WOX_OR | FIR_PPE_HALTED: FIR Register - PPE Halted. |
| 14 | RWX | WOX_AND | WOX_OR | FIR_PPE_WATCHDOG_TIMEOUT: FIR Register - A PPE Watchdog Timeout has occurred. |
| 15 | RWX | WOX_AND | WOX_OR | FIR_PPE_ARB_MISSED_SCRUB_TICK: FIR Register - A PPE Array Scrub was missed. |
| 16 | RWX | WOX_AND | WOX_OR | FIR_PPE_ARB_ARRAY_UNCORRECTABLE_ERROR: FIR Register - A PPE Array uncorrectable error has occurred. |
| 17 | RWX | WOX_AND | WOX_OR | FIR_PPE_ARB_ARRAY_CORRECTABLE_ERROR: FIR Register - A PPE Array correctable error has occurred. |
| 18 | RWX | WOX_AND | WOX_OR | FIR_PPE_CODE_RECAL_ABORT: FIR Register - A PPE Code Recal Abort has occurred. |
| 19 | RWX | WOX_AND | WOX_OR | FIR_PPE_CODE_FATAL_ERROR: FIR Register - A PPE Code Fatal Error has occurred. |
| 20 | RWX | WOX_AND | WOX_OR | FIR_PPE_CODE_WARNING: FIR Register - A PPE Code Warning has occurred. |
| 21 | RWX | WOX_AND | WOX_OR | FIR_PPE_CODE_DFT_ERROR: FIR Register - A PPE Code DFT Error has occurred. |
| 22 | RWX | WOX_AND | WOX_OR | FIR_PPE_CODE_RECAL_NOT_RUN: FIR Register - A PPE Code Recal Not Run has occurred. |
| 23 | RWX | WOX_AND | WOX_OR | FIR_PPE_CODE_THREAD_LOCKED: FIR Register - A PPE Code Thread Locked has occurred. |
| 24 | RWX | WOX_AND | WOX_OR | FIR_PPE_CODE_6: FIR Register - A PPE Code FIR 6 has occurred. |
| 25 | RWX | WOX_AND | WOX_OR | FIR_PPE_CODE_7: FIR Register - A PPE Code FIR 7 has occurred. |
| 26 | RWX | WOX_AND | WOX_OR | FIR_SCOMFIR_PARITY_ERROR: FIR Register- A SCOM FSM or FIR register parity error has occurred. |
| 27:40 | RO | n/a | n/a | constant=0b00000000000000 |
| Pervasive FIR Mask Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011012C03 (SCOM) 0000000011012C04 (SCOM1) 0000000011012C05 (SCOM2) | |||
| Name: | IOO1_OMI45.PHY_SCOM_MAC.FIR_MASK_REG | |||
| Constant(s): | ||||
| Comments: | Error mask register (Action0,Mask) = Action Select (0,0) = Recoverable Error (0,1) = Masked | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:26 | IOO1_OMI45.PHY_SCOM_MAC.SCOMFIR.PAR_ON.LEM_FIR.LOCALFIR.FIR.FIR_MASK.LATC.L2(0:26) [000000000000000000000000000] | |||
| Bit(s) | SCOM | SCOM1 | SCOM2 | Dial: Description |
| 0 | RWX | WOX_AND | WOX_OR | FIR_IOO0_RX_INVALID_STATE_OR_PARITY_ERROR_MASK: FIR Register - A RX state machine parity or mode register parity error has occurred (IOO0). |
| 1 | RWX | WOX_AND | WOX_OR | FIR_IOO1_RX_INVALID_STATE_OR_PARITY_ERROR_MASK: FIR Register - A RX state machine parity or mode register parity error has occurred (IOO1). |
| 2 | RWX | WOX_AND | WOX_OR | FIR_OMI0_RX_INVALID_STATE_OR_PARITY_ERROR_MASK: FIR Register - A RX state machine parity or mode register parity error has occurred (OMI0). |
| 3 | RWX | WOX_AND | WOX_OR | FIR_OMI1_RX_INVALID_STATE_OR_PARITY_ERROR_MASK: FIR Register - A RX state machine parity or mode register parity error has occurred (OMI1). |
| 4 | RWX | WOX_AND | WOX_OR | FIR_IOO0_TX_INVALID_STATE_OR_PARITY_ERROR_MASK: FIR Register - A TX state machine parity or mode register parity error has occurred (IOO0). |
| 5 | RWX | WOX_AND | WOX_OR | FIR_IOO1_TX_INVALID_STATE_OR_PARITY_ERROR_MASK: FIR Register - A TX state machine parity or mode register parity error has occurred (IOO1). |
| 6 | RWX | WOX_AND | WOX_OR | FIR_OMI0_TX_INVALID_STATE_OR_PARITY_ERROR_MASK: FIR Register - A TX state machine parity or mode register parity error has occurred (OMI0). |
| 7 | RWX | WOX_AND | WOX_OR | FIR_OMI1_TX_INVALID_STATE_OR_PARITY_ERROR_MASK: FIR Register - A TX state machine parity or mode register parity error has occurred (OMI1). |
| 8 | RWX | WOX_AND | WOX_OR | FIR_ZCAL_INVALID_STATE_OR_PARITY_ERROR_MASK: FIR Register - A TX ZCAL state machine parity or mode register parity error has occurred. |
| 9 | RWX | WOX_AND | WOX_OR | FIR_PPE_INT_HWERROR_MASK: FIR Register - A PPE internal error has occurred. |
| 10 | RWX | WOX_AND | WOX_OR | FIR_PPE_EXT_HWERROR_MASK: FIR Register - A PPE external error has occurred. |
| 11 | RWX | WOX_AND | WOX_OR | FIR_PPE_HALT_WATCHDOG_OR_INTERRUPT_MASK: FIR Register - A PPE Halt due to Watchdog or Interrupt has occurred. |
| 12 | RWX | WOX_AND | WOX_OR | FIR_PPE_HALT_DEBUG_MASK: FIR Register - A PPE Halt due to Debug has occurred. |
| 13 | RWX | WOX_AND | WOX_OR | FIR_PPE_HALTED_MASK: FIR Register - PPE Halted. |
| 14 | RWX | WOX_AND | WOX_OR | FIR_PPE_WATCHDOG_TIMEOUT_MASK: FIR Register - A PPE Watchdog Timeout has occurred. |
| 15 | RWX | WOX_AND | WOX_OR | FIR_PPE_ARB_MISSED_SCRUB_TICK_MASK: FIR Register - A PPE Array Scrub was missed. |
| 16 | RWX | WOX_AND | WOX_OR | FIR_PPE_ARB_ARRAY_UNCORRECTABLE_ERROR_MASK: FIR Register - A PPE Array uncorrectable error has occurred. |
| 17 | RWX | WOX_AND | WOX_OR | FIR_PPE_ARB_ARRAY_CORRECTABLE_ERROR_MASK: FIR Register - A PPE Array correctable error has occurred. |
| 18 | RWX | WOX_AND | WOX_OR | FIR_PPE_CODE_RECAL_ABORT_MASK: FIR Register - A PPE Code Recal Abort has occurred. |
| 19 | RWX | WOX_AND | WOX_OR | FIR_PPE_CODE_FATAL_ERROR_MASK: FIR Register - A PPE Code Fatal Error has occurred. |
| 20 | RWX | WOX_AND | WOX_OR | FIR_PPE_CODE_WARNING_MASK: FIR Register - A PPE Code Warning has occurred. |
| 21 | RWX | WOX_AND | WOX_OR | FIR_PPE_CODE_DFT_ERROR_MASK: FIR Register - A PPE Code DFT Error has occurred. |
| 22 | RWX | WOX_AND | WOX_OR | FIR_PPE_CODE_RECAL_NOT_RUN_MASK: FIR Register - A PPE Code Recal Not Run has occurred. |
| 23 | RWX | WOX_AND | WOX_OR | FIR_PPE_CODE_THREAD_LOCKED_MASK: FIR Register - A PPE Code Thread Locked has occurred. |
| 24 | RWX | WOX_AND | WOX_OR | FIR_PPE_CODE_6_MASK: FIR Register - A PPE Code FIR 6 has occurred. |
| 25 | RWX | WOX_AND | WOX_OR | FIR_PPE_CODE_7_MASK: FIR Register - A PPE Code FIR 7 has occurred. |
| 26 | RWX | WOX_AND | WOX_OR | FIR_SCOMFIR_PARITY_ERROR_MASK: FIR Register- A SCOM FSM or FIR register parity error has occurred. |
| 27:40 | RO | n/a | n/a | constant=0b00000000000000 |
| Fault Isolation Action0 Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011012C06 (SCOM) | |||
| Name: | IOO1_OMI45.PHY_SCOM_MAC.FIR_ACTION0_REG | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:26 | IOO1_OMI45.PHY_SCOM_MAC.SCOMFIR.PAR_ON.LEM_FIR.LOCALFIR.FIR.DO_ACTION0.FIR_ACTION0.LATC.L2(0:26) [000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:26 | RW | FIR_ACTION0: Action 0 for FIR(0:26) | ||
| 27:40 | RO | constant=0b00000000000000 | ||
| Fault Isolation Action1 Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011012C07 (SCOM) | |||
| Name: | IOO1_OMI45.PHY_SCOM_MAC.FIR_ACTION1_REG | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:26 | IOO1_OMI45.PHY_SCOM_MAC.SCOMFIR.PAR_ON.LEM_FIR.LOCALFIR.FIR.DO_ACTION1.FIR_ACTION1.LATC.L2(0:26) [000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:26 | RW | FIR_ACTION1: Action 1 for FIR(0:26) | ||
| 27:40 | RO | constant=0b00000000000000 | ||
| FIR WOF Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011012C08 (SCOM) | |||
| Name: | IOO1_OMI45.PHY_SCOM_MAC.FIR_WOF_REG | |||
| Constant(s): | ||||
| Comments: | FIR WOF Register | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:26 | IOO1_OMI45.PHY_SCOM_MAC.SCOMFIR.PAR_ON.LEM_FIR.LOCALFIR.FIR.WOF_LAT_YES.WOF.LATC.L2(0:26) [000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:26 | RWX_WCLRREG | WOF | ||
| 27:40 | RO | constant=0b00000000000000 | ||
| PPE Local SRAM Control Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011012C0A (SCOM) 0000000011012C0B (SCOM1) 0000000011012C0C (SCOM2) | |||
| Name: | IOO1_OMI45.PHY_PPE_WRAP.PPE.ARB.ARB.CSCR | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:7 | IOO1_OMI45.PHY_PPE_WRAP.PPE.ARB.ARB.CMESCR_Q_0_INST.LATC.L2(0:7) [00000000] | |||
| 47:59 | IOO1_OMI45.PHY_PPE_WRAP.PPE.ARB.ARB.SCRUB_ADDR_Q_15_INST.LATC.L2(16:28) [0000000000000] | |||
| Bit(s) | SCOM | SCOM1 | SCOM2 | Dial: Description |
| 0 | RW | WO_CLEAR | WO_OR | CSCR_SRAM_ACCESS_MODE: SRAM Access Mode Dial enums: DISABLE_LOCAL_SRAM_ADDRESS_AUTO_INCREMENT_MODE_=>0b0 ENABLE_LOCAL_SRAM_ADDRESS_AUTO_INCREMENT_MODE_=>0b1 |
| 1 | RWX | WOX_CLEAR | WOX_OR | CSCR_SRAM_SCRUB_ENABLE: Enable background scrub (atomic read-write) to periodically check, and if needed correct, the data in the SRAM for bit flips due to alpha particles. This bit is cleared by the hardware when a UE is detected to assist with fault analysis. |
| 2 | RW | WO_CLEAR | WO_OR | CSCR_ECC_CORRECT_DIS: Do not correct the data coming out of the array on ECC detected correctable errors. This will cause CEs to report an error back to the PPE in addition to the usual UEs. |
| 3 | RW | WO_CLEAR | WO_OR | CSCR_ECC_DETECT_DIS: Do not flag an error back to PPE for ECC miscompares. Data from the SRAM is always treated as good. Note that errors are always detected and reported to the FIR and must be masked there independently from this bit. |
| 4 | RW | WO_CLEAR | WO_OR | CSCR_ECC_INJECT_TYPE: Used only when ECC_INJECT_ERR is set. When set to 1, causes an ECC error to be reported on every SRAM read. When 0, causes a single ECC error to be indicated on the next SRAM read to occur, since it also clears ECC_INJECT_ERR when that happens. |
| 5 | RWX | WOX_CLEAR | WOX_OR | CSCR_ECC_INJECT_ERR: When set, the hardware will inject or cause a fake uncorrectable error (UE) to be reported to both the PPE and the FIR on all SRAM reads. The SRAM contents are not modified. Type of error to inject is determined by the previous bit. If ECC_INJECT_TYPE=1, then this bit clears when the first error is injected. Note this bit can also be set by the PPE local register CFMSR. |
| 6:7 | RW | WO_CLEAR | WO_OR | CSCR_SPARE_6_7: Implemented but unused. |
| 8:46 | RO | RO | RO | constant=0b000000000000000000000000000000000000000 |
| 47:59 | RWX | WOX_CLEAR | WOX_OR | CSCR_SRAM_SCRUB_INDEX: 32KB Scrub Index. This field is auto-incremented by hardware for every scrub operation. Upon a UE detection, this field is over-written with the index of the doubleword containing the error. Note: SRAM_SCRUB_ENABLE should be set to 0 when writing this field to prevent one cycle window from ignoring this write if a scrub update happens to occur concurrently. |
| 60:63 | RO | RO | RO | constant=0b0000 |
| PPE Local SRAM Address Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011012C0D (SCOM) | |||
| Name: | IOO1_OMI45.PHY_PPE_WRAP.PPE.ARB.ARB.CSAR | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 16:28 | IOO1_OMI45.PHY_PPE_WRAP.PPE.ARB.ARB.CSAR_Q_15_INST.LATC.L2(16:28) [0000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:15 | RO | constant=0b0000000000000000 | ||
| 16:28 | RW | CSAR_SRAM_ADDRESS: Address of an 8B SRAM entry in the 32KB SRAM array. | ||
| 29:63 | RO | constant=0b00000000000000000000000000000000000 | ||
| PPE Local SRAM Data Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011012C0E (SCOM) | |||
| Name: | IOO1_OMI45.PHY_PPE_WRAP.PPE.ARB.ARB.CSDR | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | IOO1_OMI45.PHY_PPE_WRAP.PPE.ARB.ARB.CSDR_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:63 | RWX | CSDR_SRAM_DATA: 8B SRAM Data entry for the address given by the SRAM_ADDRESS. Reads cause this register to be written with data from the Local SRAM. Writes cause the Local SRAM to be written with the contents of this register. | ||
| PPE External Interface XCR | ||||
|---|---|---|---|---|
| Addr: |
0000000011012C10 (SCOM) | |||
| Name: | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.PPE.PPE_XIXCR | |||
| Constant(s): | ||||
| Comments: | Access to the PPE cores External Interface Register (XIR) bus: External Control Register (XCR) and Count (CTR). Note this XIR is slightly modified from P9, which did not include CTR. Note: this register is SCOM-only, not local register accessible. | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 1:3 | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.PPE.LT_XIR_XCR_CMND.LATC.L2(0:2) [000] | |||
| 32:63 | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.PPE.I_C_PPE42_SPR.LT_CTR.LATC.L2(0:31) [00000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | RO | constant=0b0 | ||
| 1:3 | WOX | PPE_XIXCR_XCR: PPE External Control Register See PPE Specification for bit definitions. | ||
| 4:31 | RO | constant=0b0000000000000000000000000000 | ||
| 32:63 | RO | NULL_CTR_CTR: | ||
| PPE External Interface RAMRA | ||||
|---|---|---|---|---|
| Addr: |
0000000011012C11 (SCOM) | |||
| Name: | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.PPE.PPE_XIRAMRA | |||
| Constant(s): | ||||
| Comments: | Access to the PPE cores External Interface Register (XIR) bus: Ram Restore Acceleration Register. Can be used to restore SPRG0 plus Resume (or Single Step) with one command. Note: this register is SCOM-only, not local register accessible. | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 1:3 | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.PPE.LT_XIR_XCR_CMND.LATC.L2(0:2) [000] | |||
| 32:63 | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.PPE.I_C_PPE42_SPR.LT_SPRG0.LATC.L2(0:31) [00000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | RO | constant=0b0 | ||
| 1:3 | WOX | PPE_XIXCR_XCR: PPE External Control Register See PPE Specification for bit definitions. | ||
| 4:31 | RO | constant=0b0000000000000000000000000000 | ||
| 32:63 | WO | SPRG0 | ||
| PPE External Interface RAMGA | ||||
|---|---|---|---|---|
| Addr: |
0000000011012C12 (SCOM) | |||
| Name: | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.PPE.PPE_XIRAMGA | |||
| Constant(s): | ||||
| Comments: | Access to the PPE cores External Interface Register (XIR) bus: Ram GPR Acceleration Register. Can be used to modify a GPR with one command (where IR = MFSPRG0 instruction 0xFC2082A6 .. 0xFFD082A6). Note: this register is SCOM-only, not local register accessible. | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:31 | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.PPE.I_C_PPE42_ISP.LT_IR.LATC.L2(0:31) [00000000000000000000000000000000] | |||
| 32:63 | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.PPE.I_C_PPE42_SPR.LT_SPRG0.LATC.L2(0:31) [00000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:31 | WO | PPE_XIRAMEDR_IR: PPE Instruction Register. Writes cause a RAM operation. Provides the requested PPE Instruction to execute. | ||
| 32:63 | WO | SPRG0 | ||
| PPE External Interface RAMDBG | ||||
|---|---|---|---|---|
| Addr: |
0000000011012C13 (SCOM) | |||
| Name: | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.PPE.PPE_XIRAMDBG | |||
| Constant(s): | ||||
| Comments: | Access to the PPE cores External Interface Register (XIR) bus: Ram & Debug Register. Read status and data. Allows write ability to modify only SPRG0 for a subsequent RAM operation. Note: this register is SCOM-only, not local register accessible. | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0 | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.PPE.I_C_PPE42_SPR.XSR_INT_SPR(0) [0] | |||
| 1:3 | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.PPE.I_C_PPE42_SPR.LT_XSR_HC.LATC.L2(0:2) [000] | |||
| 4 | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.PPE.I_C_PPE42_SPR.LT_XSR_HCP.LATC.L2(0) [0] | |||
| 5 | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.PPE.I_C_PPE42_SPR.LT_XSR_RIP.LATC.L2(0) [0] | |||
| 6 | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.PPE.I_C_PPE42_SPR.LT_XSR_SIP.LATC.L2(0) [0] | |||
| 7 | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.PPE.I_C_PPE42_SPR.LT_XSR_TRAP.LATC.L2(0) [0] | |||
| 8 | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.PPE.I_C_PPE42_SPR.LT_XSR_IAC.LATC.L2(0) [0] | |||
| 9:11 | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.PPE.I_C_PPE42_SPR.LT_MSR_9_13.LATC.L2(9:11) [000] | |||
| 12 | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.PPE.I_C_PPE42_SPR.LT_XSR_RDAC.LATC.L2(0) [0] | |||
| 13 | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.PPE.I_C_PPE42_SPR.LT_XSR_WDAC.LATC.L2(0) [0] | |||
| 14 | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.PPE.I_C_PPE42_SPR.LT_MSR_9_13.LATC.L2(13) [0] | |||
| 15 | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.PPE.I_C_PPE42_SPR.LT_XSR_TRH.LATC.L2(0) [0] | |||
| 16:19 | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.PPE.I_C_PPE42_DECODER.FSM_STATE_LATCH.LATC.L2(0:3) [0000] | |||
| 20 | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.PPE.I_C_PPE42_SPR.LT_MSR_9_13.LATC.L2(12) [0] | |||
| 21 | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.PPE.I_C_PPE42_SPR.LT_XSR_EP.LATC.L2(0) [0] | |||
| 24:25 | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.PPE.I_C_PPE42_SPR.LT_ISR_24_25.LATC.L2(24:25) [00] | |||
| 28:31 | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.PPE.I_C_PPE42_SPR.LT_ISR_28_31.LATC.L2(28:31) [0000] | |||
| 32:63 | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.PPE.I_C_PPE42_SPR.LT_SPRG0.LATC.L2(0:31) [00000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | ROX | XSR_HS | ||
| 1:3 | RWX | XSR_HC | ||
| 4 | ROX | XSR_HCP | ||
| 5 | ROX | XSR_RIP | ||
| 6 | ROX | XSR_SIP | ||
| 7 | RWX | XSR_TRAP | ||
| 8 | RWX | XSR_IAC | ||
| 9:11 | ROX | NULL_MSR_SIBRC: | ||
| 12 | RWX | XSR_RDAC | ||
| 13 | RWX | XSR_WDAC | ||
| 14 | ROX | NULL_MSR_WE: | ||
| 15 | ROX | XSR_TRH | ||
| 16:19 | ROX | XSR_SMS | ||
| 20 | ROX | NULL_MSR_LP: | ||
| 21 | ROX | XSR_EP | ||
| 22:23 | RO | constant=0b00 | ||
| 24 | ROX | XSR_PTR | ||
| 25 | ROX | XSR_ST | ||
| 26:27 | RO | constant=0b00 | ||
| 28 | ROX | XSR_MFE | ||
| 29:31 | ROX | XSR_MCS | ||
| 32:63 | RWX | SPRG0 | ||
| PPE External Interface RAMEDR | ||||
|---|---|---|---|---|
| Addr: |
0000000011012C14 (SCOM) | |||
| Name: | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.PPE.PPE_XIRAMEDR | |||
| Constant(s): | ||||
| Comments: | Access to the PPE cores External Interface Register (XIR) bus: Ram & Error Diagnosis Register. Can be used to read IR and EDR for debug. Also provides ability to RAM an instruction without modifying SPRG0. Note: this register is SCOM-only, not local register accessible. | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:31 | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.PPE.I_C_PPE42_ISP.LT_IR.LATC.L2(0:31) [00000000000000000000000000000000] | |||
| 32:63 | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.PPE.I_C_PPE42_SPR.LT_EDR.LATC.L2(0:31) [00000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:31 | RW | PPE_XIRAMEDR_IR: PPE Instruction Register. Writes cause a RAM operation. Provides the requested PPE Instruction to execute. | ||
| 32:63 | ROX | PPE_XIRAMEDR_EDR: Error Data Register, set on PPE interrupts caused by an error. See PPE Specification for definition. | ||
| PPE External Interface DBGPRO | ||||
|---|---|---|---|---|
| Addr: |
0000000011012C15 (SCOM) | |||
| Name: | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.PPE.PPE_XIDBGPRO | |||
| Constant(s): | ||||
| Comments: | Access to the PPE cores External Interface Register (XIR) bus: Debug & Runtime Profiling Read program location and status. Also used to write XSR & IAR. Note: this register is SCOM-only, not local register accessible. | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0 | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.PPE.I_C_PPE42_SPR.XSR_INT_SPR(0) [0] | |||
| 1:3 | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.PPE.I_C_PPE42_SPR.LT_XSR_HC.LATC.L2(0:2) [000] | |||
| 4 | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.PPE.I_C_PPE42_SPR.LT_XSR_HCP.LATC.L2(0) [0] | |||
| 5 | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.PPE.I_C_PPE42_SPR.LT_XSR_RIP.LATC.L2(0) [0] | |||
| 6 | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.PPE.I_C_PPE42_SPR.LT_XSR_SIP.LATC.L2(0) [0] | |||
| 7 | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.PPE.I_C_PPE42_SPR.LT_XSR_TRAP.LATC.L2(0) [0] | |||
| 8 | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.PPE.I_C_PPE42_SPR.LT_XSR_IAC.LATC.L2(0) [0] | |||
| 9:11 | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.PPE.I_C_PPE42_SPR.LT_MSR_9_13.LATC.L2(9:11) [000] | |||
| 12 | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.PPE.I_C_PPE42_SPR.LT_XSR_RDAC.LATC.L2(0) [0] | |||
| 13 | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.PPE.I_C_PPE42_SPR.LT_XSR_WDAC.LATC.L2(0) [0] | |||
| 14 | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.PPE.I_C_PPE42_SPR.LT_MSR_9_13.LATC.L2(13) [0] | |||
| 15 | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.PPE.I_C_PPE42_SPR.LT_XSR_TRH.LATC.L2(0) [0] | |||
| 16:19 | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.PPE.I_C_PPE42_DECODER.FSM_STATE_LATCH.LATC.L2(0:3) [0000] | |||
| 20 | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.PPE.I_C_PPE42_SPR.LT_MSR_9_13.LATC.L2(12) [0] | |||
| 21 | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.PPE.I_C_PPE42_SPR.LT_XSR_EP.LATC.L2(0) [0] | |||
| 24:25 | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.PPE.I_C_PPE42_SPR.LT_ISR_24_25.LATC.L2(24:25) [00] | |||
| 28:31 | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.PPE.I_C_PPE42_SPR.LT_ISR_28_31.LATC.L2(28:31) [0000] | |||
| 32:61 | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.PPE.I_C_PPE42_ISP.LT_IAR.LATC.L2(0:29) [000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | ROX | XSR_HS | ||
| 1:3 | RWX | XSR_HC | ||
| 4 | ROX | XSR_HCP | ||
| 5 | ROX | XSR_RIP | ||
| 6 | ROX | XSR_SIP | ||
| 7 | RWX | XSR_TRAP | ||
| 8 | RWX | XSR_IAC | ||
| 9:11 | ROX | NULL_MSR_SIBRC: | ||
| 12 | RWX | XSR_RDAC | ||
| 13 | RWX | XSR_WDAC | ||
| 14 | ROX | NULL_MSR_WE: | ||
| 15 | ROX | XSR_TRH | ||
| 16:19 | ROX | XSR_SMS | ||
| 20 | ROX | NULL_MSR_LP: | ||
| 21 | ROX | XSR_EP | ||
| 22:23 | RO | constant=0b00 | ||
| 24 | ROX | XSR_PTR | ||
| 25 | ROX | XSR_ST | ||
| 26:27 | RO | constant=0b00 | ||
| 28 | ROX | XSR_MFE | ||
| 29:31 | ROX | XSR_MCS | ||
| 32:61 | RWX | IAR | ||
| 62:63 | RO | constant=0b00 | ||
| PPE External Interface MEM Info | ||||
|---|---|---|---|---|
| Addr: |
0000000011012C17 (SCOM) | |||
| Name: | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.MIB.PPE_XIMEM | |||
| Constant(s): | ||||
| Comments: | Access to the Memory Bolt-ons External Interface Register (XIR) bus: Memory Interface Info for debug Note: this register is SCOM-only, not local register accessible. | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:31 | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.MIB.MEM_ADDR_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000] | |||
| 32 | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.MIB.MEM_R_NW_Q_INST.LATC.L2(0) [0] | |||
| 33 | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.MIB.MEM_BUSY_Q_INST.LATC.L2(0) [0] | |||
| 34 | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.MIB.MEM_IMPRECISE_ERROR_PENDING_Q_INST.LATC.L2(0) [0] | |||
| 35:42 | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.MIB.MEM_BYTE_ENABLE_Q_0_INST.LATC.L2(0:7) [00000000] | |||
| 43 | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.MIB.MEM_LINE_MODE_Q_INST.LATC.L2(0) [0] | |||
| 49:51 | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.MIB.MEM_ERROR_Q_0_INST.LATC.L2(0:2) [000] | |||
| 62 | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.MIB.IFETCH_MEM_PENDING_Q_INST.LATC.L2(0) [0] | |||
| 63 | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.MIB.MEM_DATAOP_PENDING_Q_INST.LATC.L2(0) [0] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:31 | ROX | PPE_XIMEM_MEM_ADDR: MEM transaction buffer current or previous transaction byte address. | ||
| 32 | ROX | PPE_XIMEM_MEM_R_NW: MEM transaction buffer current or previous transaction type, read if 1 and write if 0. | ||
| 33 | ROX | PPE_XIMEM_MEM_BUSY: Indicates if the transaction buffer is occupied with an ongoing transaction. Busy is cleared when the transaction is completed. | ||
| 34 | ROX | PPE_XIMEM_MEM_IMPRECISE_ERROR_PENDING: Indicates that the current or previous transaction had an imprecise error. Cleared when it is reported back to PPE. Note: The address of the erroneous transaction is copied into the SGB address latches such that the memory interface can continue to service I-fetches. | ||
| 35:42 | ROX | PPE_XIMEM_MEM_BYTE_ENABLE: MEM transaction buffer current or previous transaction byte enables. | ||
| 43 | ROX | PPE_XIMEM_MEM_LINE_MODE: MEM transaction buffer current or previous transaction line mode. Indicates a 32B read request when set to 1. | ||
| 44:48 | RO | constant=0b00000 | ||
| 49:51 | ROX | PPE_XIMEM_MEM_ERROR: MEM transaction buffer error code. Current or previous transaction got an error on the memory interface when non-zero. | ||
| 52:61 | RO | constant=0b0000000000 | ||
| 62 | ROX | PPE_XIMEM_MEM_IFETCH_PENDING: Indicates a instruction fetch is pending on the MEM interface when set to 1. | ||
| 63 | ROX | PPE_XIMEM_MEM_DATAOP_PENDING: Indicates a data transaction is pending on the MEM interface when set to 1. | ||
| PPE External Interface SGB Info | ||||
|---|---|---|---|---|
| Addr: |
0000000011012C18 (SCOM) | |||
| Name: | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.MIB.PPE_XISGB | |||
| Constant(s): | ||||
| Comments: | Access to the Memory Bolt-ons External Interface Register (XIR) bus: Store Gather Buffer Info for debug Note: this register is SCOM-only, not local register accessible. | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:31 | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.MIB.STR_GTHR_ADDR_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000] | |||
| 35 | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.MIB.MEM_IMPRECISE_ERROR_PENDING_Q_INST.LATC.L2(0) [0] | |||
| 36:39 | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.MIB.STR_GTHR_VALID_Q_0_INST.LATC.L2(0:3) [0000] | |||
| 63 | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.MIB.STR_GTHR_FLUSH_PENDING_Q_INST.LATC.L2(0) [0] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:31 | ROX | STORE_ADDRESS | ||
| 32:34 | RO | constant=0b000 | ||
| 35 | ROX | PPE_XIMEM_MEM_IMPRECISE_ERROR_PENDING: Indicates that the current or previous transaction had an imprecise error. Cleared when it is reported back to PPE. Note: The address of the erroneous transaction is copied into the SGB address latches such that the memory interface can continue to service I-fetches. | ||
| 36:39 | ROX | SGB_BYTE_VALID | ||
| 40:62 | RO | constant=0b00000000000000000000000 | ||
| 63 | ROX | SGB_FLUSH_PENDING | ||
| PPE External Interface Icache Info | ||||
|---|---|---|---|---|
| Addr: |
0000000011012C19 (SCOM) | |||
| Name: | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.MIB.PPE_XIICAC | |||
| Constant(s): | ||||
| Comments: | Access to the Memory Bolt-ons External Interface Register (XIR) bus: Instruction Cache Info for debug Note: this register is SCOM-only, not local register accessible. | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:26 | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.MIB.ICACHE_COMP.ICACHE_TAG_ADDR_LATCH.LATC.L2(0:26) [000000000000000000000000000] | |||
| 32 | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.MIB.ICACHE_COMP.ICACHE_ERR_LATCH.LATC.L2(0) [0] | |||
| 34 | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.MIB.IFETCH_PIB_PENDING_Q_INST.LATC.L2(0) [0] | |||
| 35 | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.MIB.IFETCH_MEM_PENDING_Q_INST.LATC.L2(0) [0] | |||
| 36:39 | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.MIB.ICACHE_COMP.ICACHE_VALID_LATCH.LATC.L2(0:3) [0000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:26 | ROX | ICACHE_TAG_ADDR | ||
| 27:31 | RO | constant=0b00000 | ||
| 32 | ROX | ICACHE_ERR | ||
| 33 | RO | constant=0b0 | ||
| 34 | ROX | PIB_IFETCH_PENDING | ||
| 35 | ROX | PPE_XIMEM_MEM_IFETCH_PENDING: Indicates a instruction fetch is pending on the MEM interface when set to 1. | ||
| 36:39 | ROX | ICACHE_VALID | ||
| 40:63 | RO | constant=0b000000000000000000000000 | ||
| PPE External Interface DBGINF | ||||
|---|---|---|---|---|
| Addr: |
0000000011012C1F (SCOM) | |||
| Name: | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.PPE.PPE_XIDBGINF | |||
| Constant(s): | ||||
| Comments: | Access to the PPE cores External Interface Register (XIR) bus: Debug Information (register 15) New for P10. Read registers containing the most recent program address information, the Save & Restore (most recent interrupt) and Link Register (most recent branch & link for procedure calls). Note: this register is SCOM-only, not local register accessible. | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:29 | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.PPE.I_C_PPE42_SPR.LT_SRR0.LATC.L2(0:29) [000000000000000000000000000000] | |||
| 32:63 | IOO1_OMI45.PHY_PPE_WRAP.PPE.PPE.PPE.PPE.I_C_PPE42_SPR.LT_LR.LATC.L2(0:31) [00000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:29 | RO | NULL_SRR0_SRR0: PPE Save & Restore Register 0 Contains address of the most recent interrupt taken. | ||
| 30:31 | RO | constant=0b00 | ||
| 32:63 | RO | NULL_LR_LR: PPE Link Register. Contains address of the instruction following the most recent Branch with Link instruction executed, to give an idea from whence the code recently came. | ||
| PPE Misc Control Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011012C20 (SCOM) | |||
| Name: | IOO1_OMI45.PHY_PPE_WRAP.SCOM_PPE_CNTL | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:23 | IOO1_OMI45.PHY_PPE_WRAP.PPE.SCOMIF.SCOM_PPE_CNTL_REG_LT.LT2_NO_REAL_ADJUST_LAT.LATC.L2(0:23) [000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | RW | SCOM_PPE_IORESET: Reset IO-specific logic in the PPE macro. (This does not actually reset the PPE or ARB logic.) | ||
| 1 | RW | SCOM_PPE_PDWN: Power down IO-specific logic in the PPE macro. (This does not actually reset the PPE or ARB logic.) | ||
| 2 | RW | SCOM_PPE_ARB_ECC_INJECT_ERR: Force an ECC error in the memory arbiter | ||
| 3:4 | RW | SCOM_PPE_INTERLEAVING: Interleave PPE memory between 0 (0x0), 2 (0x1), or 4(0x2) SRAM arrays | ||
| 5:7 | RW | PPE_IO_VALID_ASYNC_DLY: Number of delay latches in GCR data signal path to IO cplts | ||
| 8:10 | RW | IO_PPE_DONE_ASYNC_DLY: Number of delay latches in GCR done signal path from IO cplts | ||
| 11 | RW | PPE_SOURCED_HANG_PULSE_EN: Used to enable the backup hang pulse, 0 using prev hang pulse, 1 using IO ppe hang pulse | ||
| 12 | RW | PPE_IO_VALID_DLY_CHKN: HW509784 chicken switch for GCR valid delay line fix | ||
| 13 | RW | IO_PPE_DONE_DLY_CHKN: HW509784 chicken switch for GCR done delay line fix | ||
| 14 | RW | MMIO_ECHO_CHKN: HW509784 chicken switch for MMIO handshake fix | ||
| 15:17 | RW | SST_4TO1_CNTL: SST 4to1 Driver controls for HFC clock probe mux | ||
| 18:23 | RW | SCOM_PPE_SPARES: PPE Misc Control Spares | ||
| 24:39 | RO | constant=0b0000000000000000 | ||
| PPE Work Register 1 | ||||
|---|---|---|---|---|
| Addr: |
0000000011012C21 (SCOM) | |||
| Name: | IOO1_OMI45.PHY_PPE_WRAP.SCOM_PPE_WORK_REG1 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:31 | IOO1_OMI45.PHY_PPE_WRAP.PPE.SCOMIF.SCOM_PPE_WORK_REG1_LT.LT2_NO_REAL_ADJUST_LAT.LATC.L2(0:31) [00000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:31 | RWX | SCOM_PPE_WORK1: PPE Work Register Field 1 | ||
| 32:63 | RO | constant=0b00000000000000000000000000000000 | ||
| PPE Work Register 2 | ||||
|---|---|---|---|---|
| Addr: |
0000000011012C22 (SCOM) | |||
| Name: | IOO1_OMI45.PHY_PPE_WRAP.SCOM_PPE_WORK_REG2 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:31 | IOO1_OMI45.PHY_PPE_WRAP.PPE.SCOMIF.SCOM_PPE_WORK_REG2_LT.LT2_NO_REAL_ADJUST_LAT.LATC.L2(0:31) [00000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:31 | RWX | SCOM_PPE_WORK2: PPE Work Register Field 2 | ||
| 32:63 | RO | constant=0b00000000000000000000000000000000 | ||
| PPE Flag Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011012C23 (SCOM) 0000000011012C24 (SCOM1) 0000000011012C25 (SCOM2) | |||
| Name: | IOO1_OMI45.PHY_PPE_WRAP.SCOM_PPE_FLAGS | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:15 | IOO1_OMI45.PHY_PPE_WRAP.PPE.SCOMIF.SCOM_PPE_FLAGS_LT.LT2_NO_REAL_ADJUST_LAT.LATC.L2(0:15) [0000000000000000] | |||
| Bit(s) | SCOM | SCOM1 | SCOM2 | Dial: Description |
| 0:15 | RWX | WOX_OR | WOX_CLEAR | SCOM_PPE_FLAGS_FIELD: PPE Flags Register Field |
| 16:31 | RO | RO | RO | constant=0b0000000000000000 |
| Normal SCOM Mode Reg | ||||
|---|---|---|---|---|
| Addr: |
0000000011012C26 (SCOM) | |||
| Name: | IOO1_OMI45.PHY_PPE_WRAP.PPE.SCOMIF.SCOM_MODE_PB | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:31 | IOO1_OMI45.PHY_PPE_WRAP.PPE.SCOMIF.FLAT_SCOM_REG.LT2_NO_REAL_ADJUST_LAT.LATC.L2(0:31) [00000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | RWX | GCR_TEST_MODE: GCR Test Mode. Put register logic into GCR Test Mode which allows all RW registers to be read and written by diagnostic code to verify all register acccesses. This mode gates off both logic inputs to the registers as well as the outputs from the logic. The outputs are gated to their scanflush value. | ||
| 1 | RWX | SCOM_MODE_PB_RESERVED1: SCOM Mode Reg Reserved | ||
| 2:9 | RWX | IORESET_HARD_BUS0: IO Unit-Level Hard Reset \n10000000:(tx_impcntl) TX Impedance Control \n01000000:(obus0) obus0 \n00100000:(obus1) obus1 \n00010000:(omi0) omi0 \n00001000:(omi1) omi1 \n00000100:(unused1) unused1 \n00000010:(unused2) unused2 \n00000001:(unused3) unused3 | ||
| 10:31 | RWX | SCOM_MODE_PB_SPARES1: SCOM Mode Reg Spares | ||
| 32:63 | RO | constant=0b00000000000000000000000000000000 | ||
| PPE Function Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011012C27 (SCOM) | |||
| Name: | IOO1_OMI45.PHY_PPE_WRAP.SCOM_PPE_FUNC | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:15 | IOO1_OMI45.PHY_PPE_WRAP.PPE.SCOMIF.SCOM_PPE_FUNC_REG_LT.LT2_NO_REAL_ADJUST_LAT.LATC.L2(0:15) [0000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | RW | EOL_SLOW_TOGGLE: PPE will toggle this bit for EOL protection of analog circuits | ||
| 1 | RW | EOL_FAST_TOGGLE: PPE will toggle this bit for EOL protection of analog circuits | ||
| 2 | RW | PPE_INTERRUPT: Manually force an external interrupt in the PPE. | ||
| 3:15 | RW | PPE_FUNC_SPARES: PPE Function Reg Spares | ||
| 16:31 | RO | constant=0b0000000000000000 | ||
| PPE Fir Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011012C28 (SCOM) 0000000011012C29 (SCOM1) 0000000011012C2A (SCOM2) | |||
| Name: | IOO1_OMI45.PHY_PPE_WRAP.SCOM_PPE_FIR | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:7 | IOO1_OMI45.PHY_PPE_WRAP.PPE.SCOMIF.SCOM_PPE_FIR_REG_LT.LATC.L2(0:7) [00000000] | |||
| Bit(s) | SCOM | SCOM1 | SCOM2 | Dial: Description |
| 0 | RWX | WOX_OR | WOX_CLEAR | PPE_FIR_RECAL_ABORT: PPE sets this to trigger a Recal Abort FIR. It must be cleared before it can be triggered again. |
| 1 | RWX | WOX_OR | WOX_CLEAR | PPE_FIR_FATAL_ERROR: PPE sets this to trigger a Fatal Error FIR. It must be cleared before it can be triggered again. |
| 2 | RWX | WOX_OR | WOX_CLEAR | PPE_FIR_WARNING: PPE sets this to trigger a Warning FIR. It must be cleared before it can be triggered again. |
| 3 | RWX | WOX_OR | WOX_CLEAR | PPE_FIR_DFT_ERROR: PPE sets this to trigger a DFT Error FIR. It must be cleared before it can be triggered again. |
| 4 | RWX | WOX_OR | WOX_CLEAR | PPE_FIR_RECAL_NOT_RUN: PPE sets this to trigger a Recal Not Run FIR. It must be cleared before it can be triggered again. |
| 5 | RWX | WOX_OR | WOX_CLEAR | PPE_FIR_THREAD_LOCKED: PPE sets this to trigger a Thread Locked FIR. It must be cleared before it can be triggered again. |
| 6 | RWX | WOX_OR | WOX_CLEAR | PPE_FIR_RSVD6: PPE sets this to trigger a RESERVED6 FIR. It must be cleared before it can be triggered again. |
| 7 | RWX | WOX_OR | WOX_CLEAR | PPE_FIR_RSVD7: PPE sets this to trigger a RESERVED7 FIR. It must be cleared before it can be triggered again. |
| 8:63 | RO | n/a | n/a | constant=0b00000000000000000000000000000000000000000000000000000000 |
| PPE Fir Mask Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011012C2B (SCOM) | |||
| Name: | IOO1_OMI45.PHY_PPE_WRAP.SCOM_PPE_FIR_MASK | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:7 | IOO1_OMI45.PHY_PPE_WRAP.PPE.SCOMIF.SCOM_PPE_FIR_MASK_REG_LT.LATC.L2(0:7) [00000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:7 | RW | PPE_FIR_MASK_FIELD: Set to 1 to disable the FIR bit sent to the scomfir | ||
| 8:63 | RO | constant=0b00000000000000000000000000000000000000000000000000000000 | ||
| configuration of CC counters | ||||
|---|---|---|---|---|
| Addr: |
0000000011030000 (SCOM) | |||
| Name: | TP.TCPAU1.SYNC_CONFIG | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:23 | TP.TCPAU1.EPS.CC.PHASE_SYNC.SYNC_CONFIG_Q_INST.LATC.L2(0:23) [000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:3 | RW | SYNC_PULSE_DELAY: Delay incoming sync pulse. Default are 8 latches incl. Async. 0000=8 , 0001=2(ungated), 0010=3, 0011=4, 0100=5, 0101=6, 0110=7, 0111=8 cycles, 1000=9, 1001=10, 1010=11, 1011=12, 1100=13, 1101=14, 1110=15, 1111=16 delay of the reset of the phase counter | ||
| 4 | RW | LISTEN_TO_SYNC_PULSE_DIS: disable phase counter synchronization by sync_pulse signal (default is enabled) ATTENTION: when ENABLE listen_to_sync, chiplet gets corrupted for 200 cycles | ||
| 5 | RW | SYNC_PULSE_INPUT_SEL: default is 0, when set to 1, the alternative input of the sync_pulse will be used ATTENTION: when toggle the input select, chiplet gets corrupted for 200 cycles | ||
| 6 | RW | USE_SYNC_FOR_SCAN: if set, use opcg initial alignment for scan requests | ||
| 7 | RW | CLEAR_CHIPLET_IS_ALIGNED: This bit will clear the chiplet_is_aligned bit - see cplt_stat register | ||
| 8 | RW | PCB_NOT_BLOCKED_BY_CLKCMD: PCB will not waiting for Clock Start/Stop Commands | ||
| 9 | RW | DISABLE_PCB_ITR: disable interrupt generation within CC - interrupt sent on each hld event | ||
| 10 | RW | CONT_SCAN_DISABLE: disable continues scan feature if that is set, you need to check for OPCG_DONE after each cont_scan request | ||
| 11 | RW | SYNC_PULSE_OUT_DIS: disable sync_pulse output when set to 1, master chiplet will not sending sync pulses to slave chiplets anymore | ||
| 12 | RW | REGION_PGOOD_OVERRIDE: Default is 0: When set to 1, region_pgood gets ignored. Allows Clock Start of Partial BAD regions | ||
| 13 | RW | CONT_SCAN_SHORT_WAIT: when 1, it shorts the delay between two scans. zThemis missed that. P10 need to set this bit to get faster scan performance | ||
| 14 | RW | PCIE32_MODE: P10 DD2: 0=DD1 default mode- 48 mode for all chiplets but PCIE, 1=DD2 Phase Counter 32 mode - only in PCIE chiplet allowed | ||
| 15 | RW | PHASE_COUNTER_ON_CLKCHANGE_EN: Enable Phase Counter capture on clk change or runn or xstop | ||
| 16:23 | RWX | PHASE_COUNTER_ON_CLKCHANGE: Capture value of phase counter on Clock Change or XSTOP | ||
| OPCG ALIGN | ||||
|---|---|---|---|---|
| Addr: |
0000000011030001 (SCOM) | |||
| Name: | TP.TCPAU1.OPCG_ALIGN | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | TP.TCPAU1.EPS.CC.OPCG.OPCG_ALIGN_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:3 | RW | INOP_ALIGN: INOP phase alignment (0: none, 1: 2:1, 2: 3:1, 3: 4:1, 4: 6:1, 5: 8:1, 6: 12:1, 7: 16:1, 8: 24:1, 9-15: max=144:1 ) | ||
| 4:7 | RW | SNOP_ALIGN: SNOP phase alignment (0: none, 1: 2:1, 2: 3:1, 3: 4:1, 4: 6:1, 5: 8:1, 6: 12:1, 7: 16:1, 8: 24:1, 9-15: max=144:1 ) | ||
| 8:11 | RW | ENOP_ALIGN: ENOP phase alignment (0: none, 1: 2:1, 2: 3:1, 3: 4:1, 4: 6:1, 5: 8:1, 6: 12:1, 7: 16:1, 8: 24:1, 9-15: max=144:1 ) | ||
| 12:19 | RW | INOP_WAIT: INOP cycle delay (0-255) | ||
| 20:31 | RW | SNOP_WAIT: SNOP cycle delay (0-4095) | ||
| 32:39 | RW | ENOP_WAIT: ENOP cycle delay (0-255) | ||
| 40 | RW | INOP_FORCE_SG: INOP: Set SG high during INOP | ||
| 41 | RW | SNOP_FORCE_SG: SNOP: Set SG high during SNOP | ||
| 42 | RW | ENOP_FORCE_SG: ENOP: Set SG high during ENOP ( including LOOP phase) | ||
| 43 | RW | NO_WAIT_ON_CLK_CMD: 0: A clock change request will first wait the OPCG_WAIT cycles. 1: A clock change request will not wait, when not in flush | ||
| 44:45 | RW | ALIGN_SOURCE_SELECT: 0: use inopa setting from opcg_reg0, 1: use rising edge of sync pulse, 2: use unit0_sync_lvl to align (for AVP - refresh0 ) 3: use unit1_sync_lvl to align (for AVP - refresh1) | ||
| 46 | RW | UNUSED46: unused | ||
| 47:51 | RW | SCAN_RATIO: scan_ratio (n=0-15: (n+1):1, 16: 24:1, 17: 32:1, 18: 48:1, 19: 64:1, 20: 128:1) - Default 4:1=00011 | ||
| 52:63 | RW | OPCG_WAIT_CYCLES: old PAD value, delay at the begin and end of the OPCG run, to allow DC signals to be there at the right time (0 4095), needs to be higher than plat depth ! Default=0x020 | ||
| OPCG Control Register 0 | ||||
|---|---|---|---|---|
| Addr: |
0000000011030002 (SCOM) | |||
| Name: | TP.TCPAU1.OPCG_REG0 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | TP.TCPAU1.EPS.CC.OPCG.OPCG_REG0_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | RW | RUNN_MODE: 0=BIST-mode used for LBIST / 1=RUNN-mode used for ABIST/IOBIST | ||
| 1 | RWX | OPCG_GO: opcg go (start OPCG) - bit will b cleared when OPCG is done - poll for opcg_done in cplt_start reg | ||
| 2 | RWX | RUN_SCAN0: run scan0 (will override all BIST mode settings but the scan_ratio) - will start a scan0 run, bit gets cleared when OPCG is done - poll for opcg_done in cplt_start reg | ||
| 3 | RW | SCAN0_MODE: set PRPGs in scan0_mode but do not run automatic scan0 sequence | ||
| 4 | RWX | OPCG_IN_SLAVE_MODE: when selected, OPCG will wait for Master chiplet to get started. When Keep_MS_Mode is 0, SLAVE_MODE will be cleared after incoming trigger. | ||
| 5 | RWX | OPCG_IN_MASTER_MODE: when selected, OPCG will send out trigger to all Slave chiplets - When Keep_MS_MODE=0, MASTER_MODE gets cleared after sending out one Master trigger | ||
| 6 | RW | KEEP_MS_MODE: when set to 1, OPCG in M/S mode bits will not be cleared after one incoming OPCG trigger. Default is clear M/S mode bits | ||
| 7 | RW | TRIGGER_OPCG_ON_UNIT0_SYNC_LVL: Unit pin used for AVP can trigger OPCG (unit0_sync_lvl) | ||
| 8 | RW | TRIGGER_OPCG_ON_UNIT1_SYNC_LVL: Unit pin used for AVP can trigger OPCG (unit1_sync_lvl) | ||
| 9:10 | RW | UNUSED910: unused | ||
| 11 | RW | RUN_OPCG_ON_UPDATE_DR: start opcg engine when scan updated (update_dr) received (set pulse) Cronus requires this bit=1 for a setpulse WRITE | ||
| 12 | RW | RUN_OPCG_ON_CAPTURE_DR: start opcg engine when scan updated (capture_dr) received (set pulse) Cronus requires this bit=1 for a setpulse READ | ||
| 13 | RW | STOP_RUNN_ON_XSTOP: runn-mode: stop run-n on xstop | ||
| 14 | RW | OPCG_STARTS_BIST: runn-mode: OPCG engine controls start_bist for ABIST or IOBIST (see BIST register) | ||
| 15 | RW | RUNN_HLD_DLY_EN: runn-mode: Enable of the HLD Delay function - programming in OPCG_CAPT1,2,3 to allow staggered stop of Cores during Cache-Contained mode | ||
| 16:20 | RW | UNUSED1620: unused | ||
| 21:63 | RWX | LOOP_COUNT: Loop counter for LBIST and RUNN - write: target value - read: current counter value - will count from 0 to target value | ||
| OPCG Control Register 1 | ||||
|---|---|---|---|---|
| Addr: |
0000000011030003 (SCOM) | |||
| Name: | TP.TCPAU1.OPCG_REG1 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | TP.TCPAU1.EPS.CC.OPCG.OPCG_REG1_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:11 | RW | SCAN_COUNT: BIST mode: Channel scan count (s = 0-4095) runn-mode: start_bist match value(0:11) | ||
| 12:23 | RW | MISR_A_VAL: BIST mode: a value for MISR aperture, runn-mode: start_bist match value(12:23) | ||
| 24:35 | RW | MISR_B_VAL: BIST mode: b value for MISR aperture, runn-mode: start_bist match value(24:35) | ||
| 36:47 | RW | MISR_INIT_WAIT: BIST mode: delay MISR aperture, MISRs get active after this number of loops | ||
| 48 | RW | UNUSED48: Unused to suppress the last RUNN clock please look at CLK_REGION register bit 54 | ||
| 49 | RW | SCAN_CLK_USE_EVEN: Generate scan clock in even cycle instead of odd. Default is 0 = odd for scan | ||
| 50 | RW | DISABLE_FCE_DURING_FILL: Scan0 and LBIST - disable FCE during NSL Fill - LBIST_COMBINED=1 | ||
| 51 | RW | UNUSED51: unused | ||
| 52 | RW | RTIM_THOLD_FORCE: force rtim_thold low when not in test_dc mode (must be 0 at all time) | ||
| 53 | RW | DISABLE_ARY_CLK_DURING_FILL: LBIST and SCAN0: prevent fire of ARY HLD during NSL-fill - LBIST_COMBINED=1 | ||
| 54 | RW | SG_HIGH_DURING_FILL: LBIST and SCAN0: Hold SG high during NSL-fill | ||
| 55:56 | RW | LBIST_SKITTER_CTL: BIST mode: 00: enable skitter during lbist_ip, 01: enable skitter when misr_active - see misr_init_wait 10: skitter OPCG_GO mode - falling edge=start, rising edge=stop 11 - unused | ||
| 57 | RW | MISR_MODE: BIST mode: MISR aperture mode (0: a-1 to b-1, 1: start to a and b to end) | ||
| 58 | RW | INFINITE_MODE: infinite mode - RUNN and LBIST will run forever and ignore the loop count | ||
| 59:63 | RW | NSL_FILL_COUNT: BIST mode: NSL-fill count (0-31) | ||
| OPCG Control Register 2 | ||||
|---|---|---|---|---|
| Addr: |
0000000011030004 (SCOM) | |||
| Name: | TP.TCPAU1.OPCG_REG2 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | TP.TCPAU1.EPS.CC.OPCG.OPCG_REG2_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | RWX | OPCG_GO2: opcg go for broadcast sequences (start sequence) | ||
| 1:3 | RW | PRPG_WEIGHTING: prpg_activate: 1/2, 1/4, 1/8, 1/16, 1/2, 3/4, 7/8, 15/16 | ||
| 4:15 | RWX | PRPG_SEED: set to 0 for prpg always on, else seed | ||
| 16:27 | RW | PRPG_A_VAL: a value for PRPG aperture | ||
| 28:39 | RW | PRPG_B_VAL: b value for PRPG aperture | ||
| 40 | RW | PRPG_MODE: PRPG aperture mode (0: a-1 to b-1, 1: start to a and b to end) | ||
| 41:47 | RW | UNUSED41_47: unused | ||
| 48:51 | RW | SM_LBIST_CTRL_WEIGHT_SEL_PRIM: Stumpmux LBIST Control - weight select primary | ||
| 52:55 | RW | SM_LBIST_CTRL_WEIGHT_SEL_SEC_OR_APERTURE_MASK: Stumpmux LBIST Control - weight select secondary (when mode_select=0) or aperture_mask (when mode_select=1) | ||
| 56 | RW | SM_LBIST_CTRL_MODE_SELECT: Stumpmux LBIST Control - mode select - 0=secondary weight 1=aperture_mask | ||
| 57 | RW | SM_LBIST_CTRL_PRPG_HOLD_MODE: Stumpmux LBIST Control - PRPG hold mode | ||
| 58 | RW | SM_LBIST_CTRL_LOCAL_OVERRIDE: Stumpmux LBIST Control - Local Override | ||
| 59 | RW | SM_LBIST_CTRL_LOAD_APERTURE_VALUE: Stumpmux LBIST Control - Aperture Value | ||
| 60:63 | RW | SM_LBIST_CTRL_LOAD_APERTURE_SELECT: Stumpmux LBIST Control - Aperture Select | ||
| Scan Region and Type | ||||
|---|---|---|---|---|
| Addr: |
0000000011030005 (SCOM) | |||
| Name: | TP.TCPAU1.SCAN_REGION_TYPE | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0 | TP.TCPAU1.EPS.CC.CLOCK_MUX.SYSTEM_FAST_INIT_Q_INST.LATC.L2(0) [0] | |||
| 1 | TP.TCPAU1.EPS.CC.CLOCK_MUX.PARALLEL_SCAN_Q_INST.LATC.L2(0) [0] | |||
| 2 | TP.TCPAU1.EPS.CC.CLOCK_MUX.PARALLEL_SCAN_AND_NOTOR_Q_INST.LATC.L2(0) [0] | |||
| 3 | TP.TCPAU1.EPS.CC.CCFG.SCAN_REGION_VITL_INST.CCFG_Q_INST.FSILAT.LATC.L2(0) [0] | |||
| 4:18 | TP.TCPAU1.EPS.CC.CCFG.SCAN_REGION_INST.CCFG_Q_INST.FSILAT.LATC.L2(0:14) [000000000000000] | |||
| 48:59 | TP.TCPAU1.EPS.CC.CCFG.SCAN_TYPE_INST.CCFG_Q_INST.FSILAT.LATC.L2(0:11) [000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | RWX | SYSTEM_FAST_INIT: Default is 0, when its set to 1, the MASK bits in the CMSK chain decide, which part will be scanned or scan0. MASK=1=scan0, MASK=0-part or scan chain | ||
| 1 | RWX | PARALLEL_SCAN: Enable Parallel Scan of several regions with the same data | ||
| 2 | RWX | PARALLEL_SCAN_AND_NOTOR: Default is 0, return data will be OR-ed. When set to 1, the return data will be AND-ed | ||
| 3 | RWX | SCAN_REGION_VITL: scan clock region vitl (Vital = Clock) | ||
| 4 | RWX | SCAN_REGION_PERV: scan clock region perv (Pervasive) | ||
| 5 | RWX | SCAN_REGION_UNIT1: scan clock region 1 - pau0 | ||
| 6 | RWX | SCAN_REGION_UNIT2: scan clock region 2 - pau1 | ||
| 7 | RWX | SCAN_REGION_UNIT3: scan clock region 3 - reserved | ||
| 8 | RWX | SCAN_REGION_UNIT4: scan clock region 4 - reserved | ||
| 9 | RWX | SCAN_REGION_UNIT5: scan clock region 5 - tl | ||
| 10 | RWX | SCAN_REGION_UNIT6: scan clock region 6 - ioppe | ||
| 11 | RWX | SCAN_REGION_UNIT7: scan clock region 7 - unused | ||
| 12 | RWX | SCAN_REGION_UNIT8: scan clock region 8 - unused | ||
| 13 | RWX | SCAN_REGION_UNIT9: scan clock region 9 - unused | ||
| 14 | RWX | SCAN_REGION_UNIT10: scan clock region 10 - unused | ||
| 15 | RWX | SCAN_REGION_UNIT11: scan clock region 11 - unused | ||
| 16 | RWX | SCAN_REGION_UNIT12: scan clock region 12 - unused | ||
| 17 | RWX | SCAN_REGION_UNIT13: scan clock region 13 - unused | ||
| 18 | RWX | SCAN_REGION_UNIT14: scan clock region 14 - unused | ||
| 19:47 | RO | constant=0b00000000000000000000000000000 | ||
| 48 | RW | SCAN_TYPE_FUNC: scan chain func (functional) | ||
| 49 | RW | SCAN_TYPE_CFG: scan chain mode (boot config and debug config) | ||
| 50 | RW | SCAN_TYPE_CCFG_GPTR: scan chain ccfg / gptr (Pervasive: CC config, Others: GPTR) | ||
| 51 | RW | SCAN_TYPE_REGF: scan chain regf (register files) | ||
| 52 | RW | SCAN_TYPE_LBIST: scan chain lbst (LBIST) | ||
| 53 | RW | SCAN_TYPE_ABIST: scan chain abst (ABIST) | ||
| 54 | RW | SCAN_TYPE_REPR: scan chain repr (Array Repair) | ||
| 55 | RW | SCAN_TYPE_TIME: scan chain time (Array Timing) | ||
| 56 | RW | SCAN_TYPE_BNDY: scan chain bndy (Boundary IO's) | ||
| 57 | RW | SCAN_TYPE_FARR: scan chain farr (fast array unload) | ||
| 58 | RW | SCAN_TYPE_CMSK: scan chain cmsk (lbist channel mask) | ||
| 59 | RW | SCAN_TYPE_INEX: scan chain idex (c14 asic) | ||
| 60:63 | RO | constant=0b0000 | ||
| start/stop of Clocks | ||||
|---|---|---|---|---|
| Addr: |
0000000011030006 (SCOM) | |||
| Name: | TP.TCPAU1.CLK_REGION | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:3 | TP.TCPAU1.EPS.CC.CLOCK_MUX.CLOCK_CMD_Q_INST.LATC.L2(0:3) [0000] | |||
| 4:18 | TP.TCPAU1.EPS.CC.CCFG.CLOCK_REGION_INST.CCFG_Q_INST.FSILAT.LATC.L2(0:14) [000000000000000] | |||
| 48:50 | TP.TCPAU1.EPS.CC.CCFG.CLOCK_TYPE_INST.CCFG_Q_INST.FSILAT.LATC.L2(0:2) [000] | |||
| 52 | TP.TCPAU1.EPS.CC.CLOCK_MUX.CLOCK_PULSE_USE_EVEN_Q_INST.LATC.L2(0) [0] | |||
| 53 | TP.TCPAU1.EPS.CC.CLOCK_MUX.CLOCK_START_RUNN_SUPPR_FIRST_CLK_Q_INST.LATC.L2(0) [0] | |||
| 54 | TP.TCPAU1.EPS.CC.CLOCK_MUX.CLOCK_STOP_RUNN_SUPPR_LAST_CLK_Q_INST.LATC.L2(0) [0] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:1 | RWX | CLOCK_CMD: command for clock control: 00 NOP 01 START 10 STOP 11 PULSE (one pulse) | ||
| 2 | RWX | SLAVE_MODE: when selected, Clock Command will wait for Master chiplet to get started. Bit gets cleared after incoming Slave trigger and Keep_MS_Mode_after_trigger is set to 0 | ||
| 3 | RWX | MASTER_MODE: when selected, Clock Command will send out trigger to all Slave chiplets - Bit gets cleared after sending out one Master trigger and Keep_MS_Mode_after_trigger is set to 0 | ||
| 4 | RWX | CLOCK_REGION_PERV: for clock region perv (Pervasive) | ||
| 5 | RWX | CLOCK_REGION_UNIT1: for clock region 1 - pau0 | ||
| 6 | RWX | CLOCK_REGION_UNIT2: for clock region 2 - pau1 | ||
| 7 | RWX | CLOCK_REGION_UNIT3: for clock region 3 - reserved | ||
| 8 | RWX | CLOCK_REGION_UNIT4: for clock region 4 - reserved | ||
| 9 | RWX | CLOCK_REGION_UNIT5: for clock region 5 - tl | ||
| 10 | RWX | CLOCK_REGION_UNIT6: for clock region 6 - ioppe | ||
| 11 | RWX | CLOCK_REGION_UNIT7: for clock region 7 - unused | ||
| 12 | RWX | CLOCK_REGION_UNIT8: for clock region 8 - unused | ||
| 13 | RWX | CLOCK_REGION_UNIT9: for clock region 9 - unused | ||
| 14 | RWX | CLOCK_REGION_UNIT10: for clock region 10 - unused | ||
| 15 | RWX | CLOCK_REGION_UNIT11: for clock region 11 - unused | ||
| 16 | RWX | CLOCK_REGION_UNIT12: for clock region 12 - unused | ||
| 17 | RWX | CLOCK_REGION_UNIT13: for clock region 13 - unused | ||
| 18 | RWX | CLOCK_REGION_UNIT14: for clock region 14 - unused | ||
| 19:47 | RO | constant=0b00000000000000000000000000000 | ||
| 48 | RWX | SEL_THOLD_SL: select sl tholds | ||
| 49 | RWX | SEL_THOLD_NSL: select nsl tholds | ||
| 50 | RWX | SEL_THOLD_ARY: select array thold | ||
| 51 | RO | constant=0b0 | ||
| 52 | RW | CLOCK_PULSE_USE_EVEN: For dual mesh support: default for pulse is ODD phase, when this bit is set, pulse will by applied on EVEN phase | ||
| 53 | RW | CLOCK_START_RUNN_SUPPR_FIRST_CLK: For dual mesh support or 2:1 CC : A clock start or a RUNN will skip the first clock (EVEN) and starts with the ODD clock. | ||
| 54 | RW | CLOCK_STOP_RUNN_SUPPR_LAST_CLK: For dual mesh support or 2:1 CC : A clock stop or a RUNN will skip the last clock (ODD) and stops earlier with an EVEN clock. | ||
| 55:63 | RO | constant=0b000000000 | ||
| Clocks running sl | ||||
|---|---|---|---|---|
| Addr: |
0000000011030008 (SCOM) | |||
| Name: | TP.TCPAU1.CLOCK_STAT_SL | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 4:18 | TP.TCPAU1.EPS.CC.CLOCK_MUX.CLOCK_STATUS_SL_Q_INST.LATC.L2(0:14) [000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:3 | RO | constant=0b1111 | ||
| 4 | ROX | CLOCK_STATUS_PERV_SL: status of perv sl hld 0=run, 1=stop | ||
| 5 | ROX | CLOCK_STATUS_UNIT1_SL: status of region 1 - pau0 sl hld 0=run, 1=stop | ||
| 6 | ROX | CLOCK_STATUS_UNIT2_SL: status of region 2 - pau1 sl hld 0=run, 1=stop | ||
| 7 | ROX | CLOCK_STATUS_UNIT3_SL: status of region 3 - reserved sl hld 0=run, 1=stop | ||
| 8 | ROX | CLOCK_STATUS_UNIT4_SL: status of region 4 - reserved sl hld 0=run, 1=stop | ||
| 9 | ROX | CLOCK_STATUS_UNIT5_SL: status of region 5 - tl sl hld 0=run, 1=stop | ||
| 10 | ROX | CLOCK_STATUS_UNIT6_SL: status of region 6 - ioppe sl hld 0=run, 1=stop | ||
| 11 | ROX | CLOCK_STATUS_UNIT7_SL: status of region 7 - unused sl hld 0=run, 1=stop | ||
| 12 | ROX | CLOCK_STATUS_UNIT8_SL: status of region 8 - unused sl hld 0=run, 1=stop | ||
| 13 | ROX | CLOCK_STATUS_UNIT9_SL: status of region 9 - unused sl hld 0=run, 1=stop | ||
| 14 | ROX | CLOCK_STATUS_UNIT10_SL: status ofuregion 10 - nused sl hld 0=run, 1=stop | ||
| 15 | ROX | CLOCK_STATUS_UNIT11_SL: status of region 11 - unused sl hld 0=run, 1=stop | ||
| 16 | ROX | CLOCK_STATUS_UNIT12_SL: status of region 12 - unused sl hld 0=run, 1=stop | ||
| 17 | ROX | CLOCK_STATUS_UNIT13_SL: status of region 13 - unused sl hld 0=run, 1=stop | ||
| 18 | ROX | CLOCK_STATUS_UNIT14_SL: status of region 14 - unused sl hld 0=run, 1=stop | ||
| 19:63 | RO | constant=0b111111111111111111111111111111111111111111111 | ||
| Clocks running nsl | ||||
|---|---|---|---|---|
| Addr: |
0000000011030009 (SCOM) | |||
| Name: | TP.TCPAU1.CLOCK_STAT_NSL | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 4:18 | TP.TCPAU1.EPS.CC.CLOCK_MUX.CLOCK_STATUS_NSL_Q_INST.LATC.L2(0:14) [000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:3 | RO | constant=0b1111 | ||
| 4 | ROX | CLOCK_STATUS_PERV_NSL: status of perv nsl hld 0=run, 1=stop | ||
| 5 | ROX | CLOCK_STATUS_UNIT1_NSL: status of region 1 - pau0 nsl hld 0=run, 1=stop | ||
| 6 | ROX | CLOCK_STATUS_UNIT2_NSL: status of region 2 - pau1 nsl hld 0=run, 1=stop | ||
| 7 | ROX | CLOCK_STATUS_UNIT3_NSL: status of region 3 - reserved nsl hld 0=run, 1=stop | ||
| 8 | ROX | CLOCK_STATUS_UNIT4_NSL: status of region 4 - reserved nsl hld 0=run, 1=stop | ||
| 9 | ROX | CLOCK_STATUS_UNIT5_NSL: status of region 5 - tl nsl hld 0=run, 1=stop | ||
| 10 | ROX | CLOCK_STATUS_UNIT6_NSL: status of region 6 - ioppe nsl hld 0=run, 1=stop | ||
| 11 | ROX | CLOCK_STATUS_UNIT7_NSL: status of region 7 - unused nsl hld 0=run, 1=stop | ||
| 12 | ROX | CLOCK_STATUS_UNIT8_NSL: status of region 8 - unused nsl hld 0=run, 1=stop | ||
| 13 | ROX | CLOCK_STATUS_UNIT9_NSL: status of region 9 - unused nsl hld 0=run, 1=stop | ||
| 14 | ROX | CLOCK_STATUS_UNIT10_NSL: status ofuregion 10 - nused nsl hld 0=run, 1=stop | ||
| 15 | ROX | CLOCK_STATUS_UNIT11_NSL: status of region 11 - unused nsl hld 0=run, 1=stop | ||
| 16 | ROX | CLOCK_STATUS_UNIT12_NSL: status of region 12 - unused nsl hld 0=run, 1=stop | ||
| 17 | ROX | CLOCK_STATUS_UNIT13_NSL: status of region 13 - unused nsl hld 0=run, 1=stop | ||
| 18 | ROX | CLOCK_STATUS_UNIT14_NSL: status of region 14 - unused nsl hld 0=run, 1=stop | ||
| 19:63 | RO | constant=0b111111111111111111111111111111111111111111111 | ||
| Clocks running ary | ||||
|---|---|---|---|---|
| Addr: |
000000001103000A (SCOM) | |||
| Name: | TP.TCPAU1.CLOCK_STAT_ARY | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 4:18 | TP.TCPAU1.EPS.CC.CLOCK_MUX.CLOCK_STATUS_ARY_Q_INST.LATC.L2(0:14) [000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:3 | RO | constant=0b1111 | ||
| 4 | ROX | CLOCK_STATUS_PERV_ARY: status of perv ary hld 0=run, 1=stop | ||
| 5 | ROX | CLOCK_STATUS_UNIT1_ARY: status of region 1 - pau0 ary hld 0=run, 1=stop | ||
| 6 | ROX | CLOCK_STATUS_UNIT2_ARY: status of region 2 - pau1 ary hld 0=run, 1=stop | ||
| 7 | ROX | CLOCK_STATUS_UNIT3_ARY: status of region 3 - reserved ary hld 0=run, 1=stop | ||
| 8 | ROX | CLOCK_STATUS_UNIT4_ARY: status of region 4 - reserved ary hld 0=run, 1=stop | ||
| 9 | ROX | CLOCK_STATUS_UNIT5_ARY: status of region 5 - tl ary hld 0=run, 1=stop | ||
| 10 | ROX | CLOCK_STATUS_UNIT6_ARY: status of region 6 - ioppe ary hld 0=run, 1=stop | ||
| 11 | ROX | CLOCK_STATUS_UNIT7_ARY: status of region 7 - unused ary hld 0=run, 1=stop | ||
| 12 | ROX | CLOCK_STATUS_UNIT8_ARY: status of region 8 - unused ary hld 0=run, 1=stop | ||
| 13 | ROX | CLOCK_STATUS_UNIT9_ARY: status of region 9 - unused ary hld 0=run, 1=stop | ||
| 14 | ROX | CLOCK_STATUS_UNIT10_ARY: status ofuregion 10 - nused ary hld 0=run, 1=stop | ||
| 15 | ROX | CLOCK_STATUS_UNIT11_ARY: status of region 11 - unused ary hld 0=run, 1=stop | ||
| 16 | ROX | CLOCK_STATUS_UNIT12_ARY: status of region 12 - unused ary hld 0=run, 1=stop | ||
| 17 | ROX | CLOCK_STATUS_UNIT13_ARY: status of region 13 - unused ary hld 0=run, 1=stop | ||
| 18 | ROX | CLOCK_STATUS_UNIT14_ARY: status of region 14 - unused ary hld 0=run, 1=stop | ||
| 19:63 | RO | constant=0b111111111111111111111111111111111111111111111 | ||
| ABIST and IOBIST per region | ||||
|---|---|---|---|---|
| Addr: |
000000001103000B (SCOM) | |||
| Name: | TP.TCPAU1.BIST | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:3 | TP.TCPAU1.EPS.CC.BIST.BIST_CONFIG_Q_INST.LATC.L2(0:3) [0000] | |||
| 4:18 | TP.TCPAU1.EPS.CC.BIST.BIST_REGIONS_Q_INST.LATC.L2(0:14) [000000000000000] | |||
| 48 | TP.TCPAU1.EPS.CC.BIST.BIST_SETUP_Q_INST.LATC.L2(0) [0] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | RW | TC_BIST_START_TEST_DC: keep this 0 during ABIST/IOBIST. It could be used to bypass the RUNN start. When this bit is set, the BIST_START_TEST will go high immediately without waiting for RUNN. BIST will start with the first hld clock cycle. | ||
| 1 | RW | TC_SRAM_ABIST_MODE_DC: select the ABIST engines for SRAMs | ||
| 2 | RW | UNUSED_BC2: unused | ||
| 3 | RW | TC_IOBIST_MODE_DC: select the IOBIST engines | ||
| 4 | RW | BIST_REGION_PERV: region perv: 1=BIST_START_TEST for this region will be triggered, 0=region take not part of the ABIST/IOBIST run. | ||
| 5 | RW | BIST_REGION_UNIT1: region 1 - pau0: 1=BIST_START_TEST for this region will be triggered, 0=region take not part of the ABIST/IOBIST run. | ||
| 6 | RW | BIST_REGION_UNIT2: region 2 - pau1: 1=BIST_START_TEST for this region will be triggered, 0=region take not part of the ABIST/IOBIST run. | ||
| 7 | RW | BIST_REGION_UNIT3: region 3 - reserved: 1=BIST_START_TEST for this region will be triggered, 0=region take not part of the ABIST/IOBIST run. | ||
| 8 | RW | BIST_REGION_UNIT4: region 4 - reserved: 1=BIST_START_TEST for this region will be triggered, 0=region take not part of the ABIST/IOBIST run. | ||
| 9 | RW | BIST_REGION_UNIT5: region 5 - tl: 1=BIST_START_TEST for this region will be triggered, 0=region take not part of the ABIST/IOBIST run. | ||
| 10 | RW | BIST_REGION_UNIT6: region 6 - ioppe: 1=BIST_START_TEST for this region will be triggered, 0=region take not part of the ABIST/IOBIST run. | ||
| 11 | RW | BIST_REGION_UNIT7: region 7 - unused: 1=BIST_START_TEST for this region will be triggered, 0=region take not part of the ABIST/IOBIST run. | ||
| 12 | RW | BIST_REGION_UNIT8: region 8 - unused: 1=BIST_START_TEST for this region will be triggered, 0=region take not part of the ABIST/IOBIST run. | ||
| 13 | RW | BIST_REGION_UNIT9: region 9 - unused: 1=BIST_START_TEST for this region will be triggered, 0=region take not part of the ABIST/IOBIST run. | ||
| 14 | RW | BIST_REGION_UNIT10: region 10 - unused: 1=BIST_START_TEST for this region will be triggered, 0=region take not part of the ABIST/IOBIST run. | ||
| 15 | RW | BIST_REGION_UNIT11: region 11 - unused: 1=BIST_START_TEST for this region will be triggered, 0=region take not part of the ABIST/IOBIST run. | ||
| 16 | RW | BIST_REGION_UNIT12: region 12 - unused: 1=BIST_START_TEST for this region will be triggered, 0=region take not part of the ABIST/IOBIST run. | ||
| 17 | RW | BIST_REGION_UNIT13: region 13 - unused: 1=BIST_START_TEST for this region will be triggered, 0=region take not part of the ABIST/IOBIST run. | ||
| 18 | RW | BIST_REGION_UNIT14: region 14 - unused: 1=BIST_START_TEST for this region will be triggered, 0=region take not part of the ABIST/IOBIST run. | ||
| 19:47 | RO | constant=0b00000000000000000000000000000 | ||
| 48 | RW | BIST_STROBE_WINDOW_EN: Enable Strobe window only in TE=1 mode OPCGGO tester pin is enabling ABIST compare, once ABIST has been started. Special setup in ABIST engine is required. default is 0. System mode can not enable this feature | ||
| 49:63 | RO | constant=0b000000000000000 | ||
| XSTOP per region | ||||
|---|---|---|---|---|
| Addr: |
000000001103000C (SCOM) | |||
| Name: | TP.TCPAU1.XSTOP1 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:3 | TP.TCPAU1.EPS.CC.XSTOP1.XSTOP_CONFIG_Q_INST.LATC.L2(0:3) [0000] | |||
| 4:18 | TP.TCPAU1.EPS.CC.XSTOP1.XSTOP_REGIONS_Q_INST.LATC.L2(0:14) [000000000000000] | |||
| 48:59 | TP.TCPAU1.EPS.CC.XSTOP1.XSTOP_WAITS_Q_INST.LATC.L2(0:11) [000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | RW | XSTOP1_ENABLE: enable xstop to clockstop of selected regions, 0 = ignore chkstop, 1= stop on chkstop | ||
| 1 | RW | XSTOP1_WAIT_SNOPA: wait for SNOP align to stop clocks on checkstop | ||
| 2 | RW | XSTOP1_TRIGGER_OPCG_GO: trigger opcg on xstop instead of performing clockstop | ||
| 3 | RW | XSTOP1_WAIT_ALWAYS: when set to 1, xstop will wait independent from flush, default is no wait, when flush in not set | ||
| 4 | RW | XSTOP1_REGION_PERV: region perv: 1=region will be stopped, 0=region will keep running on xstop | ||
| 5 | RW | XSTOP1_REGION_UNIT1: region 1 - pau0: 1=region will be stopped, 0=region will keep running on xstop | ||
| 6 | RW | XSTOP1_REGION_UNIT2: region 2 - pau1: 1=region will be stopped, 0=region will keep running on xstop | ||
| 7 | RW | XSTOP1_REGION_UNIT3: region 3 - reserved: 1=region will be stopped, 0=region will keep running on xstop | ||
| 8 | RW | XSTOP1_REGION_UNIT4: region 4 - reserved: 1=region will be stopped, 0=region will keep running on xstop | ||
| 9 | RW | XSTOP1_REGION_UNIT5: region 5 - tl: 1=region will be stopped, 0=region will keep running on xstop | ||
| 10 | RW | XSTOP1_REGION_UNIT6: region 6 - ioppe: 1=region will be stopped, 0=region will keep running on xstop | ||
| 11 | RW | XSTOP1_REGION_UNIT7: region 7 - unused: 1=region will be stopped, 0=region will keep running on xstop | ||
| 12 | RW | XSTOP1_REGION_UNIT8: region 8 - unused: 1=region will be stopped, 0=region will keep running on xstop | ||
| 13 | RW | XSTOP1_REGION_UNIT9: region 9 - unused: 1=region will be stopped, 0=region will keep running on xstop | ||
| 14 | RW | XSTOP1_REGION_UNIT10: region 10 - unused: 1=region will be stopped, 0=region will keep running on xstop | ||
| 15 | RW | XSTOP1_REGION_UNIT11: region 11 - unused: 1=region will be stopped, 0=region will keep running on xstop | ||
| 16 | RW | XSTOP1_REGION_UNIT12: region 12 - unused: 1=region will be stopped, 0=region will keep running on xstop | ||
| 17 | RW | XSTOP1_REGION_UNIT13: region 13 - unused: 1=region will be stopped, 0=region will keep running on xstop | ||
| 18 | RW | XSTOP1_REGION_UNIT14: region 14 - unused: 1=region will be stopped, 0=region will keep running on xstop | ||
| 19:47 | RO | constant=0b00000000000000000000000000000 | ||
| 48:59 | RW | XSTOP1_WAIT_CYCLES: Defines, how many cycle xstop will wait after dropping flush, before tholds get dropped. 0-4095 cycles possible | ||
| 60:63 | RO | constant=0b0000 | ||
| XSTOP per region | ||||
|---|---|---|---|---|
| Addr: |
000000001103000D (SCOM) | |||
| Name: | TP.TCPAU1.XSTOP2 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:3 | TP.TCPAU1.EPS.CC.XSTOP2.XSTOP_CONFIG_Q_INST.LATC.L2(0:3) [0000] | |||
| 4:18 | TP.TCPAU1.EPS.CC.XSTOP2.XSTOP_REGIONS_Q_INST.LATC.L2(0:14) [000000000000000] | |||
| 48:59 | TP.TCPAU1.EPS.CC.XSTOP2.XSTOP_WAITS_Q_INST.LATC.L2(0:11) [000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | RW | XSTOP2_ENABLE: enable xstop to clockstop of select regions, 0 = ignore chkstop, 1= stop on chkstop | ||
| 1 | RW | XSTOP2_WAIT_SNOPA: wait for SNOP align to stop clocks on checkstop | ||
| 2 | RW | XSTOP2_TRIGGER_OPCG_GO: trigger opcg on xstop instead of performing clockstop | ||
| 3 | RW | XSTOP2_WAIT_ALWAYS: when set to 1, xstop will wait independent from flush, default is no wait, when flush in not set | ||
| 4 | RW | XSTOP2_REGION_PERV: region perv: 1=region will be stopped, 0=region will keep running on xstop | ||
| 5 | RW | XSTOP2_REGION_UNIT1: region 1 - pau0: 1=region will be stopped, 0=region will keep running on xstop | ||
| 6 | RW | XSTOP2_REGION_UNIT2: region 2 - pau1: 1=region will be stopped, 0=region will keep running on xstop | ||
| 7 | RW | XSTOP2_REGION_UNIT3: region 3 - reserved: 1=region will be stopped, 0=region will keep running on xstop | ||
| 8 | RW | XSTOP2_REGION_UNIT4: region 4 - reserved: 1=region will be stopped, 0=region will keep running on xstop | ||
| 9 | RW | XSTOP2_REGION_UNIT5: region 5 - tl: 1=region will be stopped, 0=region will keep running on xstop | ||
| 10 | RW | XSTOP2_REGION_UNIT6: region 6 - ioppe: 1=region will be stopped, 0=region will keep running on xstop | ||
| 11 | RW | XSTOP2_REGION_UNIT7: region 7 - unused: 1=region will be stopped, 0=region will keep running on xstop | ||
| 12 | RW | XSTOP2_REGION_UNIT8: region 8 - unused: 1=region will be stopped, 0=region will keep running on xstop | ||
| 13 | RW | XSTOP2_REGION_UNIT9: region 9 - unused: 1=region will be stopped, 0=region will keep running on xstop | ||
| 14 | RW | XSTOP2_REGION_UNIT10: region 10 - unused: 1=region will be stopped, 0=region will keep running on xstop | ||
| 15 | RW | XSTOP2_REGION_UNIT11: region 11 - unused: 1=region will be stopped, 0=region will keep running on xstop | ||
| 16 | RW | XSTOP2_REGION_UNIT12: region 12 - unused: 1=region will be stopped, 0=region will keep running on xstop | ||
| 17 | RW | XSTOP2_REGION_UNIT13: region 13 - unused: 1=region will be stopped, 0=region will keep running on xstop | ||
| 18 | RW | XSTOP2_REGION_UNIT14: region 14 - unused: 1=region will be stopped, 0=region will keep running on xstop | ||
| 19:47 | RO | constant=0b00000000000000000000000000000 | ||
| 48:59 | RW | XSTOP2_WAIT_CYCLES: Defines, how many cycle xstop will wait after dropping flush, before tholds get dropped. 0-4095 cycles possible | ||
| 60:63 | RO | constant=0b0000 | ||
| XSTOP per region | ||||
|---|---|---|---|---|
| Addr: |
000000001103000E (SCOM) | |||
| Name: | TP.TCPAU1.XSTOP3 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:3 | TP.TCPAU1.EPS.CC.XSTOP3.XSTOP_CONFIG_Q_INST.LATC.L2(0:3) [0000] | |||
| 4:18 | TP.TCPAU1.EPS.CC.XSTOP3.XSTOP_REGIONS_Q_INST.LATC.L2(0:14) [000000000000000] | |||
| 48:59 | TP.TCPAU1.EPS.CC.XSTOP3.XSTOP_WAITS_Q_INST.LATC.L2(0:11) [000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | RW | XSTOP3_ENABLE: enable xstop to clockstop of select regions, 0 = ignore chkstop, 1= stop on chkstop | ||
| 1 | RW | XSTOP3_WAIT_SNOPA: wait for SNOP align to stop clocks on checkstop | ||
| 2 | RW | XSTOP3_TRIGGER_OPCG_GO: trigger opcg on xstop instead of performing clockstop | ||
| 3 | RW | XSTOP3_WAIT_ALWAYS: when set to 1, xstop will wait independent from flush, default is no wait, when flush in not set | ||
| 4 | RW | XSTOP3_REGION_PERV: region perv: 1=region will be stopped, 0=region will keep running on xstop | ||
| 5 | RW | XSTOP3_REGION_UNIT1: region 1 - pau0: 1=region will be stopped, 0=region will keep running on xstop | ||
| 6 | RW | XSTOP3_REGION_UNIT2: region 2 - pau1: 1=region will be stopped, 0=region will keep running on xstop | ||
| 7 | RW | XSTOP3_REGION_UNIT3: region 3 - reserved: 1=region will be stopped, 0=region will keep running on xstop | ||
| 8 | RW | XSTOP3_REGION_UNIT4: region 4 - reserved: 1=region will be stopped, 0=region will keep running on xstop | ||
| 9 | RW | XSTOP3_REGION_UNIT5: region 5 - tl: 1=region will be stopped, 0=region will keep running on xstop | ||
| 10 | RW | XSTOP3_REGION_UNIT6: region 6 - ioppe: 1=region will be stopped, 0=region will keep running on xstop | ||
| 11 | RW | XSTOP3_REGION_UNIT7: region 7 - unused: 1=region will be stopped, 0=region will keep running on xstop | ||
| 12 | RW | XSTOP3_REGION_UNIT8: region 8 - unused: 1=region will be stopped, 0=region will keep running on xstop | ||
| 13 | RW | XSTOP3_REGION_UNIT9: region 9 - unused: 1=region will be stopped, 0=region will keep running on xstop | ||
| 14 | RW | XSTOP3_REGION_UNIT10: region 10 - unused: 1=region will be stopped, 0=region will keep running on xstop | ||
| 15 | RW | XSTOP3_REGION_UNIT11: region 11 - unused: 1=region will be stopped, 0=region will keep running on xstop | ||
| 16 | RW | XSTOP3_REGION_UNIT12: region 12 - unused: 1=region will be stopped, 0=region will keep running on xstop | ||
| 17 | RW | XSTOP3_REGION_UNIT13: region 13 - unused: 1=region will be stopped, 0=region will keep running on xstop | ||
| 18 | RW | XSTOP3_REGION_UNIT14: region 14 - unused: 1=region will be stopped, 0=region will keep running on xstop | ||
| 19:47 | RO | constant=0b00000000000000000000000000000 | ||
| 48:59 | RW | XSTOP3_WAIT_CYCLES: Defines, how many cycle xstop will wait after dropping flush, before tholds get dropped. 0-4095 cycles possible | ||
| 60:63 | RO | constant=0b0000 | ||
| Error Status of CC | ||||
|---|---|---|---|---|
| Addr: |
000000001103000F (SCOM) | |||
| Name: | TP.TCPAU1.ERROR_STATUS | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0 | TP.TCPAU1.EPS.CC.ERROR.ERROR_REG_Q_0_INST.LATC.L2(0) [0] | |||
| 1 | TP.TCPAU1.EPS.CC.ERROR.ERROR_REG_Q_1_INST.LATC.L2(1) [0] | |||
| 2 | TP.TCPAU1.EPS.CC.ERROR.ERROR_REG_Q_2_INST.LATC.L2(2) [0] | |||
| 3 | TP.TCPAU1.EPS.CC.ERROR.ERROR_REG_Q_3_INST.LATC.L2(3) [0] | |||
| 4 | TP.TCPAU1.EPS.CC.ERROR.ERROR_REG_Q_4_INST.LATC.L2(4) [0] | |||
| 5 | TP.TCPAU1.EPS.CC.ERROR.ERROR_REG_Q_5_INST.LATC.L2(5) [0] | |||
| 6 | TP.TCPAU1.EPS.CC.ERROR.ERROR_REG_Q_6_INST.LATC.L2(6) [0] | |||
| 7 | TP.TCPAU1.EPS.CC.ERROR.ERROR_REG_Q_7_INST.LATC.L2(7) [0] | |||
| 8 | TP.TCPAU1.EPS.CC.ERROR.ERROR_REG_Q_8_INST.LATC.L2(8) [0] | |||
| 9 | TP.TCPAU1.EPS.CC.ERROR.ERROR_REG_Q_9_INST.LATC.L2(9) [0] | |||
| 10 | TP.TCPAU1.EPS.CC.ERROR.ERROR_REG_Q_10_INST.LATC.L2(10) [0] | |||
| 11 | TP.TCPAU1.EPS.CC.ERROR.ERROR_REG_Q_11_INST.LATC.L2(11) [0] | |||
| 12 | TP.TCPAU1.EPS.CC.ERROR.ERROR_REG_Q_12_INST.LATC.L2(12) [0] | |||
| 13 | TP.TCPAU1.EPS.CC.ERROR.ERROR_REG_Q_13_INST.LATC.L2(13) [0] | |||
| 14 | TP.TCPAU1.EPS.CC.ERROR.ERROR_REG_Q_14_INST.LATC.L2(14) [0] | |||
| 15 | TP.TCPAU1.EPS.CC.ERROR.ERROR_REG_Q_15_INST.LATC.L2(15) [0] | |||
| 16 | TP.TCPAU1.EPS.CC.ERROR.ERROR_REG_Q_16_INST.LATC.L2(16) [0] | |||
| 17 | TP.TCPAU1.EPS.CC.ERROR.ERROR_REG_Q_17_INST.LATC.L2(17) [0] | |||
| 18 | TP.TCPAU1.EPS.CC.ERROR.ERROR_REG_Q_18_INST.LATC.L2(18) [0] | |||
| 19 | TP.TCPAU1.EPS.CC.ERROR.ERROR_REG_Q_19_INST.LATC.L2(19) [0] | |||
| 20 | TP.TCPAU1.EPS.CC.ERROR.ERROR_REG_Q_20_INST.LATC.L2(20) [0] | |||
| 21 | TP.TCPAU1.EPS.CC.ERROR.ERROR_REG_Q_21_INST.LATC.L2(21) [0] | |||
| 22 | TP.TCPAU1.EPS.CC.ERROR.ERROR_REG_Q_22_INST.LATC.L2(22) [0] | |||
| 23 | TP.TCPAU1.EPS.CC.ERROR.ERROR_REG_Q_23_INST.LATC.L2(23) [0] | |||
| 24 | TP.TCPAU1.EPS.CC.ERROR.ERROR_REG_Q_24_INST.LATC.L2(24) [0] | |||
| 25 | TP.TCPAU1.EPS.CC.ERROR.ERROR_REG_Q_25_INST.LATC.L2(25) [0] | |||
| 26 | TP.TCPAU1.EPS.CC.ERROR.ERROR_REG_Q_26_INST.LATC.L2(26) [0] | |||
| 27 | TP.TCPAU1.EPS.CC.ERROR.ERROR_REG_Q_27_INST.LATC.L2(27) [0] | |||
| 28 | TP.TCPAU1.EPS.CC.ERROR.ERROR_REG_Q_28_INST.LATC.L2(28) [0] | |||
| 29 | TP.TCPAU1.EPS.CC.ERROR.ERROR_REG_Q_29_INST.LATC.L2(29) [0] | |||
| 30 | TP.TCPAU1.EPS.CC.ERROR.ERROR_REG_Q_30_INST.LATC.L2(30) [0] | |||
| 31 | TP.TCPAU1.EPS.CC.ERROR.ERROR_REG_Q_31_INST.LATC.L2(31) [0] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | RWX | PCB_WRITE_NOT_ALLOWED_ERR: write on read only register | ||
| 1 | RWX | PCB_READ_NOT_ALLOWED_ERR: read not allowed, maybe write only register | ||
| 2 | RWX | PCB_PARITY_ON_CMD_ERR: parity error on cmd | ||
| 3 | RWX | PCB_ADDRESS_NOT_VALID_ERR: invalid address | ||
| 4 | RWX | PCB_PARITY_ON_ADDR_ERR: parity error on addr | ||
| 5 | RWX | PCB_PARITY_ON_DATA_ERR: parity error on data | ||
| 6 | RWX | PCB_PROTECTED_ACCESS_INVALID_ERR: protection violation | ||
| 7 | RWX | PCB_PARITY_ON_SPCIF_ERR: parity error on spcif | ||
| 8 | RWX | PCB_WRITE_AND_OPCG_IP_ERR: pcb write while OPCG is running | ||
| 9 | RWX | SCAN_READ_AND_OPCG_IP_ERR: scan read when opcg is running | ||
| 10 | RWX | CLOCK_CMD_CONFLICT_ERR: clock cmd in progress | ||
| 11 | RWX | SCAN_COLLISION_ERR: scan region selected of running region | ||
| 12 | RWX | PREVENTED_SCAN_COLLISION_ERR: PCB request to set scan region which is running | ||
| 13 | RWX | OPCG_TRIGGER_ERR: OPCG gets triggered while OPCG is running | ||
| 14 | RWX | PHASE_CNT_CORRUPTION_ERR: phase counters inside chiplet out of sync | ||
| 15 | RWX | CLOCK_CMD_PREVENTED_ERR: security or scan collision prevented a clock start | ||
| 16 | RWX | PARITY_ON_OPCG_SM_ERR: parity error on OPCG state machine | ||
| 17 | RWX | PARITY_ON_CLOCK_MUX_REG_ERR: parity error on scan/clock region/type or clock status reg | ||
| 18 | RWX | PARITY_ON_OPCG_REG_ERR: parity error on OPCG regs | ||
| 19 | RWX | PARITY_ON_SYNC_CONFIG_REG_ERR: parity error on sync config reg | ||
| 20 | RWX | PARITY_ON_XSTOP_REG_ERR: parity error on xstop reg | ||
| 21 | RWX | PARITY_ON_GPIO_REG_ERR: parity error on GP0,4,5,6 regs | ||
| 22 | RWX | CLKCMD_REQUEST_ERR: region clkcmd has two requests start and stop at the same time start clkcmd will win, but this still causes this error bit go high | ||
| 23 | RWX | CBS_PROTOCOL_ERR: CBS protocol error - REQ / ACK sequence wrong ERROR is when REQ goes low before ACK goes high | ||
| 24 | RWX | VITL_ALIGN_ERR: VITL alignment is out of sync to sync pulse | ||
| 25 | RWX | UNIT_SYNC_LVL_ERR: Unit0 and Unit1 sync lvl pulse are not in sync - AVP broken | ||
| 26 | RWX | PARITY_ON_SELFBOOT_CMD_STATE_ERR: Parity error on selfboot cmd state | ||
| 27 | RWX | OPCG_STOPPED_BY_PCB_ERR: OPCG has been stopped by write on a new register | ||
| 28 | RWX | UNUSED_ERROR28: unused | ||
| 29 | RWX | UNUSED_ERROR29: unused | ||
| 30 | RWX | UNUSED_ERROR30: unused | ||
| 31 | RWX | UNUSED_ERROR31: unused | ||
| OPCG Control Register Capture1 | ||||
|---|---|---|---|---|
| Addr: |
0000000011030010 (SCOM) | |||
| Name: | TP.TCPAU1.OPCG_CAPT1 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | TP.TCPAU1.EPS.CC.OPCG.OPCG_CAPT1_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:3 | RW | COUNT: 0000=12 cycle 0001 - 1100= cycle 1-12 1101-1111=24 normal, no fast | ||
| 4:8 | RW | SEQ_01: sequence cycle 1 for normal/slow region (sl, nsl, ary, se, fce) | ||
| 9:13 | RW | SEQ_02: sequence cycle 2 for normal/slow region (sl, nsl, ary, se, fce) | ||
| 14:18 | RW | SEQ_03: sequence cycle 3 for normal/slow region (sl, nsl, ary, se, fce) | ||
| 19:23 | RW | SEQ_04: sequence cycle 4 for normal/slow region (sl, nsl, ary, se, fce) | ||
| 24:28 | RW | SEQ_05: sequence cycle 5 for normal/slow region (sl, nsl, ary, se, fce) | ||
| 29:33 | RW | SEQ_06: sequence cycle 6 for normal/slow region (sl, nsl, ary, se, fce) | ||
| 34:38 | RW | SEQ_07: sequence cycle 7 for normal/slow region (sl, nsl, ary, se, fce) | ||
| 39:43 | RW | SEQ_08: sequence cycle 8 for normal/slow region (sl, nsl, ary, se, fce) | ||
| 44:48 | RW | SEQ_09: sequence cycle 9 for normal/slow region (sl, nsl, ary, se, fce) | ||
| 49:53 | RW | SEQ_10: sequence cycle 10 for normal/slow region (sl, nsl, ary, se, fce) | ||
| 54:58 | RW | SEQ_11: sequence cycle 11 for normal/slow region (sl, nsl, ary, se, fce) | ||
| 59:63 | RW | SEQ_12: sequence cycle 12 for normal/slow region (sl, nsl, ary, se, fce) | ||
| OPCG Control Register Capture 2 | ||||
|---|---|---|---|---|
| Addr: |
0000000011030011 (SCOM) | |||
| Name: | TP.TCPAU1.OPCG_CAPT2 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | TP.TCPAU1.EPS.CC.OPCG.OPCG_CAPT2_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:3 | RW | UNUSED_CAPT2: | ||
| 4:8 | RW | SEQ_13_01EVEN: sequence cycle 1 - even - for fast region or cycle 13 for normal region (sl, nsl, ary, se, fce) | ||
| 9:13 | RW | SEQ_14_01ODD: sequence cycle 1 - odd - for fast region or cycle 14 for normal region (sl, nsl, ary, se, fce) | ||
| 14:18 | RW | SEQ_15_02EVEN: sequence cycle 2 - even - for fast region or cycle 15 for normal region (sl, nsl, ary, se, fce) | ||
| 19:23 | RW | SEQ_16_02ODD: sequence cycle 2 - odd - for fast region or cycle 16 for normal region (sl, nsl, ary, se, fce) | ||
| 24:28 | RW | SEQ_17_03EVEN: sequence cycle 3 - even - for fast region or cycle 17 for normal region (sl, nsl, ary, se, fce) | ||
| 29:33 | RW | SEQ_18_03ODD: sequence cycle 3 - odd - for fast region or cycle 18 for normal region (sl, nsl, ary, se, fce) | ||
| 34:38 | RW | SEQ_19_04EVEN: sequence cycle 4 - even - for fast region or cycle 19 for normal region (sl, nsl, ary, se, fce) | ||
| 39:43 | RW | SEQ_20_04ODD: sequence cycle 4 - odd - for fast region or cycle 20 for normal region (sl, nsl, ary, se, fce) | ||
| 44:48 | RW | SEQ_21_05EVEN: sequence cycle 5 - even - for fast region or cycle 21 for normal region (sl, nsl, ary, se, fce) | ||
| 49:53 | RW | SEQ_22_05ODD: sequence cycle 5 - odd - for fast region or cycle 22 for normal region (sl, nsl, ary, se, fce) | ||
| 54:58 | RW | SEQ_23_06EVEN: sequence cycle 6 - even - for fast region or cycle 23 for normal region (sl, nsl, ary, se, fce) | ||
| 59:63 | RW | SEQ_24_06ODD: sequence cycle 6 - odd - for fast region or cycle 24 for normal region (sl, nsl, ary, se, fce) | ||
| OPCG Control Register Capture 3 | ||||
|---|---|---|---|---|
| Addr: |
0000000011030012 (SCOM) | |||
| Name: | TP.TCPAU1.OPCG_CAPT3 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | TP.TCPAU1.EPS.CC.OPCG.OPCG_CAPT3_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:3 | RW | UNUSED_CAPT3: | ||
| 4:8 | RW | SEQ_07EVEN: sequence cycle 7 - even - for fast region (sl, nsl, ary, se, fce) | ||
| 9:13 | RW | SEQ_07ODD: sequence cycle 7 - odd - for fast region (sl, nsl, ary, se, fce) | ||
| 14:18 | RW | SEQ_08EVEN: sequence cycle 8 - even - for fast region (sl, nsl, ary, se, fce) | ||
| 19:23 | RW | SEQ_08ODD: sequence cycle 8 - odd - for fast region (sl, nsl, ary, se, fce) | ||
| 24:28 | RW | SEQ_09EVEN: sequence cycle 9 - even - for fast region (sl, nsl, ary, se, fce) | ||
| 29:33 | RW | SEQ_09ODD: sequence cycle 9 - odd - for fast region (sl, nsl, ary, se, fce) | ||
| 34:38 | RW | SEQ_10EVEN: sequence cycle 10 - even - for fast region (sl, nsl, ary, se, fce) | ||
| 39:43 | RW | SEQ_10ODD: sequence cycle 10 - odd - for fast region (sl, nsl, ary, se, fce) | ||
| 44:48 | RW | SEQ_11EVEN: sequence cycle 11 - even - for fast region (sl, nsl, ary, se, fce) | ||
| 49:53 | RW | SEQ_11ODD: sequence cycle 11 - odd - for fast region (sl, nsl, ary, se, fce) | ||
| 54:58 | RW | SEQ_12EVEN: sequence cycle 12 - even - for fast region (sl, nsl, ary, se, fce) | ||
| 59:63 | RW | SEQ_12ODD: sequence cycle 12 - odd - for fast region (sl, nsl, ary, se, fce) | ||
| Debug CBS CC Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011030013 (SCOM) | |||
| Name: | TP.TCPAU1.DBG_CBS_CC | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:31 | TP.TCPAU1.EPS.CC.SELFBOOT.DBG_CBS_CC_REG_Q_INST.LATC.L2(0:31) [00000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | ROX | DBG_RESET_EP: Reset Endpoint - Is the CC and CTRL in reset state | ||
| 1 | ROX | DBG_OPCG_IP: OPCG in progress, not in idle | ||
| 2 | ROX | DBG_VITL_CLKOFF: VITL HLD stopped, when enabled, need plat-depth cycles to switch this latch | ||
| 3 | ROX | DBG_TEST_ENABLE: Test Enable | ||
| 4 | ROX | DBG_CBS_REQ: CBS Interface - Request (Latched) | ||
| 5:7 | ROX | DBG_CBS_CMD: CBS Interface - Command (Latched) | ||
| 8:12 | ROX | DBG_CBS_STATE: CBS Command State Machine 00000=Idle | ||
| 13 | ROX | DBG_SECURITY_DEBUG_MODE: status of the security mode bit | ||
| 14 | ROX | DBG_CBS_PROTOCOL_ERROR: CBS Protocol Error - REQ raised, although state machine is not in IDLE - need reset_ep to clear this bit. No impact on IPL | ||
| 15 | ROX | DBG_PCB_IDLE: PCB Interface in IDLE state | ||
| 16:19 | ROX | DBG_CURRENT_OPCG_MODE: current / latest OPCG MODE - 0=NOP, 1=LBIST, 2=ABIST, 3=RUNN, 4=SCAN0, 5=SCAN, 6=SCAN rotate, 7=SCAN w UpdateDR, 8=SCAN w CaptureDR, 9=nonblocking SCAN, 10=CLK Change Request, 11-15=unused | ||
| 20:23 | ROX | DBG_LAST_OPCG_MODE: previous OPCG MODE | ||
| 24 | ROX | DBG_PCB_ERROR: PCB Interface Error, read CC Error Reg or set CBS_CMD=001 to switch FSI CBS Debug Information to CC Error Register. | ||
| 25 | ROX | DBG_PARITY_ERROR: Any Parity Error, non PCB Parity - read CC Error Reg or set CBS_CMD=001 to switch FSI CBS Debug Information to CC Error Register. | ||
| 26 | ROX | DBG_CC_ERROR: Any other CC Error - read CC Error Reg or set CBS_CMD=001 to switch FSI CBS Debug Information to CC Error Register. | ||
| 27 | ROX | DBG_CHIPLET_IS_ALIGNED: Is 1 when the a valid align pulse ws send out. | ||
| 28 | ROX | DBG_PCB_REQUEST_SINCE_RESET: RESET will clear that bit, the first PCB request will set it. | ||
| 29 | ROX | DBG_PARANOIA_TEST_ENABLE_CHANGE: rising or falling edge on test enable, after reset - need reset_ep to clear, no impact on IPL | ||
| 30 | ROX | DBG_PARANOIA_VITL_CLKOFF_CHANGE: rising or falling edge on vitl_clkoff, after reset - need reset_ep to clear, no impact on IPL | ||
| 31 | ROX | TP_TPFSI_CBS_ACK: only represenation of CC ack signal going to FSI | ||
| XSTOP per region | ||||
|---|---|---|---|---|
| Addr: |
0000000011030014 (SCOM) | |||
| Name: | TP.TCPAU1.XSTOP4 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:3 | TP.TCPAU1.EPS.CC.XSTOP4.XSTOP_CONFIG_Q_INST.LATC.L2(0:3) [0000] | |||
| 4:18 | TP.TCPAU1.EPS.CC.XSTOP4.XSTOP_REGIONS_Q_INST.LATC.L2(0:14) [000000000000000] | |||
| 48:59 | TP.TCPAU1.EPS.CC.XSTOP4.XSTOP_WAITS_Q_INST.LATC.L2(0:11) [000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | RW | XSTOP4_ENABLE: enable xstop to clockstop of selected regions, 0 = ignore chkstop, 1= stop on chkstop | ||
| 1 | RW | XSTOP4_WAIT_SNOPA: wait for SNOP align to stop clocks on checkstop | ||
| 2 | RW | XSTOP4_TRIGGER_OPCG_GO: trigger opcg on xstop instead of performing clockstop | ||
| 3 | RW | XSTOP4_WAIT_ALWAYS: when set to 1, xstop will wait independent from flush, default is no wait, when flush in not set | ||
| 4 | RW | XSTOP4_REGION_PERV: region perv: 1=region will be stopped, 0=region will keep running on xstop | ||
| 5 | RW | XSTOP4_REGION_UNIT1: region 1 - pau0: 1=region will be stopped, 0=region will keep running on xstop | ||
| 6 | RW | XSTOP4_REGION_UNIT2: region 2 - pau1: 1=region will be stopped, 0=region will keep running on xstop | ||
| 7 | RW | XSTOP4_REGION_UNIT3: region 3 - reserved: 1=region will be stopped, 0=region will keep running on xstop | ||
| 8 | RW | XSTOP4_REGION_UNIT4: region 4 - reserved: 1=region will be stopped, 0=region will keep running on xstop | ||
| 9 | RW | XSTOP4_REGION_UNIT5: region 5 - tl: 1=region will be stopped, 0=region will keep running on xstop | ||
| 10 | RW | XSTOP4_REGION_UNIT6: region 6 - ioppe: 1=region will be stopped, 0=region will keep running on xstop | ||
| 11 | RW | XSTOP4_REGION_UNIT7: region 7 - unused: 1=region will be stopped, 0=region will keep running on xstop | ||
| 12 | RW | XSTOP4_REGION_UNIT8: region 8 - unused: 1=region will be stopped, 0=region will keep running on xstop | ||
| 13 | RW | XSTOP4_REGION_UNIT9: region 9 - unused: 1=region will be stopped, 0=region will keep running on xstop | ||
| 14 | RW | XSTOP4_REGION_UNIT10: region 10 - unused: 1=region will be stopped, 0=region will keep running on xstop | ||
| 15 | RW | XSTOP4_REGION_UNIT11: region 11 - unused: 1=region will be stopped, 0=region will keep running on xstop | ||
| 16 | RW | XSTOP4_REGION_UNIT12: region 12 - unused: 1=region will be stopped, 0=region will keep running on xstop | ||
| 17 | RW | XSTOP4_REGION_UNIT13: region 13 - unused: 1=region will be stopped, 0=region will keep running on xstop | ||
| 18 | RW | XSTOP4_REGION_UNIT14: region 14 - unused: 1=region will be stopped, 0=region will keep running on xstop | ||
| 19:47 | RO | constant=0b00000000000000000000000000000 | ||
| 48:59 | RW | XSTOP4_WAIT_CYCLES: Defines, how many cycle xstop will wait after dropping flush, before tholds get dropped. 0-4095 cycles possible | ||
| 60:63 | RO | constant=0b0000 | ||
| XSTOP per region | ||||
|---|---|---|---|---|
| Addr: |
0000000011030015 (SCOM) | |||
| Name: | TP.TCPAU1.XSTOP5 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:3 | TP.TCPAU1.EPS.CC.XSTOP5.XSTOP_CONFIG_Q_INST.LATC.L2(0:3) [0000] | |||
| 4:18 | TP.TCPAU1.EPS.CC.XSTOP5.XSTOP_REGIONS_Q_INST.LATC.L2(0:14) [000000000000000] | |||
| 48:59 | TP.TCPAU1.EPS.CC.XSTOP5.XSTOP_WAITS_Q_INST.LATC.L2(0:11) [000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | RW | XSTOP5_ENABLE: enable xstop to clockstop of selected regions, 0 = ignore chkstop, 1= stop on chkstop | ||
| 1 | RW | XSTOP5_WAIT_SNOPA: wait for SNOP align to stop clocks on checkstop | ||
| 2 | RW | XSTOP5_TRIGGER_OPCG_GO: trigger opcg on xstop instead of performing clockstop | ||
| 3 | RW | XSTOP5_WAIT_ALWAYS: when set to 1, xstop will wait independent from flush, default is no wait, when flush in not set | ||
| 4 | RW | XSTOP5_REGION_PERV: region perv: 1=region will be stopped, 0=region will keep running on xstop | ||
| 5 | RW | XSTOP5_REGION_UNIT1: region 1 - pau0: 1=region will be stopped, 0=region will keep running on xstop | ||
| 6 | RW | XSTOP5_REGION_UNIT2: region 2 - pau1: 1=region will be stopped, 0=region will keep running on xstop | ||
| 7 | RW | XSTOP5_REGION_UNIT3: region 3 - reserved: 1=region will be stopped, 0=region will keep running on xstop | ||
| 8 | RW | XSTOP5_REGION_UNIT4: region 4 - reserved: 1=region will be stopped, 0=region will keep running on xstop | ||
| 9 | RW | XSTOP5_REGION_UNIT5: region 5 - tl: 1=region will be stopped, 0=region will keep running on xstop | ||
| 10 | RW | XSTOP5_REGION_UNIT6: region 6 - ioppe: 1=region will be stopped, 0=region will keep running on xstop | ||
| 11 | RW | XSTOP5_REGION_UNIT7: region 7 - unused: 1=region will be stopped, 0=region will keep running on xstop | ||
| 12 | RW | XSTOP5_REGION_UNIT8: region 8 - unused: 1=region will be stopped, 0=region will keep running on xstop | ||
| 13 | RW | XSTOP5_REGION_UNIT9: region 9 - unused: 1=region will be stopped, 0=region will keep running on xstop | ||
| 14 | RW | XSTOP5_REGION_UNIT10: region 10 - unused: 1=region will be stopped, 0=region will keep running on xstop | ||
| 15 | RW | XSTOP5_REGION_UNIT11: region 11 - unused: 1=region will be stopped, 0=region will keep running on xstop | ||
| 16 | RW | XSTOP5_REGION_UNIT12: region 12 - unused: 1=region will be stopped, 0=region will keep running on xstop | ||
| 17 | RW | XSTOP5_REGION_UNIT13: region 13 - unused: 1=region will be stopped, 0=region will keep running on xstop | ||
| 18 | RW | XSTOP5_REGION_UNIT14: region 14 - unused: 1=region will be stopped, 0=region will keep running on xstop | ||
| 19:47 | RO | constant=0b00000000000000000000000000000 | ||
| 48:59 | RW | XSTOP5_WAIT_CYCLES: Defines, how many cycle xstop will wait after dropping flush, before tholds get dropped. 0-4095 cycles possible | ||
| 60:63 | RO | constant=0b0000 | ||
| Region CCFLUSH Status | ||||
|---|---|---|---|---|
| Addr: |
0000000011030016 (SCOM) | |||
| Name: | TP.TCPAU1.REGION_CCFLUSH_STATUS | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 4:18 | TP.TCPAU1.EPS.CC.CLOCK_MUX.REGION_FLUSHMODE_INH_Q_INST.LATC.L2(0:14) [000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:3 | RO | constant=0b0000 | ||
| 4:18 | ROX | REGION_CCFLUSH: Region CCFLUSH status - 0=region not in flush, 1= region in flush state | ||
| 19:63 | RO | constant=0b000000000000000000000000000000000000000000000 | ||
| OPCG GO - Start OPCG on WRITE to this register | ||||
|---|---|---|---|---|
| Addr: |
0000000011030020 (SCOM) | |||
| Name: | TP.TCPAU1.PCB_OPCG_GO | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0 | TP.TCPAU1.EPS.CC.OPCG.PCB_WRITE_OPCG_GO_Q_INST.LATC.L2(0) [0] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | WOX | PCB_OPCGGO: opcg go (start OPCG) - write this register to start OPCG | ||
| Careful use only: a WRITE of xFACE000000000000 will reset the phase counter. Alignment of the chiplet is broken | ||||
|---|---|---|---|---|
| Addr: |
0000000011030028 (SCOM) | |||
| Name: | TP.TCPAU1.PHASE_COUNTER_RESET | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0 | TP.TCPAU1.EPS.CC.PCB.PCB_WRITE_RESET_PHASE_COUNTER_Q_INST.LATC.L2(0) [0] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | WOX | PHASECOUNTER_RESET: Careful use only: a WRITE of xFACE000000000000 will reset the phase counter. Alignment of the chiplet is broken | ||
| OPCG STOP - Stop OPCG when in RUNN or LBIST | ||||
|---|---|---|---|---|
| Addr: |
0000000011030030 (SCOM) | |||
| Name: | TP.TCPAU1.PCB_OPCG_STOP | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0 | TP.TCPAU1.EPS.CC.OPCG.PCB_WRITE_OPCG_LOOP_STOP_Q_INST.LATC.L2(0) [0] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | WOX | PCB_OPCGSTOP: opcg stop (stop OPCG) - write this register to stop OPCG during RUNN or LBIST | ||
| CC Protect Mode Register | ||||
|---|---|---|---|---|
| Addr: |
00000000110303FE (SCOM) | |||
| Name: | TP.TCPAU1.CC_PROTECT_MODE_REG | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0 | TP.TCPAU1.EPS.CC.PCB.PCB_IF.PROTECT_MODE.RD_PROTECT_ENA_INST.LATC.L2(0) [0] | |||
| 1 | TP.TCPAU1.EPS.CC.PCB.PCB_IF.PROTECT_MODE.WR_PROTECT_ENA_INST.LATC.L2(0) [0] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | RW | CC_READ_PROTECT_ENABLE: Enable read protection | ||
| 1 | RW | CC_WRITE_PROTECT_ENABLE: Enable write protection | ||
| Atomic Lock Register | ||||
|---|---|---|---|---|
| Addr: |
00000000110303FF (SCOM) | |||
| Name: | TP.TCPAU1.CC_ATOMIC_LOCK_REG | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0 | TP.TCPAU1.EPS.CC.PCB.PCB_IF.ATOMIC_LOCK.ATOMIC_LOCK_ENA_INST.LATC.L2(0) [0] | |||
| 1:4 | TP.TCPAU1.EPS.CC.PCB.PCB_IF.ATOMIC_LOCK.ATOMIC_ID_Q_INST.LATC.L2(0:3) [0000] | |||
| 8:15 | TP.TCPAU1.EPS.CC.PCB.PCB_IF.ATOMIC_LOCK.ATOMIC_LOCK_ACTIVITY_Q_INST.LATC.L2(0:7) [00000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | RW | CC_ATOMIC_LOCK_ENABLE: Enable atomic lock | ||
| 1:4 | ROX | CC_ATOMIC_ID: Atomic ID | ||
| 5:7 | RO | constant=0b000 | ||
| 8:15 | ROX | CC_ATOMIC_ACTIVITY: Atomic lock counter | ||
| Scan in 32bit mode | ||||
|---|---|---|---|---|
| Addr: |
0000000011038000 (SCOM) | |||
| Name: | TP.TCPAU1.SCAN32 | |||
| Constant(s): | ||||
| Comments: | nn38000 - write 32 bit and/or read 64 bit of the scan buffer - no scan cycles will be shifted nn38001 - nn3801F - write of 01 - 31 bits left aligned into the scan buffer(masking), shifting 01-31 cycles and read 64 bit nn38020 - write 32 bit, shift 32 bit, read 64 bit scan buffer nn38nnn - write max 32 bits, rotate nnn cycles, read of the 64bit scan buffer Order: WRITE - Shift - READ PCB Timout possible, if scan count is too high or scan ratio to slow Write max 32 bits (left aligned) - read will respond full 64 bit scan buffer | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:31 | TP.TCPAU1.EPS.CC.SCANPCB.SCANDATA_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:31 | RW | scan32_reg | ||
| 32:63 | RO | constant=0b11011110101011011011111011101111 | ||
| Long rotate scan - Only rotate the ring | ||||
|---|---|---|---|---|
| Addr: |
0000000011039000 (SCOM) | |||
| Name: | TP.TCPAU1.SCAN_LONG_ROTATE | |||
| Constant(s): | ||||
| Comments: | Used to rotate the ring only, the cycle number is programmmed in the scom data, not in the address example putscom nn39000 0000123400000000 - will rotate x1234 cycles PCB network will NOT be blocked - poll opcg done ! | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 12:31 | TP.TCPAU1.EPS.CC.SCANPCB.BIT_COUNT_Q_0_INST.LATC.L2(0:19) [00000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:11 | n/a | not implemented | ||
| 12:31 | WOX | |||
| Scan in 32bit mode with Update DR | ||||
|---|---|---|---|---|
| Addr: |
000000001103A000 (SCOM) | |||
| Name: | TP.TCPAU1.SCAN_UPDATEDR | |||
| Constant(s): | ||||
| Comments: | see scan32 - after the scan CC will apply a functional clock to update non-scannable latches used e.g. to load PLL cntrl ring PCB network blocked until scan has finished - timeout possible | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:31 | TP.TCPAU1.EPS.CC.SCANPCB.SCANDATA_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:31 | RW | scan_updatedr_reg | ||
| 32:63 | RO | constant=0b11011110101011011011111011101111 | ||
| Scan in 32bit mode with Update DR - PCB will not be blocked | ||||
|---|---|---|---|---|
| Addr: |
000000001103B000 (SCOM) | |||
| Name: | TP.TCPAU1.SCAN_UPDATEDR_LONG | |||
| Constant(s): | ||||
| Comments: | see scan32 - after the scan CC will apply a functional clock to update non-scannable latches used e.g. to load PLL cntrl ring PCB network will NOT be blocked - poll opcg done ! | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:31 | TP.TCPAU1.EPS.CC.SCANPCB.SCANDATA_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:31 | WOX | scan_updatedr_long_reg | ||
| 32:63 | RO | constant=0b11011110101011011011111011101111 | ||
| Scan in 32bit mode with CAPTURE DR | ||||
|---|---|---|---|---|
| Addr: |
000000001103C000 (SCOM) | |||
| Name: | TP.TCPAU1.SCAN_CAPTUREDR | |||
| Constant(s): | ||||
| Comments: | see scan32 - before the scan CC will apply a functional clock to CAPTURE non-scannable latches used e.g. to unload PLL cntrl ring PCB network blocked until scan has finished - timeout possible | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:31 | TP.TCPAU1.EPS.CC.SCANPCB.SCANDATA_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:31 | RW | scan_capturedr_reg | ||
| 32:63 | RO | constant=0b11011110101011011011111011101111 | ||
| Scan in 32bit mode with CAPTURE DR - PCB will not be blocked | ||||
|---|---|---|---|---|
| Addr: |
000000001103D000 (SCOM) | |||
| Name: | TP.TCPAU1.SCAN_CAPTUREDR_LONG | |||
| Constant(s): | ||||
| Comments: | see scan32 - before the scan CC will apply a functional clock to CAPTURE non-scannable latches used e.g. to unload PLL cntrl ring PCB network will NOT be blocked - poll opcg done ! | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:31 | TP.TCPAU1.EPS.CC.SCANPCB.SCANDATA_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:31 | WOX | scan_capturedr_long_reg | ||
| 32:63 | RO | constant=0b11011110101011011011111011101111 | ||
| Scan in 64bit mode | ||||
|---|---|---|---|---|
| Addr: |
000000001103E000 (SCOM) | |||
| Name: | TP.TCPAU1.SCAN64 | |||
| Constant(s): | ||||
| Comments: | nn3E000 - write and/or read of 64 bit scan buffer - no shift nn3E001 - nn3803F - write of 01 - 63 bits left aligned into the scan buffer(masking), shifting 01-63 cycles and read 64 bit nn3E040 - write an/or read of 64 bit scan buffer - shift 64 bit - order Write Shift Read nn3Ennn - write max 64 bit, shift nnn cycles, read max 64 bit | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | TP.TCPAU1.EPS.CC.SCANPCB.SCANDATA_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:63 | RW | scan64_reg | ||
| Scan in 64bit mode - Continues Scanning - non-blocking scan | ||||
|---|---|---|---|---|
| Addr: |
000000001103F000 (SCOM) | |||
| Name: | TP.TCPAU1.SCAN64CONTSCAN | |||
| Constant(s): | ||||
| Comments: | nn3F000 - write and/or read of 64 bit scan buffer - no shift nn3F001 - nn3803F - write of 01 - 63 bits left aligned into the scan buffer(masking), shifting 01-63 cycles and read 64 bit nn3F040 - write an/or read of 64 bit scan buffer - shift 64 bit - order Write Shift Read nn3Fnnn - write max 64 bit, shift nnn cycles, read max 64 bit | |||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | TP.TCPAU1.EPS.CC.SCANPCB.SCANDATA_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:63 | RW | scan64contscan_reg | ||
| XSTOP Register - after masking - OLD XFIR | ||||
|---|---|---|---|---|
| Addr: |
0000000011040000 (SCOM) | |||
| Name: | TP.TCPAU1.XSTOP | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:53 | TP.TCPAU1.EPS.FIR.COMP.XSTOP_MASKED_REG_Q_INST.LATC.L2(0:53) [000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | ROX | ANY_XSTOP: any xstop | ||
| 1 | ROX | SYSTEM_XSTOP: system_xstop | ||
| 2 | ROX | XSTOP_ANY_SPATTN: any_spattn | ||
| 3 | ROX | DBG_FIR_XSTOP_ON_TRIG: dbg_fir_xstop_on_trig | ||
| 4 | ROX | XSTOP_PERV: perv | ||
| 5 | ROX | XSTOP_IN05: pau0_0 | ||
| 6 | ROX | XSTOP_IN06: pau0_1 | ||
| 7 | ROX | XSTOP_IN07: pau0_2 | ||
| 8 | ROX | XSTOP_IN08: unused | ||
| 9 | ROX | XSTOP_IN09: unused | ||
| 10 | ROX | XSTOP_IN10: unused | ||
| 11 | ROX | XSTOP_IN11: unused | ||
| 12 | ROX | XSTOP_IN12: unused | ||
| 13 | ROX | XSTOP_IN13: ioppe_0 | ||
| 14 | ROX | XSTOP_IN14: ioppe_1 | ||
| 15 | ROX | XSTOP_IN15: unused | ||
| 16 | ROX | XSTOP_IN16: unused | ||
| 17 | ROX | XSTOP_IN17: ptl | ||
| 18 | ROX | XSTOP_IN18: unused | ||
| 19 | ROX | XSTOP_IN19: unused | ||
| 20 | ROX | XSTOP_IN20: unused | ||
| 21 | ROX | XSTOP_IN21: unused | ||
| 22 | ROX | XSTOP_IN22: unused | ||
| 23 | ROX | XSTOP_IN23: unused | ||
| 24 | ROX | XSTOP_IN24: unused | ||
| 25 | ROX | XSTOP_IN25: unused | ||
| 26 | ROX | XSTOP_IN26: unused | ||
| 27 | ROX | XSTOP_IN27: unused | ||
| 28 | ROX | XSTOP_IN28: unused | ||
| 29 | ROX | XSTOP_IN29: unused | ||
| 30 | ROX | XSTOP_IN30: unused | ||
| 31 | ROX | XSTOP_IN31: unused | ||
| 32 | ROX | XSTOP_IN32: unused | ||
| 33 | ROX | XSTOP_IN33: unused | ||
| 34 | ROX | XSTOP_IN34: unused | ||
| 35 | ROX | XSTOP_IN35: unused | ||
| 36 | ROX | XSTOP_IN36: unused | ||
| 37 | ROX | XSTOP_IN37: unused | ||
| 38 | ROX | XSTOP_IN38: unused | ||
| 39 | ROX | XSTOP_IN39: unused | ||
| 40 | ROX | XSTOP_IN40: unused | ||
| 41 | ROX | XSTOP_IN41: unused | ||
| 42 | ROX | XSTOP_IN42: unused | ||
| 43 | ROX | XSTOP_IN43: unused | ||
| 44 | ROX | XSTOP_IN44: unused | ||
| 45 | ROX | XSTOP_IN45: unused | ||
| 46 | ROX | XSTOP_IN46: unused | ||
| 47 | ROX | XSTOP_IN47: unused | ||
| 48 | ROX | XSTOP_IN48: unused | ||
| 49 | ROX | XSTOP_IN49: unused | ||
| 50 | ROX | XSTOP_IN50: unused | ||
| 51 | ROX | XSTOP_IN51: unused | ||
| 52 | ROX | XSTOP_IN52: unused | ||
| 53 | ROX | XSTOP_IN53: unused | ||
| RECOV Error Register - after masking - OLD RFIR | ||||
|---|---|---|---|---|
| Addr: |
0000000011040001 (SCOM) | |||
| Name: | TP.TCPAU1.RECOV | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:53 | TP.TCPAU1.EPS.FIR.COMP.RECOV_MASKED_REG_Q_INST.LATC.L2(0:53) [000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | ROX | ANY_RECOV: any_recov | ||
| 1 | ROX | RESERVED1R: RESERVED | ||
| 2 | ROX | RECOV_ANY_LOCAL_XSTOP: any_local_xstop | ||
| 3 | ROX | RESERVED3R: RESERVED | ||
| 4 | ROX | RECOV_PERV: perv | ||
| 5 | ROX | RECOV_IN05: pau0_0 | ||
| 6 | ROX | RECOV_IN06: pau0_1 | ||
| 7 | ROX | RECOV_IN07: pau0_2 | ||
| 8 | ROX | RECOV_IN08: unused | ||
| 9 | ROX | RECOV_IN09: unused | ||
| 10 | ROX | RECOV_IN10: unused | ||
| 11 | ROX | RECOV_IN11: unused | ||
| 12 | ROX | RECOV_IN12: unused | ||
| 13 | ROX | RECOV_IN13: ioppe_0 | ||
| 14 | ROX | RECOV_IN14: ioppe_1 | ||
| 15 | ROX | RECOV_IN15: unused | ||
| 16 | ROX | RECOV_IN16: unused | ||
| 17 | ROX | RECOV_IN17: ptl | ||
| 18 | ROX | RECOV_IN18: unused | ||
| 19 | ROX | RECOV_IN19: unused | ||
| 20 | ROX | RECOV_IN20: unused | ||
| 21 | ROX | RECOV_IN21: unused | ||
| 22 | ROX | RECOV_IN22: unused | ||
| 23 | ROX | RECOV_IN23: unused | ||
| 24 | ROX | RECOV_IN24: unused | ||
| 25 | ROX | RECOV_IN25: unused | ||
| 26 | ROX | RECOV_IN26: unused | ||
| 27 | ROX | RECOV_IN27: unused | ||
| 28 | ROX | RECOV_IN28: unused | ||
| 29 | ROX | RECOV_IN29: unused | ||
| 30 | ROX | RECOV_IN30: unused | ||
| 31 | ROX | RECOV_IN31: unused | ||
| 32 | ROX | RECOV_IN32: unused | ||
| 33 | ROX | RECOV_IN33: unused | ||
| 34 | ROX | RECOV_IN34: unused | ||
| 35 | ROX | RECOV_IN35: unused | ||
| 36 | ROX | RECOV_IN36: unused | ||
| 37 | ROX | RECOV_IN37: unused | ||
| 38 | ROX | RECOV_IN38: unused | ||
| 39 | ROX | RECOV_IN39: unused | ||
| 40 | ROX | RECOV_IN40: unused | ||
| 41 | ROX | RECOV_IN41: unused | ||
| 42 | ROX | RECOV_IN42: unused | ||
| 43 | ROX | RECOV_IN43: unused | ||
| 44 | ROX | RECOV_IN44: unused | ||
| 45 | ROX | RECOV_IN45: unused | ||
| 46 | ROX | RECOV_IN46: unused | ||
| 47 | ROX | RECOV_IN47: unused | ||
| 48 | ROX | RECOV_IN48: unused | ||
| 49 | ROX | RECOV_IN49: unused | ||
| 50 | ROX | RECOV_IN50: unused | ||
| 51 | ROX | RECOV_IN51: unused | ||
| 52 | ROX | RECOV_IN52: unused | ||
| 53 | ROX | RECOV_IN53: unused | ||
| Special Attention Register - after masking | ||||
|---|---|---|---|---|
| Addr: |
0000000011040002 (SCOM) | |||
| Name: | TP.TCPAU1.SPATTN | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:35 | TP.TCPAU1.EPS.FIR.COMP.SPATTN_MASKED_REG_Q_INST.LATC.L2(0:35) [000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | ROX | ANY_SPATTN: any_spattn | ||
| 1 | ROX | RESERVED1S: RESERVED | ||
| 2 | ROX | RESERVED2S: RESERVED | ||
| 3 | ROX | RESERVED3S: RESERVED | ||
| 4 | ROX | SPATTN_PERV: perv | ||
| 5 | ROX | SPATTN_IN05: unused | ||
| 6 | ROX | SPATTN_IN06: unused | ||
| 7 | ROX | SPATTN_IN07: unused | ||
| 8 | ROX | SPATTN_IN08: unused | ||
| 9 | ROX | SPATTN_IN09: unused | ||
| 10 | ROX | SPATTN_IN10: unused | ||
| 11 | ROX | SPATTN_IN11: unused | ||
| 12 | ROX | SPATTN_IN12: unused | ||
| 13 | ROX | SPATTN_IN13: ioppe_0 | ||
| 14 | ROX | SPATTN_IN14: ioppe_1 | ||
| 15 | ROX | SPATTN_IN15: unused | ||
| 16 | ROX | SPATTN_IN16: unused | ||
| 17 | ROX | SPATTN_IN17: ptl | ||
| 18 | ROX | SPATTN_IN18: unused | ||
| 19 | ROX | SPATTN_IN19: unused | ||
| 20 | ROX | SPATTN_IN20: unused | ||
| 21 | ROX | SPATTN_IN21: unused | ||
| 22 | ROX | SPATTN_IN22: unused | ||
| 23 | ROX | SPATTN_IN23: unused | ||
| 24 | ROX | SPATTN_IN24: unused | ||
| 25 | ROX | SPATTN_IN25: unused | ||
| 26 | ROX | SPATTN_IN26: unused | ||
| 27 | ROX | SPATTN_IN27: unused | ||
| 28 | ROX | SPATTN_IN28: unused | ||
| 29 | ROX | SPATTN_IN29: unused | ||
| 30 | ROX | SPATTN_IN30: unused | ||
| 31 | ROX | SPATTN_IN31: unused | ||
| 32 | ROX | SPATTN_IN32: unused | ||
| 33 | ROX | SPATTN_IN33: unused | ||
| 34 | ROX | SPATTN_IN34: unused | ||
| 35 | ROX | SPATTN_IN35: unused | ||
| Local XSTOP Register - after masking | ||||
|---|---|---|---|---|
| Addr: |
0000000011040003 (SCOM) | |||
| Name: | TP.TCPAU1.LOCAL_XSTOP | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:15 | TP.TCPAU1.EPS.FIR.COMP.LXSTOP_MASKED_REG_Q_INST.LATC.L2(0:15) [0000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | ROX | ANY_LOCAL_XSTOP: any local xstop | ||
| 1 | ROX | RESERVED1L: RESERVED | ||
| 2 | ROX | RESERVED2L: RESERVED | ||
| 3 | ROX | RESERVED3L: RESERVED | ||
| 4 | ROX | LOCAL_XSTOP_PERV: perv | ||
| 5 | ROX | LOCAL_XSTOP_IN05: pau0_0 | ||
| 6 | ROX | LOCAL_XSTOP_IN06: pau0_1 | ||
| 7 | ROX | LOCAL_XSTOP_IN07: pau0_2 | ||
| 8 | ROX | LOCAL_XSTOP_IN08: unused | ||
| 9 | ROX | LOCAL_XSTOP_IN09: unused | ||
| 10 | ROX | LOCAL_XSTOP_IN10: unused | ||
| 11 | ROX | LOCAL_XSTOP_IN11: unused | ||
| 12 | ROX | LOCAL_XSTOP_IN12: unused | ||
| 13 | ROX | LOCAL_XSTOP_IN13: ioppe_0 | ||
| 14 | ROX | LOCAL_XSTOP_IN14: ioppe_1 | ||
| 15 | ROX | LOCAL_XSTOP_IN15: unused | ||
| Host Attention - Type4 - Register - after masking | ||||
|---|---|---|---|---|
| Addr: |
0000000011040004 (SCOM) | |||
| Name: | TP.TCPAU1.HOSTATTN | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:53 | TP.TCPAU1.EPS.FIR.COMP.HOSTATTN_MASKED_REG_Q_INST.LATC.L2(0:53) [000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | ROX | ANY_HOSTATTN: any host attn | ||
| 1 | ROX | RESERVED1H: RESERVED | ||
| 2 | ROX | RESERVED2H: RESERVED | ||
| 3 | ROX | RESERVED3H: RESERVED | ||
| 4 | ROX | HOSTATTN_PERV: perv | ||
| 5 | ROX | HOSTATTN_IN05: unused | ||
| 6 | ROX | HOSTATTN_IN06: unused | ||
| 7 | ROX | HOSTATTN_IN07: unused | ||
| 8 | ROX | HOSTATTN_IN08: unused | ||
| 9 | ROX | HOSTATTN_IN09: unused | ||
| 10 | ROX | HOSTATTN_IN10: unused | ||
| 11 | ROX | HOSTATTN_IN11: unused | ||
| 12 | ROX | HOSTATTN_IN12: unused | ||
| 13 | ROX | HOSTATTN_IN13: unused | ||
| 14 | ROX | HOSTATTN_IN14: unused | ||
| 15 | ROX | HOSTATTN_IN15: unused | ||
| 16 | ROX | HOSTATTN_IN16: unused | ||
| 17 | ROX | HOSTATTN_IN17: unused | ||
| 18 | ROX | HOSTATTN_IN18: unused | ||
| 19 | ROX | HOSTATTN_IN19: unused | ||
| 20 | ROX | HOSTATTN_IN20: unused | ||
| 21 | ROX | HOSTATTN_IN21: unused | ||
| 22 | ROX | HOSTATTN_IN22: unused | ||
| 23 | ROX | HOSTATTN_IN23: unused | ||
| 24 | ROX | HOSTATTN_IN24: unused | ||
| 25 | ROX | HOSTATTN_IN25: unused | ||
| 26 | ROX | HOSTATTN_IN26: unused | ||
| 27 | ROX | HOSTATTN_IN27: unused | ||
| 28 | ROX | HOSTATTN_IN28: unused | ||
| 29 | ROX | HOSTATTN_IN29: unused | ||
| 30 | ROX | HOSTATTN_IN30: unused | ||
| 31 | ROX | HOSTATTN_IN31: unused | ||
| 32 | ROX | HOSTATTN_IN32: unused | ||
| 33 | ROX | HOSTATTN_IN33: unused | ||
| 34 | ROX | HOSTATTN_IN34: unused | ||
| 35 | ROX | HOSTATTN_IN35: unused | ||
| 36 | ROX | HOSTATTN_IN36: unused | ||
| 37 | ROX | HOSTATTN_IN37: unused | ||
| 38 | ROX | HOSTATTN_IN38: unused | ||
| 39 | ROX | HOSTATTN_IN39: unused | ||
| 40 | ROX | HOSTATTN_IN40: unused | ||
| 41 | ROX | HOSTATTN_IN41: unused | ||
| 42 | ROX | HOSTATTN_IN42: unused | ||
| 43 | ROX | HOSTATTN_IN43: unused | ||
| 44 | ROX | HOSTATTN_IN44: unused | ||
| 45 | ROX | HOSTATTN_IN45: unused | ||
| 46 | ROX | HOSTATTN_IN46: unused | ||
| 47 | ROX | HOSTATTN_IN47: unused | ||
| 48 | ROX | HOSTATTN_IN48: unused | ||
| 49 | ROX | HOSTATTN_IN49: unused | ||
| 50 | ROX | HOSTATTN_IN50: unused | ||
| 51 | ROX | HOSTATTN_IN51: unused | ||
| 52 | ROX | HOSTATTN_IN52: unused | ||
| 53 | ROX | HOSTATTN_IN53: unused | ||
| XSTOP Register - Unmasked incoming Errors - Debug only | ||||
|---|---|---|---|---|
| Addr: |
0000000011040010 (SCOM) | |||
| Name: | TP.TCPAU1.XSTOP_UNMASKED | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 1:53 | TP.TCPAU1.EPS.FIR.COMP.XSTOP_REG_Q_INST.LATC.L2(1:53) [00000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | RO | constant=0b0 | ||
| 1:53 | ROX | XSTOP_UNMASKED_IN: | ||
| RECOV Error Register - Unmasked incoming Errors - Debug only | ||||
|---|---|---|---|---|
| Addr: |
0000000011040011 (SCOM) | |||
| Name: | TP.TCPAU1.RECOV_UNMASKED | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 1:53 | TP.TCPAU1.EPS.FIR.COMP.RECOV_REG_Q_INST.LATC.L2(1:53) [00000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | RO | constant=0b0 | ||
| 1:53 | ROX | RECOV_UNMASKED_IN: | ||
| Special Attention - Unmasked incoming Errors - Debug only | ||||
|---|---|---|---|---|
| Addr: |
0000000011040012 (SCOM) | |||
| Name: | TP.TCPAU1.SPATTN_UNMASKED | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 1:35 | TP.TCPAU1.EPS.FIR.COMP.SPATTN_REG_Q_INST.LATC.L2(1:35) [00000000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | RO | constant=0b0 | ||
| 1:35 | ROX | SPATTN_UNMASKED_IN: | ||
| Local XSTOP Register - Unmasked incoming Errors - Debug only | ||||
|---|---|---|---|---|
| Addr: |
0000000011040013 (SCOM) | |||
| Name: | TP.TCPAU1.LOCAL_XSTOP_UNMASKED | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 1:15 | TP.TCPAU1.EPS.FIR.COMP.LXSTOP_REG_Q_INST.LATC.L2(1:15) [000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | RO | constant=0b0 | ||
| 1:15 | ROX | LOCAL_XSTOP_UNMASKED_IN: | ||
| Host Attention - Type4 - Unmasked incoming Errors - Debug only | ||||
|---|---|---|---|---|
| Addr: |
0000000011040014 (SCOM) | |||
| Name: | TP.TCPAU1.HOSTATTN_UNMASKED | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 1:53 | TP.TCPAU1.EPS.FIR.COMP.HOSTATTN_REG_Q_INST.LATC.L2(1:53) [00000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | RO | constant=0b0 | ||
| 1:53 | ROX | HOSTATTN_UNMASKED_IN: | ||
| WOF Who is on First of the Recovable Errors Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011040021 (SCOM) | |||
| Name: | TP.TCPAU1.WOF | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:53 | TP.TCPAU1.EPS.FIR.COMP.WOF_YES.RECOV_WOF_Q_INST.LATC.L2(0:53) [000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | RW_WCLRPART | ANY_WOF: any_recov | ||
| 1 | RW_WCLRPART | RESERVED1W: RESERVED | ||
| 2 | RW_WCLRPART | WOF_ANY_LOCAL_XSTOP: any_local_xstop | ||
| 3 | RW_WCLRPART | RESERVED3W: RESERVED | ||
| 4 | RW_WCLRPART | WOF_PERV: perv | ||
| 5 | RW_WCLRPART | WOF_IN05: pau0_0 | ||
| 6 | RW_WCLRPART | WOF_IN06: pau0_1 | ||
| 7 | RW_WCLRPART | WOF_IN07: pau0_2 | ||
| 8 | RW_WCLRPART | WOF_IN08: unused | ||
| 9 | RW_WCLRPART | WOF_IN09: unused | ||
| 10 | RW_WCLRPART | WOF_IN010: unused | ||
| 11 | RW_WCLRPART | WOF_IN011: unused | ||
| 12 | RW_WCLRPART | WOF_IN012: unused | ||
| 13 | RW_WCLRPART | WOF_IN013: ioppe_0 | ||
| 14 | RW_WCLRPART | WOF_IN014: ioppe_1 | ||
| 15 | RW_WCLRPART | WOF_IN015: unused | ||
| 16 | RW_WCLRPART | WOF_IN016: unused | ||
| 17 | RW_WCLRPART | WOF_IN017: ptl | ||
| 18 | RW_WCLRPART | WOF_IN018: unused | ||
| 19 | RW_WCLRPART | WOF_IN019: unused | ||
| 20 | RW_WCLRPART | WOF_IN020: unused | ||
| 21 | RW_WCLRPART | WOF_IN021: unused | ||
| 22 | RW_WCLRPART | WOF_IN022: unused | ||
| 23 | RW_WCLRPART | WOF_IN023: unused | ||
| 24 | RW_WCLRPART | WOF_IN024: unused | ||
| 25 | RW_WCLRPART | WOF_IN025: unused | ||
| 26 | RW_WCLRPART | WOF_IN026: unused | ||
| 27 | RW_WCLRPART | WOF_IN027: unused | ||
| 28 | RW_WCLRPART | WOF_IN028: unused | ||
| 29 | RW_WCLRPART | WOF_IN029: unused | ||
| 30 | RW_WCLRPART | WOF_IN030: unused | ||
| 31 | RW_WCLRPART | WOF_IN031: unused | ||
| 32 | RW_WCLRPART | WOF_IN032: unused | ||
| 33 | RW_WCLRPART | WOF_IN033: unused | ||
| 34 | RW_WCLRPART | WOF_IN034: unused | ||
| 35 | RW_WCLRPART | WOF_IN035: unused | ||
| 36 | RW_WCLRPART | WOF_IN036: unused | ||
| 37 | RW_WCLRPART | WOF_IN037: unused | ||
| 38 | RW_WCLRPART | WOF_IN038: unused | ||
| 39 | RW_WCLRPART | WOF_IN039: unused | ||
| 40 | RW_WCLRPART | WOF_IN040: unused | ||
| 41 | RW_WCLRPART | WOF_IN041: unused | ||
| 42 | RW_WCLRPART | WOF_IN042: unused | ||
| 43 | RW_WCLRPART | WOF_IN043: unused | ||
| 44 | RW_WCLRPART | WOF_IN044: unused | ||
| 45 | RW_WCLRPART | WOF_IN045: unused | ||
| 46 | RW_WCLRPART | WOF_IN046: unused | ||
| 47 | RW_WCLRPART | WOF_IN047: unused | ||
| 48 | RW_WCLRPART | WOF_IN048: unused | ||
| 49 | RW_WCLRPART | WOF_IN049: unused | ||
| 50 | RW_WCLRPART | WOF_IN050: unused | ||
| 51 | RW_WCLRPART | WOF_IN051: unused | ||
| 52 | RW_WCLRPART | WOF_IN052: unused | ||
| 53 | RW_WCLRPART | WOF_IN053: unused | ||
| XSTOP Mask - OLD FIR_MASK | ||||
|---|---|---|---|---|
| Addr: |
0000000011040040 (SCOM) 0000000011040050 (SCOM1) 0000000011040060 (SCOM2) | |||
| Name: | TP.TCPAU1.XSTOP_MASK | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:53 | TP.TCPAU1.EPS.FIR.COMP.XSTOP_MASK_Q_INST.LATC.L2(0:53) [000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | SCOM1 | SCOM2 | Dial: Description |
| 0 | RW | WO_OR | WO_CLEAR | XSTOP_MASK_UNUSED: Unused XSTOP Mask bit0 |
| 1 | RW | WO_OR | WO_CLEAR | XSTOP_MASK01: XSTOP Mask for bit1 - 0=firing 1=blocked - OLD FIR_MASK |
| 2 | RW | WO_OR | WO_CLEAR | XSTOP_MASK02: XSTOP Mask for bit2 - 0=firing 1=blocked - OLD FIR_MASK |
| 3 | RW | WO_OR | WO_CLEAR | XSTOP_MASK03: XSTOP Mask for bit3 - 0=firing 1=blocked - OLD FIR_MASK |
| 4 | RW | WO_OR | WO_CLEAR | XSTOP_MASK04: XSTOP Mask for bit4 - 0=firing 1=blocked - OLD FIR_MASK |
| 5 | RW | WO_OR | WO_CLEAR | XSTOP_MASK05: XSTOP Mask for bit5 - 0=firing 1=blocked - OLD FIR_MASK |
| 6 | RW | WO_OR | WO_CLEAR | XSTOP_MASK06: XSTOP Mask for bit6 - 0=firing 1=blocked - OLD FIR_MASK |
| 7 | RW | WO_OR | WO_CLEAR | XSTOP_MASK07: XSTOP Mask for bit7 - 0=firing 1=blocked - OLD FIR_MASK |
| 8 | RW | WO_OR | WO_CLEAR | XSTOP_MASK08: XSTOP Mask for bit8 - 0=firing 1=blocked - OLD FIR_MASK |
| 9 | RW | WO_OR | WO_CLEAR | XSTOP_MASK09: XSTOP Mask for bit9 - 0=firing 1=blocked - OLD FIR_MASK |
| 10 | RW | WO_OR | WO_CLEAR | XSTOP_MASK10: XSTOP Mask for bit10 - 0=firing 1=blocked - OLD FIR_MASK |
| 11 | RW | WO_OR | WO_CLEAR | XSTOP_MASK11: XSTOP Mask for bit11 - 0=firing 1=blocked - OLD FIR_MASK |
| 12 | RW | WO_OR | WO_CLEAR | XSTOP_MASK12: XSTOP Mask for bit12 - 0=firing 1=blocked - OLD FIR_MASK |
| 13 | RW | WO_OR | WO_CLEAR | XSTOP_MASK13: XSTOP Mask for bit13 - 0=firing 1=blocked - OLD FIR_MASK |
| 14 | RW | WO_OR | WO_CLEAR | XSTOP_MASK14: XSTOP Mask for bit14 - 0=firing 1=blocked - OLD FIR_MASK |
| 15 | RW | WO_OR | WO_CLEAR | XSTOP_MASK15: XSTOP Mask for bit15 - 0=firing 1=blocked - OLD FIR_MASK |
| 16 | RW | WO_OR | WO_CLEAR | XSTOP_MASK16: XSTOP Mask for bit16 - 0=firing 1=blocked - OLD FIR_MASK |
| 17 | RW | WO_OR | WO_CLEAR | XSTOP_MASK17: XSTOP Mask for bit17 - 0=firing 1=blocked - OLD FIR_MASK |
| 18 | RW | WO_OR | WO_CLEAR | XSTOP_MASK18: XSTOP Mask for bit18 - 0=firing 1=blocked - OLD FIR_MASK |
| 19 | RW | WO_OR | WO_CLEAR | XSTOP_MASK19: XSTOP Mask for bit19 - 0=firing 1=blocked - OLD FIR_MASK |
| 20 | RW | WO_OR | WO_CLEAR | XSTOP_MASK20: XSTOP Mask for bit20 - 0=firing 1=blocked - OLD FIR_MASK |
| 21 | RW | WO_OR | WO_CLEAR | XSTOP_MASK21: XSTOP Mask for bit21 - 0=firing 1=blocked - OLD FIR_MASK |
| 22 | RW | WO_OR | WO_CLEAR | XSTOP_MASK22: XSTOP Mask for bit22 - 0=firing 1=blocked - OLD FIR_MASK |
| 23 | RW | WO_OR | WO_CLEAR | XSTOP_MASK23: XSTOP Mask for bit23 - 0=firing 1=blocked - OLD FIR_MASK |
| 24 | RW | WO_OR | WO_CLEAR | XSTOP_MASK24: XSTOP Mask for bit24 - 0=firing 1=blocked - OLD FIR_MASK |
| 25 | RW | WO_OR | WO_CLEAR | XSTOP_MASK25: XSTOP Mask for bit25 - 0=firing 1=blocked - OLD FIR_MASK |
| 26 | RW | WO_OR | WO_CLEAR | XSTOP_MASK26: XSTOP Mask for bit26 - 0=firing 1=blocked - OLD FIR_MASK |
| 27 | RW | WO_OR | WO_CLEAR | XSTOP_MASK27: XSTOP Mask for bit27 - 0=firing 1=blocked - OLD FIR_MASK |
| 28 | RW | WO_OR | WO_CLEAR | XSTOP_MASK28: XSTOP Mask for bit28 - 0=firing 1=blocked - OLD FIR_MASK |
| 29 | RW | WO_OR | WO_CLEAR | XSTOP_MASK29: XSTOP Mask for bit29 - 0=firing 1=blocked - OLD FIR_MASK |
| 30 | RW | WO_OR | WO_CLEAR | XSTOP_MASK30: XSTOP Mask for bit30 - 0=firing 1=blocked - OLD FIR_MASK |
| 31 | RW | WO_OR | WO_CLEAR | XSTOP_MASK31: XSTOP Mask for bit31 - 0=firing 1=blocked - OLD FIR_MASK |
| 32 | RW | WO_OR | WO_CLEAR | XSTOP_MASK32: XSTOP Mask for bit32 - 0=firing 1=blocked - OLD FIR_MASK |
| 33 | RW | WO_OR | WO_CLEAR | XSTOP_MASK33: XSTOP Mask for bit33 - 0=firing 1=blocked - OLD FIR_MASK |
| 34 | RW | WO_OR | WO_CLEAR | XSTOP_MASK34: XSTOP Mask for bit34 - 0=firing 1=blocked - OLD FIR_MASK |
| 35 | RW | WO_OR | WO_CLEAR | XSTOP_MASK35: XSTOP Mask for bit35 - 0=firing 1=blocked - OLD FIR_MASK |
| 36 | RW | WO_OR | WO_CLEAR | XSTOP_MASK36: XSTOP Mask for bit36 - 0=firing 1=blocked - OLD FIR_MASK |
| 37 | RW | WO_OR | WO_CLEAR | XSTOP_MASK37: XSTOP Mask for bit37 - 0=firing 1=blocked - OLD FIR_MASK |
| 38 | RW | WO_OR | WO_CLEAR | XSTOP_MASK38: XSTOP Mask for bit38 - 0=firing 1=blocked - OLD FIR_MASK |
| 39 | RW | WO_OR | WO_CLEAR | XSTOP_MASK39: XSTOP Mask for bit39 - 0=firing 1=blocked - OLD FIR_MASK |
| 40 | RW | WO_OR | WO_CLEAR | XSTOP_MASK40: XSTOP Mask for bit40 - 0=firing 1=blocked - OLD FIR_MASK |
| 41 | RW | WO_OR | WO_CLEAR | XSTOP_MASK41: XSTOP Mask for bit41 - 0=firing 1=blocked - OLD FIR_MASK |
| 42 | RW | WO_OR | WO_CLEAR | XSTOP_MASK42: XSTOP Mask for bit42 - 0=firing 1=blocked - OLD FIR_MASK |
| 43 | RW | WO_OR | WO_CLEAR | XSTOP_MASK43: XSTOP Mask for bit43 - 0=firing 1=blocked - OLD FIR_MASK |
| 44 | RW | WO_OR | WO_CLEAR | XSTOP_MASK44: XSTOP Mask for bit44 - 0=firing 1=blocked - OLD FIR_MASK |
| 45 | RW | WO_OR | WO_CLEAR | XSTOP_MASK45: XSTOP Mask for bit45 - 0=firing 1=blocked - OLD FIR_MASK |
| 46 | RW | WO_OR | WO_CLEAR | XSTOP_MASK46: XSTOP Mask for bit46 - 0=firing 1=blocked - OLD FIR_MASK |
| 47 | RW | WO_OR | WO_CLEAR | XSTOP_MASK47: XSTOP Mask for bit47 - 0=firing 1=blocked - OLD FIR_MASK |
| 48 | RW | WO_OR | WO_CLEAR | XSTOP_MASK48: XSTOP Mask for bit48 - 0=firing 1=blocked - OLD FIR_MASK |
| 49 | RW | WO_OR | WO_CLEAR | XSTOP_MASK49: XSTOP Mask for bit49 - 0=firing 1=blocked - OLD FIR_MASK |
| 50 | RW | WO_OR | WO_CLEAR | XSTOP_MASK50: XSTOP Mask for bit50 - 0=firing 1=blocked - OLD FIR_MASK |
| 51 | RW | WO_OR | WO_CLEAR | XSTOP_MASK51: XSTOP Mask for bit51 - 0=firing 1=blocked - OLD FIR_MASK |
| 52 | RW | WO_OR | WO_CLEAR | XSTOP_MASK52: XSTOP Mask for bit52 - 0=firing 1=blocked - OLD FIR_MASK |
| 53 | RW | WO_OR | WO_CLEAR | XSTOP_MASK53: XSTOP Mask for bit53 - 0=firing 1=blocked - OLD FIR_MASK |
| RECOV Mask - OLD FIR_MASK | ||||
|---|---|---|---|---|
| Addr: |
0000000011040041 (SCOM) 0000000011040051 (SCOM1) 0000000011040061 (SCOM2) | |||
| Name: | TP.TCPAU1.RECOV_MASK | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:53 | TP.TCPAU1.EPS.FIR.COMP.RECOV_MASK_Q_INST.LATC.L2(0:53) [000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | SCOM1 | SCOM2 | Dial: Description |
| 0 | RW | WO_OR | WO_CLEAR | RECOV_MASK_UNUSED: Unused RECOV Mask bit0 |
| 1 | RW | WO_OR | WO_CLEAR | RECOV_MASK01: RECOV Mask for bit1 - 0=firing 1=blocked - OLD FIR_MASK |
| 2 | RW | WO_OR | WO_CLEAR | RECOV_MASK02: RECOV Mask for bit2 - 0=firing 1=blocked - OLD FIR_MASK |
| 3 | RW | WO_OR | WO_CLEAR | RECOV_MASK03: RECOV Mask for bit3 - 0=firing 1=blocked - OLD FIR_MASK |
| 4 | RW | WO_OR | WO_CLEAR | RECOV_MASK04: RECOV Mask for bit4 - 0=firing 1=blocked - OLD FIR_MASK |
| 5 | RW | WO_OR | WO_CLEAR | RECOV_MASK05: RECOV Mask for bit5 - 0=firing 1=blocked - OLD FIR_MASK |
| 6 | RW | WO_OR | WO_CLEAR | RECOV_MASK06: RECOV Mask for bit6 - 0=firing 1=blocked - OLD FIR_MASK |
| 7 | RW | WO_OR | WO_CLEAR | RECOV_MASK07: RECOV Mask for bit7 - 0=firing 1=blocked - OLD FIR_MASK |
| 8 | RW | WO_OR | WO_CLEAR | RECOV_MASK08: RECOV Mask for bit8 - 0=firing 1=blocked - OLD FIR_MASK |
| 9 | RW | WO_OR | WO_CLEAR | RECOV_MASK09: RECOV Mask for bit9 - 0=firing 1=blocked - OLD FIR_MASK |
| 10 | RW | WO_OR | WO_CLEAR | RECOV_MASK010: RECOV Mask for bit10 - 0=firing 1=blocked - OLD FIR_MASK |
| 11 | RW | WO_OR | WO_CLEAR | RECOV_MASK011: RECOV Mask for bit11 - 0=firing 1=blocked - OLD FIR_MASK |
| 12 | RW | WO_OR | WO_CLEAR | RECOV_MASK012: RECOV Mask for bit12 - 0=firing 1=blocked - OLD FIR_MASK |
| 13 | RW | WO_OR | WO_CLEAR | RECOV_MASK013: RECOV Mask for bit13 - 0=firing 1=blocked - OLD FIR_MASK |
| 14 | RW | WO_OR | WO_CLEAR | RECOV_MASK014: RECOV Mask for bit14 - 0=firing 1=blocked - OLD FIR_MASK |
| 15 | RW | WO_OR | WO_CLEAR | RECOV_MASK015: RECOV Mask for bit15 - 0=firing 1=blocked - OLD FIR_MASK |
| 16 | RW | WO_OR | WO_CLEAR | RECOV_MASK016: RECOV Mask for bit16 - 0=firing 1=blocked - OLD FIR_MASK |
| 17 | RW | WO_OR | WO_CLEAR | RECOV_MASK017: RECOV Mask for bit17 - 0=firing 1=blocked - OLD FIR_MASK |
| 18 | RW | WO_OR | WO_CLEAR | RECOV_MASK018: RECOV Mask for bit18 - 0=firing 1=blocked - OLD FIR_MASK |
| 19 | RW | WO_OR | WO_CLEAR | RECOV_MASK019: RECOV Mask for bit19 - 0=firing 1=blocked - OLD FIR_MASK |
| 20 | RW | WO_OR | WO_CLEAR | RECOV_MASK020: RECOV Mask for bit20 - 0=firing 1=blocked - OLD FIR_MASK |
| 21 | RW | WO_OR | WO_CLEAR | RECOV_MASK021: RECOV Mask for bit21 - 0=firing 1=blocked - OLD FIR_MASK |
| 22 | RW | WO_OR | WO_CLEAR | RECOV_MASK022: RECOV Mask for bit22 - 0=firing 1=blocked - OLD FIR_MASK |
| 23 | RW | WO_OR | WO_CLEAR | RECOV_MASK023: RECOV Mask for bit23 - 0=firing 1=blocked - OLD FIR_MASK |
| 24 | RW | WO_OR | WO_CLEAR | RECOV_MASK024: RECOV Mask for bit24 - 0=firing 1=blocked - OLD FIR_MASK |
| 25 | RW | WO_OR | WO_CLEAR | RECOV_MASK025: RECOV Mask for bit25 - 0=firing 1=blocked - OLD FIR_MASK |
| 26 | RW | WO_OR | WO_CLEAR | RECOV_MASK026: RECOV Mask for bit26 - 0=firing 1=blocked - OLD FIR_MASK |
| 27 | RW | WO_OR | WO_CLEAR | RECOV_MASK027: RECOV Mask for bit27 - 0=firing 1=blocked - OLD FIR_MASK |
| 28 | RW | WO_OR | WO_CLEAR | RECOV_MASK028: RECOV Mask for bit28 - 0=firing 1=blocked - OLD FIR_MASK |
| 29 | RW | WO_OR | WO_CLEAR | RECOV_MASK029: RECOV Mask for bit29 - 0=firing 1=blocked - OLD FIR_MASK |
| 30 | RW | WO_OR | WO_CLEAR | RECOV_MASK030: RECOV Mask for bit30 - 0=firing 1=blocked - OLD FIR_MASK |
| 31 | RW | WO_OR | WO_CLEAR | RECOV_MASK031: RECOV Mask for bit31 - 0=firing 1=blocked - OLD FIR_MASK |
| 32 | RW | WO_OR | WO_CLEAR | RECOV_MASK032: RECOV Mask for bit32 - 0=firing 1=blocked - OLD FIR_MASK |
| 33 | RW | WO_OR | WO_CLEAR | RECOV_MASK033: RECOV Mask for bit33 - 0=firing 1=blocked - OLD FIR_MASK |
| 34 | RW | WO_OR | WO_CLEAR | RECOV_MASK034: RECOV Mask for bit34 - 0=firing 1=blocked - OLD FIR_MASK |
| 35 | RW | WO_OR | WO_CLEAR | RECOV_MASK035: RECOV Mask for bit35 - 0=firing 1=blocked - OLD FIR_MASK |
| 36 | RW | WO_OR | WO_CLEAR | RECOV_MASK036: RECOV Mask for bit36 - 0=firing 1=blocked - OLD FIR_MASK |
| 37 | RW | WO_OR | WO_CLEAR | RECOV_MASK037: RECOV Mask for bit37 - 0=firing 1=blocked - OLD FIR_MASK |
| 38 | RW | WO_OR | WO_CLEAR | RECOV_MASK038: RECOV Mask for bit38 - 0=firing 1=blocked - OLD FIR_MASK |
| 39 | RW | WO_OR | WO_CLEAR | RECOV_MASK039: RECOV Mask for bit39 - 0=firing 1=blocked - OLD FIR_MASK |
| 40 | RW | WO_OR | WO_CLEAR | RECOV_MASK040: RECOV Mask for bit40 - 0=firing 1=blocked - OLD FIR_MASK |
| 41 | RW | WO_OR | WO_CLEAR | RECOV_MASK041: RECOV Mask for bit41 - 0=firing 1=blocked - OLD FIR_MASK |
| 42 | RW | WO_OR | WO_CLEAR | RECOV_MASK042: RECOV Mask for bit42 - 0=firing 1=blocked - OLD FIR_MASK |
| 43 | RW | WO_OR | WO_CLEAR | RECOV_MASK043: RECOV Mask for bit43 - 0=firing 1=blocked - OLD FIR_MASK |
| 44 | RW | WO_OR | WO_CLEAR | RECOV_MASK044: RECOV Mask for bit44 - 0=firing 1=blocked - OLD FIR_MASK |
| 45 | RW | WO_OR | WO_CLEAR | RECOV_MASK045: RECOV Mask for bit45 - 0=firing 1=blocked - OLD FIR_MASK |
| 46 | RW | WO_OR | WO_CLEAR | RECOV_MASK046: RECOV Mask for bit46 - 0=firing 1=blocked - OLD FIR_MASK |
| 47 | RW | WO_OR | WO_CLEAR | RECOV_MASK047: RECOV Mask for bit47 - 0=firing 1=blocked - OLD FIR_MASK |
| 48 | RW | WO_OR | WO_CLEAR | RECOV_MASK048: RECOV Mask for bit48 - 0=firing 1=blocked - OLD FIR_MASK |
| 49 | RW | WO_OR | WO_CLEAR | RECOV_MASK049: RECOV Mask for bit49 - 0=firing 1=blocked - OLD FIR_MASK |
| 50 | RW | WO_OR | WO_CLEAR | RECOV_MASK050: RECOV Mask for bit50 - 0=firing 1=blocked - OLD FIR_MASK |
| 51 | RW | WO_OR | WO_CLEAR | RECOV_MASK051: RECOV Mask for bit51 - 0=firing 1=blocked - OLD FIR_MASK |
| 52 | RW | WO_OR | WO_CLEAR | RECOV_MASK052: RECOV Mask for bit52 - 0=firing 1=blocked - OLD FIR_MASK |
| 53 | RW | WO_OR | WO_CLEAR | RECOV_MASK053: RECOV Mask for bit53 - 0=firing 1=blocked - OLD FIR_MASK |
| Special Attention Mask | ||||
|---|---|---|---|---|
| Addr: |
0000000011040042 (SCOM) 0000000011040052 (SCOM1) 0000000011040062 (SCOM2) | |||
| Name: | TP.TCPAU1.SPATTN_MASK | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:35 | TP.TCPAU1.EPS.FIR.COMP.SPATTN_MASK_Q_INST.LATC.L2(0:35) [000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | SCOM1 | SCOM2 | Dial: Description |
| 0 | RW | WO_OR | WO_CLEAR | SPATTN_MASK_UNUSED: Unused SPATTN Mask bit0 |
| 1 | RW | WO_OR | WO_CLEAR | SPATTN_MASK01: SPATTN Mask for bit1 - 0=firing 1=blocked |
| 2 | RW | WO_OR | WO_CLEAR | SPATTN_MASK02: SPATTN Mask for bit2 - 0=firing 1=blocked |
| 3 | RW | WO_OR | WO_CLEAR | SPATTN_MASK03: SPATTN Mask for bit3 - 0=firing 1=blocked |
| 4 | RW | WO_OR | WO_CLEAR | SPATTN_MASK04: SPATTN Mask for bit4 - 0=firing 1=blocked |
| 5 | RW | WO_OR | WO_CLEAR | SPATTN_MASK05: SPATTN Mask for bit5 - 0=firing 1=blocked |
| 6 | RW | WO_OR | WO_CLEAR | SPATTN_MASK06: SPATTN Mask for bit6 - 0=firing 1=blocked |
| 7 | RW | WO_OR | WO_CLEAR | SPATTN_MASK07: SPATTN Mask for bit7 - 0=firing 1=blocked |
| 8 | RW | WO_OR | WO_CLEAR | SPATTN_MASK08: SPATTN Mask for bit8 - 0=firing 1=blocked |
| 9 | RW | WO_OR | WO_CLEAR | SPATTN_MASK09: SPATTN Mask for bit9 - 0=firing 1=blocked |
| 10 | RW | WO_OR | WO_CLEAR | SPATTN_MASK10: SPATTN Mask for bit10 - 0=firing 1=blocked |
| 11 | RW | WO_OR | WO_CLEAR | SPATTN_MASK11: SPATTN Mask for bit11 - 0=firing 1=blocked |
| 12 | RW | WO_OR | WO_CLEAR | SPATTN_MASK12: SPATTN Mask for bit12 - 0=firing 1=blocked |
| 13 | RW | WO_OR | WO_CLEAR | SPATTN_MASK13: SPATTN Mask for bit13 - 0=firing 1=blocked |
| 14 | RW | WO_OR | WO_CLEAR | SPATTN_MASK14: SPATTN Mask for bit14 - 0=firing 1=blocked |
| 15 | RW | WO_OR | WO_CLEAR | SPATTN_MASK15: SPATTN Mask for bit15 - 0=firing 1=blocked |
| 16 | RW | WO_OR | WO_CLEAR | SPATTN_MASK16: SPATTN Mask for bit16 - 0=firing 1=blocked |
| 17 | RW | WO_OR | WO_CLEAR | SPATTN_MASK17: SPATTN Mask for bit17 - 0=firing 1=blocked |
| 18 | RW | WO_OR | WO_CLEAR | SPATTN_MASK18: SPATTN Mask for bit18 - 0=firing 1=blocked |
| 19 | RW | WO_OR | WO_CLEAR | SPATTN_MASK19: SPATTN Mask for bit19 - 0=firing 1=blocked |
| 20 | RW | WO_OR | WO_CLEAR | SPATTN_MASK20: SPATTN Mask for bit20 - 0=firing 1=blocked |
| 21 | RW | WO_OR | WO_CLEAR | SPATTN_MASK21: SPATTN Mask for bit21 - 0=firing 1=blocked |
| 22 | RW | WO_OR | WO_CLEAR | SPATTN_MASK22: SPATTN Mask for bit22 - 0=firing 1=blocked |
| 23 | RW | WO_OR | WO_CLEAR | SPATTN_MASK23: SPATTN Mask for bit23 - 0=firing 1=blocked |
| 24 | RW | WO_OR | WO_CLEAR | SPATTN_MASK24: SPATTN Mask for bit24 - 0=firing 1=blocked |
| 25 | RW | WO_OR | WO_CLEAR | SPATTN_MASK25: SPATTN Mask for bit25 - 0=firing 1=blocked |
| 26 | RW | WO_OR | WO_CLEAR | SPATTN_MASK26: SPATTN Mask for bit26 - 0=firing 1=blocked |
| 27 | RW | WO_OR | WO_CLEAR | SPATTN_MASK27: SPATTN Mask for bit27 - 0=firing 1=blocked |
| 28 | RW | WO_OR | WO_CLEAR | SPATTN_MASK28: SPATTN Mask for bit28 - 0=firing 1=blocked |
| 29 | RW | WO_OR | WO_CLEAR | SPATTN_MASK29: SPATTN Mask for bit29 - 0=firing 1=blocked |
| 30 | RW | WO_OR | WO_CLEAR | SPATTN_MASK30: SPATTN Mask for bit30 - 0=firing 1=blocked |
| 31 | RW | WO_OR | WO_CLEAR | SPATTN_MASK31: SPATTN Mask for bit31 - 0=firing 1=blocked |
| 32 | RW | WO_OR | WO_CLEAR | SPATTN_MASK32: SPATTN Mask for bit32 - 0=firing 1=blocked |
| 33 | RW | WO_OR | WO_CLEAR | SPATTN_MASK33: SPATTN Mask for bit33 - 0=firing 1=blocked |
| 34 | RW | WO_OR | WO_CLEAR | SPATTN_MASK34: SPATTN Mask for bit34 - 0=firing 1=blocked |
| 35 | RW | WO_OR | WO_CLEAR | SPATTN_MASK35: SPATTN Mask for bit35 - 0=firing 1=blocked |
| Local XSTOP Mask | ||||
|---|---|---|---|---|
| Addr: |
0000000011040043 (SCOM) 0000000011040053 (SCOM1) 0000000011040063 (SCOM2) | |||
| Name: | TP.TCPAU1.LOCAL_XSTOP_MASK | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:15 | TP.TCPAU1.EPS.FIR.COMP.LXSTOP_MASK_Q_INST.LATC.L2(0:15) [0000000000000000] | |||
| Bit(s) | SCOM | SCOM1 | SCOM2 | Dial: Description |
| 0 | RW | WO_OR | WO_CLEAR | LOCAL_XSTOP_MASK_UNUSED: Unused Local XSTOP Mask bit0 |
| 1 | RW | WO_OR | WO_CLEAR | LOCAL_XSTOP_MASK01: Local XSTOP Mask for bit1 - 0=firing 1=blocked |
| 2 | RW | WO_OR | WO_CLEAR | LOCAL_XSTOP_MASK02: Local XSTOP Mask for bit2 - 0=firing 1=blocked |
| 3 | RW | WO_OR | WO_CLEAR | LOCAL_XSTOP_MASK03: Local XSTOP Mask for bit3 - 0=firing 1=blocked |
| 4 | RW | WO_OR | WO_CLEAR | LOCAL_XSTOP_MASK04: Local XSTOP Mask for bit4 - 0=firing 1=blocked |
| 5 | RW | WO_OR | WO_CLEAR | LOCAL_XSTOP_MASK05: Local XSTOP Mask for bit5 - 0=firing 1=blocked |
| 6 | RW | WO_OR | WO_CLEAR | LOCAL_XSTOP_MASK06: Local XSTOP Mask for bit6 - 0=firing 1=blocked |
| 7 | RW | WO_OR | WO_CLEAR | LOCAL_XSTOP_MASK07: Local XSTOP Mask for bit7 - 0=firing 1=blocked |
| 8 | RW | WO_OR | WO_CLEAR | LOCAL_XSTOP_MASK08: Local XSTOP Mask for bit8 - 0=firing 1=blocked |
| 9 | RW | WO_OR | WO_CLEAR | LOCAL_XSTOP_MASK09: Local XSTOP Mask for bit9 - 0=firing 1=blocked |
| 10 | RW | WO_OR | WO_CLEAR | LOCAL_XSTOP_MASK10: Local XSTOP Mask for bit10 - 0=firing 1=blocked |
| 11 | RW | WO_OR | WO_CLEAR | LOCAL_XSTOP_MASK11: Local XSTOP Mask for bit11 - 0=firing 1=blocked |
| 12 | RW | WO_OR | WO_CLEAR | LOCAL_XSTOP_MASK12: Local XSTOP Mask for bit12 - 0=firing 1=blocked |
| 13 | RW | WO_OR | WO_CLEAR | LOCAL_XSTOP_MASK13: Local XSTOP Mask for bit13 - 0=firing 1=blocked |
| 14 | RW | WO_OR | WO_CLEAR | LOCAL_XSTOP_MASK14: Local XSTOP Mask for bit14 - 0=firing 1=blocked |
| 15 | RW | WO_OR | WO_CLEAR | LOCAL_XSTOP_MASK15: Local XSTOP Mask for bit15 - 0=firing 1=blocked |
| Host Attention Mask | ||||
|---|---|---|---|---|
| Addr: |
0000000011040044 (SCOM) 0000000011040054 (SCOM1) 0000000011040064 (SCOM2) | |||
| Name: | TP.TCPAU1.HOSTATTN_MASK | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:53 | TP.TCPAU1.EPS.FIR.COMP.HOSTATTN_MASK_Q_INST.LATC.L2(0:53) [000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | SCOM1 | SCOM2 | Dial: Description |
| 0 | RW | WO_OR | WO_CLEAR | HOSTATTN_MASK_UNUSED: Unused HOSTATTN Mask bit0 |
| 1 | RW | WO_OR | WO_CLEAR | HOSTATTN_MASK01: HOSTATTN Mask for bit1 - 0=firing 1=blocked |
| 2 | RW | WO_OR | WO_CLEAR | HOSTATTN_MASK02: HOSTATTN Mask for bit2 - 0=firing 1=blocked |
| 3 | RW | WO_OR | WO_CLEAR | HOSTATTN_MASK03: HOSTATTN Mask for bit3 - 0=firing 1=blocked |
| 4 | RW | WO_OR | WO_CLEAR | HOSTATTN_MASK04: HOSTATTN Mask for bit4 - 0=firing 1=blocked |
| 5 | RW | WO_OR | WO_CLEAR | HOSTATTN_MASK05: HOSTATTN Mask for bit5 - 0=firing 1=blocked |
| 6 | RW | WO_OR | WO_CLEAR | HOSTATTN_MASK06: HOSTATTN Mask for bit6 - 0=firing 1=blocked |
| 7 | RW | WO_OR | WO_CLEAR | HOSTATTN_MASK07: HOSTATTN Mask for bit7 - 0=firing 1=blocked |
| 8 | RW | WO_OR | WO_CLEAR | HOSTATTN_MASK08: HOSTATTN Mask for bit8 - 0=firing 1=blocked |
| 9 | RW | WO_OR | WO_CLEAR | HOSTATTN_MASK09: HOSTATTN Mask for bit9 - 0=firing 1=blocked |
| 10 | RW | WO_OR | WO_CLEAR | HOSTATTN_MASK10: HOSTATTN Mask for bit10 - 0=firing 1=blocked |
| 11 | RW | WO_OR | WO_CLEAR | HOSTATTN_MASK11: HOSTATTN Mask for bit11 - 0=firing 1=blocked |
| 12 | RW | WO_OR | WO_CLEAR | HOSTATTN_MASK12: HOSTATTN Mask for bit12 - 0=firing 1=blocked |
| 13 | RW | WO_OR | WO_CLEAR | HOSTATTN_MASK13: HOSTATTN Mask for bit13 - 0=firing 1=blocked |
| 14 | RW | WO_OR | WO_CLEAR | HOSTATTN_MASK14: HOSTATTN Mask for bit14 - 0=firing 1=blocked |
| 15 | RW | WO_OR | WO_CLEAR | HOSTATTN_MASK15: HOSTATTN Mask for bit15 - 0=firing 1=blocked |
| 16 | RW | WO_OR | WO_CLEAR | HOSTATTN_MASK16: HOSTATTN Mask for bit16 - 0=firing 1=blocked |
| 17 | RW | WO_OR | WO_CLEAR | HOSTATTN_MASK17: HOSTATTN Mask for bit17 - 0=firing 1=blocked |
| 18 | RW | WO_OR | WO_CLEAR | HOSTATTN_MASK18: HOSTATTN Mask for bit18 - 0=firing 1=blocked |
| 19 | RW | WO_OR | WO_CLEAR | HOSTATTN_MASK19: HOSTATTN Mask for bit19 - 0=firing 1=blocked |
| 20 | RW | WO_OR | WO_CLEAR | HOSTATTN_MASK20: HOSTATTN Mask for bit20 - 0=firing 1=blocked |
| 21 | RW | WO_OR | WO_CLEAR | HOSTATTN_MASK21: HOSTATTN Mask for bit21 - 0=firing 1=blocked |
| 22 | RW | WO_OR | WO_CLEAR | HOSTATTN_MASK22: HOSTATTN Mask for bit22 - 0=firing 1=blocked |
| 23 | RW | WO_OR | WO_CLEAR | HOSTATTN_MASK23: HOSTATTN Mask for bit23 - 0=firing 1=blocked |
| 24 | RW | WO_OR | WO_CLEAR | HOSTATTN_MASK24: HOSTATTN Mask for bit24 - 0=firing 1=blocked |
| 25 | RW | WO_OR | WO_CLEAR | HOSTATTN_MASK25: HOSTATTN Mask for bit25 - 0=firing 1=blocked |
| 26 | RW | WO_OR | WO_CLEAR | HOSTATTN_MASK26: HOSTATTN Mask for bit26 - 0=firing 1=blocked |
| 27 | RW | WO_OR | WO_CLEAR | HOSTATTN_MASK27: HOSTATTN Mask for bit27 - 0=firing 1=blocked |
| 28 | RW | WO_OR | WO_CLEAR | HOSTATTN_MASK28: HOSTATTN Mask for bit28 - 0=firing 1=blocked |
| 29 | RW | WO_OR | WO_CLEAR | HOSTATTN_MASK29: HOSTATTN Mask for bit29 - 0=firing 1=blocked |
| 30 | RW | WO_OR | WO_CLEAR | HOSTATTN_MASK30: HOSTATTN Mask for bit30 - 0=firing 1=blocked |
| 31 | RW | WO_OR | WO_CLEAR | HOSTATTN_MASK31: HOSTATTN Mask for bit31 - 0=firing 1=blocked |
| 32 | RW | WO_OR | WO_CLEAR | HOSTATTN_MASK32: HOSTATTN Mask for bit32 - 0=firing 1=blocked |
| 33 | RW | WO_OR | WO_CLEAR | HOSTATTN_MASK33: HOSTATTN Mask for bit33 - 0=firing 1=blocked |
| 34 | RW | WO_OR | WO_CLEAR | HOSTATTN_MASK34: HOSTATTN Mask for bit34 - 0=firing 1=blocked |
| 35 | RW | WO_OR | WO_CLEAR | HOSTATTN_MASK35: HOSTATTN Mask for bit35 - 0=firing 1=blocked |
| 36 | RW | WO_OR | WO_CLEAR | HOSTATTN_MASK36: HOSTATTN Mask for bit36 - 0=firing 1=blocked |
| 37 | RW | WO_OR | WO_CLEAR | HOSTATTN_MASK37: HOSTATTN Mask for bit37 - 0=firing 1=blocked |
| 38 | RW | WO_OR | WO_CLEAR | HOSTATTN_MASK38: HOSTATTN Mask for bit38 - 0=firing 1=blocked |
| 39 | RW | WO_OR | WO_CLEAR | HOSTATTN_MASK39: HOSTATTN Mask for bit39 - 0=firing 1=blocked |
| 40 | RW | WO_OR | WO_CLEAR | HOSTATTN_MASK40: HOSTATTN Mask for bit40 - 0=firing 1=blocked |
| 41 | RW | WO_OR | WO_CLEAR | HOSTATTN_MASK41: HOSTATTN Mask for bit41 - 0=firing 1=blocked |
| 42 | RW | WO_OR | WO_CLEAR | HOSTATTN_MASK42: HOSTATTN Mask for bit42 - 0=firing 1=blocked |
| 43 | RW | WO_OR | WO_CLEAR | HOSTATTN_MASK43: HOSTATTN Mask for bit43 - 0=firing 1=blocked |
| 44 | RW | WO_OR | WO_CLEAR | HOSTATTN_MASK44: HOSTATTN Mask for bit44 - 0=firing 1=blocked |
| 45 | RW | WO_OR | WO_CLEAR | HOSTATTN_MASK45: HOSTATTN Mask for bit45 - 0=firing 1=blocked |
| 46 | RW | WO_OR | WO_CLEAR | HOSTATTN_MASK46: HOSTATTN Mask for bit46 - 0=firing 1=blocked |
| 47 | RW | WO_OR | WO_CLEAR | HOSTATTN_MASK47: HOSTATTN Mask for bit47 - 0=firing 1=blocked |
| 48 | RW | WO_OR | WO_CLEAR | HOSTATTN_MASK48: HOSTATTN Mask for bit48 - 0=firing 1=blocked |
| 49 | RW | WO_OR | WO_CLEAR | HOSTATTN_MASK49: HOSTATTN Mask for bit49 - 0=firing 1=blocked |
| 50 | RW | WO_OR | WO_CLEAR | HOSTATTN_MASK50: HOSTATTN Mask for bit50 - 0=firing 1=blocked |
| 51 | RW | WO_OR | WO_CLEAR | HOSTATTN_MASK51: HOSTATTN Mask for bit51 - 0=firing 1=blocked |
| 52 | RW | WO_OR | WO_CLEAR | HOSTATTN_MASK52: HOSTATTN Mask for bit52 - 0=firing 1=blocked |
| 53 | RW | WO_OR | WO_CLEAR | HOSTATTN_MASK53: HOSTATTN Mask for bit53 - 0=firing 1=blocked |
| Any Local Error Mask - to PCB (old SUMMARY MASK) | ||||
|---|---|---|---|---|
| Addr: |
0000000011040080 (SCOM) | |||
| Name: | TP.TCPAU1.EPS.FIR.ANY_LOCAL_ERR_MASK | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:4 | TP.TCPAU1.EPS.FIR.COMP.ANY_LOCAL_ERR_MASK_Q_INST.LATC.L2(0:4) [00000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | RW | MASK_XSTOP_TO_PCB: mask XSTOP to pcb - 1=blocking | ||
| 1 | RW | MASK_RECOV_TO_PCB: mask RECOV to pcb - 1=blocking | ||
| 2 | RW | MASK_SPATTN_TO_PCB: mask SPATTN to pcb - 1=blocking | ||
| 3 | RW | MASK_LOCAL_XSTOP_TO_PCB: mask LOCAL XSTOP to pcb - 1=blocking | ||
| 4 | RW | MASK_HOSTATTN_TO_PCB: mask HOSTATTN to pcb - 1=blocking | ||
| Clockstop on XSTOP Mask1 Reg - to CC XSTOP1 | ||||
|---|---|---|---|---|
| Addr: |
0000000011040081 (SCOM) | |||
| Name: | TP.TCPAU1.EPS.FIR.CLKSTOP_ON_XSTOP_MASK1 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:26 | TP.TCPAU1.EPS.FIR.COMP.CLKSTOP_ON_XSTOP_MASK1_Q_INST.LATC.L2(0:26) [000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | RW | CLKSTOP_MASK1_XSTOP_ERR: any xstop triggers clockstop using ClockControl XSTOP1 | ||
| 1 | RW | CLKSTOP_MASK1_RECOV_ERR: any recov triggers clockstop using ClockControl XSTOP1 | ||
| 2 | RW | CLKSTOP_MASK1_SPATTN_ERR: any spattn triggers clockstop using ClockControl XSTOP1 | ||
| 3 | RW | CLKSTOP_MASK1_LXSTOP_ERR: any xstop triggers clockstop using ClockControl XSTOP1 | ||
| 4 | RW | CLKSTOP_MASK1_HOSTATTN_ERR: any hostattn triggers clockstop using ClockControl XSTOP1 | ||
| 5 | RW | CLKSTOP_MASK1_SYS_XSTOP_ERR: system xstop triggers clockstop using ClockControl XSTOP1 | ||
| 6 | RW | CLKSTOP_MASK1_SYS_XSTOP_STAGED_ERR: oob7 -system xstop staged triggers Clockstop using ClockControl XSTOP1 | ||
| 7 | RW | CLKSTOP_MASK1_DBG_TRIG_ERR: dbg triggers Clockstop using ClockControl XSTOP1 | ||
| 8 | RW | CLKSTOP_MASK1_UNUSED08: Unused | ||
| 9 | RW | CLKSTOP_MASK1_UNUSED09: Unused | ||
| 10 | RW | CLKSTOP_MASK1_UNUSED10: Unused | ||
| 11 | RW | CLKSTOP_MASK1_UNUSED11: Unused | ||
| 12 | RW | CLKSTOP_MASK1_UNIT_TC_FIR_LOCAL_XSTOP01: Local XSTOP bit 1 triggers Clockstop using ClockControl XSTOP1 | ||
| 13 | RW | CLKSTOP_MASK1_UNIT_TC_FIR_LOCAL_XSTOP02: Local XSTOP bit 2 triggers Clockstop using ClockControl XSTOP1 | ||
| 14 | RW | CLKSTOP_MASK1_UNIT_TC_FIR_LOCAL_XSTOP03: Local XSTOP bit 3 triggers Clockstop using ClockControl XSTOP1 | ||
| 15 | RW | CLKSTOP_MASK1_UNIT_TC_FIR_LOCAL_XSTOP04: Local XSTOP bit 4 triggers Clockstop using ClockControl XSTOP1 | ||
| 16 | RW | CLKSTOP_MASK1_UNIT_TC_FIR_LOCAL_XSTOP05: Local XSTOP bit 5 triggers Clockstop using ClockControl XSTOP1 | ||
| 17 | RW | CLKSTOP_MASK1_UNIT_TC_FIR_LOCAL_XSTOP06: Local XSTOP bit 6 triggers Clockstop using ClockControl XSTOP1 | ||
| 18 | RW | CLKSTOP_MASK1_UNIT_TC_FIR_LOCAL_XSTOP07: Local XSTOP bit 7 triggers Clockstop using ClockControl XSTOP1 | ||
| 19 | RW | CLKSTOP_MASK1_UNIT_TC_FIR_LOCAL_XSTOP08: Local XSTOP bit 8 triggers Clockstop using ClockControl XSTOP1 | ||
| 20 | RW | CLKSTOP_MASK1_UNIT_TC_FIR_LOCAL_XSTOP09: Local XSTOP bit 9 triggers Clockstop using ClockControl XSTOP1 | ||
| 21 | RW | CLKSTOP_MASK1_UNIT_TC_FIR_LOCAL_XSTOP10: Local XSTOP bit 10 triggers Clockstop using ClockControl XSTOP1 | ||
| 22 | RW | CLKSTOP_MASK1_UNIT_TC_FIR_LOCAL_XSTOP11: Local XSTOP bit 11 triggers Clockstop using ClockControl XSTOP1 | ||
| 23 | RW | CLKSTOP_MASK1_UNIT_TC_FIR_LOCAL_XSTOP12: Local XSTOP bit 12 triggers Clockstop using ClockControl XSTOP1 | ||
| 24 | RW | CLKSTOP_MASK1_UNIT_TC_FIR_LOCAL_XSTOP13: Local XSTOP bit 13 triggers Clockstop using ClockControl XSTOP1 | ||
| 25 | RW | CLKSTOP_MASK1_UNIT_TC_FIR_LOCAL_XSTOP14: Local XSTOP bit 14 triggers Clockstop using ClockControl XSTOP1 | ||
| 26 | RW | CLKSTOP_MASK1_UNIT_TC_FIR_LOCAL_XSTOP15: Local XSTOP bit 15 triggers Clockstop using ClockControl XSTOP1 | ||
| Clockstop on XSTOP Mask2 Reg - to CC XSTOP2 | ||||
|---|---|---|---|---|
| Addr: |
0000000011040082 (SCOM) | |||
| Name: | TP.TCPAU1.EPS.FIR.CLKSTOP_ON_XSTOP_MASK2 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:26 | TP.TCPAU1.EPS.FIR.COMP.CLKSTOP_ON_XSTOP_MASK2_Q_INST.LATC.L2(0:26) [000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | RW | CLKSTOP_MASK2_XSTOP_ERR: any xstop triggers clockstop using ClockControl XSTOP2 | ||
| 1 | RW | CLKSTOP_MASK2_RECOV_ERR: any recov triggers clockstop using ClockControl XSTOP2 | ||
| 2 | RW | CLKSTOP_MASK2_SPATTN_ERR: any spattn triggers clockstop using ClockControl XSTOP2 | ||
| 3 | RW | CLKSTOP_MASK2_LXSTOP_ERR: any xstop triggers clockstop using ClockControl XSTOP2 | ||
| 4 | RW | CLKSTOP_MASK2_HOSTATTN_ERR: any hostattn triggers clockstop using ClockControl XSTOP2 | ||
| 5 | RW | CLKSTOP_MASK2_SYS_XSTOP_ERR: system xstop triggers clockstop using ClockControl XSTOP2 | ||
| 6 | RW | CLKSTOP_MASK2_SYS_XSTOP_STAGED_ERR: oob7 -system xstop staged triggers Clockstop using ClockControl XSTOP2 | ||
| 7 | RW | CLKSTOP_MASK2_DBG_TRIG_ERR: dbg triggers Clockstop using ClockControl XSTOP2 | ||
| 8 | RW | CLKSTOP_MASK2_UNUSED08: Unused | ||
| 9 | RW | CLKSTOP_MASK2_UNUSED09: Unused | ||
| 10 | RW | CLKSTOP_MASK2_UNUSED20: Unused | ||
| 11 | RW | CLKSTOP_MASK2_UNUSED22: Unused | ||
| 12 | RW | CLKSTOP_MASK2_UNIT_TC_FIR_LOCAL_XSTOP01: Local XSTOP bit 1 triggers Clockstop using ClockControl XSTOP2 | ||
| 13 | RW | CLKSTOP_MASK2_UNIT_TC_FIR_LOCAL_XSTOP02: Local XSTOP bit 2 triggers Clockstop using ClockControl XSTOP2 | ||
| 14 | RW | CLKSTOP_MASK2_UNIT_TC_FIR_LOCAL_XSTOP03: Local XSTOP bit 3 triggers Clockstop using ClockControl XSTOP2 | ||
| 15 | RW | CLKSTOP_MASK2_UNIT_TC_FIR_LOCAL_XSTOP04: Local XSTOP bit 4 triggers Clockstop using ClockControl XSTOP2 | ||
| 16 | RW | CLKSTOP_MASK2_UNIT_TC_FIR_LOCAL_XSTOP05: Local XSTOP bit 5 triggers Clockstop using ClockControl XSTOP2 | ||
| 17 | RW | CLKSTOP_MASK2_UNIT_TC_FIR_LOCAL_XSTOP06: Local XSTOP bit 6 triggers Clockstop using ClockControl XSTOP2 | ||
| 18 | RW | CLKSTOP_MASK2_UNIT_TC_FIR_LOCAL_XSTOP07: Local XSTOP bit 7 triggers Clockstop using ClockControl XSTOP2 | ||
| 19 | RW | CLKSTOP_MASK2_UNIT_TC_FIR_LOCAL_XSTOP08: Local XSTOP bit 8 triggers Clockstop using ClockControl XSTOP2 | ||
| 20 | RW | CLKSTOP_MASK2_UNIT_TC_FIR_LOCAL_XSTOP09: Local XSTOP bit 9 triggers Clockstop using ClockControl XSTOP2 | ||
| 21 | RW | CLKSTOP_MASK2_UNIT_TC_FIR_LOCAL_XSTOP010: Local XSTOP bit 10 triggers Clockstop using ClockControl XSTOP2 | ||
| 22 | RW | CLKSTOP_MASK2_UNIT_TC_FIR_LOCAL_XSTOP011: Local XSTOP bit 11 triggers Clockstop using ClockControl XSTOP2 | ||
| 23 | RW | CLKSTOP_MASK2_UNIT_TC_FIR_LOCAL_XSTOP012: Local XSTOP bit 12 triggers Clockstop using ClockControl XSTOP2 | ||
| 24 | RW | CLKSTOP_MASK2_UNIT_TC_FIR_LOCAL_XSTOP013: Local XSTOP bit 13 triggers Clockstop using ClockControl XSTOP2 | ||
| 25 | RW | CLKSTOP_MASK2_UNIT_TC_FIR_LOCAL_XSTOP014: Local XSTOP bit 14 triggers Clockstop using ClockControl XSTOP2 | ||
| 26 | RW | CLKSTOP_MASK2_UNIT_TC_FIR_LOCAL_XSTOP015: Local XSTOP bit 15 triggers Clockstop using ClockControl XSTOP2 | ||
| Clockstop on XSTOP Mask3 Reg - to CC XSTOP3 | ||||
|---|---|---|---|---|
| Addr: |
0000000011040083 (SCOM) | |||
| Name: | TP.TCPAU1.EPS.FIR.CLKSTOP_ON_XSTOP_MASK3 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:26 | TP.TCPAU1.EPS.FIR.COMP.CLKSTOP_ON_XSTOP_MASK3_Q_INST.LATC.L2(0:26) [000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | RW | CLKSTOP_MASK3_XSTOP_ERR: any xstop triggers clockstop using ClockControl XSTOP3 | ||
| 1 | RW | CLKSTOP_MASK3_RECOV_ERR: any recov triggers clockstop using ClockControl XSTOP3 | ||
| 2 | RW | CLKSTOP_MASK3_SPATTN_ERR: any spattn triggers clockstop using ClockControl XSTOP3 | ||
| 3 | RW | CLKSTOP_MASK3_LXSTOP_ERR: any xstop triggers clockstop using ClockControl XSTOP3 | ||
| 4 | RW | CLKSTOP_MASK3_HOSTATTN_ERR: any hostattn triggers clockstop using ClockControl XSTOP3 | ||
| 5 | RW | CLKSTOP_MASK3_SYS_XSTOP_ERR: system xstop triggers clockstop using ClockControl XSTOP3 | ||
| 6 | RW | CLKSTOP_MASK3_SYS_XSTOP_STAGED_ERR: oob7 -system xstop staged triggers Clockstop using ClockControl XSTOP3 | ||
| 7 | RW | CLKSTOP_MASK3_DBG_TRIG_ERR: dbg triggers Clockstop using ClockControl XSTOP3 | ||
| 8 | RW | CLKSTOP_MASK3_UNUSED08: Unused | ||
| 9 | RW | CLKSTOP_MASK3_UNUSED09: Unused | ||
| 10 | RW | CLKSTOP_MASK3_UNUSED10: Unused | ||
| 11 | RW | CLKSTOP_MASK3_UNUSED11: Unused | ||
| 12 | RW | CLKSTOP_MASK3_UNIT_TC_FIR_LOCAL_XSTOP01: Local XSTOP bit 1 triggers Clockstop using ClockControl XSTOP3 | ||
| 13 | RW | CLKSTOP_MASK3_UNIT_TC_FIR_LOCAL_XSTOP02: Local XSTOP bit 2 triggers Clockstop using ClockControl XSTOP3 | ||
| 14 | RW | CLKSTOP_MASK3_UNIT_TC_FIR_LOCAL_XSTOP03: Local XSTOP bit 3 triggers Clockstop using ClockControl XSTOP3 | ||
| 15 | RW | CLKSTOP_MASK3_UNIT_TC_FIR_LOCAL_XSTOP04: Local XSTOP bit 4 triggers Clockstop using ClockControl XSTOP3 | ||
| 16 | RW | CLKSTOP_MASK3_UNIT_TC_FIR_LOCAL_XSTOP05: Local XSTOP bit 5 triggers Clockstop using ClockControl XSTOP3 | ||
| 17 | RW | CLKSTOP_MASK3_UNIT_TC_FIR_LOCAL_XSTOP06: Local XSTOP bit 6 triggers Clockstop using ClockControl XSTOP3 | ||
| 18 | RW | CLKSTOP_MASK3_UNIT_TC_FIR_LOCAL_XSTOP07: Local XSTOP bit 7 triggers Clockstop using ClockControl XSTOP3 | ||
| 19 | RW | CLKSTOP_MASK3_UNIT_TC_FIR_LOCAL_XSTOP08: Local XSTOP bit 8 triggers Clockstop using ClockControl XSTOP3 | ||
| 20 | RW | CLKSTOP_MASK3_UNIT_TC_FIR_LOCAL_XSTOP09: Local XSTOP bit 9 triggers Clockstop using ClockControl XSTOP3 | ||
| 21 | RW | CLKSTOP_MASK3_UNIT_TC_FIR_LOCAL_XSTOP010: Local XSTOP bit 10 triggers Clockstop using ClockControl XSTOP3 | ||
| 22 | RW | CLKSTOP_MASK3_UNIT_TC_FIR_LOCAL_XSTOP011: Local XSTOP bit 11 triggers Clockstop using ClockControl XSTOP3 | ||
| 23 | RW | CLKSTOP_MASK3_UNIT_TC_FIR_LOCAL_XSTOP012: Local XSTOP bit 12 triggers Clockstop using ClockControl XSTOP3 | ||
| 24 | RW | CLKSTOP_MASK3_UNIT_TC_FIR_LOCAL_XSTOP013: Local XSTOP bit 13 triggers Clockstop using ClockControl XSTOP3 | ||
| 25 | RW | CLKSTOP_MASK3_UNIT_TC_FIR_LOCAL_XSTOP014: Local XSTOP bit 14 triggers Clockstop using ClockControl XSTOP3 | ||
| 26 | RW | CLKSTOP_MASK3_UNIT_TC_FIR_LOCAL_XSTOP015: Local XSTOP bit 15 triggers Clockstop using ClockControl XSTOP3 | ||
| Clockstop on XSTOP Mask4 Reg - to CC XSTOP4 | ||||
|---|---|---|---|---|
| Addr: |
0000000011040084 (SCOM) | |||
| Name: | TP.TCPAU1.EPS.FIR.CLKSTOP_ON_XSTOP_MASK4 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:26 | TP.TCPAU1.EPS.FIR.COMP.CLKSTOP_ON_XSTOP_MASK4_Q_INST.LATC.L2(0:26) [000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | RW | CLKSTOP_MASK4_XSTOP_ERR: any xstop triggers clockstop using ClockControl XSTOP4 | ||
| 1 | RW | CLKSTOP_MASK4_RECOV_ERR: any recov triggers clockstop using ClockControl XSTOP4 | ||
| 2 | RW | CLKSTOP_MASK4_SPATTN_ERR: any spattn triggers clockstop using ClockControl XSTOP4 | ||
| 3 | RW | CLKSTOP_MASK4_LXSTOP_ERR: any xstop triggers clockstop using ClockControl XSTOP4 | ||
| 4 | RW | CLKSTOP_MASK4_HOSTATTN_ERR: any hostattn triggers clockstop using ClockControl XSTOP4 | ||
| 5 | RW | CLKSTOP_MASK4_SYS_XSTOP_ERR: system xstop triggers clockstop using ClockControl XSTOP4 | ||
| 6 | RW | CLKSTOP_MASK4_SYS_XSTOP_STAGED_ERR: oob7 -system xstop staged triggers Clockstop using ClockControl XSTOP4 | ||
| 7 | RW | CLKSTOP_MASK4_DBG_TRIG_ERR: dbg triggers Clockstop using ClockControl XSTOP4 | ||
| 8 | RW | CLKSTOP_MASK4_UNUSED08: Unused | ||
| 9 | RW | CLKSTOP_MASK4_UNUSED09: Unused | ||
| 10 | RW | CLKSTOP_MASK4_UNUSED10: Unused | ||
| 11 | RW | CLKSTOP_MASK4_UNUSED11: Unused | ||
| 12 | RW | CLKSTOP_MASK4_UNIT_TC_FIR_LOCAL_XSTOP01: Local XSTOP bit 1 triggers Clockstop using ClockControl XSTOP4 | ||
| 13 | RW | CLKSTOP_MASK4_UNIT_TC_FIR_LOCAL_XSTOP02: Local XSTOP bit 2 triggers Clockstop using ClockControl XSTOP4 | ||
| 14 | RW | CLKSTOP_MASK4_UNIT_TC_FIR_LOCAL_XSTOP03: Local XSTOP bit 3 triggers Clockstop using ClockControl XSTOP4 | ||
| 15 | RW | CLKSTOP_MASK4_UNIT_TC_FIR_LOCAL_XSTOP04: Local XSTOP bit 4 triggers Clockstop using ClockControl XSTOP4 | ||
| 16 | RW | CLKSTOP_MASK4_UNIT_TC_FIR_LOCAL_XSTOP05: Local XSTOP bit 5 triggers Clockstop using ClockControl XSTOP4 | ||
| 17 | RW | CLKSTOP_MASK4_UNIT_TC_FIR_LOCAL_XSTOP06: Local XSTOP bit 6 triggers Clockstop using ClockControl XSTOP4 | ||
| 18 | RW | CLKSTOP_MASK4_UNIT_TC_FIR_LOCAL_XSTOP07: Local XSTOP bit 7 triggers Clockstop using ClockControl XSTOP4 | ||
| 19 | RW | CLKSTOP_MASK4_UNIT_TC_FIR_LOCAL_XSTOP08: Local XSTOP bit 8 triggers Clockstop using ClockControl XSTOP4 | ||
| 20 | RW | CLKSTOP_MASK4_UNIT_TC_FIR_LOCAL_XSTOP09: Local XSTOP bit 9 triggers Clockstop using ClockControl XSTOP4 | ||
| 21 | RW | CLKSTOP_MASK4_UNIT_TC_FIR_LOCAL_XSTOP10: Local XSTOP bit 10 triggers Clockstop using ClockControl XSTOP4 | ||
| 22 | RW | CLKSTOP_MASK4_UNIT_TC_FIR_LOCAL_XSTOP11: Local XSTOP bit 11 triggers Clockstop using ClockControl XSTOP4 | ||
| 23 | RW | CLKSTOP_MASK4_UNIT_TC_FIR_LOCAL_XSTOP12: Local XSTOP bit 12 triggers Clockstop using ClockControl XSTOP4 | ||
| 24 | RW | CLKSTOP_MASK4_UNIT_TC_FIR_LOCAL_XSTOP13: Local XSTOP bit 13 triggers Clockstop using ClockControl XSTOP4 | ||
| 25 | RW | CLKSTOP_MASK4_UNIT_TC_FIR_LOCAL_XSTOP14: Local XSTOP bit 14 triggers Clockstop using ClockControl XSTOP4 | ||
| 26 | RW | CLKSTOP_MASK4_UNIT_TC_FIR_LOCAL_XSTOP15: Local XSTOP bit 15 triggers Clockstop using ClockControl XSTOP4 | ||
| Clockstop on XSTOP Mask5 Reg - to CC XSTOP5 | ||||
|---|---|---|---|---|
| Addr: |
0000000011040085 (SCOM) | |||
| Name: | TP.TCPAU1.EPS.FIR.CLKSTOP_ON_XSTOP_MASK5 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:26 | TP.TCPAU1.EPS.FIR.COMP.CLKSTOP_ON_XSTOP_MASK5_Q_INST.LATC.L2(0:26) [000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | RW | CLKSTOP_MASK5_XSTOP_ERR: any xstop triggers clockstop using ClockControl XSTOP5 | ||
| 1 | RW | CLKSTOP_MASK5_RECOV_ERR: any recov triggers clockstop using ClockControl XSTOP5 | ||
| 2 | RW | CLKSTOP_MASK5_SPATTN_ERR: any spattn triggers clockstop using ClockControl XSTOP5 | ||
| 3 | RW | CLKSTOP_MASK5_LXSTOP_ERR: any xstop triggers clockstop using ClockControl XSTOP5 | ||
| 4 | RW | CLKSTOP_MASK5_HOSTATTN_ERR: any hostattn triggers clockstop using ClockControl XSTOP5 | ||
| 5 | RW | CLKSTOP_MASK5_SYS_XSTOP_ERR: system xstop triggers clockstop using ClockControl XSTOP5 | ||
| 6 | RW | CLKSTOP_MASK5_SYS_XSTOP_STAGED_ERR: oob7 -system xstop staged triggers Clockstop using ClockControl XSTOP5 | ||
| 7 | RW | CLKSTOP_MASK5_DBG_TRIG_ERR: dbg triggers Clockstop using ClockControl XSTOP5 | ||
| 8 | RW | CLKSTOP_MASK5_UNUSED08: Unused | ||
| 9 | RW | CLKSTOP_MASK5_UNUSED09: Unused | ||
| 10 | RW | CLKSTOP_MASK5_UNUSED10: Unused | ||
| 11 | RW | CLKSTOP_MASK5_UNUSED11: Unused | ||
| 12 | RW | CLKSTOP_MASK5_UNIT_TC_FIR_LOCAL_XSTOP01: Local XSTOP bit 1 triggers Clockstop using ClockControl XSTOP5 | ||
| 13 | RW | CLKSTOP_MASK5_UNIT_TC_FIR_LOCAL_XSTOP02: Local XSTOP bit 2 triggers Clockstop using ClockControl XSTOP5 | ||
| 14 | RW | CLKSTOP_MASK5_UNIT_TC_FIR_LOCAL_XSTOP03: Local XSTOP bit 3 triggers Clockstop using ClockControl XSTOP5 | ||
| 15 | RW | CLKSTOP_MASK5_UNIT_TC_FIR_LOCAL_XSTOP04: Local XSTOP bit 4 triggers Clockstop using ClockControl XSTOP5 | ||
| 16 | RW | CLKSTOP_MASK5_UNIT_TC_FIR_LOCAL_XSTOP05: Local XSTOP bit 5 triggers Clockstop using ClockControl XSTOP5 | ||
| 17 | RW | CLKSTOP_MASK5_UNIT_TC_FIR_LOCAL_XSTOP06: Local XSTOP bit 6 triggers Clockstop using ClockControl XSTOP5 | ||
| 18 | RW | CLKSTOP_MASK5_UNIT_TC_FIR_LOCAL_XSTOP07: Local XSTOP bit 7 triggers Clockstop using ClockControl XSTOP5 | ||
| 19 | RW | CLKSTOP_MASK5_UNIT_TC_FIR_LOCAL_XSTOP08: Local XSTOP bit 8 triggers Clockstop using ClockControl XSTOP5 | ||
| 20 | RW | CLKSTOP_MASK5_UNIT_TC_FIR_LOCAL_XSTOP09: Local XSTOP bit 9 triggers Clockstop using ClockControl XSTOP5 | ||
| 21 | RW | CLKSTOP_MASK5_UNIT_TC_FIR_LOCAL_XSTOP10: Local XSTOP bit 10 triggers Clockstop using ClockControl XSTOP5 | ||
| 22 | RW | CLKSTOP_MASK5_UNIT_TC_FIR_LOCAL_XSTOP11: Local XSTOP bit 11 triggers Clockstop using ClockControl XSTOP5 | ||
| 23 | RW | CLKSTOP_MASK5_UNIT_TC_FIR_LOCAL_XSTOP12: Local XSTOP bit 12 triggers Clockstop using ClockControl XSTOP5 | ||
| 24 | RW | CLKSTOP_MASK5_UNIT_TC_FIR_LOCAL_XSTOP13: Local XSTOP bit 13 triggers Clockstop using ClockControl XSTOP5 | ||
| 25 | RW | CLKSTOP_MASK5_UNIT_TC_FIR_LOCAL_XSTOP14: Local XSTOP bit 14 triggers Clockstop using ClockControl XSTOP5 | ||
| 26 | RW | CLKSTOP_MASK5_UNIT_TC_FIR_LOCAL_XSTOP15: Local XSTOP bit 15 triggers Clockstop using ClockControl XSTOP5 | ||
| Mode Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011040088 (SCOM) | |||
| Name: | TP.TCPAU1.EPS.FIR.MODE_REG | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:15 | TP.TCPAU1.EPS.FIR.COMP.MODE_REG_Q_INST.LATC.L2(0:15) [0000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | RW | XSTOP_LOCK_XSTOP: XSTOP will lock XSTOP register - default = 1 | ||
| 1 | RW | XSTOP_LOCK_RECOV: XSTOP will lock RECOV register - default = 1 | ||
| 2 | RW | XSTOP_LOCK_SPATTN: XSTOP will lock SPATTN register - default = 0 | ||
| 3 | RW | XSTOP_LOCK_LXSTOP: XSTOP will lock LXSTOP register - default = 0 | ||
| 4 | RW | XSTOP_LOCK_HOSTATTN: XSTOP will lock HOSTATTN register - default = 0 | ||
| 5 | RW | MODE_REG05: unused | ||
| 6 | RW | DISABLE_IOPB_ERR: disable_iopb_err XSTOP trigger to IO/PB | ||
| 7 | RW | MODE_REG07: unused | ||
| 8 | RW | MODE_REG08: unused | ||
| 9 | RW | MASK_DIRECT_ERROR: mask direct error XSTOP trigger to Core | ||
| 10 | RW | MODE_REG10: unused | ||
| 11 | RW | MODE_REG11: unused | ||
| 12 | RW | MODE_REG12: unused | ||
| 13 | RW | MODE_REG13: unused | ||
| 14 | RW | MODE_REG14: unused | ||
| 15 | RW | MODE_REG15: unused | ||
| Local FIR | ||||
|---|---|---|---|---|
| Addr: |
0000000011040100 (SCOM) 0000000011040101 (SCOM1) 0000000011040102 (SCOM2) | |||
| Name: | TP.TCPAU1.LOCAL_FIR | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | TP.TCPAU1.EPS.FIR.LFIR.LOCALFIR.FIR.FIR.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | SCOM1 | SCOM2 | Dial: Description |
| 0 | RWX | WOX_AND | WOX_OR | LFIR_ERROR_CFIR: CFIR - Parity or PCB access error TYPE:RECOV CLEAR:only LFIR |
| 1 | RWX | WOX_AND | WOX_OR | LFIR_ERROR_CPLT_CTRL: CPLT_CTRL - PCB access error TYPE:RECOV CLEAR:by next PCB req |
| 2 | RWX | WOX_AND | WOX_OR | LFIR_ERROR_CC_PCB: CC - PCB access error TYPE:RECOV READ STATUS:nn03000F CLEAR:write 0 to nn03000F |
| 3 | RWX | WOX_AND | WOX_OR | LFIR_ERROR_CC_OTHERS: CC - Clock Control Error TYPE:RECOV READ STATUS:nn03000F CLEAR:write 0 to nn03000F |
| 4 | RWX | WOX_AND | WOX_OR | LFIR_ERROR_IN04: PSC - PSCOM access error TYPE:RECOV READ STATUS:nn010001 CLEAR:write 0 to nn010001 |
| 5 | RWX | WOX_AND | WOX_OR | LFIR_ERROR_IN05: PSC - internal or ring interface error TYPE:RECOV READ STATUS:nn010001 CLEAR:write 0 to nn010001 |
| 6 | RWX | WOX_AND | WOX_OR | LFIR_ERROR_IN06: THERM - pwr_comp_err, skitter_comp_err, scan_init_version_reg_parity_err_out , count_state_err_out TYPE:RECOV - MASK afterwards READ STATUS:nn050013 CLEAR:only scan0 |
| 7 | RWX | WOX_AND | WOX_OR | LFIR_ERROR_IN07: THERM - pcb error TYPE:RECOV CLEAR:by next PCB req |
| 8 | RWX | WOX_AND | WOX_OR | LFIR_ERROR_IN08: THERMTRIP - Critical temperature indicator TYPE:MASKED (unused) CLEAR:only LFIR |
| 9 | RWX | WOX_AND | WOX_OR | LFIR_ERROR_IN09: THERMTRIP - Fatal temperature indicator TYPE:MASKED (unused) CLEAR:only LFIR |
| 10 | RWX | WOX_AND | WOX_OR | LFIR_ERROR_IN10: VOLTTRIP - Voltage sense error TYPE:MASKED (unused) CLEAR:only LFIR |
| 11 | RWX | WOX_AND | WOX_OR | LFIR_ERROR_IN11: DBG - scom parity fail TYPE:RECOV CLEAR:by next SCOM req |
| 12 | RWX | WOX_AND | WOX_OR | LFIR_ERROR_IN12: reserved TYPE:MASKED (unused) CLEAR:only LFIR |
| 13 | RWX | WOX_AND | WOX_OR | LFIR_ERROR_IN13: reserved TYPE:MASKED (unused) CLEAR:only LFIR |
| 14 | RWX | WOX_AND | WOX_OR | LFIR_ERROR_IN14: reserved TYPE:MASKED (unused) CLEAR:only LFIR |
| 15 | RWX | WOX_AND | WOX_OR | LFIR_ERROR_IN15: reserved TYPE:MASKED (unused) CLEAR:only LFIR |
| 16 | RWX | WOX_AND | WOX_OR | LFIR_ERROR_IN16: reserved TYPE:MASKED (unused) CLEAR:only LFIR |
| 17 | RWX | WOX_AND | WOX_OR | LFIR_ERROR_IN17: reserved TYPE:MASKED (unused) CLEAR:only LFIR |
| 18 | RWX | WOX_AND | WOX_OR | LFIR_ERROR_IN18: reserved TYPE:MASKED (unused) CLEAR:only LFIR |
| 19 | RWX | WOX_AND | WOX_OR | LFIR_ERROR_IN19: reserved TYPE:MASKED (unused) CLEAR:only LFIR |
| 20 | RWX | WOX_AND | WOX_OR | LFIR_ERROR_IN20: Trace00 - scom parity err TYPE:RECOV CLEAR:by next SCOM req |
| 21 | RWX | WOX_AND | WOX_OR | LFIR_ERROR_IN21: Trace01 - scom parity err - Unused in Axon,PCI TYPE:RECOV CLEAR:by next SCOM req |
| 22 | RWX | WOX_AND | WOX_OR | LFIR_ERROR_IN22: unused TYPE:MASKED (unused) CLEAR:only LFIR |
| 23 | RWX | WOX_AND | WOX_OR | LFIR_ERROR_IN23: unused TYPE:MASKED (unused) CLEAR:only LFIR |
| 24 | RWX | WOX_AND | WOX_OR | LFIR_ERROR_IN24: unused TYPE:MASKED (unused) CLEAR:only LFIR |
| 25 | RWX | WOX_AND | WOX_OR | LFIR_ERROR_IN25: unused TYPE:MASKED (unused) CLEAR:only LFIR |
| 26 | RWX | WOX_AND | WOX_OR | LFIR_ERROR_IN26: unused TYPE:MASKED (unused) CLEAR:only LFIR |
| 27 | RWX | WOX_AND | WOX_OR | LFIR_ERROR_IN27: unused TYPE:MASKED (unused) CLEAR:only LFIR |
| 28 | RWX | WOX_AND | WOX_OR | LFIR_ERROR_IN28: unused TYPE:MASKED (unused) CLEAR:only LFIR |
| 29 | RWX | WOX_AND | WOX_OR | LFIR_ERROR_IN29: unused TYPE:MASKED (unused) CLEAR:only LFIR |
| 30 | RWX | WOX_AND | WOX_OR | LFIR_ERROR_IN30: unused TYPE:MASKED (unused) CLEAR:only LFIR |
| 31 | RWX | WOX_AND | WOX_OR | LFIR_ERROR_IN31: unused TYPE:MASKED (unused) CLEAR:only LFIR |
| 32 | RWX | WOX_AND | WOX_OR | LFIR_ERROR_IN32: unused TYPE:MASKED (unused) CLEAR:only LFIR |
| 33 | RWX | WOX_AND | WOX_OR | LFIR_ERROR_IN33: unused TYPE:MASKED (unused) CLEAR:only LFIR |
| 34 | RWX | WOX_AND | WOX_OR | LFIR_ERROR_IN34: unused TYPE:MASKED (unused) CLEAR:only LFIR |
| 35 | RWX | WOX_AND | WOX_OR | LFIR_ERROR_IN35: unused TYPE:MASKED (unused) CLEAR:only LFIR |
| 36 | RWX | WOX_AND | WOX_OR | LFIR_ERROR_IN36: unused TYPE:MASKED (unused) CLEAR:only LFIR |
| 37 | RWX | WOX_AND | WOX_OR | LFIR_ERROR_IN37: unused TYPE:MASKED (unused) CLEAR:only LFIR |
| 38 | RWX | WOX_AND | WOX_OR | LFIR_ERROR_IN38: unused TYPE:MASKED (unused) CLEAR:only LFIR |
| 39 | RWX | WOX_AND | WOX_OR | LFIR_ERROR_IN39: unused TYPE:MASKED (unused) CLEAR:only LFIR |
| 40 | RWX | WOX_AND | WOX_OR | LFIR_ERROR_IN40: unused TYPE:MASKED (unused) CLEAR:only LFIR |
| 41 | RWX | WOX_AND | WOX_OR | LFIR_ERROR_IN41: unused TYPE:MASKED (unused) CLEAR:only LFIR |
| 42 | RWX | WOX_AND | WOX_OR | LFIR_ERROR_IN42: unused TYPE:MASKED (unused) CLEAR:only LFIR |
| 43 | RWX | WOX_AND | WOX_OR | LFIR_ERROR_IN43: unused TYPE:MASKED (unused) CLEAR:only LFIR |
| 44 | RWX | WOX_AND | WOX_OR | LFIR_ERROR_IN44: unused TYPE:MASKED (unused) CLEAR:only LFIR |
| 45 | RWX | WOX_AND | WOX_OR | LFIR_ERROR_IN45: unused TYPE:MASKED (unused) CLEAR:only LFIR |
| 46 | RWX | WOX_AND | WOX_OR | LFIR_ERROR_IN46: unused TYPE:MASKED (unused) CLEAR:only LFIR |
| 47 | RWX | WOX_AND | WOX_OR | LFIR_ERROR_IN47: unused TYPE:MASKED (unused) CLEAR:only LFIR |
| 48 | RWX | WOX_AND | WOX_OR | LFIR_ERROR_IN48: unused TYPE:MASKED (unused) CLEAR:only LFIR |
| 49 | RWX | WOX_AND | WOX_OR | LFIR_ERROR_IN49: unused TYPE:MASKED (unused) CLEAR:only LFIR |
| 50 | RWX | WOX_AND | WOX_OR | LFIR_ERROR_IN50: unused TYPE:MASKED (unused) CLEAR:only LFIR |
| 51 | RWX | WOX_AND | WOX_OR | LFIR_ERROR_IN51: unused TYPE:MASKED (unused) CLEAR:only LFIR |
| 52 | RWX | WOX_AND | WOX_OR | LFIR_ERROR_IN52: unused TYPE:MASKED (unused) CLEAR:only LFIR |
| 53 | RWX | WOX_AND | WOX_OR | LFIR_ERROR_IN53: unused TYPE:MASKED (unused) CLEAR:only LFIR |
| 54 | RWX | WOX_AND | WOX_OR | LFIR_ERROR_IN54: unused TYPE:MASKED (unused) CLEAR:only LFIR |
| 55 | RWX | WOX_AND | WOX_OR | LFIR_ERROR_IN55: unused TYPE:MASKED (unused) CLEAR:only LFIR |
| 56 | RWX | WOX_AND | WOX_OR | LFIR_ERROR_IN56: unused TYPE:MASKED (unused) CLEAR:only LFIR |
| 57 | RWX | WOX_AND | WOX_OR | LFIR_ERROR_IN57: unused TYPE:MASKED (unused) CLEAR:only LFIR |
| 58 | RWX | WOX_AND | WOX_OR | LFIR_ERROR_IN58: unused TYPE:MASKED (unused) CLEAR:only LFIR |
| 59 | RWX | WOX_AND | WOX_OR | LFIR_ERROR_IN59: unused TYPE:MASKED (unused) CLEAR:only LFIR |
| 60 | RWX | WOX_AND | WOX_OR | LFIR_ERROR_IN60: unused TYPE:MASKED (unused) CLEAR:only LFIR |
| 61 | RWX | WOX_AND | WOX_OR | LFIR_ERROR_IN61: unused TYPE:MASKED (unused) CLEAR:only LFIR |
| 62 | RWX | WOX_AND | WOX_OR | LFIR_ERROR_IN62: unused TYPE:MASKED (unused) CLEAR:only LFIR |
| 63 | RWX | WOX_AND | WOX_OR | LFIR_ERROR_EXT_LOCAL_XSTOP: ext_local_xstop TYPE:MASKED (unused) CLEAR: |
| Local FIR Mask | ||||
|---|---|---|---|---|
| Addr: |
0000000011040103 (SCOM) 0000000011040104 (SCOM1) 0000000011040105 (SCOM2) | |||
| Name: | TP.TCPAU1.EPS.FIR.LOCAL_FIR_MASK | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | TP.TCPAU1.EPS.FIR.LFIR.LOCALFIR.FIR.FIR_MASK.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | SCOM1 | SCOM2 | Dial: Description |
| 0 | RW | WO_AND | WO_OR | LFIR_MASK00: MASK |
| 1 | RW | WO_AND | WO_OR | LFIR_MASK01: MASK |
| 2 | RW | WO_AND | WO_OR | LFIR_MASK02: MASK |
| 3 | RW | WO_AND | WO_OR | LFIR_MASK03: MASK |
| 4 | RW | WO_AND | WO_OR | LFIR_MASK04: MASK |
| 5 | RW | WO_AND | WO_OR | LFIR_MASK05: MASK |
| 6 | RW | WO_AND | WO_OR | LFIR_MASK06: MASK |
| 7 | RW | WO_AND | WO_OR | LFIR_MASK07: MASK |
| 8 | RW | WO_AND | WO_OR | LFIR_MASK08: MASK |
| 9 | RW | WO_AND | WO_OR | LFIR_MASK09: MASK |
| 10 | RW | WO_AND | WO_OR | LFIR_MASK10: MASK |
| 11 | RW | WO_AND | WO_OR | LFIR_MASK11: MASK |
| 12 | RW | WO_AND | WO_OR | LFIR_MASK12: MASK |
| 13 | RW | WO_AND | WO_OR | LFIR_MASK13: MASK |
| 14 | RW | WO_AND | WO_OR | LFIR_MASK14: MASK |
| 15 | RW | WO_AND | WO_OR | LFIR_MASK15: MASK |
| 16 | RW | WO_AND | WO_OR | LFIR_MASK16: MASK |
| 17 | RW | WO_AND | WO_OR | LFIR_MASK17: MASK |
| 18 | RW | WO_AND | WO_OR | LFIR_MASK18: MASK |
| 19 | RW | WO_AND | WO_OR | LFIR_MASK19: MASK |
| 20 | RW | WO_AND | WO_OR | LFIR_MASK20: MASK |
| 21 | RW | WO_AND | WO_OR | LFIR_MASK21: MASK |
| 22 | RW | WO_AND | WO_OR | LFIR_MASK22: MASK |
| 23 | RW | WO_AND | WO_OR | LFIR_MASK23: MASK |
| 24 | RW | WO_AND | WO_OR | LFIR_MASK24: MASK |
| 25 | RW | WO_AND | WO_OR | LFIR_MASK25: MASK |
| 26 | RW | WO_AND | WO_OR | LFIR_MASK26: MASK |
| 27 | RW | WO_AND | WO_OR | LFIR_MASK27: MASK |
| 28 | RW | WO_AND | WO_OR | LFIR_MASK28: MASK |
| 29 | RW | WO_AND | WO_OR | LFIR_MASK29: MASK |
| 30 | RW | WO_AND | WO_OR | LFIR_MASK30: MASK |
| 31 | RW | WO_AND | WO_OR | LFIR_MASK31: MASK |
| 32 | RW | WO_AND | WO_OR | LFIR_MASK32: MASK |
| 33 | RW | WO_AND | WO_OR | LFIR_MASK33: MASK |
| 34 | RW | WO_AND | WO_OR | LFIR_MASK34: MASK |
| 35 | RW | WO_AND | WO_OR | LFIR_MASK35: MASK |
| 36 | RW | WO_AND | WO_OR | LFIR_MASK36: MASK |
| 37 | RW | WO_AND | WO_OR | LFIR_MASK37: MASK |
| 38 | RW | WO_AND | WO_OR | LFIR_MASK38: MASK |
| 39 | RW | WO_AND | WO_OR | LFIR_MASK39: MASK |
| 40 | RW | WO_AND | WO_OR | LFIR_MASK40: MASK |
| 41 | RW | WO_AND | WO_OR | LFIR_MASK41: MASK |
| 42 | RW | WO_AND | WO_OR | LFIR_MASK42: MASK |
| 43 | RW | WO_AND | WO_OR | LFIR_MASK43: MASK |
| 44 | RW | WO_AND | WO_OR | LFIR_MASK44: MASK |
| 45 | RW | WO_AND | WO_OR | LFIR_MASK45: MASK |
| 46 | RW | WO_AND | WO_OR | LFIR_MASK46: MASK |
| 47 | RW | WO_AND | WO_OR | LFIR_MASK47: MASK |
| 48 | RW | WO_AND | WO_OR | LFIR_MASK48: MASK |
| 49 | RW | WO_AND | WO_OR | LFIR_MASK49: MASK |
| 50 | RW | WO_AND | WO_OR | LFIR_MASK50: MASK |
| 51 | RW | WO_AND | WO_OR | LFIR_MASK51: MASK |
| 52 | RW | WO_AND | WO_OR | LFIR_MASK52: MASK |
| 53 | RW | WO_AND | WO_OR | LFIR_MASK53: MASK |
| 54 | RW | WO_AND | WO_OR | LFIR_MASK54: MASK |
| 55 | RW | WO_AND | WO_OR | LFIR_MASK55: MASK |
| 56 | RW | WO_AND | WO_OR | LFIR_MASK56: MASK |
| 57 | RW | WO_AND | WO_OR | LFIR_MASK57: MASK |
| 58 | RW | WO_AND | WO_OR | LFIR_MASK58: MASK |
| 59 | RW | WO_AND | WO_OR | LFIR_MASK59: MASK |
| 60 | RW | WO_AND | WO_OR | LFIR_MASK60: MASK |
| 61 | RW | WO_AND | WO_OR | LFIR_MASK61: MASK |
| 62 | RW | WO_AND | WO_OR | LFIR_MASK62: MASK |
| 63 | RW | WO_AND | WO_OR | LFIR_MASK63: MASK |
| Local FIR Action0 | ||||
|---|---|---|---|---|
| Addr: |
0000000011040106 (SCOM) | |||
| Name: | TP.TCPAU1.EPS.FIR.LOCAL_FIR_ACTION0 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | TP.TCPAU1.EPS.FIR.LFIR.LOCALFIR.FIR.DO_ACTION0.FIR_ACTION0.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | RW | FIR_ACTION0_IN00: ACTION0 | ||
| 1 | RW | FIR_ACTION0_IN01: ACTION0 | ||
| 2 | RW | FIR_ACTION0_IN02: ACTION0 | ||
| 3 | RW | FIR_ACTION0_IN03: ACTION0 | ||
| 4 | RW | FIR_ACTION0_IN04: ACTION0 | ||
| 5 | RW | FIR_ACTION0_IN05: ACTION0 | ||
| 6 | RW | FIR_ACTION0_IN06: ACTION0 | ||
| 7 | RW | FIR_ACTION0_IN07: ACTION0 | ||
| 8 | RW | FIR_ACTION0_IN08: ACTION0 | ||
| 9 | RW | FIR_ACTION0_IN09: ACTION0 | ||
| 10 | RW | FIR_ACTION0_IN10: ACTION0 | ||
| 11 | RW | FIR_ACTION0_IN11: ACTION0 | ||
| 12 | RW | FIR_ACTION0_IN12: ACTION0 | ||
| 13 | RW | FIR_ACTION0_IN13: ACTION0 | ||
| 14 | RW | FIR_ACTION0_IN14: ACTION0 | ||
| 15 | RW | FIR_ACTION0_IN15: ACTION0 | ||
| 16 | RW | FIR_ACTION0_IN16: ACTION0 | ||
| 17 | RW | FIR_ACTION0_IN17: ACTION0 | ||
| 18 | RW | FIR_ACTION0_IN18: ACTION0 | ||
| 19 | RW | FIR_ACTION0_IN19: ACTION0 | ||
| 20 | RW | FIR_ACTION0_IN20: ACTION0 | ||
| 21 | RW | FIR_ACTION0_IN21: ACTION0 | ||
| 22 | RW | FIR_ACTION0_IN22: ACTION0 | ||
| 23 | RW | FIR_ACTION0_IN23: ACTION0 | ||
| 24 | RW | FIR_ACTION0_IN24: ACTION0 | ||
| 25 | RW | FIR_ACTION0_IN25: ACTION0 | ||
| 26 | RW | FIR_ACTION0_IN26: ACTION0 | ||
| 27 | RW | FIR_ACTION0_IN27: ACTION0 | ||
| 28 | RW | FIR_ACTION0_IN28: ACTION0 | ||
| 29 | RW | FIR_ACTION0_IN29: ACTION0 | ||
| 30 | RW | FIR_ACTION0_IN30: ACTION0 | ||
| 31 | RW | FIR_ACTION0_IN31: ACTION0 | ||
| 32 | RW | FIR_ACTION0_IN32: ACTION0 | ||
| 33 | RW | FIR_ACTION0_IN33: ACTION0 | ||
| 34 | RW | FIR_ACTION0_IN34: ACTION0 | ||
| 35 | RW | FIR_ACTION0_IN35: ACTION0 | ||
| 36 | RW | FIR_ACTION0_IN36: ACTION0 | ||
| 37 | RW | FIR_ACTION0_IN37: ACTION0 | ||
| 38 | RW | FIR_ACTION0_IN38: ACTION0 | ||
| 39 | RW | FIR_ACTION0_IN39: ACTION0 | ||
| 40 | RW | FIR_ACTION0_IN40: ACTION0 | ||
| 41 | RW | FIR_ACTION0_IN41: ACTION0 | ||
| 42 | RW | FIR_ACTION0_IN42: ACTION0 | ||
| 43 | RW | FIR_ACTION0_IN43: ACTION0 | ||
| 44 | RW | FIR_ACTION0_IN44: ACTION0 | ||
| 45 | RW | FIR_ACTION0_IN45: ACTION0 | ||
| 46 | RW | FIR_ACTION0_IN46: ACTION0 | ||
| 47 | RW | FIR_ACTION0_IN47: ACTION0 | ||
| 48 | RW | FIR_ACTION0_IN48: ACTION0 | ||
| 49 | RW | FIR_ACTION0_IN49: ACTION0 | ||
| 50 | RW | FIR_ACTION0_IN50: ACTION0 | ||
| 51 | RW | FIR_ACTION0_IN51: ACTION0 | ||
| 52 | RW | FIR_ACTION0_IN52: ACTION0 | ||
| 53 | RW | FIR_ACTION0_IN53: ACTION0 | ||
| 54 | RW | FIR_ACTION0_IN54: ACTION0 | ||
| 55 | RW | FIR_ACTION0_IN55: ACTION0 | ||
| 56 | RW | FIR_ACTION0_IN56: ACTION0 | ||
| 57 | RW | FIR_ACTION0_IN57: ACTION0 | ||
| 58 | RW | FIR_ACTION0_IN58: ACTION0 | ||
| 59 | RW | FIR_ACTION0_IN59: ACTION0 | ||
| 60 | RW | FIR_ACTION0_IN60: ACTION0 | ||
| 61 | RW | FIR_ACTION0_IN61: ACTION0 | ||
| 62 | RW | FIR_ACTION0_IN62: ACTION0 | ||
| 63 | RW | FIR_ACTION0_IN63: ACTION0 | ||
| Local FIR Action1 | ||||
|---|---|---|---|---|
| Addr: |
0000000011040107 (SCOM) | |||
| Name: | TP.TCPAU1.EPS.FIR.LOCAL_FIR_ACTION1 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | TP.TCPAU1.EPS.FIR.LFIR.LOCALFIR.FIR.DO_ACTION1.FIR_ACTION1.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | RW | FIR_ACTION1_IN00: ACTION1 | ||
| 1 | RW | FIR_ACTION1_IN01: ACTION1 | ||
| 2 | RW | FIR_ACTION1_IN02: ACTION1 | ||
| 3 | RW | FIR_ACTION1_IN03: ACTION1 | ||
| 4 | RW | FIR_ACTION1_IN04: ACTION1 | ||
| 5 | RW | FIR_ACTION1_IN05: ACTION1 | ||
| 6 | RW | FIR_ACTION1_IN06: ACTION1 | ||
| 7 | RW | FIR_ACTION1_IN07: ACTION1 | ||
| 8 | RW | FIR_ACTION1_IN08: ACTION1 | ||
| 9 | RW | FIR_ACTION1_IN09: ACTION1 | ||
| 10 | RW | FIR_ACTION1_IN10: ACTION1 | ||
| 11 | RW | FIR_ACTION1_IN11: ACTION1 | ||
| 12 | RW | FIR_ACTION1_IN12: ACTION1 | ||
| 13 | RW | FIR_ACTION1_IN13: ACTION1 | ||
| 14 | RW | FIR_ACTION1_IN14: ACTION1 | ||
| 15 | RW | FIR_ACTION1_IN15: ACTION1 | ||
| 16 | RW | FIR_ACTION1_IN16: ACTION1 | ||
| 17 | RW | FIR_ACTION1_IN17: ACTION1 | ||
| 18 | RW | FIR_ACTION1_IN18: ACTION1 | ||
| 19 | RW | FIR_ACTION1_IN19: ACTION1 | ||
| 20 | RW | FIR_ACTION1_IN20: ACTION1 | ||
| 21 | RW | FIR_ACTION1_IN21: ACTION1 | ||
| 22 | RW | FIR_ACTION1_IN22: ACTION1 | ||
| 23 | RW | FIR_ACTION1_IN23: ACTION1 | ||
| 24 | RW | FIR_ACTION1_IN24: ACTION1 | ||
| 25 | RW | FIR_ACTION1_IN25: ACTION1 | ||
| 26 | RW | FIR_ACTION1_IN26: ACTION1 | ||
| 27 | RW | FIR_ACTION1_IN27: ACTION1 | ||
| 28 | RW | FIR_ACTION1_IN28: ACTION1 | ||
| 29 | RW | FIR_ACTION1_IN29: ACTION1 | ||
| 30 | RW | FIR_ACTION1_IN30: ACTION1 | ||
| 31 | RW | FIR_ACTION1_IN31: ACTION1 | ||
| 32 | RW | FIR_ACTION1_IN32: ACTION1 | ||
| 33 | RW | FIR_ACTION1_IN33: ACTION1 | ||
| 34 | RW | FIR_ACTION1_IN34: ACTION1 | ||
| 35 | RW | FIR_ACTION1_IN35: ACTION1 | ||
| 36 | RW | FIR_ACTION1_IN36: ACTION1 | ||
| 37 | RW | FIR_ACTION1_IN37: ACTION1 | ||
| 38 | RW | FIR_ACTION1_IN38: ACTION1 | ||
| 39 | RW | FIR_ACTION1_IN39: ACTION1 | ||
| 40 | RW | FIR_ACTION1_IN40: ACTION1 | ||
| 41 | RW | FIR_ACTION1_IN41: ACTION1 | ||
| 42 | RW | FIR_ACTION1_IN42: ACTION1 | ||
| 43 | RW | FIR_ACTION1_IN43: ACTION1 | ||
| 44 | RW | FIR_ACTION1_IN44: ACTION1 | ||
| 45 | RW | FIR_ACTION1_IN45: ACTION1 | ||
| 46 | RW | FIR_ACTION1_IN46: ACTION1 | ||
| 47 | RW | FIR_ACTION1_IN47: ACTION1 | ||
| 48 | RW | FIR_ACTION1_IN48: ACTION1 | ||
| 49 | RW | FIR_ACTION1_IN49: ACTION1 | ||
| 50 | RW | FIR_ACTION1_IN50: ACTION1 | ||
| 51 | RW | FIR_ACTION1_IN51: ACTION1 | ||
| 52 | RW | FIR_ACTION1_IN52: ACTION1 | ||
| 53 | RW | FIR_ACTION1_IN53: ACTION1 | ||
| 54 | RW | FIR_ACTION1_IN54: ACTION1 | ||
| 55 | RW | FIR_ACTION1_IN55: ACTION1 | ||
| 56 | RW | FIR_ACTION1_IN56: ACTION1 | ||
| 57 | RW | FIR_ACTION1_IN57: ACTION1 | ||
| 58 | RW | FIR_ACTION1_IN58: ACTION1 | ||
| 59 | RW | FIR_ACTION1_IN59: ACTION1 | ||
| 60 | RW | FIR_ACTION1_IN60: ACTION1 | ||
| 61 | RW | FIR_ACTION1_IN61: ACTION1 | ||
| 62 | RW | FIR_ACTION1_IN62: ACTION1 | ||
| 63 | RW | FIR_ACTION1_IN63: ACTION1 | ||
| Local FIR WOF | ||||
|---|---|---|---|---|
| Addr: |
0000000011040108 (SCOM) | |||
| Name: | TP.TCPAU1.EPS.FIR.LOCAL_FIR_WOF | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | TP.TCPAU1.EPS.FIR.LFIR.LOCALFIR.FIR.WOF_LAT_YES.WOF.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | RW_WCLRPART | FIR_WOF_IN00: WOF | ||
| 1 | RW_WCLRPART | FIR_WOF_IN01: WOF | ||
| 2 | RW_WCLRPART | FIR_WOF_IN02: WOF | ||
| 3 | RW_WCLRPART | FIR_WOF_IN03: WOF | ||
| 4 | RW_WCLRPART | FIR_WOF_IN04: WOF | ||
| 5 | RW_WCLRPART | FIR_WOF_IN05: WOF | ||
| 6 | RW_WCLRPART | FIR_WOF_IN06: WOF | ||
| 7 | RW_WCLRPART | FIR_WOF_IN07: WOF | ||
| 8 | RW_WCLRPART | FIR_WOF_IN08: WOF | ||
| 9 | RW_WCLRPART | FIR_WOF_IN09: WOF | ||
| 10 | RW_WCLRPART | FIR_WOF_IN10: WOF | ||
| 11 | RW_WCLRPART | FIR_WOF_IN11: WOF | ||
| 12 | RW_WCLRPART | FIR_WOF_IN12: WOF | ||
| 13 | RW_WCLRPART | FIR_WOF_IN13: WOF | ||
| 14 | RW_WCLRPART | FIR_WOF_IN14: WOF | ||
| 15 | RW_WCLRPART | FIR_WOF_IN15: WOF | ||
| 16 | RW_WCLRPART | FIR_WOF_IN16: WOF | ||
| 17 | RW_WCLRPART | FIR_WOF_IN17: WOF | ||
| 18 | RW_WCLRPART | FIR_WOF_IN18: WOF | ||
| 19 | RW_WCLRPART | FIR_WOF_IN19: WOF | ||
| 20 | RW_WCLRPART | FIR_WOF_IN20: WOF | ||
| 21 | RW_WCLRPART | FIR_WOF_IN21: WOF | ||
| 22 | RW_WCLRPART | FIR_WOF_IN22: WOF | ||
| 23 | RW_WCLRPART | FIR_WOF_IN23: WOF | ||
| 24 | RW_WCLRPART | FIR_WOF_IN24: WOF | ||
| 25 | RW_WCLRPART | FIR_WOF_IN25: WOF | ||
| 26 | RW_WCLRPART | FIR_WOF_IN26: WOF | ||
| 27 | RW_WCLRPART | FIR_WOF_IN27: WOF | ||
| 28 | RW_WCLRPART | FIR_WOF_IN28: WOF | ||
| 29 | RW_WCLRPART | FIR_WOF_IN29: WOF | ||
| 30 | RW_WCLRPART | FIR_WOF_IN30: WOF | ||
| 31 | RW_WCLRPART | FIR_WOF_IN31: WOF | ||
| 32 | RW_WCLRPART | FIR_WOF_IN32: WOF | ||
| 33 | RW_WCLRPART | FIR_WOF_IN33: WOF | ||
| 34 | RW_WCLRPART | FIR_WOF_IN34: WOF | ||
| 35 | RW_WCLRPART | FIR_WOF_IN35: WOF | ||
| 36 | RW_WCLRPART | FIR_WOF_IN36: WOF | ||
| 37 | RW_WCLRPART | FIR_WOF_IN37: WOF | ||
| 38 | RW_WCLRPART | FIR_WOF_IN38: WOF | ||
| 39 | RW_WCLRPART | FIR_WOF_IN39: WOF | ||
| 40 | RW_WCLRPART | FIR_WOF_IN40: WOF | ||
| 41 | RW_WCLRPART | FIR_WOF_IN41: WOF | ||
| 42 | RW_WCLRPART | FIR_WOF_IN42: WOF | ||
| 43 | RW_WCLRPART | FIR_WOF_IN43: WOF | ||
| 44 | RW_WCLRPART | FIR_WOF_IN44: WOF | ||
| 45 | RW_WCLRPART | FIR_WOF_IN45: WOF | ||
| 46 | RW_WCLRPART | FIR_WOF_IN46: WOF | ||
| 47 | RW_WCLRPART | FIR_WOF_IN47: WOF | ||
| 48 | RW_WCLRPART | FIR_WOF_IN48: WOF | ||
| 49 | RW_WCLRPART | FIR_WOF_IN49: WOF | ||
| 50 | RW_WCLRPART | FIR_WOF_IN50: WOF | ||
| 51 | RW_WCLRPART | FIR_WOF_IN51: WOF | ||
| 52 | RW_WCLRPART | FIR_WOF_IN52: WOF | ||
| 53 | RW_WCLRPART | FIR_WOF_IN53: WOF | ||
| 54 | RW_WCLRPART | FIR_WOF_IN54: WOF | ||
| 55 | RW_WCLRPART | FIR_WOF_IN55: WOF | ||
| 56 | RW_WCLRPART | FIR_WOF_IN56: WOF | ||
| 57 | RW_WCLRPART | FIR_WOF_IN57: WOF | ||
| 58 | RW_WCLRPART | FIR_WOF_IN58: WOF | ||
| 59 | RW_WCLRPART | FIR_WOF_IN59: WOF | ||
| 60 | RW_WCLRPART | FIR_WOF_IN60: WOF | ||
| 61 | RW_WCLRPART | FIR_WOF_IN61: WOF | ||
| 62 | RW_WCLRPART | FIR_WOF_IN62: WOF | ||
| 63 | RW_WCLRPART | FIR_WOF_IN63: WOF | ||
| Local FIR Action2 | ||||
|---|---|---|---|---|
| Addr: |
0000000011040109 (SCOM) | |||
| Name: | TP.TCPAU1.EPS.FIR.LOCAL_FIR_ACTION2 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | TP.TCPAU1.EPS.FIR.LFIR.LOCALFIR.FIR.DO_ACTION2.FIR_ACTION2.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | RW | FIR_ACTION2_IN00: ACTION2 | ||
| 1 | RW | FIR_ACTION2_IN01: ACTION2 | ||
| 2 | RW | FIR_ACTION2_IN02: ACTION2 | ||
| 3 | RW | FIR_ACTION2_IN03: ACTION2 | ||
| 4 | RW | FIR_ACTION2_IN04: ACTION2 | ||
| 5 | RW | FIR_ACTION2_IN05: ACTION2 | ||
| 6 | RW | FIR_ACTION2_IN06: ACTION2 | ||
| 7 | RW | FIR_ACTION2_IN07: ACTION2 | ||
| 8 | RW | FIR_ACTION2_IN08: ACTION2 | ||
| 9 | RW | FIR_ACTION2_IN09: ACTION2 | ||
| 10 | RW | FIR_ACTION2_IN10: ACTION2 | ||
| 11 | RW | FIR_ACTION2_IN11: ACTION2 | ||
| 12 | RW | FIR_ACTION2_IN12: ACTION2 | ||
| 13 | RW | FIR_ACTION2_IN13: ACTION2 | ||
| 14 | RW | FIR_ACTION2_IN14: ACTION2 | ||
| 15 | RW | FIR_ACTION2_IN15: ACTION2 | ||
| 16 | RW | FIR_ACTION2_IN16: ACTION2 | ||
| 17 | RW | FIR_ACTION2_IN17: ACTION2 | ||
| 18 | RW | FIR_ACTION2_IN18: ACTION2 | ||
| 19 | RW | FIR_ACTION2_IN19: ACTION2 | ||
| 20 | RW | FIR_ACTION2_IN20: ACTION2 | ||
| 21 | RW | FIR_ACTION2_IN21: ACTION2 | ||
| 22 | RW | FIR_ACTION2_IN22: ACTION2 | ||
| 23 | RW | FIR_ACTION2_IN23: ACTION2 | ||
| 24 | RW | FIR_ACTION2_IN24: ACTION2 | ||
| 25 | RW | FIR_ACTION2_IN25: ACTION2 | ||
| 26 | RW | FIR_ACTION2_IN26: ACTION2 | ||
| 27 | RW | FIR_ACTION2_IN27: ACTION2 | ||
| 28 | RW | FIR_ACTION2_IN28: ACTION2 | ||
| 29 | RW | FIR_ACTION2_IN29: ACTION2 | ||
| 30 | RW | FIR_ACTION2_IN30: ACTION2 | ||
| 31 | RW | FIR_ACTION2_IN31: ACTION2 | ||
| 32 | RW | FIR_ACTION2_IN32: ACTION2 | ||
| 33 | RW | FIR_ACTION2_IN33: ACTION2 | ||
| 34 | RW | FIR_ACTION2_IN34: ACTION2 | ||
| 35 | RW | FIR_ACTION2_IN35: ACTION2 | ||
| 36 | RW | FIR_ACTION2_IN36: ACTION2 | ||
| 37 | RW | FIR_ACTION2_IN37: ACTION2 | ||
| 38 | RW | FIR_ACTION2_IN38: ACTION2 | ||
| 39 | RW | FIR_ACTION2_IN39: ACTION2 | ||
| 40 | RW | FIR_ACTION2_IN40: ACTION2 | ||
| 41 | RW | FIR_ACTION2_IN41: ACTION2 | ||
| 42 | RW | FIR_ACTION2_IN42: ACTION2 | ||
| 43 | RW | FIR_ACTION2_IN43: ACTION2 | ||
| 44 | RW | FIR_ACTION2_IN44: ACTION2 | ||
| 45 | RW | FIR_ACTION2_IN45: ACTION2 | ||
| 46 | RW | FIR_ACTION2_IN46: ACTION2 | ||
| 47 | RW | FIR_ACTION2_IN47: ACTION2 | ||
| 48 | RW | FIR_ACTION2_IN48: ACTION2 | ||
| 49 | RW | FIR_ACTION2_IN49: ACTION2 | ||
| 50 | RW | FIR_ACTION2_IN50: ACTION2 | ||
| 51 | RW | FIR_ACTION2_IN51: ACTION2 | ||
| 52 | RW | FIR_ACTION2_IN52: ACTION2 | ||
| 53 | RW | FIR_ACTION2_IN53: ACTION2 | ||
| 54 | RW | FIR_ACTION2_IN54: ACTION2 | ||
| 55 | RW | FIR_ACTION2_IN55: ACTION2 | ||
| 56 | RW | FIR_ACTION2_IN56: ACTION2 | ||
| 57 | RW | FIR_ACTION2_IN57: ACTION2 | ||
| 58 | RW | FIR_ACTION2_IN58: ACTION2 | ||
| 59 | RW | FIR_ACTION2_IN59: ACTION2 | ||
| 60 | RW | FIR_ACTION2_IN60: ACTION2 | ||
| 61 | RW | FIR_ACTION2_IN61: ACTION2 | ||
| 62 | RW | FIR_ACTION2_IN62: ACTION2 | ||
| 63 | RW | FIR_ACTION2_IN63: ACTION2 | ||
| DTS Thermal Sensor loop1 Results | ||||
|---|---|---|---|---|
| Addr: |
0000000011050000 (SCOM) | |||
| Name: | TP.TCPAU1.EPS.THERM.WSUB.DTS_RESULT0 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:47 | TP.TCPAU1.EPS.THERM.WSUB.THRESH.COMP.DTS_RESULT_REGQ_INT_INST.LATC.L2(0:47) [000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:15 | ROX | DTS_0_RESULT: Calibrated DTS Result of sensor with id 0. EQ x50000: CORE0 ISU EQ x50020: CORE2 ISU N0,N1,PAUE,PAUW: DTS0 AXON,PCI,TP: n/a 0-11 sensor result, 12-13 trip, 14 spare, 15 valid | ||
| 16:31 | ROX | DTS_1_RESULT: Calibrated DTS Result of sensor with id 1. EQ x50000: CORE0 VSU EQ x50020: CORE2 VSU N0,N1,PAUE,PAUW: n/a AXON,PCI,TP: n/a 0-11 sensor result, 12-13 trip, 14 spare, 15 valid . | ||
| 32:47 | ROX | DTS_2_RESULT: Calibrated DTS Result of sensor with id 2. EQ x50000: CORE0 L3 EQ x50020: CORE2 L3 N0,N1,PAUE,PAUW: n/a AXON,PCI,TP: n/a 0-11 sensor result, 12-13 trip, 14 spare, 15 valid . | ||
| 48:63 | RO | constant=0b0000000000000000 | ||
| DTS Thermal Sensor loop2 Results | ||||
|---|---|---|---|---|
| Addr: |
0000000011050001 (SCOM) | |||
| Name: | TP.TCPAU1.EPS.THERM.WSUB.DTS_RESULT1 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:47 | TP.TCPAU1.EPS.THERM.WSUB.THRESH.COMP.DTS_RESULT_REGQ_INT_INST.LATC.L2(48:95) [000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:15 | ROX | DTS_4_RESULT: Calibrated DTS Result of sensor with id 4. EQ x50001: CORE1 ISU EQ x50021: CORE3 ISU N0,N1,PAUE,PAUW: n/a AXON,PCI,TP: n/a 0-11 sensor result, 12-13 trip, 14 spare, 15 valid . | ||
| 16:31 | ROX | DTS_5_RESULT: Calibrated DTS Result of sensor with id 5. EQ x50001: CORE1 VSU EQ x50021: CORE3 VSU N0,N1,PAUE,PAUW: n/a AXON,PCI,TP: n/a 0-11 sensor result, 12-13 trip, 14 spare, 15 valid . | ||
| 32:47 | ROX | DTS_6_RESULT: Calibrated DTS Result of sensor with id 6. EQ x50001: CORE1 L3 EQ x50021: CORE3 L3 N0,N1,PAUE,PAUW: n/a AXON,PCI,TP: n/a 0-11 sensor result, 12-13 trip, 14 spare, 15 valid . | ||
| 48:63 | RO | constant=0b0000000000000000 | ||
| DTS Thermal Sensor loop3 Results | ||||
|---|---|---|---|---|
| Addr: |
0000000011050002 (SCOM) | |||
| Name: | TP.TCPAU1.EPS.THERM.WSUB.DTS_RESULT2 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:15 | TP.TCPAU1.EPS.THERM.WSUB.THRESH.COMP.DTS_RESULT_REGQ_INT_INST.LATC.L2(96:111) [0000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:15 | ROX | DTS_8_RESULT: Calibrated DTS Result of sensor with id 8. EQ x50002: Racetrack EQ x50022: n/a N0,N1,PAUE,PAUW: n/a AXON,PCI,TP: n/a 0-11 sensor result, 12-13 trip, 14 spare, 15 valid . | ||
| 16:63 | RO | constant=0b000000000000000000000000000000000000000000000000 | ||
| DTS Trace Results | ||||
|---|---|---|---|---|
| Addr: |
0000000011050003 (SCOM) | |||
| Name: | TP.TCPAU1.EPS.THERM.WSUB.DTS_TRC_RESULT | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:43 | TP.TCPAU1.EPS.THERM.WSUB.PWR.PCB.TIMESTAMP_COUNT_REG_LT_INST.LATC.L2(0:43) [00000000000000000000000000000000000000000000] | |||
| 44 | TP.TCPAU1.EPS.THERM.WSUB.PWR.PCB.TIMESTAMP_OVERFLOW_ERR_LT_INST.LATC.L2(0) [0] | |||
| 48:63 | TP.TCPAU1.EPS.THERM.WSUB.THRESH.COMP.DTS_RESULT_REGQ_INT_INST.LATC.L2(16:31) [0000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:43 | ROX | TIMESTAMP_COUNTER_VALUE: Time stamp counter value during DTS trace mode. | ||
| 44 | ROX | TIMESTAMP_COUNTER_OVERFLOW_ERR: Over flow error bit of the time stamp counter value during DTS trace mode. | ||
| 45:47 | RO | constant=0b000 | ||
| 48:63 | ROX | DTS_1_RESULT: Calibrated DTS Result of sensor with id 1. EQ x50000: CORE0 VSU EQ x50020: CORE2 VSU N0,N1,PAUE,PAUW: n/a AXON,PCI,TP: n/a 0-11 sensor result, 12-13 trip, 14 spare, 15 valid . | ||
| CPM & DTS enables and cntl's | ||||
|---|---|---|---|---|
| Addr: |
000000001105000F (SCOM) | |||
| Name: | TP.TCPAU1.EPS.THERM.WSUB.THERM_MODE_REG | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:19 | TP.TCPAU1.EPS.THERM.WSUB.PWR.COMP.THERM_MODEREG_LT_0_INST.LATC.L2(0:19) [00000000000000000000] | |||
| 20:22 | TP.TCPAU1.EPS.THERM.WSUB.PWR.COMP.THERM_DTS_ENABLE_INTQ_INST.LATC.L2(0:2) [000] | |||
| 24:26 | TP.TCPAU1.EPS.THERM.WSUB.PWR.COMP.THERM_DTS_ENABLE_INTQ_INST.LATC.L2(3:5) [000] | |||
| 28 | TP.TCPAU1.EPS.THERM.WSUB.PWR.COMP.THERM_DTS_ENABLE_INTQ_INST.LATC.L2(6) [0] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | RW | THERM_DIS_CPM_BUBBLE_CORR: critical path result bubble correction active | ||
| 1 | RW | THERM_FORCE_THRES_ACT: force tpc_therm_thres_mac clock gating off and activates clocks | ||
| 2:4 | RW | THERM_THRES_TRIP_ENA: therm_thres_trip compare enables 1xx: trip0 - warning x1x: trip1 - critical xx1: trip2 - fatal | ||
| 5 | RW | THERM_DTS_SAMPLE_ENA: 0: no dts sampling, 1: dts sampling is enabled and below counter compare match can occur. | ||
| 6:9 | RW | THERM_SAMPLE_PULSE_CNT: A 16 MHz sample pulse is feed into an 18 Bit counter, with the therm_sample_pulse_cnt it is possible to select a highorder bit of the counter to enable a resolutions of sampling dtss between 2.5 us and 80 ms. An edge detection circuit detects the rising edge of the selected counter bit and this triggers a dts sample 0000: 16 ms 0001: 8 ms 0010: 4 ms 0011: 2 ms 0100: 1 ms 0101: 0.5 ms 0110: 250 us 0111: 125 us 1000: 62 .5us 1001: 31.3 us 1010: 15.6 us 1011: 7.8 us 1100: 3.9 us 1101: 2 us 1110: 1 us 1111: 0.5 us | ||
| 10:11 | RW | THERM_THRES_MODE_ENA: forces max or min mode in threshold unit: 00: is off 11: is ilegal 10: max mode 01: min mode | ||
| 12 | RW | DTS_TRIGGER_MODE: unused | ||
| 13 | RW | DTS_TRIGGER_SEL: unused | ||
| 14 | RW | THERM_THRES_OVERFLOW_MASK: 0 - therm_overflow_err will be enabled 1 - therm_overflow_err will be disabled | ||
| 15 | RW | THERM_MODE_UNUSED: unused | ||
| 16:19 | RW | THERM_DTS_READ_SEL: selects which dts result will be provided with pcb read addr_v(3): 0000: DTS 0 0001: DTS 1 0010: DTS 2 0100: DTS 4 0101: DTS 5 0110: DTS 6 1000: DTS 8 1111: Worst Case Sensor | ||
| 20:22 | RW | THERM_DTS_ENABLE_L1: loop1 dts enables: If there is only a single DTS enabled, it has to be the first DTS in a loop - here DTS 0 1xxx: DTS 0 available x1xx: DTS 1 available xx1x: DTS 2 available | ||
| 23 | RO | constant=0b0 | ||
| 24:26 | RW | THERM_DTS_ENABLE_L2: loop2 dts enables: If there is only a single DTS enabled, it has to be the first DTS in a loop - here DTS 4 1xxx: DTS 4 available x1xx: DTS 5 available xx1x: DTS 6 available | ||
| 27 | RO | constant=0b0 | ||
| 28 | RW | THERM_DTS_ENABLE_L3: dts enables: If there is only a single DTS enabled, it has to be the first DTS in a loop - here DTS 8 1xxx: DTS 8 available | ||
| 29:36 | RO | constant=0b00000000 | ||
| Skitter Control Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011050010 (SCOM) | |||
| Name: | TP.TCPAU1.EPS.THERM.WSUB.SKITTER_MODE_REG | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:7 | TP.TCPAU1.EPS.THERM.WSUB.PWR.SKIT.SKITTER_MODEREG_LT_0_INST.LATC.L2(0:7) [00000000] | |||
| 8:9 | TP.TCPAU1.EPS.THERM.WSUB.PWR.SKIT.SKITTER_MODEREG_LT_8_INST.LATC.L2(8:9) [00] | |||
| 44 | TP.TCPAU1.EPS.THERM.WSUB.PWR.SKIT.SKITTER_HOLD_SAMPLE_LT_INST.LATC.L2(0) [0] | |||
| 45 | TP.TCPAU1.EPS.THERM.WSUB.PWR.SKIT.SKITTER_DATA_V_LT_INST.LATC.L2(0) [0] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | RW | SKITTER_HOLD_SAMPLE: forces skitter to hold current sample | ||
| 1 | RW | DISABLE_SKITTER_STICKINESS: if '0' accumulation mode, '1' samples new value each cycle and resets sticky value | ||
| 2:3 | RW | SKITTER_MODE_UNUSED1: unused | ||
| 4:5 | RW | SKITTER_HOLD_DBGTRIG_SEL: bit0: hold_on_trigger0 bit1: _on_trigger1 | ||
| 6:7 | RW | SKITTER_RESET_TRIG_SEL: bit0: reset_sticky_on_trigger0 bit1: reset_sticky_on_trigger1 | ||
| 8:9 | RW | SKITTER_SAMPLE_GUTS: selects guts to measure: 00: guts1 01: guts2 10: guts3 11: guts4 | ||
| 10:43 | RO | constant=0b0000000000000000000000000000000000 | ||
| 44 | ROX | SKITTER_HOLD_SAMPLE_WITH_TRIGGER: forces skitter to hold current sample on dbg trigger, this has highest priority | ||
| 45 | ROX | SKITTER_DATA_V_LT: if '1' the data requested by a skitter force read register has finished and data is present in skitter data register in the collector macro. The data be read by any combination of V25/V26/V27 pcb reads | ||
| Error Injection Control Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011050011 (SCOM) | |||
| Name: | TP.TCPAU1.EPS.THERM.WSUB.INJECT_REG | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:3 | TP.TCPAU1.EPS.THERM.WSUB.PWR.COMP.INJECT_REG_LT_INST.LATC.L2(0:3) [0000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:1 | RW | THERM_INJECT_TRIP: 00: no injection 01: warning trip level injection 10: crtical trip level injection 11: fatal trip level injection | ||
| 2:3 | RW | THERM_INJECT_MODE: 00: no injection 01: injection on the next dts sample 10: solid injection for the next dts samples till bit setting changes 11: not used | ||
| Control / Force Reset Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011050012 (SCOM) | |||
| Name: | TP.TCPAU1.EPS.THERM.WSUB.CONTROL_REG | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 12 | TP.TCPAU1.EPS.THERM.WSUB.PWR.COMP.F_SHIFT_SENSOR [X] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | WO_1P | reset_trip_history | ||
| 1 | WO_1P | reset_sample_pulse_cnt | ||
| 2 | WO_1P | f_reset_cpm_rd | ||
| 3 | WO_1P | f_reset_cpm_wr | ||
| 4 | WO_1P | reset_sample_dts | ||
| 5 | WO_1P | force_sample_dts | ||
| 6 | WO_1P | force_sample_dts_interruptible | ||
| 7 | WO_1P | force_reset_thres_l1results | ||
| 8 | WO_1P | force_reset_thres_l2results | ||
| 9 | WO_1P | force_reset_thres_l3results | ||
| 10 | WO_1P | force_measure_volt_interruptible | ||
| 11 | WO_1P | force_reset_measure_volt | ||
| 12 | WO_1P | force_shift_sensor | ||
| Thermal Error Status Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011050013 (SCOM) | |||
| Name: | TP.TCPAU1.EPS.THERM.WSUB.ERR_STATUS_REG | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:1 | TP.TCPAU1.EPS.THERM.WSUB.PWR.COMP.CERR0.HOLD_LATCH_INST.HOLD.LATC.L2(0:1) [00] | |||
| 2:3 | TP.TCPAU1.EPS.THERM.WSUB.PWR.SKIT.CERR0.HOLD_LATCH_INST.HOLD.LATC.L2(0:1) [00] | |||
| 4 | TP.TCPAU1.EPS.THERM.WSUB.PWR.PCB.CERR0.HOLD_LATCH_INST.HOLD.LATC.L2(0) [0] | |||
| 5 | TP.TCPAU1.EPS.THERM.WSUB.PWR.COMP.CERR0.HOLD_LATCH_INST.HOLD.LATC.L2(2) [0] | |||
| 6 | TP.TCPAU1.EPS.THERM.WSUB.PWR.SKIT.CERR0.HOLD_LATCH_INST.HOLD.LATC.L2(3) [0] | |||
| 7 | TP.TCPAU1.EPS.THERM.WSUB.PWR.PCB.CERR0.HOLD_LATCH_INST.HOLD.LATC.L2(1) [0] | |||
| 8 | TP.TCPAU1.EPS.THERM.WSUB.PWR.COMP.CERR0.HOLD_LATCH_INST.HOLD.LATC.L2(7) [0] | |||
| 9 | TP.TCPAU1.EPS.THERM.WSUB.PWR.COMP.CERR0.HOLD_LATCH_INST.HOLD.LATC.L2(3) [0] | |||
| 10 | TP.TCPAU1.EPS.THERM.WSUB.PWR.COMP.CERR0.HOLD_LATCH_INST.HOLD.LATC.L2(12) [0] | |||
| 11:13 | TP.TCPAU1.EPS.THERM.WSUB.PWR.COMP.CERR0.HOLD_LATCH_INST.HOLD.LATC.L2(8:10) [000] | |||
| 14 | TP.TCPAU1.EPS.THERM.WSUB.PWR.SKIT.CERR0.HOLD_LATCH_INST.HOLD.LATC.L2(2) [0] | |||
| 15 | TP.TCPAU1.EPS.THERM.WSUB.PWR.PCB.CERR0.HOLD_LATCH_INST.HOLD.LATC.L2(2) [0] | |||
| 40:43 | TP.TCPAU1.EPS.THERM.WSUB.PWR.PCB.COUNT_STATE_LT_INST.LATC.L2(0:3) [0000] | |||
| 44:46 | TP.TCPAU1.EPS.THERM.WSUB.PWR.COMP.RUN_STATE_LT_INST.LATC.L2(0:2) [000] | |||
| 47 | TP.TCPAU1.EPS.THERM.WSUB.PWR.COMP.SHIFT_DTS_LT_INST.LATC.L2(0) [0] | |||
| 48 | TP.TCPAU1.EPS.THERM.WSUB.PWR.COMP.SHIFT_VOLT_LT_INST.LATC.L2(0) [0] | |||
| 49:50 | TP.TCPAU1.EPS.THERM.WSUB.PWR.COMP.READ_STATE_LT_INST.LATC.L2(0:1) [00] | |||
| 51:54 | TP.TCPAU1.EPS.THERM.WSUB.PWR.COMP.WRITE_STATE_LT_INST.LATC.L2(0:3) [0000] | |||
| 55 | TP.TCPAU1.EPS.THERM.WSUB.PWR.COMP.SAMPLE_DTS_LT_INST.LATC.L2(0) [0] | |||
| 56 | TP.TCPAU1.EPS.THERM.WSUB.PWR.COMP.MEASURE_VOLT_LT_INST.LATC.L2(0) [0] | |||
| 57 | TP.TCPAU1.EPS.THERM.WSUB.PWR.COMP.READ_CPM_LT_INST.LATC.L2(0) [0] | |||
| 58 | TP.TCPAU1.EPS.THERM.WSUB.PWR.COMP.WRITE_CPM_LT_INST.LATC.L2(0) [0] | |||
| 59 | TP.TCPAU1.EPS.THERM.WSUB.PWR.PWR_STATUS(15) [0] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | ROX | serial_shiftcnt_modereg_parity_err_hold | ||
| 1 | ROX | therm_modereg_parity_err_hold | ||
| 2 | ROX | skitter_modereg_parity_err_hold | ||
| 3 | ROX | skitter_forcereg_parity_err_hold | ||
| 4 | ROX | scan_init_version_reg_parity_err_hold | ||
| 5 | ROX | volt_modereg_parity_err_hold | ||
| 6 | ROX | skitter_clksrcreg_parity_err_hold | ||
| 7 | ROX | count_state_err_hold | ||
| 8 | ROX | run_state_err_hold | ||
| 9 | ROX | thres_therm_state_err_hold | ||
| 10 | ROX | thres_therm_overflow_err_hold | ||
| 11 | ROX | shifter_parity_err_hold | ||
| 12 | ROX | shifter_valid_err_hold | ||
| 13 | ROX | timeout_err_hold | ||
| 14 | ROX | f_skitter_err_hold | ||
| 15 | ROX | pcb_err_hold_out | ||
| 16:39 | RO | constant=0b000000000000000000000000 | ||
| 40:43 | ROX | count_state_lt | ||
| 44:46 | ROX | run_state_lt | ||
| 47 | ROX | shift_dts_lt | ||
| 48 | ROX | shift_volt_lt | ||
| 49:50 | ROX | read_state_lt | ||
| 51:54 | ROX | write_state_lt | ||
| 55 | ROX | sample_dts_lt | ||
| 56 | ROX | measure_volt_lt | ||
| 57 | ROX | read_cpm_lt | ||
| 58 | ROX | write_cpm_lt | ||
| 59 | ROX | unused | ||
| 60:63 | RO | constant=0b0000 | ||
| Skitter Force Read Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011050014 (SCOM) | |||
| Name: | TP.TCPAU1.EPS.THERM.WSUB.SKITTER_FORCE_REG | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0 | TP.TCPAU1.EPS.THERM.WSUB.PWR.SKIT.SKITTER_FORCEREG_LT_0_INST.LATC.L2(0) [0] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0 | RW | F_SKITTER_READ: Forces the read of that particular skitter | ||
| Skitter Clock src control Register | ||||
|---|---|---|---|---|
| Addr: |
0000000011050016 (SCOM) | |||
| Name: | TP.TCPAU1.EPS.THERM.WSUB.SKITTER_CLKSRC_REG | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:2 | TP.TCPAU1.EPS.THERM.WSUB.PWR.SKIT.SKITTER_CLKSRCREG_LT_0_INST.LATC.L2(0:2) [000] | |||
| 36:37 | TP.TCPAU1.EPS.THERM.WSUB.PWR.SKIT.SKITTER_CLKSRCREG_LT_36_INST.LATC.L2(36:37) [00] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:2 | RW | SKITTER0_CLKSRC: selects clock to measure: 000: local mesh clock 001: external pin skitter_c1_1_in 010: local d1clk only if d_mode = 1 011: external pin skitter_c1_2_in 100: local lclk only if d_mode = 1 101: external pin skitter_c1_3_in 110: unused 111: external pin skitter_c1_4_in | ||
| 3:35 | RO | constant=0b000000000000000000000000000000000 | ||
| 36:37 | RW | SKITTER0_DELAY_SELECT: To select delay to be added between clock source mux and inverter chain(base line delay is 12.2psec) of skitter0. 00 - No delay 01 - 0.6psec 10 - 1.8psec 11 - 5 psec | ||
| Skitter Data Register Read Bit0:63 | ||||
|---|---|---|---|---|
| Addr: |
0000000011050019 (SCOM) | |||
| Name: | TP.TCPAU1.EPS.THERM.WSUB.SKITTER_DATA0 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | TP.TCPAU1.EPS.THERM.WSUB.PWR.SKIT.SKITTER_DATA_LT_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:63 | ROX | |||
| Skitter Data Register Read Bit32:95 | ||||
|---|---|---|---|---|
| Addr: |
000000001105001A (SCOM) | |||
| Name: | TP.TCPAU1.EPS.THERM.WSUB.SKITTER_DATA1 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | TP.TCPAU1.EPS.THERM.WSUB.PWR.SKIT.SKITTER_DATA_LT_INST.LATC.L2(32:95) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:63 | ROX | |||
| Skitter Data Register Read Bit64:127 | ||||
|---|---|---|---|---|
| Addr: |
000000001105001B (SCOM) | |||
| Name: | TP.TCPAU1.EPS.THERM.WSUB.SKITTER_DATA2 | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:63 | TP.TCPAU1.EPS.THERM.WSUB.PWR.SKIT.SKITTER_DATA_LT_INST.LATC.L2(64:127) [0000000000000000000000000000000000000000000000000000000000000000] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:63 | ROX | |||
| Timestamp Counter Read | ||||
|---|---|---|---|---|
| Addr: |
000000001105001C (SCOM) | |||
| Name: | TP.TCPAU1.EPS.THERM.WSUB.TIMESTAMP_COUNTER_READ | |||
| Constant(s): | ||||
| Comments: | ||||
| SelectedAttributes: | ||||
| Latches | Bits | Latch Name [flushval] | ||
| 0:43 | TP.TCPAU1.EPS.THERM.WSUB.PWR.PCB.TIMESTAMP_COUNT_REG_LT_INST.LATC.L2(0:43) [00000000000000000000000000000000000000000000] | |||
| 44 | TP.TCPAU1.EPS.THERM.WSUB.PWR.PCB.TIMESTAMP_OVERFLOW_ERR_LT_INST.LATC.L2(0) [0] | |||
| Bit(s) | SCOM | Dial: Description | ||
| 0:43 | ROX | TIMESTAMP_COUNTER_VALUE: Time stamp counter value during DTS trace mode. | ||
| 44 | ROX | TIMESTAMP_COUNTER_OVERFLOW_ERR: Over flow error bit of the time stamp counter value during DTS trace mode. | ||